target/linux/ipq806x/patches-4.9/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch

   1 From d27c303e828d7e42f339a459d2abfe30c51698e9 Mon Sep 17 00:00:00 2001
   2 From: Sham Muthayyan <smuthayy@codeaurora.org>
   3 Date: Tue, 26 Jul 2016 12:28:31 +0530
   4 Subject: PCI: qcom: Programming the PCIE iATU for IPQ806x
   5
   6 Resolved PCIE EP detection errors caused due to missing iATU programming.
   7
   8 Change-Id: Ie95c0f8cb940abc0192a8a3c4e825ddba54b72fe
   9 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  10 ---
  11  drivers/pci/host/pcie-qcom.c | 77 ++++++++++++++++++++++++++++++++++++++++++++
  12  1 file changed, 77 insertions(+)
  13
  14 --- a/drivers/pci/host/pcie-qcom.c
  15 +++ b/drivers/pci/host/pcie-qcom.c
  16 @@ -52,6 +52,29 @@
  17  #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE         BIT(0)
  18
  19  #define PCIE20_CAP                             0x70
  20 +#define PCIE20_CAP_LINKCTRLSTATUS              (PCIE20_CAP + 0x10)
  21 +
  22 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0                0x818
  23 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1                0x81c
  24 +
  25 +#define PCIE20_PLR_IATU_VIEWPORT               0x900
  26 +#define PCIE20_PLR_IATU_REGION_OUTBOUND                (0x0 << 31)
  27 +#define PCIE20_PLR_IATU_REGION_INDEX(x)                (x << 0)
  28 +
  29 +#define PCIE20_PLR_IATU_CTRL1                  0x904
  30 +#define PCIE20_PLR_IATU_TYPE_CFG0              (0x4 << 0)
  31 +#define PCIE20_PLR_IATU_TYPE_MEM               (0x0 << 0)
  32 +
  33 +#define PCIE20_PLR_IATU_CTRL2                  0x908
  34 +#define PCIE20_PLR_IATU_ENABLE                 BIT(31)
  35 +
  36 +#define PCIE20_PLR_IATU_LBAR                   0x90C
  37 +#define PCIE20_PLR_IATU_UBAR                   0x910
  38 +#define PCIE20_PLR_IATU_LAR                    0x914
  39 +#define PCIE20_PLR_IATU_LTAR                   0x918
  40 +#define PCIE20_PLR_IATU_UTAR                   0x91c
  41 +
  42 +#define MSM_PCIE_DEV_CFG_ADDR          0x01000000
  43
  44  #define PERST_DELAY_US                         1000
  45  /* PARF registers */
  46 @@ -163,6 +186,57 @@ static int qcom_pcie_establish_link(stru
  47         return dw_pcie_wait_for_link(&pcie->pp);
  48  }
  49
  50 +static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
  51 +{
  52 +       struct pcie_port *pp = &pcie->pp;
  53 +
  54 +       /*
  55 +        * program and enable address translation region 0 (device config
  56 +        * address space); region type config;
  57 +        * axi config address range to device config address range
  58 +        */
  59 +       writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
  60 +              PCIE20_PLR_IATU_REGION_INDEX(0),
  61 +              pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
  62 +
  63 +       writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
  64 +       writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
  65 +       writel(pp->cfg0_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
  66 +       writel((pp->cfg0_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
  67 +       writel((pp->cfg0_base + pp->cfg0_size - 1),
  68 +              pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
  69 +       writel(busdev, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
  70 +       writel(0, pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
  71 +}
  72 +
  73 +static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
  74 +{
  75 +       struct pcie_port *pp = &pcie->pp;
  76 +
  77 +       /*
  78 +        * program and enable address translation region 2 (device resource
  79 +        * address space); region type memory;
  80 +        * axi device bar address range to device bar address range
  81 +        */
  82 +       writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
  83 +              PCIE20_PLR_IATU_REGION_INDEX(2),
  84 +              pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
  85 +
  86 +       writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
  87 +       writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
  88 +       writel(pp->mem_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
  89 +       writel((pp->mem_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
  90 +       writel(pp->mem_base + pp->mem_size - 1,
  91 +              pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
  92 +       writel(pp->mem_bus_addr, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
  93 +       writel(upper_32_bits(pp->mem_bus_addr),
  94 +              pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
  95 +
  96 +       /* 256B PCIE buffer setting */
  97 +       writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
  98 +       writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
  99 +}
 100 +
 101  static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
 102  {
 103         struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
 104 @@ -404,6 +478,9 @@ static int qcom_pcie_init_v0(struct qcom
 105         /* wait for clock acquisition */
 106         usleep_range(1000, 1500);
 107
 108 +       qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
 109 +       qcom_pcie_prog_viewport_mem2_outbound(pcie);
 110 +
 111         return 0;
 112
 113  err_deassert_ahb: