ipq806x: route gpio interrupts to APPS processor through scm firmware
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.9 / 0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
1 From 2034addc7e193dc81d7ca60d8884832751b76758 Mon Sep 17 00:00:00 2001
2 From: Ajay Kishore <akisho@codeaurora.org>
3 Date: Tue, 24 Jan 2017 14:14:16 +0530
4 Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
5
6 For IPQ806x targets, TZ protects the registers that are used to
7 configure the routing of interrupts to a target processor.
8 To resolve this, this patch uses scm call to route GPIO interrupts
9 to application processor. Also the scm call interface is changed.
10
11 Change-Id: Ib6c06829d04bc8c20483c36e63da92e26cdef9ce
12 Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
13 ---
14 drivers/firmware/qcom_scm-32.c | 17 +++++++++++++++++
15 drivers/firmware/qcom_scm-64.c | 9 +++++++++
16 drivers/firmware/qcom_scm.c | 13 +++++++++++++
17 drivers/firmware/qcom_scm.h | 8 ++++++++
18 drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++------
19 include/linux/qcom_scm.h | 3 ++-
20 6 files changed, 77 insertions(+), 7 deletions(-)
21
22 --- a/drivers/firmware/qcom_scm-32.c
23 +++ b/drivers/firmware/qcom_scm-32.c
24 @@ -560,3 +560,21 @@ int __qcom_scm_pas_mss_reset(struct devi
25
26 return ret ? : le32_to_cpu(out);
27 }
28 +
29 +int __qcom_scm_pinmux_read(u32 svc_id, u32 cmd_id, u32 arg1)
30 +{
31 + s32 ret;
32 +
33 + ret = qcom_scm_call_atomic1(svc_id, cmd_id, arg1);
34 +
35 + return ret;
36 +}
37 +
38 +int __qcom_scm_pinmux_write(u32 svc_id, u32 cmd_id, u32 arg1, u32 arg2)
39 +{
40 + s32 ret;
41 +
42 + ret = qcom_scm_call_atomic2(svc_id, cmd_id, arg1, arg2);
43 +
44 + return ret;
45 + }
46 --- a/drivers/firmware/qcom_scm-64.c
47 +++ b/drivers/firmware/qcom_scm-64.c
48 @@ -358,3 +358,12 @@ int __qcom_scm_pas_mss_reset(struct devi
49
50 return ret ? : res.a1;
51 }
52 +int __qcom_scm_pinmux_read(u32 svc_id, u32 cmd_id, u32 arg1)
53 +{
54 + return -ENOTSUPP;
55 +}
56 +
57 +int __qcom_scm_pinmux_write(u32 svc_id, u32 cmd_id, u32 arg1, u32 arg2)
58 +{
59 + return -ENOTSUPP;
60 +}
61 --- a/drivers/firmware/qcom_scm.c
62 +++ b/drivers/firmware/qcom_scm.c
63 @@ -443,3 +443,16 @@ static int __init qcom_scm_init(void)
64 return platform_driver_register(&qcom_scm_driver);
65 }
66 subsys_initcall(qcom_scm_init);
67 +
68 +int qcom_scm_pinmux_read(u32 arg1)
69 +{
70 + return __qcom_scm_pinmux_read(SCM_SVC_IO_ACCESS, SCM_IO_READ, arg1);
71 +}
72 +EXPORT_SYMBOL(qcom_scm_pinmux_read);
73 +
74 +int qcom_scm_pinmux_write(u32 arg1, u32 arg2)
75 +{
76 + return __qcom_scm_pinmux_write(SCM_SVC_IO_ACCESS, SCM_IO_WRITE,
77 + arg1, arg2);
78 +}
79 +EXPORT_SYMBOL(qcom_scm_pinmux_write);
80 --- a/drivers/firmware/qcom_scm.h
81 +++ b/drivers/firmware/qcom_scm.h
82 @@ -56,6 +56,13 @@ extern int __qcom_scm_pas_auth_and_rese
83 extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
84 extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
85
86 +#define SCM_IO_READ 1
87 +#define SCM_IO_WRITE 2
88 +#define SCM_SVC_IO_ACCESS 0x5
89 +
90 +s32 __qcom_scm_pinmux_read(u32 svc_id, u32 cmd_id, u32 arg1);
91 +s32 __qcom_scm_pinmux_write(u32 svc_id, u32 cmd_id, u32 arg1, u32 arg2);
92 +
93 /* common error codes */
94 #define QCOM_SCM_V2_EBUSY -12
95 #define QCOM_SCM_ENOMEM -5
96 --- a/drivers/pinctrl/qcom/pinctrl-msm.c
97 +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
98 @@ -30,7 +30,8 @@
99 #include <linux/reboot.h>
100 #include <linux/pm.h>
101 #include <linux/log2.h>
102 -
103 +#include <linux/qcom_scm.h>
104 +#include <linux/io.h>
105 #include "../core.h"
106 #include "../pinconf.h"
107 #include "pinctrl-msm.h"
108 @@ -639,6 +640,9 @@ static int msm_gpio_irq_set_type(struct
109 const struct msm_pingroup *g;
110 unsigned long flags;
111 u32 val;
112 + u32 addr;
113 + int ret;
114 + const __be32 *reg;
115
116 g = &pctrl->soc->groups[d->hwirq];
117
118 @@ -652,11 +656,30 @@ static int msm_gpio_irq_set_type(struct
119 else
120 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
121
122 + ret = of_device_is_compatible(pctrl->dev->of_node,
123 + "qcom,ipq8064-pinctrl");
124 /* Route interrupts to application cpu */
125 - val = readl(pctrl->regs + g->intr_target_reg);
126 - val &= ~(7 << g->intr_target_bit);
127 - val |= g->intr_target_kpss_val << g->intr_target_bit;
128 - writel(val, pctrl->regs + g->intr_target_reg);
129 + if (!ret) {
130 + val = readl(pctrl->regs + g->intr_target_reg);
131 + val &= ~(7 << g->intr_target_bit);
132 + val |= g->intr_target_kpss_val << g->intr_target_bit;
133 + writel(val, pctrl->regs + g->intr_target_reg);
134 + } else {
135 + reg = of_get_property(pctrl->dev->of_node, "reg", NULL);
136 + if (reg) {
137 + addr = be32_to_cpup(reg) + g->intr_target_reg;
138 + val = qcom_scm_pinmux_read(addr);
139 + __iormb();
140 +
141 + val &= ~(7 << g->intr_target_bit);
142 + val |= g->intr_target_kpss_val << g->intr_target_bit;
143 +
144 + __iowmb();
145 + ret = qcom_scm_pinmux_write(addr, val);
146 + if (ret)
147 + pr_err("\n Routing interrupts to Apps proc failed");
148 + }
149 + }
150
151 /* Update configuration for gpio.
152 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
153 @@ -930,4 +953,3 @@ int msm_pinctrl_remove(struct platform_d
154 return 0;
155 }
156 EXPORT_SYMBOL(msm_pinctrl_remove);
157 -
158 --- a/include/linux/qcom_scm.h
159 +++ b/include/linux/qcom_scm.h
160 @@ -46,4 +46,6 @@ extern void qcom_scm_cpu_power_down(u32
161
162 extern u32 qcom_scm_get_version(void);
163
164 +extern s32 qcom_scm_pinmux_read(u32 arg1);
165 +extern s32 qcom_scm_pinmux_write(u32 arg1, u32 arg2);
166 #endif