ipq806x: refresh patches
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.9 / 012-1-clk-qcom-Add-support-for-SMD-RPM-Clocks.patch
1 From patchwork Wed Nov 2 15:56:56 2016
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 Subject: [v9,1/3] clk: qcom: Add support for SMD-RPM Clocks
6 From: Georgi Djakov <georgi.djakov@linaro.org>
7 X-Patchwork-Id: 9409419
8 Message-Id: <20161102155658.32203-2-georgi.djakov@linaro.org>
9 To: sboyd@codeaurora.org, mturquette@baylibre.com
10 Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
11 robh+dt@kernel.org, mark.rutland@arm.com,
12 linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
13 georgi.djakov@linaro.org
14 Date: Wed, 2 Nov 2016 17:56:56 +0200
15
16 This adds initial support for clocks controlled by the Resource
17 Power Manager (RPM) processor on some Qualcomm SoCs, which use
18 the qcom_smd_rpm driver to communicate with RPM.
19 Such platforms are msm8916, apq8084 and msm8974.
20
21 The RPM is a dedicated hardware engine for managing the shared
22 SoC resources in order to keep the lowest power profile. It
23 communicates with other hardware subsystems via shared memory
24 and accepts clock requests, aggregates the requests and turns
25 the clocks on/off or scales them on demand.
26
27 This driver is based on the codeaurora.org driver:
28 https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c
29
30 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
31 ---
32 .../devicetree/bindings/clock/qcom,rpmcc.txt | 36 ++
33 drivers/clk/qcom/Kconfig | 16 +
34 drivers/clk/qcom/Makefile | 1 +
35 drivers/clk/qcom/clk-smd-rpm.c | 571 +++++++++++++++++++++
36 include/dt-bindings/clock/qcom,rpmcc.h | 45 ++
37 5 files changed, 669 insertions(+)
38 create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
39 create mode 100644 drivers/clk/qcom/clk-smd-rpm.c
40 create mode 100644 include/dt-bindings/clock/qcom,rpmcc.h
41
42 --
43 To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
44 the body of a message to majordomo@vger.kernel.org
45 More majordomo info at http://vger.kernel.org/majordomo-info.html
46
47 --- /dev/null
48 +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
49 @@ -0,0 +1,36 @@
50 +Qualcomm RPM Clock Controller Binding
51 +------------------------------------------------
52 +The RPM is a dedicated hardware engine for managing the shared
53 +SoC resources in order to keep the lowest power profile. It
54 +communicates with other hardware subsystems via shared memory
55 +and accepts clock requests, aggregates the requests and turns
56 +the clocks on/off or scales them on demand.
57 +
58 +Required properties :
59 +- compatible : shall contain only one of the following. The generic
60 + compatible "qcom,rpmcc" should be also included.
61 +
62 + "qcom,rpmcc-msm8916", "qcom,rpmcc"
63 +
64 +- #clock-cells : shall contain 1
65 +
66 +Example:
67 + smd {
68 + compatible = "qcom,smd";
69 +
70 + rpm {
71 + interrupts = <0 168 1>;
72 + qcom,ipc = <&apcs 8 0>;
73 + qcom,smd-edge = <15>;
74 +
75 + rpm_requests {
76 + compatible = "qcom,rpm-msm8916";
77 + qcom,smd-channels = "rpm_requests";
78 +
79 + rpmcc: clock-controller {
80 + compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
81 + #clock-cells = <1>;
82 + };
83 + };
84 + };
85 + };
86 --- a/drivers/clk/qcom/Kconfig
87 +++ b/drivers/clk/qcom/Kconfig
88 @@ -2,6 +2,9 @@ config QCOM_GDSC
89 bool
90 select PM_GENERIC_DOMAINS if PM
91
92 +config QCOM_RPMCC
93 + bool
94 +
95 config COMMON_CLK_QCOM
96 tristate "Support for Qualcomm's clock controllers"
97 depends on OF
98 @@ -9,6 +12,19 @@ config COMMON_CLK_QCOM
99 select REGMAP_MMIO
100 select RESET_CONTROLLER
101
102 +config QCOM_CLK_SMD_RPM
103 + tristate "RPM over SMD based Clock Controller"
104 + depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
105 + select QCOM_RPMCC
106 + help
107 + The RPM (Resource Power Manager) is a dedicated hardware engine for
108 + managing the shared SoC resources in order to keep the lowest power
109 + profile. It communicates with other hardware subsystems via shared
110 + memory and accepts clock requests, aggregates the requests and turns
111 + the clocks on/off or scales them on demand.
112 + Say Y if you want to support the clocks exposed by the RPM on
113 + platforms such as apq8016, apq8084, msm8974 etc.
114 +
115 config APQ_GCC_8084
116 tristate "APQ8084 Global Clock Controller"
117 select QCOM_GDSC
118 --- a/drivers/clk/qcom/Makefile
119 +++ b/drivers/clk/qcom/Makefile
120 @@ -29,3 +29,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm896
121 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
122 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
123 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
124 +obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
125 --- /dev/null
126 +++ b/drivers/clk/qcom/clk-smd-rpm.c
127 @@ -0,0 +1,571 @@
128 +/*
129 + * Copyright (c) 2016, Linaro Limited
130 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
131 + *
132 + * This software is licensed under the terms of the GNU General Public
133 + * License version 2, as published by the Free Software Foundation, and
134 + * may be copied, distributed, and modified under those terms.
135 + *
136 + * This program is distributed in the hope that it will be useful,
137 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
138 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
139 + * GNU General Public License for more details.
140 + */
141 +
142 +#include <linux/clk-provider.h>
143 +#include <linux/err.h>
144 +#include <linux/export.h>
145 +#include <linux/init.h>
146 +#include <linux/kernel.h>
147 +#include <linux/module.h>
148 +#include <linux/mutex.h>
149 +#include <linux/of.h>
150 +#include <linux/of_device.h>
151 +#include <linux/platform_device.h>
152 +#include <linux/soc/qcom/smd-rpm.h>
153 +
154 +#include <dt-bindings/clock/qcom,rpmcc.h>
155 +#include <dt-bindings/mfd/qcom-rpm.h>
156 +
157 +#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
158 +#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
159 +#define QCOM_RPM_SMD_KEY_RATE 0x007a484b
160 +#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
161 +#define QCOM_RPM_SMD_KEY_STATE 0x54415453
162 +#define QCOM_RPM_SCALING_ENABLE_ID 0x2
163 +
164 +#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \
165 + key) \
166 + static struct clk_smd_rpm _platform##_##_active; \
167 + static struct clk_smd_rpm _platform##_##_name = { \
168 + .rpm_res_type = (type), \
169 + .rpm_clk_id = (r_id), \
170 + .rpm_status_id = (stat_id), \
171 + .rpm_key = (key), \
172 + .peer = &_platform##_##_active, \
173 + .rate = INT_MAX, \
174 + .hw.init = &(struct clk_init_data){ \
175 + .ops = &clk_smd_rpm_ops, \
176 + .name = #_name, \
177 + .parent_names = (const char *[]){ "xo_board" }, \
178 + .num_parents = 1, \
179 + }, \
180 + }; \
181 + static struct clk_smd_rpm _platform##_##_active = { \
182 + .rpm_res_type = (type), \
183 + .rpm_clk_id = (r_id), \
184 + .rpm_status_id = (stat_id), \
185 + .active_only = true, \
186 + .rpm_key = (key), \
187 + .peer = &_platform##_##_name, \
188 + .rate = INT_MAX, \
189 + .hw.init = &(struct clk_init_data){ \
190 + .ops = &clk_smd_rpm_ops, \
191 + .name = #_active, \
192 + .parent_names = (const char *[]){ "xo_board" }, \
193 + .num_parents = 1, \
194 + }, \
195 + }
196 +
197 +#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \
198 + stat_id, r, key) \
199 + static struct clk_smd_rpm _platform##_##_active; \
200 + static struct clk_smd_rpm _platform##_##_name = { \
201 + .rpm_res_type = (type), \
202 + .rpm_clk_id = (r_id), \
203 + .rpm_status_id = (stat_id), \
204 + .rpm_key = (key), \
205 + .branch = true, \
206 + .peer = &_platform##_##_active, \
207 + .rate = (r), \
208 + .hw.init = &(struct clk_init_data){ \
209 + .ops = &clk_smd_rpm_branch_ops, \
210 + .name = #_name, \
211 + .parent_names = (const char *[]){ "xo_board" }, \
212 + .num_parents = 1, \
213 + }, \
214 + }; \
215 + static struct clk_smd_rpm _platform##_##_active = { \
216 + .rpm_res_type = (type), \
217 + .rpm_clk_id = (r_id), \
218 + .rpm_status_id = (stat_id), \
219 + .active_only = true, \
220 + .rpm_key = (key), \
221 + .branch = true, \
222 + .peer = &_platform##_##_name, \
223 + .rate = (r), \
224 + .hw.init = &(struct clk_init_data){ \
225 + .ops = &clk_smd_rpm_branch_ops, \
226 + .name = #_active, \
227 + .parent_names = (const char *[]){ "xo_board" }, \
228 + .num_parents = 1, \
229 + }, \
230 + }
231 +
232 +#define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \
233 + __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
234 + 0, QCOM_RPM_SMD_KEY_RATE)
235 +
236 +#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \
237 + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \
238 + r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
239 +
240 +#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \
241 + __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
242 + 0, QCOM_RPM_SMD_KEY_STATE)
243 +
244 +#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id) \
245 + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
246 + QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
247 + QCOM_RPM_KEY_SOFTWARE_ENABLE)
248 +
249 +#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \
250 + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
251 + QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
252 + QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
253 +
254 +#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
255 +
256 +struct clk_smd_rpm {
257 + const int rpm_res_type;
258 + const int rpm_key;
259 + const int rpm_clk_id;
260 + const int rpm_status_id;
261 + const bool active_only;
262 + bool enabled;
263 + bool branch;
264 + struct clk_smd_rpm *peer;
265 + struct clk_hw hw;
266 + unsigned long rate;
267 + struct qcom_smd_rpm *rpm;
268 +};
269 +
270 +struct clk_smd_rpm_req {
271 + __le32 key;
272 + __le32 nbytes;
273 + __le32 value;
274 +};
275 +
276 +struct rpm_cc {
277 + struct qcom_rpm *rpm;
278 + struct clk_hw_onecell_data data;
279 + struct clk_hw *hws[];
280 +};
281 +
282 +struct rpm_smd_clk_desc {
283 + struct clk_smd_rpm **clks;
284 + size_t num_clks;
285 +};
286 +
287 +static DEFINE_MUTEX(rpm_smd_clk_lock);
288 +
289 +static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
290 +{
291 + int ret;
292 + struct clk_smd_rpm_req req = {
293 + .key = cpu_to_le32(r->rpm_key),
294 + .nbytes = cpu_to_le32(sizeof(u32)),
295 + .value = cpu_to_le32(INT_MAX),
296 + };
297 +
298 + ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
299 + r->rpm_res_type, r->rpm_clk_id, &req,
300 + sizeof(req));
301 + if (ret)
302 + return ret;
303 + ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
304 + r->rpm_res_type, r->rpm_clk_id, &req,
305 + sizeof(req));
306 + if (ret)
307 + return ret;
308 +
309 + return 0;
310 +}
311 +
312 +static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
313 + unsigned long rate)
314 +{
315 + struct clk_smd_rpm_req req = {
316 + .key = cpu_to_le32(r->rpm_key),
317 + .nbytes = cpu_to_le32(sizeof(u32)),
318 + .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
319 + };
320 +
321 + return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
322 + r->rpm_res_type, r->rpm_clk_id, &req,
323 + sizeof(req));
324 +}
325 +
326 +static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
327 + unsigned long rate)
328 +{
329 + struct clk_smd_rpm_req req = {
330 + .key = cpu_to_le32(r->rpm_key),
331 + .nbytes = cpu_to_le32(sizeof(u32)),
332 + .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
333 + };
334 +
335 + return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
336 + r->rpm_res_type, r->rpm_clk_id, &req,
337 + sizeof(req));
338 +}
339 +
340 +static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
341 + unsigned long *active, unsigned long *sleep)
342 +{
343 + *active = rate;
344 +
345 + /*
346 + * Active-only clocks don't care what the rate is during sleep. So,
347 + * they vote for zero.
348 + */
349 + if (r->active_only)
350 + *sleep = 0;
351 + else
352 + *sleep = *active;
353 +}
354 +
355 +static int clk_smd_rpm_prepare(struct clk_hw *hw)
356 +{
357 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
358 + struct clk_smd_rpm *peer = r->peer;
359 + unsigned long this_rate = 0, this_sleep_rate = 0;
360 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
361 + unsigned long active_rate, sleep_rate;
362 + int ret = 0;
363 +
364 + mutex_lock(&rpm_smd_clk_lock);
365 +
366 + /* Don't send requests to the RPM if the rate has not been set. */
367 + if (!r->rate)
368 + goto out;
369 +
370 + to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
371 +
372 + /* Take peer clock's rate into account only if it's enabled. */
373 + if (peer->enabled)
374 + to_active_sleep(peer, peer->rate,
375 + &peer_rate, &peer_sleep_rate);
376 +
377 + active_rate = max(this_rate, peer_rate);
378 +
379 + if (r->branch)
380 + active_rate = !!active_rate;
381 +
382 + ret = clk_smd_rpm_set_rate_active(r, active_rate);
383 + if (ret)
384 + goto out;
385 +
386 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
387 + if (r->branch)
388 + sleep_rate = !!sleep_rate;
389 +
390 + ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
391 + if (ret)
392 + /* Undo the active set vote and restore it */
393 + ret = clk_smd_rpm_set_rate_active(r, peer_rate);
394 +
395 +out:
396 + if (!ret)
397 + r->enabled = true;
398 +
399 + mutex_unlock(&rpm_smd_clk_lock);
400 +
401 + return ret;
402 +}
403 +
404 +static void clk_smd_rpm_unprepare(struct clk_hw *hw)
405 +{
406 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
407 + struct clk_smd_rpm *peer = r->peer;
408 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
409 + unsigned long active_rate, sleep_rate;
410 + int ret;
411 +
412 + mutex_lock(&rpm_smd_clk_lock);
413 +
414 + if (!r->rate)
415 + goto out;
416 +
417 + /* Take peer clock's rate into account only if it's enabled. */
418 + if (peer->enabled)
419 + to_active_sleep(peer, peer->rate, &peer_rate,
420 + &peer_sleep_rate);
421 +
422 + active_rate = r->branch ? !!peer_rate : peer_rate;
423 + ret = clk_smd_rpm_set_rate_active(r, active_rate);
424 + if (ret)
425 + goto out;
426 +
427 + sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
428 + ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
429 + if (ret)
430 + goto out;
431 +
432 + r->enabled = false;
433 +
434 +out:
435 + mutex_unlock(&rpm_smd_clk_lock);
436 +}
437 +
438 +static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
439 + unsigned long parent_rate)
440 +{
441 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
442 + struct clk_smd_rpm *peer = r->peer;
443 + unsigned long active_rate, sleep_rate;
444 + unsigned long this_rate = 0, this_sleep_rate = 0;
445 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
446 + int ret = 0;
447 +
448 + mutex_lock(&rpm_smd_clk_lock);
449 +
450 + if (!r->enabled)
451 + goto out;
452 +
453 + to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
454 +
455 + /* Take peer clock's rate into account only if it's enabled. */
456 + if (peer->enabled)
457 + to_active_sleep(peer, peer->rate,
458 + &peer_rate, &peer_sleep_rate);
459 +
460 + active_rate = max(this_rate, peer_rate);
461 + ret = clk_smd_rpm_set_rate_active(r, active_rate);
462 + if (ret)
463 + goto out;
464 +
465 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
466 + ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
467 + if (ret)
468 + goto out;
469 +
470 + r->rate = rate;
471 +
472 +out:
473 + mutex_unlock(&rpm_smd_clk_lock);
474 +
475 + return ret;
476 +}
477 +
478 +static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
479 + unsigned long *parent_rate)
480 +{
481 + /*
482 + * RPM handles rate rounding and we don't have a way to
483 + * know what the rate will be, so just return whatever
484 + * rate is requested.
485 + */
486 + return rate;
487 +}
488 +
489 +static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
490 + unsigned long parent_rate)
491 +{
492 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
493 +
494 + /*
495 + * RPM handles rate rounding and we don't have a way to
496 + * know what the rate will be, so just return whatever
497 + * rate was set.
498 + */
499 + return r->rate;
500 +}
501 +
502 +static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
503 +{
504 + int ret;
505 + struct clk_smd_rpm_req req = {
506 + .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
507 + .nbytes = cpu_to_le32(sizeof(u32)),
508 + .value = cpu_to_le32(1),
509 + };
510 +
511 + ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
512 + QCOM_SMD_RPM_MISC_CLK,
513 + QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
514 + if (ret) {
515 + pr_err("RPM clock scaling (sleep set) not enabled!\n");
516 + return ret;
517 + }
518 +
519 + ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
520 + QCOM_SMD_RPM_MISC_CLK,
521 + QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
522 + if (ret) {
523 + pr_err("RPM clock scaling (active set) not enabled!\n");
524 + return ret;
525 + }
526 +
527 + pr_debug("%s: RPM clock scaling is enabled\n", __func__);
528 + return 0;
529 +}
530 +
531 +static const struct clk_ops clk_smd_rpm_ops = {
532 + .prepare = clk_smd_rpm_prepare,
533 + .unprepare = clk_smd_rpm_unprepare,
534 + .set_rate = clk_smd_rpm_set_rate,
535 + .round_rate = clk_smd_rpm_round_rate,
536 + .recalc_rate = clk_smd_rpm_recalc_rate,
537 +};
538 +
539 +static const struct clk_ops clk_smd_rpm_branch_ops = {
540 + .prepare = clk_smd_rpm_prepare,
541 + .unprepare = clk_smd_rpm_unprepare,
542 + .round_rate = clk_smd_rpm_round_rate,
543 + .recalc_rate = clk_smd_rpm_recalc_rate,
544 +};
545 +
546 +/* msm8916 */
547 +DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
548 +DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
549 +DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
550 +DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
551 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);
552 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);
553 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);
554 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);
555 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);
556 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);
557 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);
558 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);
559 +
560 +static struct clk_smd_rpm *msm8916_clks[] = {
561 + [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
562 + [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
563 + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
564 + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
565 + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
566 + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
567 + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
568 + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
569 + [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
570 + [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
571 + [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
572 + [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
573 + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
574 + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
575 + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
576 + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
577 + [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
578 + [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
579 + [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
580 + [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
581 + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
582 + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
583 + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
584 + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
585 +};
586 +
587 +static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
588 + .clks = msm8916_clks,
589 + .num_clks = ARRAY_SIZE(msm8916_clks),
590 +};
591 +
592 +static const struct of_device_id rpm_smd_clk_match_table[] = {
593 + { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
594 + { }
595 +};
596 +MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
597 +
598 +static int rpm_smd_clk_probe(struct platform_device *pdev)
599 +{
600 + struct clk_hw **hws;
601 + struct rpm_cc *rcc;
602 + struct clk_hw_onecell_data *data;
603 + int ret;
604 + size_t num_clks, i;
605 + struct qcom_smd_rpm *rpm;
606 + struct clk_smd_rpm **rpm_smd_clks;
607 + const struct rpm_smd_clk_desc *desc;
608 +
609 + rpm = dev_get_drvdata(pdev->dev.parent);
610 + if (!rpm) {
611 + dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
612 + return -ENODEV;
613 + }
614 +
615 + desc = of_device_get_match_data(&pdev->dev);
616 + if (!desc)
617 + return -EINVAL;
618 +
619 + rpm_smd_clks = desc->clks;
620 + num_clks = desc->num_clks;
621 +
622 + rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
623 + GFP_KERNEL);
624 + if (!rcc)
625 + return -ENOMEM;
626 +
627 + hws = rcc->hws;
628 + data = &rcc->data;
629 + data->num = num_clks;
630 +
631 + for (i = 0; i < num_clks; i++) {
632 + if (!rpm_smd_clks[i]) {
633 + continue;
634 + }
635 +
636 + rpm_smd_clks[i]->rpm = rpm;
637 +
638 + ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
639 + if (ret)
640 + goto err;
641 + }
642 +
643 + ret = clk_smd_rpm_enable_scaling(rpm);
644 + if (ret)
645 + goto err;
646 +
647 + for (i = 0; i < num_clks; i++) {
648 + if (!rpm_smd_clks[i]) {
649 + data->hws[i] = ERR_PTR(-ENOENT);
650 + continue;
651 + }
652 +
653 + ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
654 + if (ret)
655 + goto err;
656 + }
657 +
658 + ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
659 + data);
660 + if (ret)
661 + goto err;
662 +
663 + return 0;
664 +err:
665 + dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
666 + return ret;
667 +}
668 +
669 +static int rpm_smd_clk_remove(struct platform_device *pdev)
670 +{
671 + of_clk_del_provider(pdev->dev.of_node);
672 + return 0;
673 +}
674 +
675 +static struct platform_driver rpm_smd_clk_driver = {
676 + .driver = {
677 + .name = "qcom-clk-smd-rpm",
678 + .of_match_table = rpm_smd_clk_match_table,
679 + },
680 + .probe = rpm_smd_clk_probe,
681 + .remove = rpm_smd_clk_remove,
682 +};
683 +
684 +static int __init rpm_smd_clk_init(void)
685 +{
686 + return platform_driver_register(&rpm_smd_clk_driver);
687 +}
688 +core_initcall(rpm_smd_clk_init);
689 +
690 +static void __exit rpm_smd_clk_exit(void)
691 +{
692 + platform_driver_unregister(&rpm_smd_clk_driver);
693 +}
694 +module_exit(rpm_smd_clk_exit);
695 +
696 +MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
697 +MODULE_LICENSE("GPL v2");
698 +MODULE_ALIAS("platform:qcom-clk-smd-rpm");
699 --- /dev/null
700 +++ b/include/dt-bindings/clock/qcom,rpmcc.h
701 @@ -0,0 +1,45 @@
702 +/*
703 + * Copyright 2015 Linaro Limited
704 + *
705 + * This software is licensed under the terms of the GNU General Public
706 + * License version 2, as published by the Free Software Foundation, and
707 + * may be copied, distributed, and modified under those terms.
708 + *
709 + * This program is distributed in the hope that it will be useful,
710 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
711 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
712 + * GNU General Public License for more details.
713 + */
714 +
715 +#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
716 +#define _DT_BINDINGS_CLK_MSM_RPMCC_H
717 +
718 +/* msm8916 */
719 +#define RPM_SMD_XO_CLK_SRC 0
720 +#define RPM_SMD_XO_A_CLK_SRC 1
721 +#define RPM_SMD_PCNOC_CLK 2
722 +#define RPM_SMD_PCNOC_A_CLK 3
723 +#define RPM_SMD_SNOC_CLK 4
724 +#define RPM_SMD_SNOC_A_CLK 5
725 +#define RPM_SMD_BIMC_CLK 6
726 +#define RPM_SMD_BIMC_A_CLK 7
727 +#define RPM_SMD_QDSS_CLK 8
728 +#define RPM_SMD_QDSS_A_CLK 9
729 +#define RPM_SMD_BB_CLK1 10
730 +#define RPM_SMD_BB_CLK1_A 11
731 +#define RPM_SMD_BB_CLK2 12
732 +#define RPM_SMD_BB_CLK2_A 13
733 +#define RPM_SMD_RF_CLK1 14
734 +#define RPM_SMD_RF_CLK1_A 15
735 +#define RPM_SMD_RF_CLK2 16
736 +#define RPM_SMD_RF_CLK2_A 17
737 +#define RPM_SMD_BB_CLK1_PIN 18
738 +#define RPM_SMD_BB_CLK1_A_PIN 19
739 +#define RPM_SMD_BB_CLK2_PIN 20
740 +#define RPM_SMD_BB_CLK2_A_PIN 21
741 +#define RPM_SMD_RF_CLK1_PIN 22
742 +#define RPM_SMD_RF_CLK1_A_PIN 23
743 +#define RPM_SMD_RF_CLK2_PIN 24
744 +#define RPM_SMD_RF_CLK2_A_PIN 25
745 +
746 +#endif