ipq806x: refresh patches
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.9 / 012-2-clk-qcom-Add-support-for-RPM-Clocks.patch
1 From 872f91b5ea720c72f81fb46d353c43ecb3263ffa Mon Sep 17 00:00:00 2001
2 From: Georgi Djakov <georgi.djakov@linaro.org>
3 Date: Wed, 2 Nov 2016 17:56:57 +0200
4 Subject: clk: qcom: Add support for RPM Clocks
5
6 This adds initial support for clocks controlled by the Resource
7 Power Manager (RPM) processor on some Qualcomm SoCs, which use
8 the qcom_rpm driver to communicate with RPM.
9 Such platforms are apq8064 and msm8960.
10
11 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
12 Acked-by: Rob Herring <robh@kernel.org>
13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
14 ---
15 .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
16 drivers/clk/qcom/Kconfig | 13 +
17 drivers/clk/qcom/Makefile | 1 +
18 drivers/clk/qcom/clk-rpm.c | 489 +++++++++++++++++++++
19 include/dt-bindings/clock/qcom,rpmcc.h | 24 +
20 5 files changed, 528 insertions(+)
21 create mode 100644 drivers/clk/qcom/clk-rpm.c
22
23 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
24 +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
25 @@ -11,6 +11,7 @@ Required properties :
26 compatible "qcom,rpmcc" should be also included.
27
28 "qcom,rpmcc-msm8916", "qcom,rpmcc"
29 + "qcom,rpmcc-apq8064", "qcom,rpmcc"
30
31 - #clock-cells : shall contain 1
32
33 --- a/drivers/clk/qcom/Kconfig
34 +++ b/drivers/clk/qcom/Kconfig
35 @@ -12,6 +12,19 @@ config COMMON_CLK_QCOM
36 select REGMAP_MMIO
37 select RESET_CONTROLLER
38
39 +config QCOM_CLK_RPM
40 + tristate "RPM based Clock Controller"
41 + depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
42 + select QCOM_RPMCC
43 + help
44 + The RPM (Resource Power Manager) is a dedicated hardware engine for
45 + managing the shared SoC resources in order to keep the lowest power
46 + profile. It communicates with other hardware subsystems via shared
47 + memory and accepts clock requests, aggregates the requests and turns
48 + the clocks on/off or scales them on demand.
49 + Say Y if you want to support the clocks exposed by the RPM on
50 + platforms such as ipq806x, msm8660, msm8960 etc.
51 +
52 config QCOM_CLK_SMD_RPM
53 tristate "RPM over SMD based Clock Controller"
54 depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
55 --- a/drivers/clk/qcom/Makefile
56 +++ b/drivers/clk/qcom/Makefile
57 @@ -30,3 +30,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8
58 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
59 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
60 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
61 +obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
62 --- /dev/null
63 +++ b/drivers/clk/qcom/clk-rpm.c
64 @@ -0,0 +1,489 @@
65 +/*
66 + * Copyright (c) 2016, Linaro Limited
67 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
68 + *
69 + * This software is licensed under the terms of the GNU General Public
70 + * License version 2, as published by the Free Software Foundation, and
71 + * may be copied, distributed, and modified under those terms.
72 + *
73 + * This program is distributed in the hope that it will be useful,
74 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
75 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
76 + * GNU General Public License for more details.
77 + */
78 +
79 +#include <linux/clk-provider.h>
80 +#include <linux/err.h>
81 +#include <linux/export.h>
82 +#include <linux/init.h>
83 +#include <linux/kernel.h>
84 +#include <linux/module.h>
85 +#include <linux/mutex.h>
86 +#include <linux/mfd/qcom_rpm.h>
87 +#include <linux/of.h>
88 +#include <linux/of_device.h>
89 +#include <linux/platform_device.h>
90 +
91 +#include <dt-bindings/mfd/qcom-rpm.h>
92 +#include <dt-bindings/clock/qcom,rpmcc.h>
93 +
94 +#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
95 +#define QCOM_RPM_SCALING_ENABLE_ID 0x2
96 +
97 +#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
98 + static struct clk_rpm _platform##_##_active; \
99 + static struct clk_rpm _platform##_##_name = { \
100 + .rpm_clk_id = (r_id), \
101 + .peer = &_platform##_##_active, \
102 + .rate = INT_MAX, \
103 + .hw.init = &(struct clk_init_data){ \
104 + .ops = &clk_rpm_ops, \
105 + .name = #_name, \
106 + .parent_names = (const char *[]){ "pxo_board" }, \
107 + .num_parents = 1, \
108 + }, \
109 + }; \
110 + static struct clk_rpm _platform##_##_active = { \
111 + .rpm_clk_id = (r_id), \
112 + .peer = &_platform##_##_name, \
113 + .active_only = true, \
114 + .rate = INT_MAX, \
115 + .hw.init = &(struct clk_init_data){ \
116 + .ops = &clk_rpm_ops, \
117 + .name = #_active, \
118 + .parent_names = (const char *[]){ "pxo_board" }, \
119 + .num_parents = 1, \
120 + }, \
121 + }
122 +
123 +#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
124 + static struct clk_rpm _platform##_##_active; \
125 + static struct clk_rpm _platform##_##_name = { \
126 + .rpm_clk_id = (r_id), \
127 + .active_only = true, \
128 + .peer = &_platform##_##_active, \
129 + .rate = (r), \
130 + .branch = true, \
131 + .hw.init = &(struct clk_init_data){ \
132 + .ops = &clk_rpm_branch_ops, \
133 + .name = #_name, \
134 + .parent_names = (const char *[]){ "pxo_board" }, \
135 + .num_parents = 1, \
136 + }, \
137 + }; \
138 + static struct clk_rpm _platform##_##_active = { \
139 + .rpm_clk_id = (r_id), \
140 + .peer = &_platform##_##_name, \
141 + .rate = (r), \
142 + .branch = true, \
143 + .hw.init = &(struct clk_init_data){ \
144 + .ops = &clk_rpm_branch_ops, \
145 + .name = #_active, \
146 + .parent_names = (const char *[]){ "pxo_board" }, \
147 + .num_parents = 1, \
148 + }, \
149 + }
150 +
151 +#define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \
152 + static struct clk_rpm _platform##_##_active; \
153 + static struct clk_rpm _platform##_##_name = { \
154 + .rpm_clk_id = (r_id), \
155 + .peer = &_platform##_##_active, \
156 + .rate = (r), \
157 + .branch = true, \
158 + .hw.init = &(struct clk_init_data){ \
159 + .ops = &clk_rpm_branch_ops, \
160 + .name = #_name, \
161 + .parent_names = (const char *[]){ "cxo_board" }, \
162 + .num_parents = 1, \
163 + }, \
164 + }; \
165 + static struct clk_rpm _platform##_##_active = { \
166 + .rpm_clk_id = (r_id), \
167 + .active_only = true, \
168 + .peer = &_platform##_##_name, \
169 + .rate = (r), \
170 + .branch = true, \
171 + .hw.init = &(struct clk_init_data){ \
172 + .ops = &clk_rpm_branch_ops, \
173 + .name = #_active, \
174 + .parent_names = (const char *[]){ "cxo_board" }, \
175 + .num_parents = 1, \
176 + }, \
177 + }
178 +
179 +#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
180 +
181 +struct clk_rpm {
182 + const int rpm_clk_id;
183 + const bool active_only;
184 + unsigned long rate;
185 + bool enabled;
186 + bool branch;
187 + struct clk_rpm *peer;
188 + struct clk_hw hw;
189 + struct qcom_rpm *rpm;
190 +};
191 +
192 +struct rpm_cc {
193 + struct qcom_rpm *rpm;
194 + struct clk_hw_onecell_data data;
195 + struct clk_hw *hws[];
196 +};
197 +
198 +struct rpm_clk_desc {
199 + struct clk_rpm **clks;
200 + size_t num_clks;
201 +};
202 +
203 +static DEFINE_MUTEX(rpm_clk_lock);
204 +
205 +static int clk_rpm_handoff(struct clk_rpm *r)
206 +{
207 + int ret;
208 + u32 value = INT_MAX;
209 +
210 + ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
211 + r->rpm_clk_id, &value, 1);
212 + if (ret)
213 + return ret;
214 + ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
215 + r->rpm_clk_id, &value, 1);
216 + if (ret)
217 + return ret;
218 +
219 + return 0;
220 +}
221 +
222 +static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
223 +{
224 + u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
225 +
226 + return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
227 + r->rpm_clk_id, &value, 1);
228 +}
229 +
230 +static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
231 +{
232 + u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
233 +
234 + return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
235 + r->rpm_clk_id, &value, 1);
236 +}
237 +
238 +static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
239 + unsigned long *active, unsigned long *sleep)
240 +{
241 + *active = rate;
242 +
243 + /*
244 + * Active-only clocks don't care what the rate is during sleep. So,
245 + * they vote for zero.
246 + */
247 + if (r->active_only)
248 + *sleep = 0;
249 + else
250 + *sleep = *active;
251 +}
252 +
253 +static int clk_rpm_prepare(struct clk_hw *hw)
254 +{
255 + struct clk_rpm *r = to_clk_rpm(hw);
256 + struct clk_rpm *peer = r->peer;
257 + unsigned long this_rate = 0, this_sleep_rate = 0;
258 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
259 + unsigned long active_rate, sleep_rate;
260 + int ret = 0;
261 +
262 + mutex_lock(&rpm_clk_lock);
263 +
264 + /* Don't send requests to the RPM if the rate has not been set. */
265 + if (!r->rate)
266 + goto out;
267 +
268 + to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
269 +
270 + /* Take peer clock's rate into account only if it's enabled. */
271 + if (peer->enabled)
272 + to_active_sleep(peer, peer->rate,
273 + &peer_rate, &peer_sleep_rate);
274 +
275 + active_rate = max(this_rate, peer_rate);
276 +
277 + if (r->branch)
278 + active_rate = !!active_rate;
279 +
280 + ret = clk_rpm_set_rate_active(r, active_rate);
281 + if (ret)
282 + goto out;
283 +
284 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
285 + if (r->branch)
286 + sleep_rate = !!sleep_rate;
287 +
288 + ret = clk_rpm_set_rate_sleep(r, sleep_rate);
289 + if (ret)
290 + /* Undo the active set vote and restore it */
291 + ret = clk_rpm_set_rate_active(r, peer_rate);
292 +
293 +out:
294 + if (!ret)
295 + r->enabled = true;
296 +
297 + mutex_unlock(&rpm_clk_lock);
298 +
299 + return ret;
300 +}
301 +
302 +static void clk_rpm_unprepare(struct clk_hw *hw)
303 +{
304 + struct clk_rpm *r = to_clk_rpm(hw);
305 + struct clk_rpm *peer = r->peer;
306 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
307 + unsigned long active_rate, sleep_rate;
308 + int ret;
309 +
310 + mutex_lock(&rpm_clk_lock);
311 +
312 + if (!r->rate)
313 + goto out;
314 +
315 + /* Take peer clock's rate into account only if it's enabled. */
316 + if (peer->enabled)
317 + to_active_sleep(peer, peer->rate, &peer_rate,
318 + &peer_sleep_rate);
319 +
320 + active_rate = r->branch ? !!peer_rate : peer_rate;
321 + ret = clk_rpm_set_rate_active(r, active_rate);
322 + if (ret)
323 + goto out;
324 +
325 + sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
326 + ret = clk_rpm_set_rate_sleep(r, sleep_rate);
327 + if (ret)
328 + goto out;
329 +
330 + r->enabled = false;
331 +
332 +out:
333 + mutex_unlock(&rpm_clk_lock);
334 +}
335 +
336 +static int clk_rpm_set_rate(struct clk_hw *hw,
337 + unsigned long rate, unsigned long parent_rate)
338 +{
339 + struct clk_rpm *r = to_clk_rpm(hw);
340 + struct clk_rpm *peer = r->peer;
341 + unsigned long active_rate, sleep_rate;
342 + unsigned long this_rate = 0, this_sleep_rate = 0;
343 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
344 + int ret = 0;
345 +
346 + mutex_lock(&rpm_clk_lock);
347 +
348 + if (!r->enabled)
349 + goto out;
350 +
351 + to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
352 +
353 + /* Take peer clock's rate into account only if it's enabled. */
354 + if (peer->enabled)
355 + to_active_sleep(peer, peer->rate,
356 + &peer_rate, &peer_sleep_rate);
357 +
358 + active_rate = max(this_rate, peer_rate);
359 + ret = clk_rpm_set_rate_active(r, active_rate);
360 + if (ret)
361 + goto out;
362 +
363 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
364 + ret = clk_rpm_set_rate_sleep(r, sleep_rate);
365 + if (ret)
366 + goto out;
367 +
368 + r->rate = rate;
369 +
370 +out:
371 + mutex_unlock(&rpm_clk_lock);
372 +
373 + return ret;
374 +}
375 +
376 +static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
377 + unsigned long *parent_rate)
378 +{
379 + /*
380 + * RPM handles rate rounding and we don't have a way to
381 + * know what the rate will be, so just return whatever
382 + * rate is requested.
383 + */
384 + return rate;
385 +}
386 +
387 +static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
388 + unsigned long parent_rate)
389 +{
390 + struct clk_rpm *r = to_clk_rpm(hw);
391 +
392 + /*
393 + * RPM handles rate rounding and we don't have a way to
394 + * know what the rate will be, so just return whatever
395 + * rate was set.
396 + */
397 + return r->rate;
398 +}
399 +
400 +static const struct clk_ops clk_rpm_ops = {
401 + .prepare = clk_rpm_prepare,
402 + .unprepare = clk_rpm_unprepare,
403 + .set_rate = clk_rpm_set_rate,
404 + .round_rate = clk_rpm_round_rate,
405 + .recalc_rate = clk_rpm_recalc_rate,
406 +};
407 +
408 +static const struct clk_ops clk_rpm_branch_ops = {
409 + .prepare = clk_rpm_prepare,
410 + .unprepare = clk_rpm_unprepare,
411 + .round_rate = clk_rpm_round_rate,
412 + .recalc_rate = clk_rpm_recalc_rate,
413 +};
414 +
415 +/* apq8064 */
416 +DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
417 +DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
418 +DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
419 +DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
420 +DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
421 +DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
422 +DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
423 +DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
424 +DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
425 +
426 +static struct clk_rpm *apq8064_clks[] = {
427 + [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
428 + [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
429 + [RPM_CFPB_CLK] = &apq8064_cfpb_clk,
430 + [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk,
431 + [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk,
432 + [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk,
433 + [RPM_EBI1_CLK] = &apq8064_ebi1_clk,
434 + [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk,
435 + [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk,
436 + [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk,
437 + [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk,
438 + [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk,
439 + [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk,
440 + [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk,
441 + [RPM_SFPB_CLK] = &apq8064_sfpb_clk,
442 + [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk,
443 + [RPM_QDSS_CLK] = &apq8064_qdss_clk,
444 + [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
445 +};
446 +
447 +static const struct rpm_clk_desc rpm_clk_apq8064 = {
448 + .clks = apq8064_clks,
449 + .num_clks = ARRAY_SIZE(apq8064_clks),
450 +};
451 +
452 +static const struct of_device_id rpm_clk_match_table[] = {
453 + { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
454 + { }
455 +};
456 +MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
457 +
458 +static int rpm_clk_probe(struct platform_device *pdev)
459 +{
460 + struct clk_hw **hws;
461 + struct rpm_cc *rcc;
462 + struct clk_hw_onecell_data *data;
463 + int ret;
464 + size_t num_clks, i;
465 + struct qcom_rpm *rpm;
466 + struct clk_rpm **rpm_clks;
467 + const struct rpm_clk_desc *desc;
468 +
469 + rpm = dev_get_drvdata(pdev->dev.parent);
470 + if (!rpm) {
471 + dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
472 + return -ENODEV;
473 + }
474 +
475 + desc = of_device_get_match_data(&pdev->dev);
476 + if (!desc)
477 + return -EINVAL;
478 +
479 + rpm_clks = desc->clks;
480 + num_clks = desc->num_clks;
481 +
482 + rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
483 + GFP_KERNEL);
484 + if (!rcc)
485 + return -ENOMEM;
486 +
487 + hws = rcc->hws;
488 + data = &rcc->data;
489 + data->num = num_clks;
490 +
491 + for (i = 0; i < num_clks; i++) {
492 + if (!rpm_clks[i])
493 + continue;
494 +
495 + rpm_clks[i]->rpm = rpm;
496 +
497 + ret = clk_rpm_handoff(rpm_clks[i]);
498 + if (ret)
499 + goto err;
500 + }
501 +
502 + for (i = 0; i < num_clks; i++) {
503 + if (!rpm_clks[i]) {
504 + data->hws[i] = ERR_PTR(-ENOENT);
505 + continue;
506 + }
507 +
508 + ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
509 + if (ret)
510 + goto err;
511 + }
512 +
513 + ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
514 + data);
515 + if (ret)
516 + goto err;
517 +
518 + return 0;
519 +err:
520 + dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
521 + return ret;
522 +}
523 +
524 +static int rpm_clk_remove(struct platform_device *pdev)
525 +{
526 + of_clk_del_provider(pdev->dev.of_node);
527 + return 0;
528 +}
529 +
530 +static struct platform_driver rpm_clk_driver = {
531 + .driver = {
532 + .name = "qcom-clk-rpm",
533 + .of_match_table = rpm_clk_match_table,
534 + },
535 + .probe = rpm_clk_probe,
536 + .remove = rpm_clk_remove,
537 +};
538 +
539 +static int __init rpm_clk_init(void)
540 +{
541 + return platform_driver_register(&rpm_clk_driver);
542 +}
543 +core_initcall(rpm_clk_init);
544 +
545 +static void __exit rpm_clk_exit(void)
546 +{
547 + platform_driver_unregister(&rpm_clk_driver);
548 +}
549 +module_exit(rpm_clk_exit);
550 +
551 +MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
552 +MODULE_LICENSE("GPL v2");
553 +MODULE_ALIAS("platform:qcom-clk-rpm");
554 --- a/include/dt-bindings/clock/qcom,rpmcc.h
555 +++ b/include/dt-bindings/clock/qcom,rpmcc.h
556 @@ -14,6 +14,30 @@
557 #ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
558 #define _DT_BINDINGS_CLK_MSM_RPMCC_H
559
560 +/* apq8064 */
561 +#define RPM_PXO_CLK 0
562 +#define RPM_PXO_A_CLK 1
563 +#define RPM_CXO_CLK 2
564 +#define RPM_CXO_A_CLK 3
565 +#define RPM_APPS_FABRIC_CLK 4
566 +#define RPM_APPS_FABRIC_A_CLK 5
567 +#define RPM_CFPB_CLK 6
568 +#define RPM_CFPB_A_CLK 7
569 +#define RPM_QDSS_CLK 8
570 +#define RPM_QDSS_A_CLK 9
571 +#define RPM_DAYTONA_FABRIC_CLK 10
572 +#define RPM_DAYTONA_FABRIC_A_CLK 11
573 +#define RPM_EBI1_CLK 12
574 +#define RPM_EBI1_A_CLK 13
575 +#define RPM_MM_FABRIC_CLK 14
576 +#define RPM_MM_FABRIC_A_CLK 15
577 +#define RPM_MMFPB_CLK 16
578 +#define RPM_MMFPB_A_CLK 17
579 +#define RPM_SYS_FABRIC_CLK 18
580 +#define RPM_SYS_FABRIC_A_CLK 19
581 +#define RPM_SFPB_CLK 20
582 +#define RPM_SFPB_A_CLK 21
583 +
584 /* msm8916 */
585 #define RPM_SMD_XO_CLK_SRC 0
586 #define RPM_SMD_XO_A_CLK_SRC 1