kernel: update 4.9 to 4.9.50
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.9 / 860-qcom-mtd-nand-Add-bam_dma-support-in-qcom_nand-drive.patch
1 From 074036f9de6b8c5fc642e8e2540950f6a35aa804 Mon Sep 17 00:00:00 2001
2 From: Ram Chandra Jangir <rjangir@codeaurora.org>
3 Date: Thu, 20 Apr 2017 10:31:10 +0530
4 Subject: [PATCH] qcom: mtd: nand: Add bam_dma support in qcom_nand driver
5
6 The current driver only support ADM DMA so this patch adds the
7 BAM DMA support in current NAND driver with compatible string
8 qcom,ebi2-nandc-bam.
9 Added bam channels and data buffers, NAND BAM uses 3 channels:
10 command, data tx and data rx, while ADM uses only single channel.
11 So this patch adds the BAM channel in device tree and using the
12 same in NAND driver allocation function.
13
14 Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
15 ---
16 .../devicetree/bindings/mtd/qcom_nandc.txt | 69 +++++++--
17 drivers/mtd/nand/qcom_nandc.c | 160 +++++++++++++++++----
18 2 files changed, 190 insertions(+), 39 deletions(-)
19
20 --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
21 +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
22 @@ -1,21 +1,26 @@
23 * Qualcomm NAND controller
24
25 Required properties:
26 -- compatible: should be "qcom,ipq806x-nand"
27 +- compatible: "qcom,ipq806x-nand" for IPQ8064 which uses
28 + ADM DMA.
29 + "qcom,ebi2-nand-bam" - nand drivers using BAM DMA
30 + like IPQ4019.
31 - reg: MMIO address range
32 - clocks: must contain core clock and always on clock
33 - clock-names: must contain "core" for the core clock and "aon" for the
34 always on clock
35 - dmas: DMA specifier, consisting of a phandle to the ADM DMA
36 - controller node and the channel number to be used for
37 - NAND. Refer to dma.txt and qcom_adm.txt for more details
38 -- dma-names: must be "rxtx"
39 -- qcom,cmd-crci: must contain the ADM command type CRCI block instance
40 - number specified for the NAND controller on the given
41 - platform
42 -- qcom,data-crci: must contain the ADM data type CRCI block instance
43 - number specified for the NAND controller on the given
44 - platform
45 + or BAM DMA controller node and the channel number to
46 + be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
47 + and qcom_bam_dma.txt(BAM) for more details
48 +- dma-names: "rxtx" - ADM
49 + "tx", "rx", "cmd" - BAM
50 +- qcom,cmd-crci: Only required for ADM DMA. must contain the ADM command
51 + type CRCI block instance number specified for the NAND
52 + controller on the given platform.
53 +- qcom,data-crci: Only required for ADM DMA. must contain the ADM data
54 + type CRCI block instance number specified for the NAND
55 + controller on the given platform.
56 - #address-cells: <1> - subnodes give the chip-select number
57 - #size-cells: <0>
58
59 @@ -44,7 +49,7 @@ partition.txt for more detail.
60 Example:
61
62 nand@1ac00000 {
63 - compatible = "qcom,ebi2-nandc";
64 + compatible = "qcom,ipq806x-nand","qcom.qcom_nand";
65 reg = <0x1ac00000 0x800>;
66
67 clocks = <&gcc EBI2_CLK>,
68 @@ -58,6 +63,48 @@ nand@1ac00000 {
69
70 #address-cells = <1>;
71 #size-cells = <0>;
72 +
73 + nandcs@0 {
74 + compatible = "qcom,nandcs";
75 + reg = <0>;
76 +
77 + nand-ecc-strength = <4>;
78 + nand-ecc-step-size = <512>;
79 + nand-bus-width = <8>;
80 +
81 + partitions {
82 + compatible = "fixed-partitions";
83 + #address-cells = <1>;
84 + #size-cells = <1>;
85 +
86 + partition@0 {
87 + label = "boot-nand";
88 + reg = <0 0x58a0000>;
89 + };
90 +
91 + partition@58a0000 {
92 + label = "fs-nand";
93 + reg = <0x58a0000 0x4000000>;
94 + };
95 + };
96 + };
97 +};
98 +
99 +nand@79B0000 {
100 + compatible = "qcom,ebi2-nandc-bam";
101 + reg = <0x79B0000 0x1000>;
102 +
103 + clocks = <&gcc EBI2_CLK>,
104 + <&gcc EBI2_AON_CLK>;
105 + clock-names = "core", "aon";
106 +
107 + dmas = <&qpicbam 0>,
108 + <&qpicbam 1>,
109 + <&qpicbam 2>;
110 + dma-names = "tx", "rx", "cmd";
111 +
112 + #address-cells = <1>;
113 + #size-cells = <0>;
114
115 nandcs@0 {
116 compatible = "qcom,nandcs";
117 --- a/drivers/mtd/nand/qcom_nandc.c
118 +++ b/drivers/mtd/nand/qcom_nandc.c
119 @@ -234,6 +234,7 @@ struct nandc_regs {
120 * by upper layers directly
121 * @buf_size/count/start: markers for chip->read_buf/write_buf functions
122 * @reg_read_buf: local buffer for reading back registers via DMA
123 + * @reg_read_buf_phys: contains dma address for register read buffer
124 * @reg_read_pos: marker for data read in reg_read_buf
125 *
126 * @regs: a contiguous chunk of memory for DMA register
127 @@ -242,7 +243,10 @@ struct nandc_regs {
128 * @cmd1/vld: some fixed controller register values
129 * @ecc_modes: supported ECC modes by the current controller,
130 * initialized via DT match data
131 - */
132 + * @bch_enabled: flag to tell whether BCH or RS ECC mode is used
133 + * @dma_bam_enabled: flag to tell whether nand controller is using
134 + * bam dma
135 +*/
136 struct qcom_nand_controller {
137 struct nand_hw_control controller;
138 struct list_head host_list;
139 @@ -255,17 +259,28 @@ struct qcom_nand_controller {
140 struct clk *core_clk;
141 struct clk *aon_clk;
142
143 - struct dma_chan *chan;
144 - unsigned int cmd_crci;
145 - unsigned int data_crci;
146 struct list_head desc_list;
147 + union {
148 + struct {
149 + struct dma_chan *tx_chan;
150 + struct dma_chan *rx_chan;
151 + struct dma_chan *cmd_chan;
152 + };
153 + struct {
154 + struct dma_chan *chan;
155 + unsigned int cmd_crci;
156 + unsigned int data_crci;
157 + };
158 + };
159
160 u8 *data_buffer;
161 + bool dma_bam_enabled;
162 int buf_size;
163 int buf_count;
164 int buf_start;
165
166 __le32 *reg_read_buf;
167 + dma_addr_t reg_read_buf_phys;
168 int reg_read_pos;
169
170 struct nandc_regs *regs;
171 @@ -324,6 +339,17 @@ struct qcom_nand_host {
172 u32 clrreadstatus;
173 };
174
175 +/*
176 + * This data type corresponds to the nand driver data which will be used at
177 + * driver probe time
178 + * @ecc_modes - ecc mode for nand
179 + * @dma_bam_enabled - whether this driver is using bam
180 + */
181 +struct qcom_nand_driver_data {
182 + u32 ecc_modes;
183 + bool dma_bam_enabled;
184 +};
185 +
186 static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
187 {
188 return container_of(chip, struct qcom_nand_host, chip);
189 @@ -1949,16 +1975,46 @@ static int qcom_nandc_alloc(struct qcom_
190 if (!nandc->regs)
191 return -ENOMEM;
192
193 - nandc->reg_read_buf = devm_kzalloc(nandc->dev,
194 - MAX_REG_RD * sizeof(*nandc->reg_read_buf),
195 - GFP_KERNEL);
196 - if (!nandc->reg_read_buf)
197 - return -ENOMEM;
198 + if (!nandc->dma_bam_enabled) {
199 + nandc->reg_read_buf = devm_kzalloc(nandc->dev,
200 + MAX_REG_RD *
201 + sizeof(*nandc->reg_read_buf),
202 + GFP_KERNEL);
203
204 - nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
205 - if (!nandc->chan) {
206 - dev_err(nandc->dev, "failed to request slave channel\n");
207 - return -ENODEV;
208 + if (!nandc->reg_read_buf)
209 + return -ENOMEM;
210 +
211 + nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
212 + if (!nandc->chan) {
213 + dev_err(nandc->dev, "failed to request slave channel\n");
214 + return -ENODEV;
215 + }
216 + } else {
217 + nandc->reg_read_buf = dmam_alloc_coherent(nandc->dev,
218 + MAX_REG_RD *
219 + sizeof(*nandc->reg_read_buf),
220 + &nandc->reg_read_buf_phys, GFP_KERNEL);
221 +
222 + if (!nandc->reg_read_buf)
223 + return -ENOMEM;
224 +
225 + nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
226 + if (!nandc->tx_chan) {
227 + dev_err(nandc->dev, "failed to request tx channel\n");
228 + return -ENODEV;
229 + }
230 +
231 + nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
232 + if (!nandc->rx_chan) {
233 + dev_err(nandc->dev, "failed to request rx channel\n");
234 + return -ENODEV;
235 + }
236 +
237 + nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
238 + if (!nandc->cmd_chan) {
239 + dev_err(nandc->dev, "failed to request cmd channel\n");
240 + return -ENODEV;
241 + }
242 }
243
244 INIT_LIST_HEAD(&nandc->desc_list);
245 @@ -1971,8 +2027,35 @@ static int qcom_nandc_alloc(struct qcom_
246
247 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
248 {
249 - dma_release_channel(nandc->chan);
250 -}
251 + if (nandc->dma_bam_enabled) {
252 + if (nandc->tx_chan)
253 + dma_release_channel(nandc->tx_chan);
254 +
255 + if (nandc->rx_chan)
256 + dma_release_channel(nandc->rx_chan);
257 +
258 + if (nandc->cmd_chan)
259 + dma_release_channel(nandc->tx_chan);
260 +
261 + if (nandc->reg_read_buf)
262 + dmam_free_coherent(nandc->dev, MAX_REG_RD *
263 + sizeof(*nandc->reg_read_buf),
264 + nandc->reg_read_buf,
265 + nandc->reg_read_buf_phys);
266 + } else {
267 + if (nandc->chan)
268 + dma_release_channel(nandc->chan);
269 +
270 + if (nandc->reg_read_buf)
271 + devm_kfree(nandc->dev, nandc->reg_read_buf);
272 + }
273 +
274 + if (nandc->regs)
275 + devm_kfree(nandc->dev, nandc->regs);
276 +
277 + if (nandc->data_buffer)
278 + devm_kfree(nandc->dev, nandc->data_buffer);
279 + }
280
281 /* one time setup of a few nand controller registers */
282 static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
283 @@ -2010,6 +2093,8 @@ static int qcom_nand_host_init(struct qc
284 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs);
285 mtd->owner = THIS_MODULE;
286 mtd->dev.parent = dev;
287 + mtd->priv = chip;
288 + chip->priv = nandc;
289
290 chip->cmdfunc = qcom_nandc_command;
291 chip->select_chip = qcom_nandc_select_chip;
292 @@ -2057,16 +2142,20 @@ static int qcom_nandc_parse_dt(struct pl
293 struct device_node *np = nandc->dev->of_node;
294 int ret;
295
296 - ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
297 - if (ret) {
298 - dev_err(nandc->dev, "command CRCI unspecified\n");
299 - return ret;
300 - }
301 + if (!nandc->dma_bam_enabled) {
302 + ret = of_property_read_u32(np, "qcom,cmd-crci",
303 + &nandc->cmd_crci);
304 + if (ret) {
305 + dev_err(nandc->dev, "command CRCI unspecified\n");
306 + return ret;
307 + }
308
309 - ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
310 - if (ret) {
311 - dev_err(nandc->dev, "data CRCI unspecified\n");
312 - return ret;
313 + ret = of_property_read_u32(np, "qcom,data-crci",
314 + &nandc->data_crci);
315 + if (ret) {
316 + dev_err(nandc->dev, "data CRCI unspecified\n");
317 + return ret;
318 + }
319 }
320
321 return 0;
322 @@ -2081,6 +2170,7 @@ static int qcom_nandc_probe(struct platf
323 struct device_node *dn = dev->of_node, *child;
324 struct resource *res;
325 int ret;
326 + struct qcom_nand_driver_data *driver_data;
327
328 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
329 if (!nandc)
330 @@ -2095,7 +2185,10 @@ static int qcom_nandc_probe(struct platf
331 return -ENODEV;
332 }
333
334 - nandc->ecc_modes = (unsigned long)dev_data;
335 + driver_data = (struct qcom_nand_driver_data *)dev_data;
336 +
337 + nandc->ecc_modes = driver_data->ecc_modes;
338 + nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
339
340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
341 nandc->base = devm_ioremap_resource(dev, res);
342 @@ -2187,7 +2280,15 @@ static int qcom_nandc_remove(struct plat
343 return 0;
344 }
345
346 -#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
347 +struct qcom_nand_driver_data ebi2_nandc_bam_data = {
348 + .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
349 + .dma_bam_enabled = true,
350 +};
351 +
352 +struct qcom_nand_driver_data ebi2_nandc_data = {
353 + .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
354 + .dma_bam_enabled = false,
355 +};
356
357 /*
358 * data will hold a struct pointer containing more differences once we support
359 @@ -2195,7 +2296,10 @@ static int qcom_nandc_remove(struct plat
360 */
361 static const struct of_device_id qcom_nandc_of_match[] = {
362 { .compatible = "qcom,ipq806x-nand",
363 - .data = (void *)EBI2_NANDC_ECC_MODES,
364 + .data = (void *) &ebi2_nandc_data,
365 + },
366 + { .compatible = "qcom,ebi2-nandc-bam",
367 + .data = (void *) &ebi2_nandc_bam_data,
368 },
369 {}
370 };