projects / openwrt / openwrt.git / blob
? search:


ff970ea0ece21902c4ad57007bca4eff1b4de58b
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.9 / 999-dts.patch
1 --- a/arch/arm/boot/dts/Makefile
2 +++ b/arch/arm/boot/dts/Makefile
3 @@ -619,6 +619,14 @@ dtb-$(CONFIG_ARCH_QCOM) += \
4 qcom-ipq4019-ap.dk01.1-c1.dtb \
5 qcom-ipq4019-ap.dk04.1-c1.dtb \
6 qcom-ipq8064-ap148.dtb \
7 + qcom-ipq8064-c2600.dtb \
8 + qcom-ipq8064-d7800.dtb \
9 + qcom-ipq8064-db149.dtb \
10 + qcom-ipq8064-ea8500.dtb \
11 + qcom-ipq8064-r7500.dtb \
12 + qcom-ipq8064-r7500v2.dtb \
13 + qcom-ipq8065-nbg6817.dtb \
14 + qcom-ipq8065-r7800.dtb \
15 qcom-msm8660-surf.dtb \
16 qcom-msm8960-cdp.dtb \
17 qcom-msm8974-lge-nexus5-hammerhead.dtb \
18 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
19 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
20 @@ -60,6 +60,25 @@
21 bias-bus-hold;
22 };
23 };
24 +
25 + mdio0_pins: mdio0_pins {
26 + mux {
27 + pins = "gpio0", "gpio1";
28 + function = "gpio";
29 + drive-strength = <8>;
30 + bias-disable;
31 + };
32 + };
33 +
34 + rgmii2_pins: rgmii2_pins {
35 + mux {
36 + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
37 + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
38 + function = "rgmii2";
39 + drive-strength = <8>;
40 + bias-disable;
41 + };
42 + };
43 };
44
45 gsbi@16300000 {
46 @@ -69,14 +88,12 @@
47 status = "ok";
48 };
49
50 - i2c4: i2c@16380000 {
51 - status = "ok";
52 -
53 - clock-frequency = <200000>;
54 -
55 - pinctrl-0 = <&i2c4_pins>;
56 - pinctrl-names = "default";
57 - };
58 + /*
59 + * The i2c device on gsbi4 should not be enabled.
60 + * On ipq806x designs gsbi4 i2c is meant for exclusive
61 + * RPM usage. Turning this on in kernel manifests as
62 + * i2c failure for the RPM.
63 + */
64 };
65
66 gsbi5: gsbi@1a200000 {
67 @@ -99,15 +116,7 @@
68 spi-max-frequency = <50000000>;
69 reg = <0>;
70
71 - partition@0 {
72 - label = "rootfs";
73 - reg = <0x0 0x1000000>;
74 - };
75 -
76 - partition@1 {
77 - label = "scratch";
78 - reg = <0x1000000 0x1000000>;
79 - };
80 + linux,part-probe = "qcom-smem";
81 };
82 };
83 };
84 @@ -121,19 +130,102 @@
85 status = "ok";
86 };
87
88 + phy@100f8800 { /* USB3 port 1 HS phy */
89 + status = "ok";
90 + };
91 +
92 + phy@100f8830 { /* USB3 port 1 SS phy */
93 + status = "ok";
94 + };
95 +
96 + phy@110f8800 { /* USB3 port 0 HS phy */
97 + status = "ok";
98 + };
99 +
100 + phy@110f8830 { /* USB3 port 0 SS phy */
101 + status = "ok";
102 + };
103 +
104 + usb30@0 {
105 + status = "ok";
106 + };
107 +
108 + usb30@1 {
109 + status = "ok";
110 + };
111 +
112 + pcie0: pci@1b500000 {
113 + status = "ok";
114 + phy-tx0-term-offset = <7>;
115 + };
116 +
117 + pcie1: pci@1b700000 {
118 + status = "ok";
119 + phy-tx0-term-offset = <7>;
120 + };
121 +
122 nand@1ac00000 {
123 status = "ok";
124
125 pinctrl-0 = <&nand_pins>;
126 pinctrl-names = "default";
127
128 - nandcs@0 {
129 - compatible = "qcom,nandcs";
130 + nand-ecc-strength = <4>;
131 + nand-bus-width = <8>;
132 +
133 + linux,part-probe = "qcom-smem";
134 + };
135 +
136 + mdio0: mdio {
137 + compatible = "virtual,mdio-gpio";
138 + #address-cells = <1>;
139 + #size-cells = <0>;
140 + gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>;
141 + pinctrl-0 = <&mdio0_pins>;
142 + pinctrl-names = "default";
143 +
144 + phy0: ethernet-phy@0 {
145 + device_type = "ethernet-phy";
146 reg = <0>;
147 + qca,ar8327-initvals = <
148 + 0x00004 0x7600000 /* PAD0_MODE */
149 + 0x00008 0x1000000 /* PAD5_MODE */
150 + 0x0000c 0x80 /* PAD6_MODE */
151 + 0x000e4 0x6a545 /* MAC_POWER_SEL */
152 + 0x000e0 0xc74164de /* SGMII_CTRL */
153 + 0x0007c 0x4e /* PORT0_STATUS */
154 + 0x00094 0x4e /* PORT6_STATUS */
155 + >;
156 + };
157
158 - nand-ecc-strength = <4>;
159 - nand-ecc-step-size = <512>;
160 - nand-bus-width = <8>;
161 + phy4: ethernet-phy@4 {
162 + device_type = "ethernet-phy";
163 + reg = <4>;
164 + };
165 + };
166 +
167 + gmac1: ethernet@37200000 {
168 + status = "ok";
169 + phy-mode = "rgmii";
170 + qcom,id = <1>;
171 +
172 + pinctrl-0 = <&rgmii2_pins>;
173 + pinctrl-names = "default";
174 +
175 + fixed-link {
176 + speed = <1000>;
177 + full-duplex;
178 + };
179 + };
180 +
181 + gmac2: ethernet@37400000 {
182 + status = "ok";
183 + phy-mode = "sgmii";
184 + qcom,id = <2>;
185 +
186 + fixed-link {
187 + speed = <1000>;
188 + full-duplex;
189 };
190 };
191 };
192 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
193 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
194 @@ -1,11 +1,13 @@
195 /dts-v1/;
196
197 #include "skeleton.dtsi"
198 -#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
199 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
200 +#include <dt-bindings/mfd/qcom-rpm.h>
201 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
202 #include <dt-bindings/soc/qcom,gsbi.h>
203 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
204 #include <dt-bindings/interrupt-controller/arm-gic.h>
205 +#include <dt-bindings/gpio/gpio.h>
206
207 / {
208 model = "Qualcomm IPQ8064";
209 @@ -16,7 +18,7 @@
210 #address-cells = <1>;
211 #size-cells = <0>;
212
213 - cpu@0 {
214 + cpu0: cpu@0 {
215 compatible = "qcom,krait";
216 enable-method = "qcom,kpss-acc-v1";
217 device_type = "cpu";
218 @@ -24,9 +26,18 @@
219 next-level-cache = <&L2>;
220 qcom,acc = <&acc0>;
221 qcom,saw = <&saw0>;
222 + clocks = <&kraitcc 0>, <&kraitcc 4>;
223 + clock-names = "cpu", "l2";
224 + clock-latency = <100000>;
225 + cpu-supply = <&smb208_s2a>;
226 + voltage-tolerance = <5>;
227 + cooling-min-state = <0>;
228 + cooling-max-state = <10>;
229 + #cooling-cells = <2>;
230 + cpu-idle-states = <&CPU_SPC>;
231 };
232
233 - cpu@1 {
234 + cpu1: cpu@1 {
235 compatible = "qcom,krait";
236 enable-method = "qcom,kpss-acc-v1";
237 device_type = "cpu";
238 @@ -34,11 +45,120 @@
239 next-level-cache = <&L2>;
240 qcom,acc = <&acc1>;
241 qcom,saw = <&saw1>;
242 + clocks = <&kraitcc 1>, <&kraitcc 4>;
243 + clock-names = "cpu", "l2";
244 + clock-latency = <100000>;
245 + cpu-supply = <&smb208_s2b>;
246 + cooling-min-state = <0>;
247 + cooling-max-state = <10>;
248 + #cooling-cells = <2>;
249 + cpu-idle-states = <&CPU_SPC>;
250 };
251
252 L2: l2-cache {
253 compatible = "cache";
254 cache-level = <2>;
255 + qcom,saw = <&saw_l2>;
256 + };
257 +
258 + qcom,l2 {
259 + qcom,l2-rates = <384000000 1000000000 1200000000>;
260 + };
261 +
262 + idle-states {
263 + CPU_SPC: spc {
264 + compatible = "qcom,idle-state-spc",
265 + "arm,idle-state";
266 + entry-latency-us = <400>;
267 + exit-latency-us = <900>;
268 + min-residency-us = <3000>;
269 + };
270 + };
271 + };
272 +
273 + thermal-zones {
274 + cpu-thermal0 {
275 + polling-delay-passive = <250>;
276 + polling-delay = <1000>;
277 +
278 + thermal-sensors = <&gcc 5>;
279 + coefficients = <1132 0>;
280 +
281 + trips {
282 + cpu_alert0: trip0 {
283 + temperature = <75000>;
284 + hysteresis = <2000>;
285 + type = "passive";
286 + };
287 + cpu_crit0: trip1 {
288 + temperature = <110000>;
289 + hysteresis = <2000>;
290 + type = "critical";
291 + };
292 + };
293 + };
294 +
295 + cpu-thermal1 {
296 + polling-delay-passive = <250>;
297 + polling-delay = <1000>;
298 +
299 + thermal-sensors = <&gcc 6>;
300 + coefficients = <1132 0>;
301 +
302 + trips {
303 + cpu_alert1: trip0 {
304 + temperature = <75000>;
305 + hysteresis = <2000>;
306 + type = "passive";
307 + };
308 + cpu_crit1: trip1 {
309 + temperature = <110000>;
310 + hysteresis = <2000>;
311 + type = "critical";
312 + };
313 + };
314 + };
315 +
316 + cpu-thermal2 {
317 + polling-delay-passive = <250>;
318 + polling-delay = <1000>;
319 +
320 + thermal-sensors = <&gcc 7>;
321 + coefficients = <1199 0>;
322 +
323 + trips {
324 + cpu_alert2: trip0 {
325 + temperature = <75000>;
326 + hysteresis = <2000>;
327 + type = "passive";
328 + };
329 + cpu_crit2: trip1 {
330 + temperature = <110000>;
331 + hysteresis = <2000>;
332 + type = "critical";
333 + };
334 + };
335 + };
336 +
337 + cpu-thermal3 {
338 + polling-delay-passive = <250>;
339 + polling-delay = <1000>;
340 +
341 + thermal-sensors = <&gcc 8>;
342 + coefficients = <1132 0>;
343 +
344 + trips {
345 + cpu_alert3: trip0 {
346 + temperature = <75000>;
347 + hysteresis = <2000>;
348 + type = "passive";
349 + };
350 + cpu_crit3: trip1 {
351 + temperature = <110000>;
352 + hysteresis = <2000>;
353 + type = "critical";
354 + };
355 + };
356 };
357 };
358
359 @@ -57,7 +177,7 @@
360 no-map;
361 };
362
363 - smem@41000000 {
364 + smem: smem@41000000 {
365 reg = <0x41000000 0x200000>;
366 no-map;
367 };
368 @@ -67,13 +187,13 @@
369 cxo_board {
370 compatible = "fixed-clock";
371 #clock-cells = <0>;
372 - clock-frequency = <19200000>;
373 + clock-frequency = <25000000>;
374 };
375
376 pxo_board {
377 compatible = "fixed-clock";
378 #clock-cells = <0>;
379 - clock-frequency = <27000000>;
380 + clock-frequency = <25000000>;
381 };
382
383 sleep_clk: sleep_clk {
384 @@ -83,6 +203,46 @@
385 };
386 };
387
388 + kraitcc: clock-controller {
389 + compatible = "qcom,krait-cc-v1";
390 + #clock-cells = <1>;
391 + };
392 +
393 + qcom,pvs {
394 + qcom,pvs-format-a;
395 + qcom,speed0-pvs0-bin-v0 =
396 + < 1400000000 1250000 >,
397 + < 1200000000 1200000 >,
398 + < 1000000000 1150000 >,
399 + < 800000000 1100000 >,
400 + < 600000000 1050000 >,
401 + < 384000000 1000000 >;
402 +
403 + qcom,speed0-pvs1-bin-v0 =
404 + < 1400000000 1175000 >,
405 + < 1200000000 1125000 >,
406 + < 1000000000 1075000 >,
407 + < 800000000 1025000 >,
408 + < 600000000 975000 >,
409 + < 384000000 925000 >;
410 +
411 + qcom,speed0-pvs2-bin-v0 =
412 + < 1400000000 1125000 >,
413 + < 1200000000 1075000 >,
414 + < 1000000000 1025000 >,
415 + < 800000000 995000 >,
416 + < 600000000 925000 >,
417 + < 384000000 875000 >;
418 +
419 + qcom,speed0-pvs3-bin-v0 =
420 + < 1400000000 1050000 >,
421 + < 1200000000 1000000 >,
422 + < 1000000000 950000 >,
423 + < 800000000 900000 >,
424 + < 600000000 850000 >,
425 + < 384000000 800000 >;
426 + };
427 +
428 soc: soc {
429 #address-cells = <1>;
430 #size-cells = <1>;
431 @@ -104,6 +264,85 @@
432 reg-names = "lpass-lpaif";
433 };
434
435 + qfprom: qfprom@700000 {
436 + compatible = "qcom,qfprom", "syscon";
437 + reg = <0x00700000 0x1000>;
438 + #address-cells = <1>;
439 + #size-cells = <1>;
440 + ranges;
441 +
442 + tsens_calib: calib {
443 + reg = <0x400 0x10>;
444 + };
445 + tsens_backup: backup_calib {
446 + reg = <0x410 0x10>;
447 + };
448 + };
449 +
450 + rpm@108000 {
451 + compatible = "qcom,rpm-ipq8064";
452 + reg = <0x108000 0x1000>;
453 + qcom,ipc = <&l2cc 0x8 2>;
454 +
455 + interrupts = <0 19 0>,
456 + <0 21 0>,
457 + <0 22 0>;
458 + interrupt-names = "ack",
459 + "err",
460 + "wakeup";
461 +
462 + clocks = <&gcc RPM_MSG_RAM_H_CLK>;
463 + clock-names = "ram";
464 +
465 + #address-cells = <1>;
466 + #size-cells = <0>;
467 +
468 + rpmcc: clock-controller {
469 + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
470 + #clock-cells = <1>;
471 + };
472 +
473 + regulators {
474 + compatible = "qcom,rpm-smb208-regulators";
475 +
476 + smb208_s1a: s1a {
477 + regulator-min-microvolt = <1050000>;
478 + regulator-max-microvolt = <1150000>;
479 +
480 + qcom,switch-mode-frequency = <1200000>;
481 +
482 + };
483 +
484 + smb208_s1b: s1b {
485 + regulator-min-microvolt = <1050000>;
486 + regulator-max-microvolt = <1150000>;
487 +
488 + qcom,switch-mode-frequency = <1200000>;
489 + };
490 +
491 + smb208_s2a: s2a {
492 + regulator-min-microvolt = < 800000>;
493 + regulator-max-microvolt = <1250000>;
494 +
495 + qcom,switch-mode-frequency = <1200000>;
496 + };
497 +
498 + smb208_s2b: s2b {
499 + regulator-min-microvolt = < 800000>;
500 + regulator-max-microvolt = <1250000>;
501 +
502 + qcom,switch-mode-frequency = <1200000>;
503 + };
504 + };
505 + };
506 +
507 + rng@1a500000 {
508 + compatible = "qcom,prng";
509 + reg = <0x1a500000 0x200>;
510 + clocks = <&gcc PRNG_CLK>;
511 + clock-names = "core";
512 + };
513 +
514 qcom_pinmux: pinmux@800000 {
515 compatible = "qcom,ipq8064-pinctrl";
516 reg = <0x800000 0x4000>;
517 @@ -113,6 +352,34 @@
518 interrupt-controller;
519 #interrupt-cells = <2>;
520 interrupts = <0 16 0x4>;
521 +
522 + pcie0_pins: pcie0_pinmux {
523 + mux {
524 + pins = "gpio3";
525 + function = "pcie1_rst";
526 + drive-strength = <2>;
527 + bias-disable;
528 + };
529 + };
530 +
531 + pcie1_pins: pcie1_pinmux {
532 + mux {
533 + pins = "gpio48";
534 + function = "pcie2_rst";
535 + drive-strength = <2>;
536 + bias-disable;
537 + };
538 + };
539 +
540 + pcie2_pins: pcie2_pinmux {
541 + mux {
542 + pins = "gpio63";
543 + function = "pcie3_rst";
544 + drive-strength = <2>;
545 + bias-disable;
546 + output-low;
547 + };
548 + };
549 };
550
551 intc: interrupt-controller@2000000 {
552 @@ -124,8 +391,7 @@
553 };
554
555 timer@200a000 {
556 - compatible = "qcom,kpss-timer",
557 - "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
558 + compatible = "qcom,kpss-timer", "qcom,msm-timer";
559 interrupts = <1 1 0x301>,
560 <1 2 0x301>,
561 <1 3 0x301>,
562 @@ -142,25 +408,44 @@
563 acc0: clock-controller@2088000 {
564 compatible = "qcom,kpss-acc-v1";
565 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
566 + clock-output-names = "acpu0_aux";
567 };
568
569 acc1: clock-controller@2098000 {
570 compatible = "qcom,kpss-acc-v1";
571 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
572 + clock-output-names = "acpu1_aux";
573 };
574
575 + l2cc: clock-controller@2011000 {
576 + compatible = "qcom,kpss-gcc", "syscon";
577 + reg = <0x2011000 0x1000>;
578 + clock-output-names = "acpu_l2_aux";
579 + };
580 +
581 saw0: regulator@2089000 {
582 - compatible = "qcom,saw2";
583 + compatible = "qcom,saw2", "syscon";
584 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
585 regulator;
586 };
587
588 saw1: regulator@2099000 {
589 - compatible = "qcom,saw2";
590 + compatible = "qcom,saw2", "syscon";
591 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
592 regulator;
593 };
594
595 + saw_l2: regulator@02012000 {
596 + compatible = "qcom,saw2", "syscon";
597 + reg = <0x02012000 0x1000>;
598 + regulator;
599 + };
600 +
601 + sic_non_secure: sic-non-secure@12100000 {
602 + compatible = "syscon";
603 + reg = <0x12100000 0x10000>;
604 + };
605 +
606 gsbi2: gsbi@12480000 {
607 compatible = "qcom,gsbi-v1.0.0";
608 cell-index = <2>;
609 @@ -328,8 +613,12 @@
610 gcc: clock-controller@900000 {
611 compatible = "qcom,gcc-ipq8064";
612 reg = <0x00900000 0x4000>;
613 + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
614 + nvmem-cell-names = "calib", "calib_backup";
615 #clock-cells = <1>;
616 #reset-cells = <1>;
617 + #power-domain-cells = <1>;
618 + #thermal-sensor-cells = <1>;
619 };
620
621 tcsr: syscon@1a400000 {
622 @@ -344,10 +633,259 @@
623 #reset-cells = <1>;
624 };
625
626 + sfpb_mutex_block: syscon@1200600 {
627 + compatible = "syscon";
628 + reg = <0x01200600 0x100>;
629 + };
630 +
631 + hs_phy_1: phy@100f8800 {
632 + compatible = "qcom,dwc3-hs-usb-phy";
633 + reg = <0x100f8800 0x30>;
634 + clocks = <&gcc USB30_1_UTMI_CLK>;
635 + clock-names = "ref";
636 + #phy-cells = <0>;
637 +
638 + status = "disabled";
639 + };
640 +
641 + ss_phy_1: phy@100f8830 {
642 + compatible = "qcom,dwc3-ss-usb-phy";
643 + reg = <0x100f8830 0x30>;
644 + clocks = <&gcc USB30_1_MASTER_CLK>;
645 + clock-names = "ref";
646 + #phy-cells = <0>;
647 +
648 + status = "disabled";
649 + };
650 +
651 + hs_phy_0: phy@110f8800 {
652 + compatible = "qcom,dwc3-hs-usb-phy";
653 + reg = <0x110f8800 0x30>;
654 + clocks = <&gcc USB30_0_UTMI_CLK>;
655 + clock-names = "ref";
656 + #phy-cells = <0>;
657 +
658 + status = "disabled";
659 + };
660 +
661 + ss_phy_0: phy@110f8830 {
662 + compatible = "qcom,dwc3-ss-usb-phy";
663 + reg = <0x110f8830 0x30>;
664 + clocks = <&gcc USB30_0_MASTER_CLK>;
665 + clock-names = "ref";
666 + #phy-cells = <0>;
667 +
668 + status = "disabled";
669 + };
670 +
671 + usb3_0: usb30@0 {
672 + compatible = "qcom,dwc3";
673 + #address-cells = <1>;
674 + #size-cells = <1>;
675 + clocks = <&gcc USB30_0_MASTER_CLK>;
676 + clock-names = "core";
677 +
678 + syscon-tcsr = <&tcsr 0xb0 1>;
679 +
680 + ranges;
681 +
682 + status = "disabled";
683 +
684 + dwc3@11000000 {
685 + compatible = "snps,dwc3";
686 + reg = <0x11000000 0xcd00>;
687 + interrupts = <0 110 0x4>;
688 + phys = <&hs_phy_0>, <&ss_phy_0>;
689 + phy-names = "usb2-phy", "usb3-phy";
690 + dr_mode = "host";
691 + snps,dis_u3_susphy_quirk;
692 + };
693 + };
694 +
695 + usb3_1: usb30@1 {
696 + compatible = "qcom,dwc3";
697 + #address-cells = <1>;
698 + #size-cells = <1>;
699 + clocks = <&gcc USB30_1_MASTER_CLK>;
700 + clock-names = "core";
701 +
702 + syscon-tcsr = <&tcsr 0xb0 0>;
703 +
704 + ranges;
705 +
706 + status = "disabled";
707 +
708 + dwc3@10000000 {
709 + compatible = "snps,dwc3";
710 + reg = <0x10000000 0xcd00>;
711 + interrupts = <0 205 0x4>;
712 + phys = <&hs_phy_1>, <&ss_phy_1>;
713 + phy-names = "usb2-phy", "usb3-phy";
714 + dr_mode = "host";
715 + snps,dis_u3_susphy_quirk;
716 + };
717 + };
718 +
719 + pcie0: pci@1b500000 {
720 + compatible = "qcom,pcie-v0";
721 + reg = <0x1b500000 0x1000
722 + 0x1b502000 0x80
723 + 0x1b600000 0x100
724 + 0x0ff00000 0x100000>;
725 + reg-names = "dbi", "elbi", "parf", "config";
726 + device_type = "pci";
727 + linux,pci-domain = <0>;
728 + bus-range = <0x00 0xff>;
729 + num-lanes = <1>;
730 + #address-cells = <3>;
731 + #size-cells = <2>;
732 +
733 + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
734 + 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
735 +
736 + interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
737 + interrupt-names = "msi";
738 + #interrupt-cells = <1>;
739 + interrupt-map-mask = <0 0 0 0x7>;
740 + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
741 + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
742 + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
743 + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
744 +
745 + clocks = <&gcc PCIE_A_CLK>,
746 + <&gcc PCIE_H_CLK>,
747 + <&gcc PCIE_PHY_CLK>,
748 + <&gcc PCIE_AUX_CLK>,
749 + <&gcc PCIE_ALT_REF_CLK>;
750 + clock-names = "core", "iface", "phy", "aux", "ref";
751 +
752 + assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
753 + assigned-clock-rates = <100000000>;
754 +
755 + resets = <&gcc PCIE_ACLK_RESET>,
756 + <&gcc PCIE_HCLK_RESET>,
757 + <&gcc PCIE_POR_RESET>,
758 + <&gcc PCIE_PCI_RESET>,
759 + <&gcc PCIE_PHY_RESET>,
760 + <&gcc PCIE_EXT_RESET>;
761 + reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
762 +
763 + pinctrl-0 = <&pcie0_pins>;
764 + pinctrl-names = "default";
765 +
766 + perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
767 +
768 + status = "disabled";
769 + };
770 +
771 + pcie1: pci@1b700000 {
772 + compatible = "qcom,pcie-v0";
773 + reg = <0x1b700000 0x1000
774 + 0x1b702000 0x80
775 + 0x1b800000 0x100
776 + 0x31f00000 0x100000>;
777 + reg-names = "dbi", "elbi", "parf", "config";
778 + device_type = "pci";
779 + linux,pci-domain = <1>;
780 + bus-range = <0x00 0xff>;
781 + num-lanes = <1>;
782 + #address-cells = <3>;
783 + #size-cells = <2>;
784 +
785 + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
786 + 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
787 +
788 + interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
789 + interrupt-names = "msi";
790 + #interrupt-cells = <1>;
791 + interrupt-map-mask = <0 0 0 0x7>;
792 + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
793 + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
794 + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
795 + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
796 +
797 + clocks = <&gcc PCIE_1_A_CLK>,
798 + <&gcc PCIE_1_H_CLK>,
799 + <&gcc PCIE_1_PHY_CLK>,
800 + <&gcc PCIE_1_AUX_CLK>,
801 + <&gcc PCIE_1_ALT_REF_CLK>;
802 + clock-names = "core", "iface", "phy", "aux", "ref";
803 +
804 + assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
805 + assigned-clock-rates = <100000000>;
806 +
807 + resets = <&gcc PCIE_1_ACLK_RESET>,
808 + <&gcc PCIE_1_HCLK_RESET>,
809 + <&gcc PCIE_1_POR_RESET>,
810 + <&gcc PCIE_1_PCI_RESET>,
811 + <&gcc PCIE_1_PHY_RESET>,
812 + <&gcc PCIE_1_EXT_RESET>;
813 + reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
814 +
815 + pinctrl-0 = <&pcie1_pins>;
816 + pinctrl-names = "default";
817 +
818 + perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
819 +
820 + status = "disabled";
821 + };
822 +
823 + pcie2: pci@1b900000 {
824 + compatible = "qcom,pcie-v0";
825 + reg = <0x1b900000 0x1000
826 + 0x1b902000 0x80
827 + 0x1ba00000 0x100
828 + 0x35f00000 0x100000>;
829 + reg-names = "dbi", "elbi", "parf", "config";
830 + device_type = "pci";
831 + linux,pci-domain = <2>;
832 + bus-range = <0x00 0xff>;
833 + num-lanes = <1>;
834 + #address-cells = <3>;
835 + #size-cells = <2>;
836 +
837 + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
838 + 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
839 +
840 + interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
841 + interrupt-names = "msi";
842 + #interrupt-cells = <1>;
843 + interrupt-map-mask = <0 0 0 0x7>;
844 + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
845 + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
846 + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
847 + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
848 +
849 + clocks = <&gcc PCIE_2_A_CLK>,
850 + <&gcc PCIE_2_H_CLK>,
851 + <&gcc PCIE_2_PHY_CLK>,
852 + <&gcc PCIE_2_AUX_CLK>,
853 + <&gcc PCIE_2_ALT_REF_CLK>;
854 + clock-names = "core", "iface", "phy", "aux", "ref";
855 +
856 + assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
857 + assigned-clock-rates = <100000000>;
858 +
859 + resets = <&gcc PCIE_2_ACLK_RESET>,
860 + <&gcc PCIE_2_HCLK_RESET>,
861 + <&gcc PCIE_2_POR_RESET>,
862 + <&gcc PCIE_2_PCI_RESET>,
863 + <&gcc PCIE_2_PHY_RESET>,
864 + <&gcc PCIE_2_EXT_RESET>;
865 + reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
866 +
867 + pinctrl-0 = <&pcie2_pins>;
868 + pinctrl-names = "default";
869 +
870 + perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
871 +
872 + status = "disabled";
873 + };
874 +
875 adm_dma: dma@18300000 {
876 compatible = "qcom,adm";
877 reg = <0x18300000 0x100000>;
878 - interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
879 + interrupts = <0 170 0>;
880 #dma-cells = <1>;
881
882 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
883 @@ -365,7 +903,7 @@
884 };
885
886 nand@1ac00000 {
887 - compatible = "qcom,ipq806x-nand";
888 + compatible = "qcom,ebi2-nandc";
889 reg = <0x1ac00000 0x800>;
890
891 clocks = <&gcc EBI2_CLK>,
892 @@ -380,5 +918,103 @@
893 status = "disabled";
894 };
895
896 + nss_common: syscon@03000000 {
897 + compatible = "syscon";
898 + reg = <0x03000000 0x0000FFFF>;
899 + };
900 +
901 + qsgmii_csr: syscon@1bb00000 {
902 + compatible = "syscon";
903 + reg = <0x1bb00000 0x000001FF>;
904 + };
905 +
906 + gmac0: ethernet@37000000 {
907 + device_type = "network";
908 + compatible = "qcom,ipq806x-gmac";
909 + reg = <0x37000000 0x200000>;
910 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
911 + interrupt-names = "macirq";
912 +
913 + qcom,nss-common = <&nss_common>;
914 + qcom,qsgmii-csr = <&qsgmii_csr>;
915 +
916 + clocks = <&gcc GMAC_CORE1_CLK>;
917 + clock-names = "stmmaceth";
918 +
919 + resets = <&gcc GMAC_CORE1_RESET>;
920 + reset-names = "stmmaceth";
921 +
922 + status = "disabled";
923 + };
924 +
925 + gmac1: ethernet@37200000 {
926 + device_type = "network";
927 + compatible = "qcom,ipq806x-gmac";
928 + reg = <0x37200000 0x200000>;
929 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
930 + interrupt-names = "macirq";
931 +
932 + qcom,nss-common = <&nss_common>;
933 + qcom,qsgmii-csr = <&qsgmii_csr>;
934 +
935 + clocks = <&gcc GMAC_CORE2_CLK>;
936 + clock-names = "stmmaceth";
937 +
938 + resets = <&gcc GMAC_CORE2_RESET>;
939 + reset-names = "stmmaceth";
940 +
941 + status = "disabled";
942 + };
943 +
944 + gmac2: ethernet@37400000 {
945 + device_type = "network";
946 + compatible = "qcom,ipq806x-gmac";
947 + reg = <0x37400000 0x200000>;
948 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
949 + interrupt-names = "macirq";
950 +
951 + qcom,nss-common = <&nss_common>;
952 + qcom,qsgmii-csr = <&qsgmii_csr>;
953 +
954 + clocks = <&gcc GMAC_CORE3_CLK>;
955 + clock-names = "stmmaceth";
956 +
957 + resets = <&gcc GMAC_CORE3_RESET>;
958 + reset-names = "stmmaceth";
959 +
960 + status = "disabled";
961 + };
962 +
963 + gmac3: ethernet@37600000 {
964 + device_type = "network";
965 + compatible = "qcom,ipq806x-gmac";
966 + reg = <0x37600000 0x200000>;
967 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
968 + interrupt-names = "macirq";
969 +
970 + qcom,nss-common = <&nss_common>;
971 + qcom,qsgmii-csr = <&qsgmii_csr>;
972 +
973 + clocks = <&gcc GMAC_CORE4_CLK>;
974 + clock-names = "stmmaceth";
975 +
976 + resets = <&gcc GMAC_CORE4_RESET>;
977 + reset-names = "stmmaceth";
978 +
979 + status = "disabled";
980 + };
981 + };
982 +
983 + sfpb_mutex: sfpb-mutex {
984 + compatible = "qcom,sfpb-mutex";
985 + syscon = <&sfpb_mutex_block 4 4>;
986 +
987 + #hwlock-cells = <1>;
988 + };
989 +
990 + smem {
991 + compatible = "qcom,smem";
992 + memory-region = <&smem>;
993 + hwlocks = <&sfpb_mutex 3>;
994 };
995 };
OpenWrt Source Repository