target/linux/ipq806x/patches/0040-pinctrl-qcom-Add-definitions-for-IPQ8064.patch

   1 From 9bbd9d7e40944ca95e07f363b68700225beb9bef Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Mon, 14 Apr 2014 22:10:35 -0500
   4 Subject: [PATCH 040/182] pinctrl: qcom: Add definitions for IPQ8064
   5
   6 This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
   7 Qualcomm IPQ8064 platform.
   8
   9 Signed-off-by: Andy Gross <agross@codeaurora.org>
  10 Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
  11 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  12 ---
  13  drivers/pinctrl/Kconfig           |    8 +
  14  drivers/pinctrl/Makefile          |    1 +
  15  drivers/pinctrl/pinctrl-ipq8064.c |  653 +++++++++++++++++++++++++++++++++++++
  16  3 files changed, 662 insertions(+)
  17  create mode 100644 drivers/pinctrl/pinctrl-ipq8064.c
  18
  19 --- a/drivers/pinctrl/Kconfig
  20 +++ b/drivers/pinctrl/Kconfig
  21 @@ -230,6 +230,14 @@ config PINCTRL_APQ8064
  22           This is the pinctrl, pinmux, pinconf and gpiolib driver for the
  23           Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
  24
  25 +config PINCTRL_IPQ8064
  26 +       tristate "Qualcomm IPQ8064 pin controller driver"
  27 +       depends on GPIOLIB && OF
  28 +       select PINCTRL_MSM
  29 +       help
  30 +         This is the pinctrl, pinmux, pinconf and gpiolib driver for the
  31 +         Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
  32 +
  33  config PINCTRL_MSM8X74
  34         tristate "Qualcomm 8x74 pin controller driver"
  35         depends on GPIOLIB && OF && (ARCH_QCOM || COMPILE_TEST)
  36 --- a/drivers/pinctrl/Makefile
  37 +++ b/drivers/pinctrl/Makefile
  38 @@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_IMX25)   += pinctrl-i
  39  obj-$(CONFIG_PINCTRL_IMX28)    += pinctrl-imx28.o
  40  obj-$(CONFIG_PINCTRL_MSM)      += pinctrl-msm.o
  41  obj-$(CONFIG_PINCTRL_APQ8064)  += pinctrl-apq8064.o
  42 +obj-$(CONFIG_PINCTRL_IPQ8064)  += pinctrl-ipq8064.o
  43  obj-$(CONFIG_PINCTRL_MSM8X74)  += pinctrl-msm8x74.o
  44  obj-$(CONFIG_PINCTRL_NOMADIK)  += pinctrl-nomadik.o
  45  obj-$(CONFIG_PINCTRL_STN8815)  += pinctrl-nomadik-stn8815.o
  46 --- /dev/null
  47 +++ b/drivers/pinctrl/pinctrl-ipq8064.c
  48 @@ -0,0 +1,653 @@
  49 +/*
  50 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  51 + *
  52 + * This program is free software; you can redistribute it and/or modify
  53 + * it under the terms of the GNU General Public License version 2 and
  54 + * only version 2 as published by the Free Software Foundation.
  55 + *
  56 + * This program is distributed in the hope that it will be useful,
  57 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  58 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  59 + * GNU General Public License for more details.
  60 + *
  61 + */
  62 +
  63 +#include <linux/module.h>
  64 +#include <linux/of.h>
  65 +#include <linux/platform_device.h>
  66 +#include <linux/pinctrl/pinctrl.h>
  67 +
  68 +#include "pinctrl-msm.h"
  69 +
  70 +static const struct pinctrl_pin_desc ipq8064_pins[] = {
  71 +       PINCTRL_PIN(0, "GPIO_1"),
  72 +       PINCTRL_PIN(1, "GPIO_1"),
  73 +       PINCTRL_PIN(2, "GPIO_2"),
  74 +       PINCTRL_PIN(3, "GPIO_3"),
  75 +       PINCTRL_PIN(4, "GPIO_4"),
  76 +       PINCTRL_PIN(5, "GPIO_5"),
  77 +       PINCTRL_PIN(6, "GPIO_6"),
  78 +       PINCTRL_PIN(7, "GPIO_7"),
  79 +       PINCTRL_PIN(8, "GPIO_8"),
  80 +       PINCTRL_PIN(9, "GPIO_9"),
  81 +       PINCTRL_PIN(10, "GPIO_10"),
  82 +       PINCTRL_PIN(11, "GPIO_11"),
  83 +       PINCTRL_PIN(12, "GPIO_12"),
  84 +       PINCTRL_PIN(13, "GPIO_13"),
  85 +       PINCTRL_PIN(14, "GPIO_14"),
  86 +       PINCTRL_PIN(15, "GPIO_15"),
  87 +       PINCTRL_PIN(16, "GPIO_16"),
  88 +       PINCTRL_PIN(17, "GPIO_17"),
  89 +       PINCTRL_PIN(18, "GPIO_18"),
  90 +       PINCTRL_PIN(19, "GPIO_19"),
  91 +       PINCTRL_PIN(20, "GPIO_20"),
  92 +       PINCTRL_PIN(21, "GPIO_21"),
  93 +       PINCTRL_PIN(22, "GPIO_22"),
  94 +       PINCTRL_PIN(23, "GPIO_23"),
  95 +       PINCTRL_PIN(24, "GPIO_24"),
  96 +       PINCTRL_PIN(25, "GPIO_25"),
  97 +       PINCTRL_PIN(26, "GPIO_26"),
  98 +       PINCTRL_PIN(27, "GPIO_27"),
  99 +       PINCTRL_PIN(28, "GPIO_28"),
 100 +       PINCTRL_PIN(29, "GPIO_29"),
 101 +       PINCTRL_PIN(30, "GPIO_30"),
 102 +       PINCTRL_PIN(31, "GPIO_31"),
 103 +       PINCTRL_PIN(32, "GPIO_32"),
 104 +       PINCTRL_PIN(33, "GPIO_33"),
 105 +       PINCTRL_PIN(34, "GPIO_34"),
 106 +       PINCTRL_PIN(35, "GPIO_35"),
 107 +       PINCTRL_PIN(36, "GPIO_36"),
 108 +       PINCTRL_PIN(37, "GPIO_37"),
 109 +       PINCTRL_PIN(38, "GPIO_38"),
 110 +       PINCTRL_PIN(39, "GPIO_39"),
 111 +       PINCTRL_PIN(40, "GPIO_40"),
 112 +       PINCTRL_PIN(41, "GPIO_41"),
 113 +       PINCTRL_PIN(42, "GPIO_42"),
 114 +       PINCTRL_PIN(43, "GPIO_43"),
 115 +       PINCTRL_PIN(44, "GPIO_44"),
 116 +       PINCTRL_PIN(45, "GPIO_45"),
 117 +       PINCTRL_PIN(46, "GPIO_46"),
 118 +       PINCTRL_PIN(47, "GPIO_47"),
 119 +       PINCTRL_PIN(48, "GPIO_48"),
 120 +       PINCTRL_PIN(49, "GPIO_49"),
 121 +       PINCTRL_PIN(50, "GPIO_50"),
 122 +       PINCTRL_PIN(51, "GPIO_51"),
 123 +       PINCTRL_PIN(52, "GPIO_52"),
 124 +       PINCTRL_PIN(53, "GPIO_53"),
 125 +       PINCTRL_PIN(54, "GPIO_54"),
 126 +       PINCTRL_PIN(55, "GPIO_55"),
 127 +       PINCTRL_PIN(56, "GPIO_56"),
 128 +       PINCTRL_PIN(57, "GPIO_57"),
 129 +       PINCTRL_PIN(58, "GPIO_58"),
 130 +       PINCTRL_PIN(59, "GPIO_59"),
 131 +       PINCTRL_PIN(60, "GPIO_60"),
 132 +       PINCTRL_PIN(61, "GPIO_61"),
 133 +       PINCTRL_PIN(62, "GPIO_62"),
 134 +       PINCTRL_PIN(63, "GPIO_63"),
 135 +       PINCTRL_PIN(64, "GPIO_64"),
 136 +       PINCTRL_PIN(65, "GPIO_65"),
 137 +       PINCTRL_PIN(66, "GPIO_66"),
 138 +       PINCTRL_PIN(67, "GPIO_67"),
 139 +       PINCTRL_PIN(68, "GPIO_68"),
 140 +
 141 +       PINCTRL_PIN(69, "SDC3_CLK"),
 142 +       PINCTRL_PIN(70, "SDC3_CMD"),
 143 +       PINCTRL_PIN(71, "SDC3_DATA"),
 144 +};
 145 +
 146 +#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
 147 +DECLARE_IPQ_GPIO_PINS(0);
 148 +DECLARE_IPQ_GPIO_PINS(1);
 149 +DECLARE_IPQ_GPIO_PINS(2);
 150 +DECLARE_IPQ_GPIO_PINS(3);
 151 +DECLARE_IPQ_GPIO_PINS(4);
 152 +DECLARE_IPQ_GPIO_PINS(5);
 153 +DECLARE_IPQ_GPIO_PINS(6);
 154 +DECLARE_IPQ_GPIO_PINS(7);
 155 +DECLARE_IPQ_GPIO_PINS(8);
 156 +DECLARE_IPQ_GPIO_PINS(9);
 157 +DECLARE_IPQ_GPIO_PINS(10);
 158 +DECLARE_IPQ_GPIO_PINS(11);
 159 +DECLARE_IPQ_GPIO_PINS(12);
 160 +DECLARE_IPQ_GPIO_PINS(13);
 161 +DECLARE_IPQ_GPIO_PINS(14);
 162 +DECLARE_IPQ_GPIO_PINS(15);
 163 +DECLARE_IPQ_GPIO_PINS(16);
 164 +DECLARE_IPQ_GPIO_PINS(17);
 165 +DECLARE_IPQ_GPIO_PINS(18);
 166 +DECLARE_IPQ_GPIO_PINS(19);
 167 +DECLARE_IPQ_GPIO_PINS(20);
 168 +DECLARE_IPQ_GPIO_PINS(21);
 169 +DECLARE_IPQ_GPIO_PINS(22);
 170 +DECLARE_IPQ_GPIO_PINS(23);
 171 +DECLARE_IPQ_GPIO_PINS(24);
 172 +DECLARE_IPQ_GPIO_PINS(25);
 173 +DECLARE_IPQ_GPIO_PINS(26);
 174 +DECLARE_IPQ_GPIO_PINS(27);
 175 +DECLARE_IPQ_GPIO_PINS(28);
 176 +DECLARE_IPQ_GPIO_PINS(29);
 177 +DECLARE_IPQ_GPIO_PINS(30);
 178 +DECLARE_IPQ_GPIO_PINS(31);
 179 +DECLARE_IPQ_GPIO_PINS(32);
 180 +DECLARE_IPQ_GPIO_PINS(33);
 181 +DECLARE_IPQ_GPIO_PINS(34);
 182 +DECLARE_IPQ_GPIO_PINS(35);
 183 +DECLARE_IPQ_GPIO_PINS(36);
 184 +DECLARE_IPQ_GPIO_PINS(37);
 185 +DECLARE_IPQ_GPIO_PINS(38);
 186 +DECLARE_IPQ_GPIO_PINS(39);
 187 +DECLARE_IPQ_GPIO_PINS(40);
 188 +DECLARE_IPQ_GPIO_PINS(41);
 189 +DECLARE_IPQ_GPIO_PINS(42);
 190 +DECLARE_IPQ_GPIO_PINS(43);
 191 +DECLARE_IPQ_GPIO_PINS(44);
 192 +DECLARE_IPQ_GPIO_PINS(45);
 193 +DECLARE_IPQ_GPIO_PINS(46);
 194 +DECLARE_IPQ_GPIO_PINS(47);
 195 +DECLARE_IPQ_GPIO_PINS(48);
 196 +DECLARE_IPQ_GPIO_PINS(49);
 197 +DECLARE_IPQ_GPIO_PINS(50);
 198 +DECLARE_IPQ_GPIO_PINS(51);
 199 +DECLARE_IPQ_GPIO_PINS(52);
 200 +DECLARE_IPQ_GPIO_PINS(53);
 201 +DECLARE_IPQ_GPIO_PINS(54);
 202 +DECLARE_IPQ_GPIO_PINS(55);
 203 +DECLARE_IPQ_GPIO_PINS(56);
 204 +DECLARE_IPQ_GPIO_PINS(57);
 205 +DECLARE_IPQ_GPIO_PINS(58);
 206 +DECLARE_IPQ_GPIO_PINS(59);
 207 +DECLARE_IPQ_GPIO_PINS(60);
 208 +DECLARE_IPQ_GPIO_PINS(61);
 209 +DECLARE_IPQ_GPIO_PINS(62);
 210 +DECLARE_IPQ_GPIO_PINS(63);
 211 +DECLARE_IPQ_GPIO_PINS(64);
 212 +DECLARE_IPQ_GPIO_PINS(65);
 213 +DECLARE_IPQ_GPIO_PINS(66);
 214 +DECLARE_IPQ_GPIO_PINS(67);
 215 +DECLARE_IPQ_GPIO_PINS(68);
 216 +
 217 +static const unsigned int sdc3_clk_pins[] = { 69 };
 218 +static const unsigned int sdc3_cmd_pins[] = { 70 };
 219 +static const unsigned int sdc3_data_pins[] = { 71 };
 220 +
 221 +#define FUNCTION(fname)                                        \
 222 +       [IPQ_MUX_##fname] = {                           \
 223 +               .name = #fname,                         \
 224 +               .groups = fname##_groups,               \
 225 +               .ngroups = ARRAY_SIZE(fname##_groups),  \
 226 +       }
 227 +
 228 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
 229 +       {                                               \
 230 +               .name = "gpio" #id,                     \
 231 +               .pins = gpio##id##_pins,                \
 232 +               .npins = ARRAY_SIZE(gpio##id##_pins),   \
 233 +               .funcs = (int[]){                       \
 234 +                       IPQ_MUX_NA, /* gpio mode */     \
 235 +                       IPQ_MUX_##f1,                   \
 236 +                       IPQ_MUX_##f2,                   \
 237 +                       IPQ_MUX_##f3,                   \
 238 +                       IPQ_MUX_##f4,                   \
 239 +                       IPQ_MUX_##f5,                   \
 240 +                       IPQ_MUX_##f6,                   \
 241 +                       IPQ_MUX_##f7,                   \
 242 +                       IPQ_MUX_##f8,                   \
 243 +                       IPQ_MUX_##f9,                   \
 244 +                       IPQ_MUX_##f10,                  \
 245 +               },                                      \
 246 +               .nfuncs = 11,                           \
 247 +               .ctl_reg = 0x1000 + 0x10 * id,          \
 248 +               .io_reg = 0x1004 + 0x10 * id,           \
 249 +               .intr_cfg_reg = 0x1008 + 0x10 * id,     \
 250 +               .intr_status_reg = 0x100c + 0x10 * id,  \
 251 +               .intr_target_reg = 0x400 + 0x4 * id,    \
 252 +               .mux_bit = 2,                           \
 253 +               .pull_bit = 0,                          \
 254 +               .drv_bit = 6,                           \
 255 +               .oe_bit = 9,                            \
 256 +               .in_bit = 0,                            \
 257 +               .out_bit = 1,                           \
 258 +               .intr_enable_bit = 0,                   \
 259 +               .intr_status_bit = 0,                   \
 260 +               .intr_ack_high = 1,                     \
 261 +               .intr_target_bit = 0,                   \
 262 +               .intr_raw_status_bit = 3,               \
 263 +               .intr_polarity_bit = 1,                 \
 264 +               .intr_detection_bit = 2,                \
 265 +               .intr_detection_width = 1,              \
 266 +       }
 267 +
 268 +#define SDC_PINGROUP(pg_name, ctl, pull, drv)          \
 269 +       {                                               \
 270 +               .name = #pg_name,                       \
 271 +               .pins = pg_name##_pins,                 \
 272 +               .npins = ARRAY_SIZE(pg_name##_pins),    \
 273 +               .ctl_reg = ctl,                         \
 274 +               .io_reg = 0,                            \
 275 +               .intr_cfg_reg = 0,                      \
 276 +               .intr_status_reg = 0,                   \
 277 +               .intr_target_reg = 0,                   \
 278 +               .mux_bit = -1,                          \
 279 +               .pull_bit = pull,                       \
 280 +               .drv_bit = drv,                         \
 281 +               .oe_bit = -1,                           \
 282 +               .in_bit = -1,                           \
 283 +               .out_bit = -1,                          \
 284 +               .intr_enable_bit = -1,                  \
 285 +               .intr_status_bit = -1,                  \
 286 +               .intr_target_bit = -1,                  \
 287 +               .intr_raw_status_bit = -1,              \
 288 +               .intr_polarity_bit = -1,                \
 289 +               .intr_detection_bit = -1,               \
 290 +               .intr_detection_width = -1,             \
 291 +       }
 292 +
 293 +enum ipq8064_functions {
 294 +       IPQ_MUX_mdio,
 295 +       IPQ_MUX_mi2s,
 296 +       IPQ_MUX_pdm,
 297 +       IPQ_MUX_ssbi,
 298 +       IPQ_MUX_spmi,
 299 +       IPQ_MUX_audio_pcm,
 300 +       IPQ_MUX_gsbi1,
 301 +       IPQ_MUX_gsbi2,
 302 +       IPQ_MUX_gsbi4,
 303 +       IPQ_MUX_gsbi5,
 304 +       IPQ_MUX_gsbi5_spi_cs1,
 305 +       IPQ_MUX_gsbi5_spi_cs2,
 306 +       IPQ_MUX_gsbi5_spi_cs3,
 307 +       IPQ_MUX_gsbi6,
 308 +       IPQ_MUX_gsbi7,
 309 +       IPQ_MUX_nss_spi,
 310 +       IPQ_MUX_sdc1,
 311 +       IPQ_MUX_spdif,
 312 +       IPQ_MUX_nand,
 313 +       IPQ_MUX_tsif1,
 314 +       IPQ_MUX_tsif2,
 315 +       IPQ_MUX_usb_fs_n,
 316 +       IPQ_MUX_usb_fs,
 317 +       IPQ_MUX_usb2_hsic,
 318 +       IPQ_MUX_rgmii2,
 319 +       IPQ_MUX_sata,
 320 +       IPQ_MUX_pcie1_rst,
 321 +       IPQ_MUX_pcie1_prsnt,
 322 +       IPQ_MUX_pcie1_pwrflt,
 323 +       IPQ_MUX_pcie1_pwren_n,
 324 +       IPQ_MUX_pcie1_pwren,
 325 +       IPQ_MUX_pcie1_clk_req,
 326 +       IPQ_MUX_pcie2_rst,
 327 +       IPQ_MUX_pcie2_prsnt,
 328 +       IPQ_MUX_pcie2_pwrflt,
 329 +       IPQ_MUX_pcie2_pwren_n,
 330 +       IPQ_MUX_pcie2_pwren,
 331 +       IPQ_MUX_pcie2_clk_req,
 332 +       IPQ_MUX_pcie3_rst,
 333 +       IPQ_MUX_pcie3_prsnt,
 334 +       IPQ_MUX_pcie3_pwrflt,
 335 +       IPQ_MUX_pcie3_pwren_n,
 336 +       IPQ_MUX_pcie3_pwren,
 337 +       IPQ_MUX_pcie3_clk_req,
 338 +       IPQ_MUX_ps_hold,
 339 +       IPQ_MUX_NA,
 340 +};
 341 +
 342 +static const char * const mdio_groups[] = {
 343 +       "gpio0", "gpio1", "gpio10", "gpio11",
 344 +};
 345 +
 346 +static const char * const mi2s_groups[] = {
 347 +       "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
 348 +       "gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
 349 +};
 350 +
 351 +static const char * const pdm_groups[] = {
 352 +       "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
 353 +       "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
 354 +       "gpio59",
 355 +};
 356 +
 357 +static const char * const ssbi_groups[] = {
 358 +       "gpio10", "gpio11",
 359 +};
 360 +
 361 +static const char * const spmi_groups[] = {
 362 +       "gpio10", "gpio11",
 363 +};
 364 +
 365 +static const char * const audio_pcm_groups[] = {
 366 +       "gpio14", "gpio15", "gpio16", "gpio17",
 367 +};
 368 +
 369 +static const char * const gsbi1_groups[] = {
 370 +       "gpio51", "gpio52", "gpio53", "gpio54",
 371 +};
 372 +
 373 +static const char * const gsbi2_groups[] = {
 374 +       "gpio22", "gpio23", "gpio24", "gpio25",
 375 +};
 376 +
 377 +static const char * const gsbi4_groups[] = {
 378 +       "gpio10", "gpio11", "gpio12", "gpio13",
 379 +};
 380 +
 381 +static const char * const gsbi5_groups[] = {
 382 +       "gpio18", "gpio19", "gpio20", "gpio21",
 383 +};
 384 +
 385 +static const char * const gsbi5_spi_cs1_groups[] = {
 386 +       "gpio6", "gpio61",
 387 +};
 388 +
 389 +static const char * const gsbi5_spi_cs2_groups[] = {
 390 +       "gpio7", "gpio62",
 391 +};
 392 +
 393 +static const char * const gsbi5_spi_cs3_groups[] = {
 394 +       "gpio2",
 395 +};
 396 +
 397 +static const char * const gsbi6_groups[] = {
 398 +       "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
 399 +       "gpio57", "gpio58",
 400 +};
 401 +
 402 +static const char * const gsbi7_groups[] = {
 403 +       "gpio6", "gpio7", "gpio8", "gpio9",
 404 +};
 405 +
 406 +static const char * const nss_spi_groups[] = {
 407 +       "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
 408 +       "gpio57", "gpio58",
 409 +};
 410 +
 411 +static const char * const sdc1_groups[] = {
 412 +       "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
 413 +       "gpio44", "gpio45", "gpio46", "gpio47",
 414 +};
 415 +
 416 +static const char * const spdif_groups[] = {
 417 +       "gpio_10", "gpio_48",
 418 +};
 419 +
 420 +static const char * const nand_groups[] = {
 421 +       "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
 422 +       "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
 423 +       "gpio46", "gpio47",
 424 +};
 425 +
 426 +static const char * const tsif1_groups[] = {
 427 +       "gpio55", "gpio56", "gpio57", "gpio58",
 428 +};
 429 +
 430 +static const char * const tsif2_groups[] = {
 431 +       "gpio59", "gpio60", "gpio61", "gpio62",
 432 +};
 433 +
 434 +static const char * const usb_fs_n_groups[] = {
 435 +       "gpio6",
 436 +};
 437 +
 438 +static const char * const usb_fs_groups[] = {
 439 +       "gpio6", "gpio7", "gpio8",
 440 +};
 441 +
 442 +static const char * const usb2_hsic_groups[] = {
 443 +       "gpio67", "gpio68",
 444 +};
 445 +
 446 +static const char * const rgmii2_groups[] = {
 447 +       "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
 448 +       "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
 449 +};
 450 +
 451 +static const char * const sata_groups[] = {
 452 +       "gpio10",
 453 +};
 454 +
 455 +static const char * const pcie1_rst_groups[] = {
 456 +       "gpio3",
 457 +};
 458 +
 459 +static const char * const pcie1_prsnt_groups[] = {
 460 +       "gpio3", "gpio11",
 461 +};
 462 +
 463 +static const char * const pcie1_pwren_n_groups[] = {
 464 +       "gpio4", "gpio12",
 465 +};
 466 +
 467 +static const char * const pcie1_pwren_groups[] = {
 468 +       "gpio4", "gpio12",
 469 +};
 470 +
 471 +static const char * const pcie1_pwrflt_groups[] = {
 472 +       "gpio5", "gpio13",
 473 +};
 474 +
 475 +static const char * const pcie1_clk_req_groups[] = {
 476 +       "gpio5",
 477 +};
 478 +
 479 +static const char * const pcie2_rst_groups[] = {
 480 +       "gpio48",
 481 +};
 482 +
 483 +static const char * const pcie2_prsnt_groups[] = {
 484 +       "gpio11", "gpio48",
 485 +};
 486 +
 487 +static const char * const pcie2_pwren_n_groups[] = {
 488 +       "gpio12", "gpio49",
 489 +};
 490 +
 491 +static const char * const pcie2_pwren_groups[] = {
 492 +       "gpio12", "gpio49",
 493 +};
 494 +
 495 +static const char * const pcie2_pwrflt_groups[] = {
 496 +       "gpio13", "gpio50",
 497 +};
 498 +
 499 +static const char * const pcie2_clk_req_groups[] = {
 500 +       "gpio50",
 501 +};
 502 +
 503 +static const char * const pcie3_rst_groups[] = {
 504 +       "gpio63",
 505 +};
 506 +
 507 +static const char * const pcie3_prsnt_groups[] = {
 508 +       "gpio11",
 509 +};
 510 +
 511 +static const char * const pcie3_pwren_n_groups[] = {
 512 +       "gpio12",
 513 +};
 514 +
 515 +static const char * const pcie3_pwren_groups[] = {
 516 +       "gpio12",
 517 +};
 518 +
 519 +static const char * const pcie3_pwrflt_groups[] = {
 520 +       "gpio13",
 521 +};
 522 +
 523 +static const char * const pcie3_clk_req_groups[] = {
 524 +       "gpio65",
 525 +};
 526 +
 527 +static const char * const ps_hold_groups[] = {
 528 +       "gpio26",
 529 +};
 530 +
 531 +static const struct msm_function ipq8064_functions[] = {
 532 +       FUNCTION(mdio),
 533 +       FUNCTION(ssbi),
 534 +       FUNCTION(spmi),
 535 +       FUNCTION(mi2s),
 536 +       FUNCTION(pdm),
 537 +       FUNCTION(audio_pcm),
 538 +       FUNCTION(gsbi1),
 539 +       FUNCTION(gsbi2),
 540 +       FUNCTION(gsbi4),
 541 +       FUNCTION(gsbi5),
 542 +       FUNCTION(gsbi5_spi_cs1),
 543 +       FUNCTION(gsbi5_spi_cs2),
 544 +       FUNCTION(gsbi5_spi_cs3),
 545 +       FUNCTION(gsbi6),
 546 +       FUNCTION(gsbi7),
 547 +       FUNCTION(nss_spi),
 548 +       FUNCTION(sdc1),
 549 +       FUNCTION(spdif),
 550 +       FUNCTION(nand),
 551 +       FUNCTION(tsif1),
 552 +       FUNCTION(tsif2),
 553 +       FUNCTION(usb_fs_n),
 554 +       FUNCTION(usb_fs),
 555 +       FUNCTION(usb2_hsic),
 556 +       FUNCTION(rgmii2),
 557 +       FUNCTION(sata),
 558 +       FUNCTION(pcie1_rst),
 559 +       FUNCTION(pcie1_prsnt),
 560 +       FUNCTION(pcie1_pwren_n),
 561 +       FUNCTION(pcie1_pwren),
 562 +       FUNCTION(pcie1_pwrflt),
 563 +       FUNCTION(pcie1_clk_req),
 564 +       FUNCTION(pcie2_rst),
 565 +       FUNCTION(pcie2_prsnt),
 566 +       FUNCTION(pcie2_pwren_n),
 567 +       FUNCTION(pcie2_pwren),
 568 +       FUNCTION(pcie2_pwrflt),
 569 +       FUNCTION(pcie2_clk_req),
 570 +       FUNCTION(pcie3_rst),
 571 +       FUNCTION(pcie3_prsnt),
 572 +       FUNCTION(pcie3_pwren_n),
 573 +       FUNCTION(pcie3_pwren),
 574 +       FUNCTION(pcie3_pwrflt),
 575 +       FUNCTION(pcie3_clk_req),
 576 +       FUNCTION(ps_hold),
 577 +};
 578 +
 579 +static const struct msm_pingroup ipq8064_groups[] = {
 580 +       PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 581 +       PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 582 +       PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 583 +       PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
 584 +       PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
 585 +       PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
 586 +       PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
 587 +       PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
 588 +       PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
 589 +       PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 590 +       PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
 591 +       PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
 592 +       PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
 593 +       PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
 594 +       PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
 595 +       PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
 596 +       PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
 597 +       PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
 598 +       PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 599 +       PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 600 +       PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 601 +       PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 602 +       PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
 603 +       PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 604 +       PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 605 +       PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 606 +       PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 607 +       PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
 608 +       PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
 609 +       PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
 610 +       PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
 611 +       PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
 612 +       PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 613 +       PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 614 +       PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
 615 +       PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
 616 +       PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 617 +       PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 618 +       PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 619 +       PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 620 +       PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 621 +       PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 622 +       PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 623 +       PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 624 +       PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 625 +       PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 626 +       PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 627 +       PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 628 +       PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
 629 +       PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
 630 +       PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
 631 +       PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 632 +       PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
 633 +       PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 634 +       PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 635 +       PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
 636 +       PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
 637 +       PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
 638 +       PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
 639 +       PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
 640 +       PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 641 +       PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
 642 +       PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
 643 +       PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 644 +       PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 645 +       PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 646 +       PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 647 +       PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 648 +       PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 649 +       SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
 650 +       SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
 651 +       SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
 652 +};
 653 +
 654 +#define NUM_GPIO_PINGROUPS 69
 655 +
 656 +static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
 657 +       .pins = ipq8064_pins,
 658 +       .npins = ARRAY_SIZE(ipq8064_pins),
 659 +       .functions = ipq8064_functions,
 660 +       .nfunctions = ARRAY_SIZE(ipq8064_functions),
 661 +       .groups = ipq8064_groups,
 662 +       .ngroups = ARRAY_SIZE(ipq8064_groups),
 663 +       .ngpios = NUM_GPIO_PINGROUPS,
 664 +};
 665 +
 666 +static int ipq8064_pinctrl_probe(struct platform_device *pdev)
 667 +{
 668 +       return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
 669 +}
 670 +
 671 +static const struct of_device_id ipq8064_pinctrl_of_match[] = {
 672 +       { .compatible = "qcom,ipq8064-pinctrl", },
 673 +       { },
 674 +};
 675 +
 676 +static struct platform_driver ipq8064_pinctrl_driver = {
 677 +       .driver = {
 678 +               .name = "ipq8064-pinctrl",
 679 +               .owner = THIS_MODULE,
 680 +               .of_match_table = ipq8064_pinctrl_of_match,
 681 +       },
 682 +       .probe = ipq8064_pinctrl_probe,
 683 +       .remove = msm_pinctrl_remove,
 684 +};
 685 +
 686 +static int __init ipq8064_pinctrl_init(void)
 687 +{
 688 +       return platform_driver_register(&ipq8064_pinctrl_driver);
 689 +}
 690 +arch_initcall(ipq8064_pinctrl_init);
 691 +
 692 +static void __exit ipq8064_pinctrl_exit(void)
 693 +{
 694 +       platform_driver_unregister(&ipq8064_pinctrl_driver);
 695 +}
 696 +module_exit(ipq8064_pinctrl_exit);
 697 +
 698 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 699 +MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
 700 +MODULE_LICENSE("GPL v2");
 701 +MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);