ipq806x: Add support for IPQ806x chip family
[openwrt/openwrt.git] / target / linux / ipq806x / patches / 0044-dmaengine-qcom_bam_dma-Add-device-tree-binding.patch
1 From b5e19b657e352d565c5ddeae5f6dfd542de9d7e5 Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Mon, 10 Mar 2014 16:40:19 -0500
4 Subject: [PATCH 044/182] dmaengine: qcom_bam_dma: Add device tree binding
5
6 Add device tree binding support for the QCOM BAM DMA driver.
7
8 Acked-by: Kumar Gala <galak@codeaurora.org>
9 Signed-off-by: Andy Gross <agross@codeaurora.org>
10 Signed-off-by: Vinod Koul <vinod.koul@intel.com>
11 ---
12 .../devicetree/bindings/dma/qcom_bam_dma.txt | 41 ++++++++++++++++++++
13 1 file changed, 41 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
15
16 diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
17 new file mode 100644
18 index 0000000..d75a9d7
19 --- /dev/null
20 +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
21 @@ -0,0 +1,41 @@
22 +QCOM BAM DMA controller
23 +
24 +Required properties:
25 +- compatible: must contain "qcom,bam-v1.4.0" for MSM8974
26 +- reg: Address range for DMA registers
27 +- interrupts: Should contain the one interrupt shared by all channels
28 +- #dma-cells: must be <1>, the cell in the dmas property of the client device
29 + represents the channel number
30 +- clocks: required clock
31 +- clock-names: must contain "bam_clk" entry
32 +- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
33 + the secure world.
34 +
35 +Example:
36 +
37 + uart-bam: dma@f9984000 = {
38 + compatible = "qcom,bam-v1.4.0";
39 + reg = <0xf9984000 0x15000>;
40 + interrupts = <0 94 0>;
41 + clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
42 + clock-names = "bam_clk";
43 + #dma-cells = <1>;
44 + qcom,ee = <0>;
45 + };
46 +
47 +DMA clients must use the format described in the dma.txt file, using a two cell
48 +specifier for each channel.
49 +
50 +Example:
51 + serial@f991e000 {
52 + compatible = "qcom,msm-uart";
53 + reg = <0xf991e000 0x1000>
54 + <0xf9944000 0x19000>;
55 + interrupts = <0 108 0>;
56 + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
57 + <&gcc GCC_BLSP1_AHB_CLK>;
58 + clock-names = "core", "iface";
59 +
60 + dmas = <&uart-bam 0>, <&uart-bam 1>;
61 + dma-names = "rx", "tx";
62 + };
63 --
64 1.7.10.4
65