target/linux/ipq806x/patches/0107-clk-qcom-Support-msm8974pro-global-clock-control-har.patch

   1 From a740d2b024c5b71c6f9989976049f03b634bb13d Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 16 May 2014 16:07:13 -0700
   4 Subject: [PATCH 107/182] clk: qcom: Support msm8974pro global clock control
   5  hardware
   6
   7 A new PLL (gpll4) is added on msm8974 PRO devices to support a
   8 faster sdc1 clock rate. Add support for this and the two new sdcc
   9 cal clocks.
  10
  11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  12 Signed-off-by: Mike Turquette <mturquette@linaro.org>
  13 ---
  14  .../devicetree/bindings/clock/qcom,gcc.txt         |    2 +
  15  drivers/clk/qcom/gcc-msm8974.c                     |  130 +++++++++++++++++++-
  16  include/dt-bindings/clock/qcom,gcc-msm8974.h       |    4 +
  17  3 files changed, 130 insertions(+), 6 deletions(-)
  18
  19 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
  20 +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
  21 @@ -8,6 +8,8 @@ Required properties :
  22                         "qcom,gcc-msm8660"
  23                         "qcom,gcc-msm8960"
  24                         "qcom,gcc-msm8974"
  25 +                       "qcom,gcc-msm8974pro"
  26 +                       "qcom,gcc-msm8974pro-ac"
  27
  28  - reg : shall contain base register location and length
  29  - #clock-cells : shall contain 1
  30 --- a/drivers/clk/qcom/gcc-msm8974.c
  31 +++ b/drivers/clk/qcom/gcc-msm8974.c
  32 @@ -35,6 +35,7 @@
  33  #define P_XO   0
  34  #define P_GPLL0        1
  35  #define P_GPLL1        1
  36 +#define P_GPLL4        2
  37
  38  static const u8 gcc_xo_gpll0_map[] = {
  39         [P_XO]          = 0,
  40 @@ -46,6 +47,18 @@ static const char *gcc_xo_gpll0[] = {
  41         "gpll0_vote",
  42  };
  43
  44 +static const u8 gcc_xo_gpll0_gpll4_map[] = {
  45 +       [P_XO]          = 0,
  46 +       [P_GPLL0]       = 1,
  47 +       [P_GPLL4]       = 5,
  48 +};
  49 +
  50 +static const char *gcc_xo_gpll0_gpll4[] = {
  51 +       "xo",
  52 +       "gpll0_vote",
  53 +       "gpll4_vote",
  54 +};
  55 +
  56  #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  57
  58  static struct clk_pll gpll0 = {
  59 @@ -138,6 +151,33 @@ static struct clk_regmap gpll1_vote = {
  60         },
  61  };
  62
  63 +static struct clk_pll gpll4 = {
  64 +       .l_reg = 0x1dc4,
  65 +       .m_reg = 0x1dc8,
  66 +       .n_reg = 0x1dcc,
  67 +       .config_reg = 0x1dd4,
  68 +       .mode_reg = 0x1dc0,
  69 +       .status_reg = 0x1ddc,
  70 +       .status_bit = 17,
  71 +       .clkr.hw.init = &(struct clk_init_data){
  72 +               .name = "gpll4",
  73 +               .parent_names = (const char *[]){ "xo" },
  74 +               .num_parents = 1,
  75 +               .ops = &clk_pll_ops,
  76 +       },
  77 +};
  78 +
  79 +static struct clk_regmap gpll4_vote = {
  80 +       .enable_reg = 0x1480,
  81 +       .enable_mask = BIT(4),
  82 +       .hw.init = &(struct clk_init_data){
  83 +               .name = "gpll4_vote",
  84 +               .parent_names = (const char *[]){ "gpll4" },
  85 +               .num_parents = 1,
  86 +               .ops = &clk_pll_vote_ops,
  87 +       },
  88 +};
  89 +
  90  static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
  91         F(125000000, P_GPLL0, 1, 5, 24),
  92         { }
  93 @@ -812,18 +852,33 @@ static const struct freq_tbl ftbl_gcc_sd
  94         { }
  95  };
  96
  97 +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
  98 +       F(144000, P_XO, 16, 3, 25),
  99 +       F(400000, P_XO, 12, 1, 4),
 100 +       F(20000000, P_GPLL0, 15, 1, 2),
 101 +       F(25000000, P_GPLL0, 12, 1, 2),
 102 +       F(50000000, P_GPLL0, 12, 0, 0),
 103 +       F(100000000, P_GPLL0, 6, 0, 0),
 104 +       F(192000000, P_GPLL4, 4, 0, 0),
 105 +       F(200000000, P_GPLL0, 3, 0, 0),
 106 +       F(384000000, P_GPLL4, 2, 0, 0),
 107 +       { }
 108 +};
 109 +
 110 +static struct clk_init_data sdcc1_apps_clk_src_init = {
 111 +       .name = "sdcc1_apps_clk_src",
 112 +       .parent_names = gcc_xo_gpll0,
 113 +       .num_parents = 2,
 114 +       .ops = &clk_rcg2_ops,
 115 +};
 116 +
 117  static struct clk_rcg2 sdcc1_apps_clk_src = {
 118         .cmd_rcgr = 0x04d0,
 119         .mnd_width = 8,
 120         .hid_width = 5,
 121         .parent_map = gcc_xo_gpll0_map,
 122         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 123 -       .clkr.hw.init = &(struct clk_init_data){
 124 -               .name = "sdcc1_apps_clk_src",
 125 -               .parent_names = gcc_xo_gpll0,
 126 -               .num_parents = 2,
 127 -               .ops = &clk_rcg2_ops,
 128 -       },
 129 +       .clkr.hw.init = &sdcc1_apps_clk_src_init,
 130  };
 131
 132  static struct clk_rcg2 sdcc2_apps_clk_src = {
 133 @@ -1995,6 +2050,38 @@ static struct clk_branch gcc_sdcc1_apps_
 134         },
 135  };
 136
 137 +static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
 138 +       .halt_reg = 0x04e8,
 139 +       .clkr = {
 140 +               .enable_reg = 0x04e8,
 141 +               .enable_mask = BIT(0),
 142 +               .hw.init = &(struct clk_init_data){
 143 +                       .name = "gcc_sdcc1_cdccal_ff_clk",
 144 +                       .parent_names = (const char *[]){
 145 +                               "xo"
 146 +                       },
 147 +                       .num_parents = 1,
 148 +                       .ops = &clk_branch2_ops,
 149 +               },
 150 +       },
 151 +};
 152 +
 153 +static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
 154 +       .halt_reg = 0x04e4,
 155 +       .clkr = {
 156 +               .enable_reg = 0x04e4,
 157 +               .enable_mask = BIT(0),
 158 +               .hw.init = &(struct clk_init_data){
 159 +                       .name = "gcc_sdcc1_cdccal_sleep_clk",
 160 +                       .parent_names = (const char *[]){
 161 +                               "sleep_clk_src"
 162 +                       },
 163 +                       .num_parents = 1,
 164 +                       .ops = &clk_branch2_ops,
 165 +               },
 166 +       },
 167 +};
 168 +
 169  static struct clk_branch gcc_sdcc2_ahb_clk = {
 170         .halt_reg = 0x0508,
 171         .clkr = {
 172 @@ -2484,6 +2571,10 @@ static struct clk_regmap *gcc_msm8974_cl
 173         [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
 174         [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
 175         [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
 176 +       [GPLL4] = NULL,
 177 +       [GPLL4_VOTE] = NULL,
 178 +       [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL,
 179 +       [GCC_SDCC1_CDCCAL_FF_CLK] = NULL,
 180  };
 181
 182  static const struct qcom_reset_map gcc_msm8974_resets[] = {
 183 @@ -2585,14 +2676,41 @@ static const struct qcom_cc_desc gcc_msm
 184
 185  static const struct of_device_id gcc_msm8974_match_table[] = {
 186         { .compatible = "qcom,gcc-msm8974" },
 187 +       { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL },
 188 +       { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL },
 189         { }
 190  };
 191  MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
 192
 193 +static void msm8974_pro_clock_override(void)
 194 +{
 195 +       sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
 196 +       sdcc1_apps_clk_src_init.num_parents = 3;
 197 +       sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro;
 198 +       sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map;
 199 +
 200 +       gcc_msm8974_clocks[GPLL4] = &gpll4.clkr;
 201 +       gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote;
 202 +       gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] =
 203 +               &gcc_sdcc1_cdccal_sleep_clk.clkr;
 204 +       gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] =
 205 +               &gcc_sdcc1_cdccal_ff_clk.clkr;
 206 +}
 207 +
 208  static int gcc_msm8974_probe(struct platform_device *pdev)
 209  {
 210         struct clk *clk;
 211         struct device *dev = &pdev->dev;
 212 +       bool pro;
 213 +       const struct of_device_id *id;
 214 +
 215 +       id = of_match_device(gcc_msm8974_match_table, dev);
 216 +       if (!id)
 217 +               return -ENODEV;
 218 +       pro = !!(id->data);
 219 +
 220 +       if (pro)
 221 +               msm8974_pro_clock_override();
 222
 223         /* Temporary until RPM clocks supported */
 224         clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
 225 --- a/include/dt-bindings/clock/qcom,gcc-msm8974.h
 226 +++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
 227 @@ -316,5 +316,9 @@
 228  #define GCC_CE2_CLK_SLEEP_ENA                                  299
 229  #define GCC_CE2_AXI_CLK_SLEEP_ENA                              300
 230  #define GCC_CE2_AHB_CLK_SLEEP_ENA                              301
 231 +#define GPLL4                                                  302
 232 +#define GPLL4_VOTE                                             303
 233 +#define GCC_SDCC1_CDCCAL_SLEEP_CLK                             304
 234 +#define GCC_SDCC1_CDCCAL_FF_CLK                                        305
 235
 236  #endif