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* upgrade ixp4xx to 2.6.23.12 * upgrade to the new ethernet driver (temporary breaks...
[openwrt/openwrt.git] / target / linux / ixp4xx / patches-2.6.23 / 200-npe_driver.patch
1 diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/kernel/setup.c ixp4xx-nep.git/arch/arm/kernel/setup.c
2 --- linux-2.6.23/arch/arm/kernel/setup.c 2007-10-09 22:31:38.000000000 +0200
3 +++ ixp4xx-nep.git/arch/arm/kernel/setup.c 2007-10-22 19:19:41.000000000 +0200
4 @@ -61,6 +61,7 @@
5 extern void _stext, _text, _etext, __data_start, _edata, _end;
6
7 unsigned int processor_id;
8 +EXPORT_SYMBOL(processor_id);
9 unsigned int __machine_arch_type;
10 EXPORT_SYMBOL(__machine_arch_type);
11
12 diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig ixp4xx-nep.git/arch/arm/mach-ixp4xx/Kconfig
13 --- linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-09 22:31:38.000000000 +0200
14 +++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/Kconfig 2007-10-22 19:19:41.000000000 +0200
15 @@ -189,6 +189,20 @@
16 need to use the indirect method instead. If you don't know
17 what you need, leave this option unselected.
18
19 +config IXP4XX_QMGR
20 + tristate "IXP4xx Queue Manager support"
21 + help
22 + This driver supports IXP4xx built-in hardware queue manager
23 + and is automatically selected by Ethernet and HSS drivers.
24 +
25 +config IXP4XX_NPE
26 + tristate "IXP4xx Network Processor Engine support"
27 + select HOTPLUG
28 + select FW_LOADER
29 + help
30 + This driver supports IXP4xx built-in network coprocessors
31 + and is automatically selected by Ethernet and HSS drivers.
32 +
33 endmenu
34
35 endif
36 diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/Makefile ixp4xx-nep.git/arch/arm/mach-ixp4xx/Makefile
37 --- linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-09 22:31:38.000000000 +0200
38 +++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/Makefile 2007-10-22 19:19:41.000000000 +0200
39 @@ -30,3 +30,5 @@
40 obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
41
42 obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
43 +obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
44 +obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
45 diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-setup.c ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixdp425-setup.c
46 --- linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-setup.c 2007-10-09 22:31:38.000000000 +0200
47 +++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixdp425-setup.c 2007-10-22 19:19:41.000000000 +0200
48 @@ -177,6 +177,31 @@
49 .resource = ixdp425_uart_resources
50 };
51
52 +/* Built-in 10/100 Ethernet MAC interfaces */
53 +static struct eth_plat_info ixdp425_plat_eth[] = {
54 + {
55 + .phy = 0,
56 + .rxq = 3,
57 + .txreadyq = 20,
58 + }, {
59 + .phy = 1,
60 + .rxq = 4,
61 + .txreadyq = 21,
62 + }
63 +};
64 +
65 +static struct platform_device ixdp425_eth[] = {
66 + {
67 + .name = "ixp4xx_eth",
68 + .id = IXP4XX_ETH_NPEB,
69 + .dev.platform_data = ixdp425_plat_eth,
70 + }, {
71 + .name = "ixp4xx_eth",
72 + .id = IXP4XX_ETH_NPEC,
73 + .dev.platform_data = ixdp425_plat_eth + 1,
74 + }
75 +};
76 +
77 static struct platform_device *ixdp425_devices[] __initdata = {
78 &ixdp425_i2c_controller,
79 &ixdp425_flash,
80 @@ -184,7 +209,9 @@
81 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
82 &ixdp425_flash_nand,
83 #endif
84 - &ixdp425_uart
85 + &ixdp425_uart,
86 + &ixdp425_eth[0],
87 + &ixdp425_eth[1],
88 };
89
90 static void __init ixdp425_init(void)
91 diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_npe.c ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixp4xx_npe.c
92 --- linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_npe.c 1970-01-01 01:00:00.000000000 +0100
93 +++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixp4xx_npe.c 2007-10-22 19:19:41.000000000 +0200
94 @@ -0,0 +1,737 @@
95 +/*
96 + * Intel IXP4xx Network Processor Engine driver for Linux
97 + *
98 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
99 + *
100 + * This program is free software; you can redistribute it and/or modify it
101 + * under the terms of version 2 of the GNU General Public License
102 + * as published by the Free Software Foundation.
103 + *
104 + * The code is based on publicly available information:
105 + * - Intel IXP4xx Developer's Manual and other e-papers
106 + * - Intel IXP400 Access Library Software (BSD license)
107 + * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
108 + * Thanks, Christian.
109 + */
110 +
111 +#include <linux/dma-mapping.h>
112 +#include <linux/firmware.h>
113 +#include <linux/kernel.h>
114 +#include <linux/module.h>
115 +#include <linux/slab.h>
116 +#include <asm/delay.h>
117 +#include <asm/io.h>
118 +#include <asm/arch/npe.h>
119 +
120 +#define DEBUG_MSG 0
121 +#define DEBUG_FW 0
122 +
123 +#define NPE_COUNT 3
124 +#define MAX_RETRIES 1000 /* microseconds */
125 +#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
126 +#define NPE_46X_DATA_SIZE 0x1000
127 +#define NPE_A_42X_INSTR_SIZE 0x1000
128 +#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
129 +#define NPE_46X_INSTR_SIZE 0x1000
130 +#define REGS_SIZE 0x1000
131 +
132 +#define NPE_PHYS_REG 32
133 +
134 +#define FW_MAGIC 0xFEEDF00D
135 +#define FW_BLOCK_TYPE_INSTR 0x0
136 +#define FW_BLOCK_TYPE_DATA 0x1
137 +#define FW_BLOCK_TYPE_EOF 0xF
138 +
139 +/* NPE exec status (read) and command (write) */
140 +#define CMD_NPE_STEP 0x01
141 +#define CMD_NPE_START 0x02
142 +#define CMD_NPE_STOP 0x03
143 +#define CMD_NPE_CLR_PIPE 0x04
144 +#define CMD_CLR_PROFILE_CNT 0x0C
145 +#define CMD_RD_INS_MEM 0x10 /* instruction memory */
146 +#define CMD_WR_INS_MEM 0x11
147 +#define CMD_RD_DATA_MEM 0x12 /* data memory */
148 +#define CMD_WR_DATA_MEM 0x13
149 +#define CMD_RD_ECS_REG 0x14 /* exec access register */
150 +#define CMD_WR_ECS_REG 0x15
151 +
152 +#define STAT_RUN 0x80000000
153 +#define STAT_STOP 0x40000000
154 +#define STAT_CLEAR 0x20000000
155 +#define STAT_ECS_K 0x00800000 /* pipeline clean */
156 +
157 +#define NPE_STEVT 0x1B
158 +#define NPE_STARTPC 0x1C
159 +#define NPE_REGMAP 0x1E
160 +#define NPE_CINDEX 0x1F
161 +
162 +#define INSTR_WR_REG_SHORT 0x0000C000
163 +#define INSTR_WR_REG_BYTE 0x00004000
164 +#define INSTR_RD_FIFO 0x0F888220
165 +#define INSTR_RESET_MBOX 0x0FAC8210
166 +
167 +#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
168 +#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
169 +#define ECS_BG_CTXT_REG_2 0x02
170 +#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
171 +#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
172 +#define ECS_PRI_1_CTXT_REG_2 0x06
173 +#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
174 +#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
175 +#define ECS_PRI_2_CTXT_REG_2 0x0A
176 +#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
177 +#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
178 +#define ECS_DBG_CTXT_REG_2 0x0E
179 +#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
180 +
181 +#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
182 +#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
183 +#define ECS_REG_0_LDUR_BITS 8
184 +#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
185 +#define ECS_REG_1_CCTXT_BITS 16
186 +#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
187 +#define ECS_REG_1_SELCTXT_BITS 0
188 +#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
189 +#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
190 +#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
191 +
192 +/* NPE watchpoint_fifo register bit */
193 +#define WFIFO_VALID 0x80000000
194 +
195 +/* NPE messaging_status register bit definitions */
196 +#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
197 +#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
198 +#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
199 +#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
200 +#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
201 +#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
202 +#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
203 +#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
204 +
205 +/* NPE messaging_control register bit definitions */
206 +#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
207 +#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
208 +#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
209 +#define MSGCTL_IN_FIFO_WRITE 0x02000000
210 +
211 +/* NPE mailbox_status value for reset */
212 +#define RESET_MBOX_STAT 0x0000F0F0
213 +
214 +const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
215 +
216 +#define print_npe(pri, npe, fmt, ...) \
217 + printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
218 +
219 +#if DEBUG_MSG
220 +#define debug_msg(npe, fmt, ...) \
221 + print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
222 +#else
223 +#define debug_msg(npe, fmt, ...)
224 +#endif
225 +
226 +static struct {
227 + u32 reg, val;
228 +}ecs_reset[] = {
229 + { ECS_BG_CTXT_REG_0, 0xA0000000 },
230 + { ECS_BG_CTXT_REG_1, 0x01000000 },
231 + { ECS_BG_CTXT_REG_2, 0x00008000 },
232 + { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
233 + { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
234 + { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
235 + { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
236 + { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
237 + { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
238 + { ECS_DBG_CTXT_REG_0, 0x20000000 },
239 + { ECS_DBG_CTXT_REG_1, 0x00000000 },
240 + { ECS_DBG_CTXT_REG_2, 0x001E0000 },
241 + { ECS_INSTRUCT_REG, 0x1003C00F },
242 +};
243 +
244 +static struct npe npe_tab[NPE_COUNT] = {
245 + {
246 + .id = 0,
247 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
248 + .regs_phys = IXP4XX_NPEA_BASE_PHYS,
249 + }, {
250 + .id = 1,
251 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
252 + .regs_phys = IXP4XX_NPEB_BASE_PHYS,
253 + }, {
254 + .id = 2,
255 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
256 + .regs_phys = IXP4XX_NPEC_BASE_PHYS,
257 + }
258 +};
259 +
260 +int npe_running(struct npe *npe)
261 +{
262 + return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
263 +}
264 +
265 +static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
266 +{
267 + __raw_writel(data, &npe->regs->exec_data);
268 + __raw_writel(addr, &npe->regs->exec_addr);
269 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
270 +}
271 +
272 +static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
273 +{
274 + __raw_writel(addr, &npe->regs->exec_addr);
275 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
276 + /* Iintroduce extra read cycles after issuing read command to NPE
277 + so that we read the register after the NPE has updated it.
278 + This is to overcome race condition between XScale and NPE */
279 + __raw_readl(&npe->regs->exec_data);
280 + __raw_readl(&npe->regs->exec_data);
281 + return __raw_readl(&npe->regs->exec_data);
282 +}
283 +
284 +static void npe_clear_active(struct npe *npe, u32 reg)
285 +{
286 + u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
287 + npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
288 +}
289 +
290 +static void npe_start(struct npe *npe)
291 +{
292 + /* ensure only Background Context Stack Level is active */
293 + npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
294 + npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
295 + npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
296 +
297 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
298 + __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
299 +}
300 +
301 +static void npe_stop(struct npe *npe)
302 +{
303 + __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
304 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
305 +}
306 +
307 +static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
308 + u32 ldur)
309 +{
310 + u32 wc;
311 + int i;
312 +
313 + /* set the Active bit, and the LDUR, in the debug level */
314 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
315 + ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
316 +
317 + /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
318 + the instruction, and set SELCTXT at ECS DEBUG Level to specify
319 + which context store to access.
320 + Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
321 + */
322 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
323 + (ctx << ECS_REG_1_CCTXT_BITS) |
324 + (ctx << ECS_REG_1_SELCTXT_BITS));
325 +
326 + /* clear the pipeline */
327 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
328 +
329 + /* load NPE instruction into the instruction register */
330 + npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
331 +
332 + /* we need this value later to wait for completion of NPE execution
333 + step */
334 + wc = __raw_readl(&npe->regs->watch_count);
335 +
336 + /* issue a Step One command via the Execution Control register */
337 + __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
338 +
339 + /* Watch Count register increments when NPE completes an instruction */
340 + for (i = 0; i < MAX_RETRIES; i++) {
341 + if (wc != __raw_readl(&npe->regs->watch_count))
342 + return 0;
343 + udelay(1);
344 + }
345 +
346 + print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
347 + return -ETIMEDOUT;
348 +}
349 +
350 +static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
351 + u8 val, u32 ctx)
352 +{
353 + /* here we build the NPE assembler instruction: mov8 d0, #0 */
354 + u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
355 + addr << 9 | /* base Operand */
356 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
357 + (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
358 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
359 +}
360 +
361 +static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
362 + u16 val, u32 ctx)
363 +{
364 + /* here we build the NPE assembler instruction: mov16 d0, #0 */
365 + u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
366 + addr << 9 | /* base Operand */
367 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
368 + (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
369 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
370 +}
371 +
372 +static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
373 + u32 val, u32 ctx)
374 +{
375 + /* write in 16 bit steps first the high and then the low value */
376 + if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
377 + return -ETIMEDOUT;
378 + return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
379 +}
380 +
381 +static int npe_reset(struct npe *npe)
382 +{
383 + u32 val, ctl, exec_count, ctx_reg2;
384 + int i;
385 +
386 + ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
387 + 0x3F3FFFFF;
388 +
389 + /* disable parity interrupt */
390 + __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
391 +
392 + /* pre exec - debug instruction */
393 + /* turn off the halt bit by clearing Execution Count register. */
394 + exec_count = __raw_readl(&npe->regs->exec_count);
395 + __raw_writel(0, &npe->regs->exec_count);
396 + /* ensure that IF and IE are on (temporarily), so that we don't end up
397 + stepping forever */
398 + ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
399 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
400 + ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
401 +
402 + /* clear the FIFOs */
403 + while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
404 + ;
405 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
406 + /* read from the outFIFO until empty */
407 + print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
408 + __raw_readl(&npe->regs->in_out_fifo));
409 +
410 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
411 + /* step execution of the NPE intruction to read inFIFO using
412 + the Debug Executing Context stack */
413 + if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
414 + return -ETIMEDOUT;
415 +
416 + /* reset the mailbox reg from the XScale side */
417 + __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
418 + /* from NPE side */
419 + if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
420 + return -ETIMEDOUT;
421 +
422 + /* Reset the physical registers in the NPE register file */
423 + for (val = 0; val < NPE_PHYS_REG; val++) {
424 + if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
425 + return -ETIMEDOUT;
426 + /* address is either 0 or 4 */
427 + if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
428 + return -ETIMEDOUT;
429 + }
430 +
431 + /* Reset the context store = each context's Context Store registers */
432 +
433 + /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
434 + for Background ECS, to set where NPE starts executing code */
435 + val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
436 + val &= ~ECS_REG_0_NEXTPC_MASK;
437 + val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
438 + npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
439 +
440 + for (i = 0; i < 16; i++) {
441 + if (i) { /* Context 0 has no STEVT nor STARTPC */
442 + /* STEVT = off, 0x80 */
443 + if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
444 + return -ETIMEDOUT;
445 + if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
446 + return -ETIMEDOUT;
447 + }
448 + /* REGMAP = d0->p0, d8->p2, d16->p4 */
449 + if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
450 + return -ETIMEDOUT;
451 + if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
452 + return -ETIMEDOUT;
453 + }
454 +
455 + /* post exec */
456 + /* clear active bit in debug level */
457 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
458 + /* clear the pipeline */
459 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
460 + /* restore previous values */
461 + __raw_writel(exec_count, &npe->regs->exec_count);
462 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
463 +
464 + /* write reset values to Execution Context Stack registers */
465 + for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
466 + npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
467 + ecs_reset[val].val);
468 +
469 + /* clear the profile counter */
470 + __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
471 +
472 + __raw_writel(0, &npe->regs->exec_count);
473 + __raw_writel(0, &npe->regs->action_points[0]);
474 + __raw_writel(0, &npe->regs->action_points[1]);
475 + __raw_writel(0, &npe->regs->action_points[2]);
476 + __raw_writel(0, &npe->regs->action_points[3]);
477 + __raw_writel(0, &npe->regs->watch_count);
478 +
479 + val = ixp4xx_read_fuses();
480 + /* reset the NPE */
481 + ixp4xx_write_fuses(val & ~(IXP4XX_FUSE_RESET_NPEA << npe->id));
482 + for (i = 0; i < MAX_RETRIES; i++) {
483 + if (!(ixp4xx_read_fuses() &
484 + (IXP4XX_FUSE_RESET_NPEA << npe->id)))
485 + break; /* reset completed */
486 + udelay(1);
487 + }
488 + if (i == MAX_RETRIES)
489 + return -ETIMEDOUT;
490 +
491 + /* deassert reset */
492 + ixp4xx_write_fuses(val | (IXP4XX_FUSE_RESET_NPEA << npe->id));
493 + for (i = 0; i < MAX_RETRIES; i++) {
494 + if (ixp4xx_read_fuses() & (IXP4XX_FUSE_RESET_NPEA << npe->id))
495 + break; /* NPE is back alive */
496 + udelay(1);
497 + }
498 + if (i == MAX_RETRIES)
499 + return -ETIMEDOUT;
500 +
501 + npe_stop(npe);
502 +
503 + /* restore NPE configuration bus Control Register - parity settings */
504 + __raw_writel(ctl, &npe->regs->messaging_control);
505 + return 0;
506 +}
507 +
508 +
509 +int npe_send_message(struct npe *npe, const void *msg, const char *what)
510 +{
511 + const u32 *send = msg;
512 + int cycles = 0;
513 +
514 + debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
515 + what, send[0], send[1]);
516 +
517 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
518 + debug_msg(npe, "NPE input FIFO not empty\n");
519 + return -EIO;
520 + }
521 +
522 + __raw_writel(send[0], &npe->regs->in_out_fifo);
523 +
524 + if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
525 + debug_msg(npe, "NPE input FIFO full\n");
526 + return -EIO;
527 + }
528 +
529 + __raw_writel(send[1], &npe->regs->in_out_fifo);
530 +
531 + while ((cycles < MAX_RETRIES) &&
532 + (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
533 + udelay(1);
534 + cycles++;
535 + }
536 +
537 + if (cycles == MAX_RETRIES) {
538 + debug_msg(npe, "Timeout sending message\n");
539 + return -ETIMEDOUT;
540 + }
541 +
542 + debug_msg(npe, "Sending a message took %i cycles\n", cycles);
543 + return 0;
544 +}
545 +
546 +int npe_recv_message(struct npe *npe, void *msg, const char *what)
547 +{
548 + u32 *recv = msg;
549 + int cycles = 0, cnt = 0;
550 +
551 + debug_msg(npe, "Trying to receive message %s\n", what);
552 +
553 + while (cycles < MAX_RETRIES) {
554 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
555 + recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
556 + if (cnt == 2)
557 + break;
558 + } else {
559 + udelay(1);
560 + cycles++;
561 + }
562 + }
563 +
564 + switch(cnt) {
565 + case 1:
566 + debug_msg(npe, "Received [%08X]\n", recv[0]);
567 + break;
568 + case 2:
569 + debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
570 + break;
571 + }
572 +
573 + if (cycles == MAX_RETRIES) {
574 + debug_msg(npe, "Timeout waiting for message\n");
575 + return -ETIMEDOUT;
576 + }
577 +
578 + debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
579 + return 0;
580 +}
581 +
582 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
583 +{
584 + int result;
585 + u32 *send = msg, recv[2];
586 +
587 + if ((result = npe_send_message(npe, msg, what)) != 0)
588 + return result;
589 + if ((result = npe_recv_message(npe, recv, what)) != 0)
590 + return result;
591 +
592 + if ((recv[0] != send[0]) || (recv[1] != send[1])) {
593 + debug_msg(npe, "Message %s: unexpected message received\n",
594 + what);
595 + return -EIO;
596 + }
597 + return 0;
598 +}
599 +
600 +
601 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
602 +{
603 + const struct firmware *fw_entry;
604 +
605 + struct dl_block {
606 + u32 type;
607 + u32 offset;
608 + } *blk;
609 +
610 + struct dl_image {
611 + u32 magic;
612 + u32 id;
613 + u32 size;
614 + union {
615 + u32 data[0];
616 + struct dl_block blocks[0];
617 + };
618 + } *image;
619 +
620 + struct dl_codeblock {
621 + u32 npe_addr;
622 + u32 size;
623 + u32 data[0];
624 + } *cb;
625 +
626 + int i, j, err, data_size, instr_size, blocks, table_end;
627 + u32 cmd;
628 +
629 + if ((err = request_firmware(&fw_entry, name, dev)) != 0)
630 + return err;
631 +
632 + err = -EINVAL;
633 + if (fw_entry->size < sizeof(struct dl_image)) {
634 + print_npe(KERN_ERR, npe, "incomplete firmware file\n");
635 + goto err;
636 + }
637 + image = (struct dl_image*)fw_entry->data;
638 +
639 +#if DEBUG_FW
640 + print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
641 + image->magic, image->id, image->size, image->size * 4);
642 +#endif
643 +
644 + if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
645 + image->id = swab32(image->id);
646 + image->size = swab32(image->size);
647 + } else if (image->magic != FW_MAGIC) {
648 + print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
649 + image->magic);
650 + goto err;
651 + }
652 + if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
653 + print_npe(KERN_ERR, npe,
654 + "inconsistent size of firmware file\n");
655 + goto err;
656 + }
657 + if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
658 + print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
659 + goto err;
660 + }
661 + if (image->magic == swab32(FW_MAGIC))
662 + for (i = 0; i < image->size; i++)
663 + image->data[i] = swab32(image->data[i]);
664 +
665 + if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
666 + print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
667 + "IXP42x\n");
668 + goto err;
669 + }
670 +
671 + if (npe_running(npe)) {
672 + print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
673 + "already running\n");
674 + err = -EBUSY;
675 + goto err;
676 + }
677 +#if 0
678 + npe_stop(npe);
679 + npe_reset(npe);
680 +#endif
681 +
682 + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
683 + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
684 + (image->id >> 8) & 0xFF, image->id & 0xFF);
685 +
686 + if (!cpu_is_ixp46x()) {
687 + if (!npe->id)
688 + instr_size = NPE_A_42X_INSTR_SIZE;
689 + else
690 + instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
691 + data_size = NPE_42X_DATA_SIZE;
692 + } else {
693 + instr_size = NPE_46X_INSTR_SIZE;
694 + data_size = NPE_46X_DATA_SIZE;
695 + }
696 +
697 + for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
698 + blocks++)
699 + if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
700 + break;
701 + if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
702 + print_npe(KERN_INFO, npe, "firmware EOF block marker not "
703 + "found\n");
704 + goto err;
705 + }
706 +
707 +#if DEBUG_FW
708 + print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
709 +#endif
710 +
711 + table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
712 + for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
713 + if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
714 + || blk->offset < table_end) {
715 + print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
716 + "firmware block #%i\n", blk->offset, i);
717 + goto err;
718 + }
719 +
720 + cb = (struct dl_codeblock*)&image->data[blk->offset];
721 + if (blk->type == FW_BLOCK_TYPE_INSTR) {
722 + if (cb->npe_addr + cb->size > instr_size)
723 + goto too_big;
724 + cmd = CMD_WR_INS_MEM;
725 + } else if (blk->type == FW_BLOCK_TYPE_DATA) {
726 + if (cb->npe_addr + cb->size > data_size)
727 + goto too_big;
728 + cmd = CMD_WR_DATA_MEM;
729 + } else {
730 + print_npe(KERN_INFO, npe, "invalid firmware block #%i "
731 + "type 0x%X\n", i, blk->type);
732 + goto err;
733 + }
734 + if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
735 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
736 + "fit in firmware image: type %c, start 0x%X,"
737 + " length 0x%X\n", i,
738 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
739 + cb->npe_addr, cb->size);
740 + goto err;
741 + }
742 +
743 + for (j = 0; j < cb->size; j++)
744 + npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
745 + }
746 +
747 + npe_start(npe);
748 + if (!npe_running(npe))
749 + print_npe(KERN_ERR, npe, "unable to start\n");
750 + release_firmware(fw_entry);
751 + return 0;
752 +
753 +too_big:
754 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
755 + "memory: type %c, start 0x%X, length 0x%X\n", i,
756 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
757 + cb->npe_addr, cb->size);
758 +err:
759 + release_firmware(fw_entry);
760 + return err;
761 +}
762 +
763 +
764 +struct npe *npe_request(int id)
765 +{
766 + if (id < NPE_COUNT)
767 + if (npe_tab[id].valid)
768 + if (try_module_get(THIS_MODULE))
769 + return &npe_tab[id];
770 + return NULL;
771 +}
772 +
773 +void npe_release(struct npe *npe)
774 +{
775 + module_put(THIS_MODULE);
776 +}
777 +
778 +
779 +static int __init npe_init_module(void)
780 +{
781 +
782 + int i, found = 0;
783 +
784 + for (i = 0; i < NPE_COUNT; i++) {
785 + struct npe *npe = &npe_tab[i];
786 + if (!(ixp4xx_read_fuses() & (IXP4XX_FUSE_RESET_NPEA << i)))
787 + continue; /* NPE already disabled or not present */
788 + if (!(npe->mem_res = request_mem_region(npe->regs_phys,
789 + REGS_SIZE,
790 + npe_name(npe)))) {
791 + print_npe(KERN_ERR, npe,
792 + "failed to request memory region\n");
793 + continue;
794 + }
795 +
796 + if (npe_reset(npe))
797 + continue;
798 + npe->valid = 1;
799 + found++;
800 + }
801 +
802 + if (!found)
803 + return -ENOSYS;
804 + return 0;
805 +}
806 +
807 +static void __exit npe_cleanup_module(void)
808 +{
809 + int i;
810 +
811 + for (i = 0; i < NPE_COUNT; i++)
812 + if (npe_tab[i].mem_res) {
813 + npe_reset(&npe_tab[i]);
814 + release_resource(npe_tab[i].mem_res);
815 + }
816 +}
817 +
818 +module_init(npe_init_module);
819 +module_exit(npe_cleanup_module);
820 +
821 +MODULE_AUTHOR("Krzysztof Halasa");
822 +MODULE_LICENSE("GPL v2");
823 +
824 +EXPORT_SYMBOL(npe_names);
825 +EXPORT_SYMBOL(npe_running);
826 +EXPORT_SYMBOL(npe_request);
827 +EXPORT_SYMBOL(npe_release);
828 +EXPORT_SYMBOL(npe_load_firmware);
829 +EXPORT_SYMBOL(npe_send_message);
830 +EXPORT_SYMBOL(npe_recv_message);
831 +EXPORT_SYMBOL(npe_send_recv_message);
832 diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
833 --- linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c 1970-01-01 01:00:00.000000000 +0100
834 +++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c 2007-10-22 19:19:41.000000000 +0200
835 @@ -0,0 +1,274 @@
836 +/*
837 + * Intel IXP4xx Queue Manager driver for Linux
838 + *
839 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
840 + *
841 + * This program is free software; you can redistribute it and/or modify it
842 + * under the terms of version 2 of the GNU General Public License
843 + * as published by the Free Software Foundation.
844 + */
845 +
846 +#include <linux/ioport.h>
847 +#include <linux/interrupt.h>
848 +#include <linux/kernel.h>
849 +#include <linux/module.h>
850 +#include <asm/arch/qmgr.h>
851 +
852 +#define DEBUG 0
853 +
854 +struct qmgr_regs __iomem *qmgr_regs;
855 +static struct resource *mem_res;
856 +static spinlock_t qmgr_lock;
857 +static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
858 +static void (*irq_handlers[HALF_QUEUES])(void *pdev);
859 +static void *irq_pdevs[HALF_QUEUES];
860 +
861 +void qmgr_set_irq(unsigned int queue, int src,
862 + void (*handler)(void *pdev), void *pdev)
863 +{
864 + u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
865 + int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
866 + unsigned long flags;
867 +
868 + src &= 7;
869 + spin_lock_irqsave(&qmgr_lock, flags);
870 + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
871 + irq_handlers[queue] = handler;
872 + irq_pdevs[queue] = pdev;
873 + spin_unlock_irqrestore(&qmgr_lock, flags);
874 +}
875 +
876 +
877 +static irqreturn_t qmgr_irq1(int irq, void *pdev)
878 +{
879 + int i;
880 + u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
881 + __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
882 +
883 + for (i = 0; i < HALF_QUEUES; i++)
884 + if (val & (1 << i))
885 + irq_handlers[i](irq_pdevs[i]);
886 +
887 + return val ? IRQ_HANDLED : 0;
888 +}
889 +
890 +
891 +void qmgr_enable_irq(unsigned int queue)
892 +{
893 + unsigned long flags;
894 +
895 + spin_lock_irqsave(&qmgr_lock, flags);
896 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
897 + &qmgr_regs->irqen[0]);
898 + spin_unlock_irqrestore(&qmgr_lock, flags);
899 +}
900 +
901 +void qmgr_disable_irq(unsigned int queue)
902 +{
903 + unsigned long flags;
904 +
905 + spin_lock_irqsave(&qmgr_lock, flags);
906 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
907 + &qmgr_regs->irqen[0]);
908 + spin_unlock_irqrestore(&qmgr_lock, flags);
909 +}
910 +
911 +static inline void shift_mask(u32 *mask)
912 +{
913 + mask[3] = mask[3] << 1 | mask[2] >> 31;
914 + mask[2] = mask[2] << 1 | mask[1] >> 31;
915 + mask[1] = mask[1] << 1 | mask[0] >> 31;
916 + mask[0] <<= 1;
917 +}
918 +
919 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
920 + unsigned int nearly_empty_watermark,
921 + unsigned int nearly_full_watermark)
922 +{
923 + u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
924 + int err;
925 +
926 + if (queue >= HALF_QUEUES)
927 + return -ERANGE;
928 +
929 + if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
930 + return -EINVAL;
931 +
932 + switch (len) {
933 + case 16:
934 + cfg = 0 << 24;
935 + mask[0] = 0x1;
936 + break;
937 + case 32:
938 + cfg = 1 << 24;
939 + mask[0] = 0x3;
940 + break;
941 + case 64:
942 + cfg = 2 << 24;
943 + mask[0] = 0xF;
944 + break;
945 + case 128:
946 + cfg = 3 << 24;
947 + mask[0] = 0xFF;
948 + break;
949 + default:
950 + return -EINVAL;
951 + }
952 +
953 + cfg |= nearly_empty_watermark << 26;
954 + cfg |= nearly_full_watermark << 29;
955 + len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
956 + mask[1] = mask[2] = mask[3] = 0;
957 +
958 + if (!try_module_get(THIS_MODULE))
959 + return -ENODEV;
960 +
961 + spin_lock_irq(&qmgr_lock);
962 + if (__raw_readl(&qmgr_regs->sram[queue])) {
963 + err = -EBUSY;
964 + goto err;
965 + }
966 +
967 + while (1) {
968 + if (!(used_sram_bitmap[0] & mask[0]) &&
969 + !(used_sram_bitmap[1] & mask[1]) &&
970 + !(used_sram_bitmap[2] & mask[2]) &&
971 + !(used_sram_bitmap[3] & mask[3]))
972 + break; /* found free space */
973 +
974 + addr++;
975 + shift_mask(mask);
976 + if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
977 + printk(KERN_ERR "qmgr: no free SRAM space for"
978 + " queue %i\n", queue);
979 + err = -ENOMEM;
980 + goto err;
981 + }
982 + }
983 +
984 + used_sram_bitmap[0] |= mask[0];
985 + used_sram_bitmap[1] |= mask[1];
986 + used_sram_bitmap[2] |= mask[2];
987 + used_sram_bitmap[3] |= mask[3];
988 + __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
989 + spin_unlock_irq(&qmgr_lock);
990 +
991 +#if DEBUG
992 + printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n",
993 + queue, addr);
994 +#endif
995 + return 0;
996 +
997 +err:
998 + spin_unlock_irq(&qmgr_lock);
999 + module_put(THIS_MODULE);
1000 + return err;
1001 +}
1002 +
1003 +void qmgr_release_queue(unsigned int queue)
1004 +{
1005 + u32 cfg, addr, mask[4];
1006 +
1007 + BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
1008 +
1009 + spin_lock_irq(&qmgr_lock);
1010 + cfg = __raw_readl(&qmgr_regs->sram[queue]);
1011 + addr = (cfg >> 14) & 0xFF;
1012 +
1013 + BUG_ON(!addr); /* not requested */
1014 +
1015 + switch ((cfg >> 24) & 3) {
1016 + case 0: mask[0] = 0x1; break;
1017 + case 1: mask[0] = 0x3; break;
1018 + case 2: mask[0] = 0xF; break;
1019 + case 3: mask[0] = 0xFF; break;
1020 + }
1021 +
1022 + while (addr--)
1023 + shift_mask(mask);
1024 +
1025 + __raw_writel(0, &qmgr_regs->sram[queue]);
1026 +
1027 + used_sram_bitmap[0] &= ~mask[0];
1028 + used_sram_bitmap[1] &= ~mask[1];
1029 + used_sram_bitmap[2] &= ~mask[2];
1030 + used_sram_bitmap[3] &= ~mask[3];
1031 + irq_handlers[queue] = NULL; /* catch IRQ bugs */
1032 + spin_unlock_irq(&qmgr_lock);
1033 +
1034 + module_put(THIS_MODULE);
1035 +#if DEBUG
1036 + printk(KERN_DEBUG "qmgr: released queue %i\n", queue);
1037 +#endif
1038 +}
1039 +
1040 +static int qmgr_init(void)
1041 +{
1042 + int i, err;
1043 + mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
1044 + IXP4XX_QMGR_REGION_SIZE,
1045 + "IXP4xx Queue Manager");
1046 + if (mem_res == NULL)
1047 + return -EBUSY;
1048 +
1049 + qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1050 + if (qmgr_regs == NULL) {
1051 + err = -ENOMEM;
1052 + goto error_map;
1053 + }
1054 +
1055 + /* reset qmgr registers */
1056 + for (i = 0; i < 4; i++) {
1057 + __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
1058 + __raw_writel(0, &qmgr_regs->irqsrc[i]);
1059 + }
1060 + for (i = 0; i < 2; i++) {
1061 + __raw_writel(0, &qmgr_regs->stat2[i]);
1062 + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
1063 + __raw_writel(0, &qmgr_regs->irqen[i]);
1064 + }
1065 +
1066 + for (i = 0; i < QUEUES; i++)
1067 + __raw_writel(0, &qmgr_regs->sram[i]);
1068 +
1069 + err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
1070 + "IXP4xx Queue Manager", NULL);
1071 + if (err) {
1072 + printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
1073 + IRQ_IXP4XX_QM1);
1074 + goto error_irq;
1075 + }
1076 +
1077 + used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
1078 + spin_lock_init(&qmgr_lock);
1079 +
1080 + printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
1081 + return 0;
1082 +
1083 +error_irq:
1084 + iounmap(qmgr_regs);
1085 +error_map:
1086 + release_resource(mem_res);
1087 + return err;
1088 +}
1089 +
1090 +static void qmgr_remove(void)
1091 +{
1092 + free_irq(IRQ_IXP4XX_QM1, NULL);
1093 + synchronize_irq(IRQ_IXP4XX_QM1);
1094 + iounmap(qmgr_regs);
1095 + release_resource(mem_res);
1096 +}
1097 +
1098 +module_init(qmgr_init);
1099 +module_exit(qmgr_remove);
1100 +
1101 +MODULE_LICENSE("GPL v2");
1102 +MODULE_AUTHOR("Krzysztof Halasa");
1103 +
1104 +EXPORT_SYMBOL(qmgr_regs);
1105 +EXPORT_SYMBOL(qmgr_set_irq);
1106 +EXPORT_SYMBOL(qmgr_enable_irq);
1107 +EXPORT_SYMBOL(qmgr_disable_irq);
1108 +EXPORT_SYMBOL(qmgr_request_queue);
1109 +EXPORT_SYMBOL(qmgr_release_queue);
1110 diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/arm/Kconfig ixp4xx-nep.git/drivers/net/arm/Kconfig
1111 --- linux-2.6.23/drivers/net/arm/Kconfig 2007-10-09 22:31:38.000000000 +0200
1112 +++ ixp4xx-nep.git/drivers/net/arm/Kconfig 2007-10-22 19:20:02.000000000 +0200
1113 @@ -47,3 +47,13 @@
1114 help
1115 This is a driver for the ethernet hardware included in EP93xx CPUs.
1116 Say Y if you are building a kernel for EP93xx based devices.
1117 +
1118 +config IXP4XX_ETH
1119 + tristate "IXP4xx Ethernet support"
1120 + depends on NET_ETHERNET && ARM && ARCH_IXP4XX
1121 + select IXP4XX_NPE
1122 + select IXP4XX_QMGR
1123 + select MII
1124 + help
1125 + Say Y here if you want to use built-in Ethernet ports
1126 + on IXP4xx processor.
1127 diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/arm/Makefile ixp4xx-nep.git/drivers/net/arm/Makefile
1128 --- linux-2.6.23/drivers/net/arm/Makefile 2007-10-09 22:31:38.000000000 +0200
1129 +++ ixp4xx-nep.git/drivers/net/arm/Makefile 2007-10-22 19:20:02.000000000 +0200
1130 @@ -9,3 +9,4 @@
1131 obj-$(CONFIG_ARM_ETHER1) += ether1.o
1132 obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
1133 obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
1134 +obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o
1135 diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/arm/ixp4xx_eth.c ixp4xx-nep.git/drivers/net/arm/ixp4xx_eth.c
1136 --- linux-2.6.23/drivers/net/arm/ixp4xx_eth.c 1970-01-01 01:00:00.000000000 +0100
1137 +++ ixp4xx-nep.git/drivers/net/arm/ixp4xx_eth.c 2007-10-22 19:20:02.000000000 +0200
1138 @@ -0,0 +1,1258 @@
1139 +/*
1140 + * Intel IXP4xx Ethernet driver for Linux
1141 + *
1142 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
1143 + *
1144 + * This program is free software; you can redistribute it and/or modify it
1145 + * under the terms of version 2 of the GNU General Public License
1146 + * as published by the Free Software Foundation.
1147 + *
1148 + * Ethernet port config (0x00 is not present on IXP42X):
1149 + *
1150 + * logical port 0x00 0x10 0x20
1151 + * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
1152 + * physical PortId 2 0 1
1153 + * TX queue 23 24 25
1154 + * RX-free queue 26 27 28
1155 + * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
1156 + *
1157 + *
1158 + * Queue entries:
1159 + * bits 0 -> 1 - NPE ID (RX and TX-done)
1160 + * bits 0 -> 2 - priority (TX, per 802.1D)
1161 + * bits 3 -> 4 - port ID (user-set?)
1162 + * bits 5 -> 31 - physical descriptor address
1163 + */
1164 +
1165 +#include <linux/delay.h>
1166 +#include <linux/dma-mapping.h>
1167 +#include <linux/dmapool.h>
1168 +#include <linux/kernel.h>
1169 +#include <linux/mii.h>
1170 +#include <linux/platform_device.h>
1171 +#include <asm/io.h>
1172 +#include <asm/arch/npe.h>
1173 +#include <asm/arch/qmgr.h>
1174 +
1175 +#define DEBUG_QUEUES 0
1176 +#define DEBUG_DESC 0
1177 +#define DEBUG_RX 0
1178 +#define DEBUG_TX 0
1179 +#define DEBUG_PKT_BYTES 0
1180 +#define DEBUG_MDIO 0
1181 +#define DEBUG_CLOSE 0
1182 +
1183 +#define DRV_NAME "ixp4xx_eth"
1184 +
1185 +#define MAX_NPES 3
1186 +
1187 +#define RX_DESCS 64 /* also length of all RX queues */
1188 +#define TX_DESCS 16 /* also length of all TX queues */
1189 +#define TXDONE_QUEUE_LEN 64 /* dwords */
1190 +
1191 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
1192 +#define REGS_SIZE 0x1000
1193 +#define MAX_MRU 1536 /* 0x600 */
1194 +
1195 +#define MDIO_INTERVAL (3 * HZ)
1196 +#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
1197 +#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
1198 +#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
1199 +
1200 +#define NPE_ID(port_id) ((port_id) >> 4)
1201 +#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
1202 +#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
1203 +#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
1204 +#define TXDONE_QUEUE 31
1205 +
1206 +/* TX Control Registers */
1207 +#define TX_CNTRL0_TX_EN 0x01
1208 +#define TX_CNTRL0_HALFDUPLEX 0x02
1209 +#define TX_CNTRL0_RETRY 0x04
1210 +#define TX_CNTRL0_PAD_EN 0x08
1211 +#define TX_CNTRL0_APPEND_FCS 0x10
1212 +#define TX_CNTRL0_2DEFER 0x20
1213 +#define TX_CNTRL0_RMII 0x40 /* reduced MII */
1214 +#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
1215 +
1216 +/* RX Control Registers */
1217 +#define RX_CNTRL0_RX_EN 0x01
1218 +#define RX_CNTRL0_PADSTRIP_EN 0x02
1219 +#define RX_CNTRL0_SEND_FCS 0x04
1220 +#define RX_CNTRL0_PAUSE_EN 0x08
1221 +#define RX_CNTRL0_LOOP_EN 0x10
1222 +#define RX_CNTRL0_ADDR_FLTR_EN 0x20
1223 +#define RX_CNTRL0_RX_RUNT_EN 0x40
1224 +#define RX_CNTRL0_BCAST_DIS 0x80
1225 +#define RX_CNTRL1_DEFER_EN 0x01
1226 +
1227 +/* Core Control Register */
1228 +#define CORE_RESET 0x01
1229 +#define CORE_RX_FIFO_FLUSH 0x02
1230 +#define CORE_TX_FIFO_FLUSH 0x04
1231 +#define CORE_SEND_JAM 0x08
1232 +#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
1233 +
1234 +#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
1235 + TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
1236 + TX_CNTRL0_2DEFER)
1237 +#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
1238 +#define DEFAULT_CORE_CNTRL CORE_MDC_EN
1239 +
1240 +
1241 +/* NPE message codes */
1242 +#define NPE_GETSTATUS 0x00
1243 +#define NPE_EDB_SETPORTADDRESS 0x01
1244 +#define NPE_EDB_GETMACADDRESSDATABASE 0x02
1245 +#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
1246 +#define NPE_GETSTATS 0x04
1247 +#define NPE_RESETSTATS 0x05
1248 +#define NPE_SETMAXFRAMELENGTHS 0x06
1249 +#define NPE_VLAN_SETRXTAGMODE 0x07
1250 +#define NPE_VLAN_SETDEFAULTRXVID 0x08
1251 +#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
1252 +#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
1253 +#define NPE_VLAN_SETRXQOSENTRY 0x0B
1254 +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
1255 +#define NPE_STP_SETBLOCKINGSTATE 0x0D
1256 +#define NPE_FW_SETFIREWALLMODE 0x0E
1257 +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
1258 +#define NPE_PC_SETAPMACTABLE 0x11
1259 +#define NPE_SETLOOPBACK_MODE 0x12
1260 +#define NPE_PC_SETBSSIDTABLE 0x13
1261 +#define NPE_ADDRESS_FILTER_CONFIG 0x14
1262 +#define NPE_APPENDFCSCONFIG 0x15
1263 +#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
1264 +#define NPE_MAC_RECOVERY_START 0x17
1265 +
1266 +
1267 +#ifdef __ARMEB__
1268 +typedef struct sk_buff buffer_t;
1269 +#define free_buffer dev_kfree_skb
1270 +#define free_buffer_irq dev_kfree_skb_irq
1271 +#else
1272 +typedef void buffer_t;
1273 +#define free_buffer kfree
1274 +#define free_buffer_irq kfree
1275 +#endif
1276 +
1277 +struct eth_regs {
1278 + u32 tx_control[2], __res1[2]; /* 000 */
1279 + u32 rx_control[2], __res2[2]; /* 010 */
1280 + u32 random_seed, __res3[3]; /* 020 */
1281 + u32 partial_empty_threshold, __res4; /* 030 */
1282 + u32 partial_full_threshold, __res5; /* 038 */
1283 + u32 tx_start_bytes, __res6[3]; /* 040 */
1284 + u32 tx_deferral, rx_deferral,__res7[2]; /* 050 */
1285 + u32 tx_2part_deferral[2], __res8[2]; /* 060 */
1286 + u32 slot_time, __res9[3]; /* 070 */
1287 + u32 mdio_command[4]; /* 080 */
1288 + u32 mdio_status[4]; /* 090 */
1289 + u32 mcast_mask[6], __res10[2]; /* 0A0 */
1290 + u32 mcast_addr[6], __res11[2]; /* 0C0 */
1291 + u32 int_clock_threshold, __res12[3]; /* 0E0 */
1292 + u32 hw_addr[6], __res13[61]; /* 0F0 */
1293 + u32 core_control; /* 1FC */
1294 +};
1295 +
1296 +struct port {
1297 + struct resource *mem_res;
1298 + struct eth_regs __iomem *regs;
1299 + struct npe *npe;
1300 + struct net_device *netdev;
1301 + struct net_device_stats stat;
1302 + struct mii_if_info mii;
1303 + struct delayed_work mdio_thread;
1304 + struct eth_plat_info *plat;
1305 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
1306 + struct desc *desc_tab; /* coherent */
1307 + u32 desc_tab_phys;
1308 + int id; /* logical port ID */
1309 + u16 mii_bmcr;
1310 +};
1311 +
1312 +/* NPE message structure */
1313 +struct msg {
1314 +#ifdef __ARMEB__
1315 + u8 cmd, eth_id, byte2, byte3;
1316 + u8 byte4, byte5, byte6, byte7;
1317 +#else
1318 + u8 byte3, byte2, eth_id, cmd;
1319 + u8 byte7, byte6, byte5, byte4;
1320 +#endif
1321 +};
1322 +
1323 +/* Ethernet packet descriptor */
1324 +struct desc {
1325 + u32 next; /* pointer to next buffer, unused */
1326 +
1327 +#ifdef __ARMEB__
1328 + u16 buf_len; /* buffer length */
1329 + u16 pkt_len; /* packet length */
1330 + u32 data; /* pointer to data buffer in RAM */
1331 + u8 dest_id;
1332 + u8 src_id;
1333 + u16 flags;
1334 + u8 qos;
1335 + u8 padlen;
1336 + u16 vlan_tci;
1337 +#else
1338 + u16 pkt_len; /* packet length */
1339 + u16 buf_len; /* buffer length */
1340 + u32 data; /* pointer to data buffer in RAM */
1341 + u16 flags;
1342 + u8 src_id;
1343 + u8 dest_id;
1344 + u16 vlan_tci;
1345 + u8 padlen;
1346 + u8 qos;
1347 +#endif
1348 +
1349 +#ifdef __ARMEB__
1350 + u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
1351 + u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
1352 + u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
1353 +#else
1354 + u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
1355 + u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
1356 + u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
1357 +#endif
1358 +};
1359 +
1360 +
1361 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
1362 + (n) * sizeof(struct desc))
1363 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
1364 +
1365 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
1366 + ((n) + RX_DESCS) * sizeof(struct desc))
1367 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
1368 +
1369 +#ifndef __ARMEB__
1370 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
1371 +{
1372 + int i;
1373 + for (i = 0; i < cnt; i++)
1374 + dest[i] = swab32(src[i]);
1375 +}
1376 +#endif
1377 +
1378 +static spinlock_t mdio_lock;
1379 +static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
1380 +static int ports_open;
1381 +static struct port *npe_port_tab[MAX_NPES];
1382 +static struct dma_pool *dma_pool;
1383 +
1384 +
1385 +static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
1386 + int write, u16 cmd)
1387 +{
1388 + int cycles = 0;
1389 +
1390 + if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
1391 + printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
1392 + return 0;
1393 + }
1394 +
1395 + if (write) {
1396 + __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
1397 + __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
1398 + }
1399 + __raw_writel(((phy_id << 5) | location) & 0xFF,
1400 + &mdio_regs->mdio_command[2]);
1401 + __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
1402 + &mdio_regs->mdio_command[3]);
1403 +
1404 + while ((cycles < MAX_MDIO_RETRIES) &&
1405 + (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
1406 + udelay(1);
1407 + cycles++;
1408 + }
1409 +
1410 + if (cycles == MAX_MDIO_RETRIES) {
1411 + printk(KERN_ERR "%s: MII write failed\n", dev->name);
1412 + return 0;
1413 + }
1414 +
1415 +#if DEBUG_MDIO
1416 + printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
1417 + cycles);
1418 +#endif
1419 +
1420 + if (write)
1421 + return 0;
1422 +
1423 + if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
1424 + printk(KERN_ERR "%s: MII read failed\n", dev->name);
1425 + return 0;
1426 + }
1427 +
1428 + return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
1429 + (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
1430 +}
1431 +
1432 +static int mdio_read(struct net_device *dev, int phy_id, int location)
1433 +{
1434 + unsigned long flags;
1435 + u16 val;
1436 +
1437 + spin_lock_irqsave(&mdio_lock, flags);
1438 + val = mdio_cmd(dev, phy_id, location, 0, 0);
1439 + spin_unlock_irqrestore(&mdio_lock, flags);
1440 + return val;
1441 +}
1442 +
1443 +static void mdio_write(struct net_device *dev, int phy_id, int location,
1444 + int val)
1445 +{
1446 + unsigned long flags;
1447 +
1448 + spin_lock_irqsave(&mdio_lock, flags);
1449 + mdio_cmd(dev, phy_id, location, 1, val);
1450 + spin_unlock_irqrestore(&mdio_lock, flags);
1451 +}
1452 +
1453 +static void phy_reset(struct net_device *dev, int phy_id)
1454 +{
1455 + struct port *port = netdev_priv(dev);
1456 + int cycles = 0;
1457 +
1458 + mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
1459 +
1460 + while (cycles < MAX_MII_RESET_RETRIES) {
1461 + if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
1462 +#if DEBUG_MDIO
1463 + printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
1464 + dev->name, cycles);
1465 +#endif
1466 + return;
1467 + }
1468 + udelay(1);
1469 + cycles++;
1470 + }
1471 +
1472 + printk(KERN_ERR "%s: MII reset failed\n", dev->name);
1473 +}
1474 +
1475 +static void eth_set_duplex(struct port *port)
1476 +{
1477 + if (port->mii.full_duplex)
1478 + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
1479 + &port->regs->tx_control[0]);
1480 + else
1481 + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
1482 + &port->regs->tx_control[0]);
1483 +}
1484 +
1485 +
1486 +static void phy_check_media(struct port *port, int init)
1487 +{
1488 + if (mii_check_media(&port->mii, 1, init))
1489 + eth_set_duplex(port);
1490 + if (port->mii.force_media) { /* mii_check_media() doesn't work */
1491 + struct net_device *dev = port->netdev;
1492 + int cur_link = mii_link_ok(&port->mii);
1493 + int prev_link = netif_carrier_ok(dev);
1494 +
1495 + if (!prev_link && cur_link) {
1496 + printk(KERN_INFO "%s: link up\n", dev->name);
1497 + netif_carrier_on(dev);
1498 + } else if (prev_link && !cur_link) {
1499 + printk(KERN_INFO "%s: link down\n", dev->name);
1500 + netif_carrier_off(dev);
1501 + }
1502 + }
1503 +}
1504 +
1505 +
1506 +static void mdio_thread(struct work_struct *work)
1507 +{
1508 + struct port *port = container_of(work, struct port, mdio_thread.work);
1509 +
1510 + phy_check_media(port, 0);
1511 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1512 +}
1513 +
1514 +
1515 +static inline void debug_pkt(struct net_device *dev, const char *func,
1516 + u8 *data, int len)
1517 +{
1518 +#if DEBUG_PKT_BYTES
1519 + int i;
1520 +
1521 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
1522 + for (i = 0; i < len; i++) {
1523 + if (i >= DEBUG_PKT_BYTES)
1524 + break;
1525 + printk("%s%02X",
1526 + ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
1527 + data[i]);
1528 + }
1529 + printk("\n");
1530 +#endif
1531 +}
1532 +
1533 +
1534 +static inline void debug_desc(u32 phys, struct desc *desc)
1535 +{
1536 +#if DEBUG_DESC
1537 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
1538 + " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
1539 + phys, desc->next, desc->buf_len, desc->pkt_len,
1540 + desc->data, desc->dest_id, desc->src_id, desc->flags,
1541 + desc->qos, desc->padlen, desc->vlan_tci,
1542 + desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
1543 + desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
1544 + desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
1545 + desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
1546 +#endif
1547 +}
1548 +
1549 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
1550 +{
1551 +#if DEBUG_QUEUES
1552 + static struct {
1553 + int queue;
1554 + char *name;
1555 + } names[] = {
1556 + { TX_QUEUE(0x10), "TX#0 " },
1557 + { TX_QUEUE(0x20), "TX#1 " },
1558 + { TX_QUEUE(0x00), "TX#2 " },
1559 + { RXFREE_QUEUE(0x10), "RX-free#0 " },
1560 + { RXFREE_QUEUE(0x20), "RX-free#1 " },
1561 + { RXFREE_QUEUE(0x00), "RX-free#2 " },
1562 + { TXDONE_QUEUE, "TX-done " },
1563 + };
1564 + int i;
1565 +
1566 + for (i = 0; i < ARRAY_SIZE(names); i++)
1567 + if (names[i].queue == queue)
1568 + break;
1569 +
1570 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
1571 + i < ARRAY_SIZE(names) ? names[i].name : "",
1572 + is_get ? "->" : "<-", phys);
1573 +#endif
1574 +}
1575 +
1576 +static inline u32 queue_get_entry(unsigned int queue)
1577 +{
1578 + u32 phys = qmgr_get_entry(queue);
1579 + debug_queue(queue, 1, phys);
1580 + return phys;
1581 +}
1582 +
1583 +static inline int queue_get_desc(unsigned int queue, struct port *port,
1584 + int is_tx)
1585 +{
1586 + u32 phys, tab_phys, n_desc;
1587 + struct desc *tab;
1588 +
1589 + if (!(phys = queue_get_entry(queue)))
1590 + return -1;
1591 +
1592 + phys &= ~0x1F; /* mask out non-address bits */
1593 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
1594 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
1595 + n_desc = (phys - tab_phys) / sizeof(struct desc);
1596 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
1597 + debug_desc(phys, &tab[n_desc]);
1598 + BUG_ON(tab[n_desc].next);
1599 + return n_desc;
1600 +}
1601 +
1602 +static inline void queue_put_desc(unsigned int queue, u32 phys,
1603 + struct desc *desc)
1604 +{
1605 + debug_queue(queue, 0, phys);
1606 + debug_desc(phys, desc);
1607 + BUG_ON(phys & 0x1F);
1608 + qmgr_put_entry(queue, phys);
1609 + BUG_ON(qmgr_stat_overflow(queue));
1610 +}
1611 +
1612 +
1613 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
1614 +{
1615 +#ifdef __ARMEB__
1616 + dma_unmap_single(&port->netdev->dev, desc->data,
1617 + desc->buf_len, DMA_TO_DEVICE);
1618 +#else
1619 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
1620 + ALIGN((desc->data & 3) + desc->buf_len, 4),
1621 + DMA_TO_DEVICE);
1622 +#endif
1623 +}
1624 +
1625 +
1626 +static void eth_rx_irq(void *pdev)
1627 +{
1628 + struct net_device *dev = pdev;
1629 + struct port *port = netdev_priv(dev);
1630 +
1631 +#if DEBUG_RX
1632 + printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
1633 +#endif
1634 + qmgr_disable_irq(port->plat->rxq);
1635 + netif_rx_schedule(dev);
1636 +}
1637 +
1638 +static int eth_poll(struct net_device *dev, int *budget)
1639 +{
1640 + struct port *port = netdev_priv(dev);
1641 + unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
1642 + int quota = dev->quota, received = 0;
1643 +
1644 +#if DEBUG_RX
1645 + printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
1646 +#endif
1647 +
1648 + while (quota) {
1649 + struct sk_buff *skb;
1650 + struct desc *desc;
1651 + int n;
1652 +#ifdef __ARMEB__
1653 + struct sk_buff *temp;
1654 + u32 phys;
1655 +#endif
1656 +
1657 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
1658 + dev->quota -= received; /* No packet received */
1659 + *budget -= received;
1660 + received = 0;
1661 +#if DEBUG_RX
1662 + printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
1663 + dev->name);
1664 +#endif
1665 + netif_rx_complete(dev);
1666 + qmgr_enable_irq(rxq);
1667 + if (!qmgr_stat_empty(rxq) &&
1668 + netif_rx_reschedule(dev, 0)) {
1669 +#if DEBUG_RX
1670 + printk(KERN_DEBUG "%s: eth_poll"
1671 + " netif_rx_reschedule successed\n",
1672 + dev->name);
1673 +#endif
1674 + qmgr_disable_irq(rxq);
1675 + continue;
1676 + }
1677 +#if DEBUG_RX
1678 + printk(KERN_DEBUG "%s: eth_poll all done\n",
1679 + dev->name);
1680 +#endif
1681 + return 0; /* all work done */
1682 + }
1683 +
1684 + desc = rx_desc_ptr(port, n);
1685 +
1686 +#ifdef __ARMEB__
1687 + if ((skb = netdev_alloc_skb(dev, MAX_MRU)) != NULL) {
1688 + phys = dma_map_single(&dev->dev, skb->data,
1689 + MAX_MRU, DMA_FROM_DEVICE);
1690 + if (dma_mapping_error(phys)) {
1691 + dev_kfree_skb(skb);
1692 + skb = NULL;
1693 + }
1694 + }
1695 +#else
1696 + skb = netdev_alloc_skb(dev, desc->pkt_len);
1697 +#endif
1698 +
1699 + if (!skb) {
1700 + port->stat.rx_dropped++;
1701 + /* put the desc back on RX-ready queue */
1702 + desc->buf_len = MAX_MRU;
1703 + desc->pkt_len = 0;
1704 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1705 + continue;
1706 + }
1707 +
1708 + /* process received frame */
1709 +#ifdef __ARMEB__
1710 + temp = skb;
1711 + skb = port->rx_buff_tab[n];
1712 + dma_unmap_single(&dev->dev, desc->data,
1713 + MAX_MRU, DMA_FROM_DEVICE);
1714 +#else
1715 + dma_sync_single(&dev->dev, desc->data,
1716 + MAX_MRU, DMA_FROM_DEVICE);
1717 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
1718 + ALIGN(desc->pkt_len, 4) / 4);
1719 +#endif
1720 + skb_put(skb, desc->pkt_len);
1721 +
1722 + debug_pkt(dev, "eth_poll", skb->data, skb->len);
1723 +
1724 + skb->protocol = eth_type_trans(skb, dev);
1725 + dev->last_rx = jiffies;
1726 + port->stat.rx_packets++;
1727 + port->stat.rx_bytes += skb->len;
1728 + netif_receive_skb(skb);
1729 +
1730 + /* put the new buffer on RX-free queue */
1731 +#ifdef __ARMEB__
1732 + port->rx_buff_tab[n] = temp;
1733 + desc->data = phys;
1734 +#endif
1735 + desc->buf_len = MAX_MRU;
1736 + desc->pkt_len = 0;
1737 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1738 + quota--;
1739 + received++;
1740 + }
1741 + dev->quota -= received;
1742 + *budget -= received;
1743 +#if DEBUG_RX
1744 + printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
1745 +#endif
1746 + return 1; /* not all work done */
1747 +}
1748 +
1749 +
1750 +static void eth_txdone_irq(void *unused)
1751 +{
1752 + u32 phys;
1753 +
1754 +#if DEBUG_TX
1755 + printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
1756 +#endif
1757 + while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
1758 + u32 npe_id, n_desc;
1759 + struct port *port;
1760 + struct desc *desc;
1761 + int start;
1762 +
1763 + npe_id = phys & 3;
1764 + BUG_ON(npe_id >= MAX_NPES);
1765 + port = npe_port_tab[npe_id];
1766 + BUG_ON(!port);
1767 + phys &= ~0x1F; /* mask out non-address bits */
1768 + n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
1769 + BUG_ON(n_desc >= TX_DESCS);
1770 + desc = tx_desc_ptr(port, n_desc);
1771 + debug_desc(phys, desc);
1772 +
1773 + if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
1774 + port->stat.tx_packets++;
1775 + port->stat.tx_bytes += desc->pkt_len;
1776 +
1777 + dma_unmap_tx(port, desc);
1778 +#if DEBUG_TX
1779 + printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
1780 + port->netdev->name, port->tx_buff_tab[n_desc]);
1781 +#endif
1782 + free_buffer_irq(port->tx_buff_tab[n_desc]);
1783 + port->tx_buff_tab[n_desc] = NULL;
1784 + }
1785 +
1786 + start = qmgr_stat_empty(port->plat->txreadyq);
1787 + queue_put_desc(port->plat->txreadyq, phys, desc);
1788 + if (start) {
1789 +#if DEBUG_TX
1790 + printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
1791 + port->netdev->name);
1792 +#endif
1793 + netif_wake_queue(port->netdev);
1794 + }
1795 + }
1796 +}
1797 +
1798 +static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
1799 +{
1800 + struct port *port = netdev_priv(dev);
1801 + unsigned int txreadyq = port->plat->txreadyq;
1802 + int len, offset, bytes, n;
1803 + void *mem;
1804 + u32 phys;
1805 + struct desc *desc;
1806 +
1807 +#if DEBUG_TX
1808 + printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
1809 +#endif
1810 +
1811 + if (unlikely(skb->len > MAX_MRU)) {
1812 + dev_kfree_skb(skb);
1813 + port->stat.tx_errors++;
1814 + return NETDEV_TX_OK;
1815 + }
1816 +
1817 + debug_pkt(dev, "eth_xmit", skb->data, skb->len);
1818 +
1819 + len = skb->len;
1820 +#ifdef __ARMEB__
1821 + offset = 0; /* no need to keep alignment */
1822 + bytes = len;
1823 + mem = skb->data;
1824 +#else
1825 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
1826 + bytes = ALIGN(offset + len, 4);
1827 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
1828 + dev_kfree_skb(skb);
1829 + port->stat.tx_dropped++;
1830 + return NETDEV_TX_OK;
1831 + }
1832 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
1833 + dev_kfree_skb(skb);
1834 +#endif
1835 +
1836 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
1837 + if (dma_mapping_error(phys)) {
1838 +#ifdef __ARMEB__
1839 + dev_kfree_skb(skb);
1840 +#else
1841 + kfree(mem);
1842 +#endif
1843 + port->stat.tx_dropped++;
1844 + return NETDEV_TX_OK;
1845 + }
1846 +
1847 + n = queue_get_desc(txreadyq, port, 1);
1848 + BUG_ON(n < 0);
1849 + desc = tx_desc_ptr(port, n);
1850 +
1851 +#ifdef __ARMEB__
1852 + port->tx_buff_tab[n] = skb;
1853 +#else
1854 + port->tx_buff_tab[n] = mem;
1855 +#endif
1856 + desc->data = phys + offset;
1857 + desc->buf_len = desc->pkt_len = len;
1858 +
1859 + /* NPE firmware pads short frames with zeros internally */
1860 + wmb();
1861 + queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
1862 + dev->trans_start = jiffies;
1863 +
1864 + if (qmgr_stat_empty(txreadyq)) {
1865 +#if DEBUG_TX
1866 + printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
1867 +#endif
1868 + netif_stop_queue(dev);
1869 + /* we could miss TX ready interrupt */
1870 + if (!qmgr_stat_empty(txreadyq)) {
1871 +#if DEBUG_TX
1872 + printk(KERN_DEBUG "%s: eth_xmit ready again\n",
1873 + dev->name);
1874 +#endif
1875 + netif_wake_queue(dev);
1876 + }
1877 + }
1878 +
1879 +#if DEBUG_TX
1880 + printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
1881 +#endif
1882 + return NETDEV_TX_OK;
1883 +}
1884 +
1885 +
1886 +static struct net_device_stats *eth_stats(struct net_device *dev)
1887 +{
1888 + struct port *port = netdev_priv(dev);
1889 + return &port->stat;
1890 +}
1891 +
1892 +static void eth_set_mcast_list(struct net_device *dev)
1893 +{
1894 + struct port *port = netdev_priv(dev);
1895 + struct dev_mc_list *mclist = dev->mc_list;
1896 + u8 diffs[ETH_ALEN], *addr;
1897 + int cnt = dev->mc_count, i;
1898 +
1899 + if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
1900 + __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
1901 + &port->regs->rx_control[0]);
1902 + return;
1903 + }
1904 +
1905 + memset(diffs, 0, ETH_ALEN);
1906 + addr = mclist->dmi_addr; /* first MAC address */
1907 +
1908 + while (--cnt && (mclist = mclist->next))
1909 + for (i = 0; i < ETH_ALEN; i++)
1910 + diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
1911 +
1912 + for (i = 0; i < ETH_ALEN; i++) {
1913 + __raw_writel(addr[i], &port->regs->mcast_addr[i]);
1914 + __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
1915 + }
1916 +
1917 + __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
1918 + &port->regs->rx_control[0]);
1919 +}
1920 +
1921 +
1922 +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1923 +{
1924 + struct port *port = netdev_priv(dev);
1925 + unsigned int duplex_chg;
1926 + int err;
1927 +
1928 + if (!netif_running(dev))
1929 + return -EINVAL;
1930 + err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
1931 + if (duplex_chg)
1932 + eth_set_duplex(port);
1933 + return err;
1934 +}
1935 +
1936 +
1937 +static int request_queues(struct port *port)
1938 +{
1939 + int err;
1940 +
1941 + err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
1942 + if (err)
1943 + return err;
1944 +
1945 + err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
1946 + if (err)
1947 + goto rel_rxfree;
1948 +
1949 + err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
1950 + if (err)
1951 + goto rel_rx;
1952 +
1953 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
1954 + if (err)
1955 + goto rel_tx;
1956 +
1957 + /* TX-done queue handles skbs sent out by the NPEs */
1958 + if (!ports_open) {
1959 + err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
1960 + if (err)
1961 + goto rel_txready;
1962 + }
1963 + return 0;
1964 +
1965 +rel_txready:
1966 + qmgr_release_queue(port->plat->txreadyq);
1967 +rel_tx:
1968 + qmgr_release_queue(TX_QUEUE(port->id));
1969 +rel_rx:
1970 + qmgr_release_queue(port->plat->rxq);
1971 +rel_rxfree:
1972 + qmgr_release_queue(RXFREE_QUEUE(port->id));
1973 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1974 + port->netdev->name);
1975 + return err;
1976 +}
1977 +
1978 +static void release_queues(struct port *port)
1979 +{
1980 + qmgr_release_queue(RXFREE_QUEUE(port->id));
1981 + qmgr_release_queue(port->plat->rxq);
1982 + qmgr_release_queue(TX_QUEUE(port->id));
1983 + qmgr_release_queue(port->plat->txreadyq);
1984 +
1985 + if (!ports_open)
1986 + qmgr_release_queue(TXDONE_QUEUE);
1987 +}
1988 +
1989 +static int init_queues(struct port *port)
1990 +{
1991 + int i;
1992 +
1993 + if (!ports_open)
1994 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
1995 + POOL_ALLOC_SIZE, 32, 0)))
1996 + return -ENOMEM;
1997 +
1998 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1999 + &port->desc_tab_phys)))
2000 + return -ENOMEM;
2001 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
2002 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
2003 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
2004 +
2005 + /* Setup RX buffers */
2006 + for (i = 0; i < RX_DESCS; i++) {
2007 + struct desc *desc = rx_desc_ptr(port, i);
2008 + buffer_t *buff;
2009 + void *data;
2010 +#ifdef __ARMEB__
2011 + if (!(buff = netdev_alloc_skb(port->netdev, MAX_MRU)))
2012 + return -ENOMEM;
2013 + data = buff->data;
2014 +#else
2015 + if (!(buff = kmalloc(MAX_MRU, GFP_KERNEL)))
2016 + return -ENOMEM;
2017 + data = buff;
2018 +#endif
2019 + desc->buf_len = MAX_MRU;
2020 + desc->data = dma_map_single(&port->netdev->dev, data,
2021 + MAX_MRU, DMA_FROM_DEVICE);
2022 + if (dma_mapping_error(desc->data)) {
2023 + free_buffer(buff);
2024 + return -EIO;
2025 + }
2026 + port->rx_buff_tab[i] = buff;
2027 + }
2028 +
2029 + return 0;
2030 +}
2031 +
2032 +static void destroy_queues(struct port *port)
2033 +{
2034 + int i;
2035 +
2036 + if (port->desc_tab) {
2037 + for (i = 0; i < RX_DESCS; i++) {
2038 + struct desc *desc = rx_desc_ptr(port, i);
2039 + buffer_t *buff = port->rx_buff_tab[i];
2040 + if (buff) {
2041 + dma_unmap_single(&port->netdev->dev,
2042 + desc->data, MAX_MRU,
2043 + DMA_FROM_DEVICE);
2044 + free_buffer(buff);
2045 + }
2046 + }
2047 + for (i = 0; i < TX_DESCS; i++) {
2048 + struct desc *desc = tx_desc_ptr(port, i);
2049 + buffer_t *buff = port->tx_buff_tab[i];
2050 + if (buff) {
2051 + dma_unmap_tx(port, desc);
2052 + free_buffer(buff);
2053 + }
2054 + }
2055 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
2056 + port->desc_tab = NULL;
2057 + }
2058 +
2059 + if (!ports_open && dma_pool) {
2060 + dma_pool_destroy(dma_pool);
2061 + dma_pool = NULL;
2062 + }
2063 +}
2064 +
2065 +static int eth_open(struct net_device *dev)
2066 +{
2067 + struct port *port = netdev_priv(dev);
2068 + struct npe *npe = port->npe;
2069 + struct msg msg;
2070 + int i, err;
2071 +
2072 + if (!npe_running(npe)) {
2073 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
2074 + if (err)
2075 + return err;
2076 +
2077 + if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
2078 + printk(KERN_ERR "%s: %s not responding\n", dev->name,
2079 + npe_name(npe));
2080 + return -EIO;
2081 + }
2082 + }
2083 +
2084 + mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
2085 +
2086 + memset(&msg, 0, sizeof(msg));
2087 + msg.cmd = NPE_VLAN_SETRXQOSENTRY;
2088 + msg.eth_id = port->id;
2089 + msg.byte5 = port->plat->rxq | 0x80;
2090 + msg.byte7 = port->plat->rxq << 4;
2091 + for (i = 0; i < 8; i++) {
2092 + msg.byte3 = i;
2093 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
2094 + return -EIO;
2095 + }
2096 +
2097 + msg.cmd = NPE_EDB_SETPORTADDRESS;
2098 + msg.eth_id = PHYSICAL_ID(port->id);
2099 + msg.byte2 = dev->dev_addr[0];
2100 + msg.byte3 = dev->dev_addr[1];
2101 + msg.byte4 = dev->dev_addr[2];
2102 + msg.byte5 = dev->dev_addr[3];
2103 + msg.byte6 = dev->dev_addr[4];
2104 + msg.byte7 = dev->dev_addr[5];
2105 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
2106 + return -EIO;
2107 +
2108 + memset(&msg, 0, sizeof(msg));
2109 + msg.cmd = NPE_FW_SETFIREWALLMODE;
2110 + msg.eth_id = port->id;
2111 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
2112 + return -EIO;
2113 +
2114 + if ((err = request_queues(port)) != 0)
2115 + return err;
2116 +
2117 + if ((err = init_queues(port)) != 0) {
2118 + destroy_queues(port);
2119 + release_queues(port);
2120 + return err;
2121 + }
2122 +
2123 + for (i = 0; i < ETH_ALEN; i++)
2124 + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
2125 + __raw_writel(0x08, &port->regs->random_seed);
2126 + __raw_writel(0x12, &port->regs->partial_empty_threshold);
2127 + __raw_writel(0x30, &port->regs->partial_full_threshold);
2128 + __raw_writel(0x08, &port->regs->tx_start_bytes);
2129 + __raw_writel(0x15, &port->regs->tx_deferral);
2130 + __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
2131 + __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
2132 + __raw_writel(0x80, &port->regs->slot_time);
2133 + __raw_writel(0x01, &port->regs->int_clock_threshold);
2134 +
2135 + /* Populate queues with buffers, no failure after this point */
2136 + for (i = 0; i < TX_DESCS; i++)
2137 + queue_put_desc(port->plat->txreadyq,
2138 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
2139 +
2140 + for (i = 0; i < RX_DESCS; i++)
2141 + queue_put_desc(RXFREE_QUEUE(port->id),
2142 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
2143 +
2144 + __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
2145 + __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
2146 + __raw_writel(0, &port->regs->rx_control[1]);
2147 + __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
2148 +
2149 + phy_check_media(port, 1);
2150 + eth_set_mcast_list(dev);
2151 + netif_start_queue(dev);
2152 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
2153 +
2154 + qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
2155 + eth_rx_irq, dev);
2156 + if (!ports_open) {
2157 + qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
2158 + eth_txdone_irq, NULL);
2159 + qmgr_enable_irq(TXDONE_QUEUE);
2160 + }
2161 + ports_open++;
2162 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
2163 + return 0;
2164 +}
2165 +
2166 +static int eth_close(struct net_device *dev)
2167 +{
2168 + struct port *port = netdev_priv(dev);
2169 + struct msg msg;
2170 + int buffs = RX_DESCS; /* allocated RX buffers */
2171 + int i;
2172 +
2173 + ports_open--;
2174 + qmgr_disable_irq(port->plat->rxq);
2175 + netif_stop_queue(dev);
2176 +
2177 + while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
2178 + buffs--;
2179 +
2180 + memset(&msg, 0, sizeof(msg));
2181 + msg.cmd = NPE_SETLOOPBACK_MODE;
2182 + msg.eth_id = port->id;
2183 + msg.byte3 = 1;
2184 + if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
2185 + printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
2186 +
2187 + i = 0;
2188 + do { /* drain RX buffers */
2189 + while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
2190 + buffs--;
2191 + if (!buffs)
2192 + break;
2193 + if (qmgr_stat_empty(TX_QUEUE(port->id))) {
2194 + /* we have to inject some packet */
2195 + struct desc *desc;
2196 + u32 phys;
2197 + int n = queue_get_desc(port->plat->txreadyq, port, 1);
2198 + BUG_ON(n < 0);
2199 + desc = tx_desc_ptr(port, n);
2200 + phys = tx_desc_phys(port, n);
2201 + desc->buf_len = desc->pkt_len = 1;
2202 + wmb();
2203 + queue_put_desc(TX_QUEUE(port->id), phys, desc);
2204 + }
2205 + udelay(1);
2206 + } while (++i < MAX_CLOSE_WAIT);
2207 +
2208 + if (buffs)
2209 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
2210 + " left in NPE\n", dev->name, buffs);
2211 +#if DEBUG_CLOSE
2212 + if (!buffs)
2213 + printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
2214 +#endif
2215 +
2216 + buffs = TX_DESCS;
2217 + while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
2218 + buffs--; /* cancel TX */
2219 +
2220 + i = 0;
2221 + do {
2222 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
2223 + buffs--;
2224 + if (!buffs)
2225 + break;
2226 + } while (++i < MAX_CLOSE_WAIT);
2227 +
2228 + if (buffs)
2229 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
2230 + "left in NPE\n", dev->name, buffs);
2231 +#if DEBUG_CLOSE
2232 + if (!buffs)
2233 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
2234 +#endif
2235 +
2236 + msg.byte3 = 0;
2237 + if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
2238 + printk(KERN_CRIT "%s: unable to disable loopback\n",
2239 + dev->name);
2240 +
2241 + port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
2242 + ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
2243 + mdio_write(dev, port->plat->phy, MII_BMCR,
2244 + port->mii_bmcr | BMCR_PDOWN);
2245 +
2246 + if (!ports_open)
2247 + qmgr_disable_irq(TXDONE_QUEUE);
2248 + cancel_rearming_delayed_work(&port->mdio_thread);
2249 + destroy_queues(port);
2250 + release_queues(port);
2251 + return 0;
2252 +}
2253 +
2254 +static int __devinit eth_init_one(struct platform_device *pdev)
2255 +{
2256 + struct port *port;
2257 + struct net_device *dev;
2258 + struct eth_plat_info *plat = pdev->dev.platform_data;
2259 + u32 regs_phys;
2260 + int err;
2261 +
2262 + if (!(dev = alloc_etherdev(sizeof(struct port))))
2263 + return -ENOMEM;
2264 +
2265 + SET_MODULE_OWNER(dev);
2266 + SET_NETDEV_DEV(dev, &pdev->dev);
2267 + port = netdev_priv(dev);
2268 + port->netdev = dev;
2269 + port->id = pdev->id;
2270 +
2271 + switch (port->id) {
2272 + case IXP4XX_ETH_NPEA:
2273 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
2274 + regs_phys = IXP4XX_EthA_BASE_PHYS;
2275 + break;
2276 + case IXP4XX_ETH_NPEB:
2277 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
2278 + regs_phys = IXP4XX_EthB_BASE_PHYS;
2279 + break;
2280 + case IXP4XX_ETH_NPEC:
2281 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
2282 + regs_phys = IXP4XX_EthC_BASE_PHYS;
2283 + break;
2284 + default:
2285 + err = -ENOSYS;
2286 + goto err_free;
2287 + }
2288 +
2289 + dev->open = eth_open;
2290 + dev->hard_start_xmit = eth_xmit;
2291 + dev->poll = eth_poll;
2292 + dev->stop = eth_close;
2293 + dev->get_stats = eth_stats;
2294 + dev->do_ioctl = eth_ioctl;
2295 + dev->set_multicast_list = eth_set_mcast_list;
2296 + dev->weight = 16;
2297 + dev->tx_queue_len = 100;
2298 +
2299 + if (!(port->npe = npe_request(NPE_ID(port->id)))) {
2300 + err = -EIO;
2301 + goto err_free;
2302 + }
2303 +
2304 + if (register_netdev(dev)) {
2305 + err = -EIO;
2306 + goto err_npe_rel;
2307 + }
2308 +
2309 + port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
2310 + if (!port->mem_res) {
2311 + err = -EBUSY;
2312 + goto err_unreg;
2313 + }
2314 +
2315 + port->plat = plat;
2316 + npe_port_tab[NPE_ID(port->id)] = port;
2317 + memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
2318 +
2319 + platform_set_drvdata(pdev, dev);
2320 +
2321 + __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
2322 + &port->regs->core_control);
2323 + udelay(50);
2324 + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
2325 + udelay(50);
2326 +
2327 + port->mii.dev = dev;
2328 + port->mii.mdio_read = mdio_read;
2329 + port->mii.mdio_write = mdio_write;
2330 + port->mii.phy_id = plat->phy;
2331 + port->mii.phy_id_mask = 0x1F;
2332 + port->mii.reg_num_mask = 0x1F;
2333 +
2334 + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
2335 + npe_name(port->npe));
2336 +
2337 + phy_reset(dev, plat->phy);
2338 + port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
2339 + ~(BMCR_RESET | BMCR_PDOWN);
2340 + mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
2341 +
2342 + INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
2343 + return 0;
2344 +
2345 +err_unreg:
2346 + unregister_netdev(dev);
2347 +err_npe_rel:
2348 + npe_release(port->npe);
2349 +err_free:
2350 + free_netdev(dev);
2351 + return err;
2352 +}
2353 +
2354 +static int __devexit eth_remove_one(struct platform_device *pdev)
2355 +{
2356 + struct net_device *dev = platform_get_drvdata(pdev);
2357 + struct port *port = netdev_priv(dev);
2358 +
2359 + unregister_netdev(dev);
2360 + npe_port_tab[NPE_ID(port->id)] = NULL;
2361 + platform_set_drvdata(pdev, NULL);
2362 + npe_release(port->npe);
2363 + release_resource(port->mem_res);
2364 + free_netdev(dev);
2365 + return 0;
2366 +}
2367 +
2368 +static struct platform_driver drv = {
2369 + .driver.name = DRV_NAME,
2370 + .probe = eth_init_one,
2371 + .remove = eth_remove_one,
2372 +};
2373 +
2374 +static int __init eth_init_module(void)
2375 +{
2376 + if (!(ixp4xx_read_fuses() & IXP4XX_FUSE_NPEB_ETH0))
2377 + return -ENOSYS;
2378 +
2379 + /* All MII PHY accesses use NPE-B Ethernet registers */
2380 + spin_lock_init(&mdio_lock);
2381 + mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
2382 + __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
2383 +
2384 + return platform_driver_register(&drv);
2385 +}
2386 +
2387 +static void __exit eth_cleanup_module(void)
2388 +{
2389 + platform_driver_unregister(&drv);
2390 +}
2391 +
2392 +MODULE_AUTHOR("Krzysztof Halasa");
2393 +MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
2394 +MODULE_LICENSE("GPL v2");
2395 +module_init(eth_init_module);
2396 +module_exit(eth_cleanup_module);
2397 diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/wan/Kconfig ixp4xx-nep.git/drivers/net/wan/Kconfig
2398 --- linux-2.6.23/drivers/net/wan/Kconfig 2007-10-09 22:31:38.000000000 +0200
2399 +++ ixp4xx-nep.git/drivers/net/wan/Kconfig 2007-10-22 19:20:05.000000000 +0200
2400 @@ -334,6 +334,15 @@
2401
2402 Say Y if your card supports this feature.
2403
2404 +config IXP4XX_HSS
2405 + tristate "IXP4xx HSS (synchronous serial port) support"
2406 + depends on HDLC && ARM && ARCH_IXP4XX
2407 + select IXP4XX_NPE
2408 + select IXP4XX_QMGR
2409 + help
2410 + Say Y here if you want to use built-in HSS ports
2411 + on IXP4xx processor.
2412 +
2413 config DLCI
2414 tristate "Frame Relay DLCI support"
2415 ---help---
2416 diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/wan/Makefile ixp4xx-nep.git/drivers/net/wan/Makefile
2417 --- linux-2.6.23/drivers/net/wan/Makefile 2007-10-09 22:31:38.000000000 +0200
2418 +++ ixp4xx-nep.git/drivers/net/wan/Makefile 2007-10-22 19:20:05.000000000 +0200
2419 @@ -42,6 +42,7 @@
2420 obj-$(CONFIG_WANXL) += wanxl.o
2421 obj-$(CONFIG_PCI200SYN) += pci200syn.o
2422 obj-$(CONFIG_PC300TOO) += pc300too.o
2423 +obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
2424
2425 clean-files := wanxlfw.inc
2426 $(obj)/wanxl.o: $(obj)/wanxlfw.inc
2427 diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/wan/ixp4xx_hss.c ixp4xx-nep.git/drivers/net/wan/ixp4xx_hss.c
2428 --- linux-2.6.23/drivers/net/wan/ixp4xx_hss.c 1970-01-01 01:00:00.000000000 +0100
2429 +++ ixp4xx-nep.git/drivers/net/wan/ixp4xx_hss.c 2007-10-22 19:20:05.000000000 +0200
2430 @@ -0,0 +1,1248 @@
2431 +/*
2432 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
2433 + *
2434 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
2435 + *
2436 + * This program is free software; you can redistribute it and/or modify it
2437 + * under the terms of version 2 of the GNU General Public License
2438 + * as published by the Free Software Foundation.
2439 + */
2440 +
2441 +#include <linux/dma-mapping.h>
2442 +#include <linux/dmapool.h>
2443 +#include <linux/kernel.h>
2444 +#include <linux/hdlc.h>
2445 +#include <linux/platform_device.h>
2446 +#include <asm/io.h>
2447 +#include <asm/arch/npe.h>
2448 +#include <asm/arch/qmgr.h>
2449 +
2450 +#define DEBUG_QUEUES 0
2451 +#define DEBUG_DESC 0
2452 +#define DEBUG_RX 0
2453 +#define DEBUG_TX 0
2454 +#define DEBUG_PKT_BYTES 0
2455 +#define DEBUG_CLOSE 0
2456 +
2457 +#define DRV_NAME "ixp4xx_hss"
2458 +
2459 +#define PKT_EXTRA_FLAGS 0 /* orig 1 */
2460 +#define FRAME_SYNC_OFFSET 0 /* unused, channelized only */
2461 +#define FRAME_SYNC_SIZE 1024
2462 +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
2463 +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
2464 +
2465 +#define RX_DESCS 16 /* also length of all RX queues */
2466 +#define TX_DESCS 16 /* also length of all TX queues */
2467 +
2468 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
2469 +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
2470 +#define MAX_CLOSE_WAIT 1000 /* microseconds */
2471 +
2472 +/* Queue IDs */
2473 +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
2474 +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
2475 +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
2476 +#define HSS0_PKT_TX1_QUEUE 15
2477 +#define HSS0_PKT_TX2_QUEUE 16
2478 +#define HSS0_PKT_TX3_QUEUE 17
2479 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
2480 +#define HSS0_PKT_RXFREE1_QUEUE 19
2481 +#define HSS0_PKT_RXFREE2_QUEUE 20
2482 +#define HSS0_PKT_RXFREE3_QUEUE 21
2483 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
2484 +
2485 +#define HSS1_CHL_RXTRIG_QUEUE 10
2486 +#define HSS1_PKT_RX_QUEUE 0
2487 +#define HSS1_PKT_TX0_QUEUE 5
2488 +#define HSS1_PKT_TX1_QUEUE 6
2489 +#define HSS1_PKT_TX2_QUEUE 7
2490 +#define HSS1_PKT_TX3_QUEUE 8
2491 +#define HSS1_PKT_RXFREE0_QUEUE 1
2492 +#define HSS1_PKT_RXFREE1_QUEUE 2
2493 +#define HSS1_PKT_RXFREE2_QUEUE 3
2494 +#define HSS1_PKT_RXFREE3_QUEUE 4
2495 +#define HSS1_PKT_TXDONE_QUEUE 9
2496 +
2497 +#define NPE_PKT_MODE_HDLC 0
2498 +#define NPE_PKT_MODE_RAW 1
2499 +#define NPE_PKT_MODE_56KMODE 2
2500 +#define NPE_PKT_MODE_56KENDIAN_MSB 4
2501 +
2502 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
2503 +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
2504 +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
2505 +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
2506 +
2507 +
2508 +/* hss_config, PCRs */
2509 +/* Frame sync sampling, default = active low */
2510 +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
2511 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
2512 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
2513 +
2514 +/* Frame sync pin: input (default) or output generated off a given clk edge */
2515 +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
2516 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
2517 +
2518 +/* Frame and data clock sampling on edge, default = falling */
2519 +#define PCR_FCLK_EDGE_RISING 0x08000000
2520 +#define PCR_DCLK_EDGE_RISING 0x04000000
2521 +
2522 +/* Clock direction, default = input */
2523 +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
2524 +
2525 +/* Generate/Receive frame pulses, default = enabled */
2526 +#define PCR_FRM_PULSE_DISABLED 0x01000000
2527 +
2528 + /* Data rate is full (default) or half the configured clk speed */
2529 +#define PCR_HALF_CLK_RATE 0x00200000
2530 +
2531 +/* Invert data between NPE and HSS FIFOs? (default = no) */
2532 +#define PCR_DATA_POLARITY_INVERT 0x00100000
2533 +
2534 +/* TX/RX endianness, default = LSB */
2535 +#define PCR_MSB_ENDIAN 0x00080000
2536 +
2537 +/* Normal (default) / open drain mode (TX only) */
2538 +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
2539 +
2540 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
2541 +#define PCR_SOF_NO_FBIT 0x00020000
2542 +
2543 +/* Drive data pins? */
2544 +#define PCR_TX_DATA_ENABLE 0x00010000
2545 +
2546 +/* Voice 56k type: drive the data pins low (default), high, high Z */
2547 +#define PCR_TX_V56K_HIGH 0x00002000
2548 +#define PCR_TX_V56K_HIGH_IMP 0x00004000
2549 +
2550 +/* Unassigned type: drive the data pins low (default), high, high Z */
2551 +#define PCR_TX_UNASS_HIGH 0x00000800
2552 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000
2553 +
2554 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
2555 +#define PCR_TX_FB_HIGH_IMP 0x00000400
2556 +
2557 +/* 56k data endiannes - which bit unused: high (default) or low */
2558 +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
2559 +
2560 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
2561 +#define PCR_TX_56KS_56K_DATA 0x00000100
2562 +
2563 +/* hss_config, cCR */
2564 +/* Number of packetized clients, default = 1 */
2565 +#define CCR_NPE_HFIFO_2_HDLC 0x04000000
2566 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
2567 +
2568 +/* default = no loopback */
2569 +#define CCR_LOOPBACK 0x02000000
2570 +
2571 +/* HSS number, default = 0 (first) */
2572 +#define CCR_SECOND_HSS 0x01000000
2573 +
2574 +
2575 +/* hss_config, clkCR: main:10, num:10, denom:12 */
2576 +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
2577 +
2578 +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
2579 +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
2580 +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
2581 +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
2582 +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
2583 +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
2584 +
2585 +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
2586 +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
2587 +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
2588 +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
2589 +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
2590 +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
2591 +
2592 +
2593 +/* hss_config, LUTs: default = unassigned */
2594 +#define TDMMAP_HDLC 1 /* HDLC - packetised */
2595 +#define TDMMAP_VOICE56K 2 /* Voice56K - channelised */
2596 +#define TDMMAP_VOICE64K 3 /* Voice64K - channelised */
2597 +
2598 +
2599 +/* NPE command codes */
2600 +/* writes the ConfigWord value to the location specified by offset */
2601 +#define PORT_CONFIG_WRITE 0x40
2602 +
2603 +/* triggers the NPE to load the contents of the configuration table */
2604 +#define PORT_CONFIG_LOAD 0x41
2605 +
2606 +/* triggers the NPE to return an HssErrorReadResponse message */
2607 +#define PORT_ERROR_READ 0x42
2608 +
2609 +/* reset NPE internal status and enable the HssChannelized operation */
2610 +#define CHAN_FLOW_ENABLE 0x43
2611 +#define CHAN_FLOW_DISABLE 0x44
2612 +#define CHAN_IDLE_PATTERN_WRITE 0x45
2613 +#define CHAN_NUM_CHANS_WRITE 0x46
2614 +#define CHAN_RX_BUF_ADDR_WRITE 0x47
2615 +#define CHAN_RX_BUF_CFG_WRITE 0x48
2616 +#define CHAN_TX_BLK_CFG_WRITE 0x49
2617 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A
2618 +#define CHAN_TX_BUF_SIZE_WRITE 0x4B
2619 +#define CHAN_TSLOTSWITCH_ENABLE 0x4C
2620 +#define CHAN_TSLOTSWITCH_DISABLE 0x4D
2621 +
2622 +/* downloads the gainWord value for a timeslot switching channel associated
2623 + with bypassNum */
2624 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
2625 +
2626 +/* triggers the NPE to reset internal status and enable the HssPacketized
2627 + operation for the flow specified by pPipe */
2628 +#define PKT_PIPE_FLOW_ENABLE 0x50
2629 +#define PKT_PIPE_FLOW_DISABLE 0x51
2630 +#define PKT_NUM_PIPES_WRITE 0x52
2631 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
2632 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54
2633 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
2634 +#define PKT_PIPE_RX_SIZE_WRITE 0x56
2635 +#define PKT_PIPE_MODE_WRITE 0x57
2636 +
2637 +
2638 +#define HSS_TIMESLOTS 128
2639 +#define HSS_LUT_BITS 2
2640 +
2641 +/* HDLC packet status values - desc->status */
2642 +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
2643 +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
2644 +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
2645 +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
2646 + this packet (if buf_len < pkt_len) */
2647 +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
2648 +#define ERR_HDLC_ABORT 6 /* abort sequence received */
2649 +#define ERR_DISCONNECTING 7 /* disconnect is in progress */
2650 +
2651 +
2652 +#ifdef __ARMEB__
2653 +typedef struct sk_buff buffer_t;
2654 +#define free_buffer dev_kfree_skb
2655 +#define free_buffer_irq dev_kfree_skb_irq
2656 +#else
2657 +typedef void buffer_t;
2658 +#define free_buffer kfree
2659 +#define free_buffer_irq kfree
2660 +#endif
2661 +
2662 +struct port {
2663 + struct npe *npe;
2664 + struct net_device *netdev;
2665 + struct hss_plat_info *plat;
2666 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
2667 + struct desc *desc_tab; /* coherent */
2668 + u32 desc_tab_phys;
2669 + sync_serial_settings settings;
2670 + int id;
2671 + u8 hdlc_cfg;
2672 +};
2673 +
2674 +/* NPE message structure */
2675 +struct msg {
2676 +#ifdef __ARMEB__
2677 + u8 cmd, unused, hss_port, index;
2678 + union {
2679 + struct { u8 data8a, data8b, data8c, data8d; };
2680 + struct { u16 data16a, data16b; };
2681 + struct { u32 data32; };
2682 + };
2683 +#else
2684 + u8 index, hss_port, unused, cmd;
2685 + union {
2686 + struct { u8 data8d, data8c, data8b, data8a; };
2687 + struct { u16 data16b, data16a; };
2688 + struct { u32 data32; };
2689 + };
2690 +#endif
2691 +};
2692 +
2693 +/* HDLC packet descriptor */
2694 +struct desc {
2695 + u32 next; /* pointer to next buffer, unused */
2696 +
2697 +#ifdef __ARMEB__
2698 + u16 buf_len; /* buffer length */
2699 + u16 pkt_len; /* packet length */
2700 + u32 data; /* pointer to data buffer in RAM */
2701 + u8 status;
2702 + u8 error_count;
2703 + u16 __reserved;
2704 +#else
2705 + u16 pkt_len; /* packet length */
2706 + u16 buf_len; /* buffer length */
2707 + u32 data; /* pointer to data buffer in RAM */
2708 + u16 __reserved;
2709 + u8 error_count;
2710 + u8 status;
2711 +#endif
2712 + u32 __reserved1[4];
2713 +};
2714 +
2715 +
2716 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
2717 + (n) * sizeof(struct desc))
2718 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
2719 +
2720 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
2721 + ((n) + RX_DESCS) * sizeof(struct desc))
2722 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
2723 +
2724 +#ifndef __ARMEB__
2725 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
2726 +{
2727 + int i;
2728 + for (i = 0; i < cnt; i++)
2729 + dest[i] = swab32(src[i]);
2730 +}
2731 +#endif
2732 +
2733 +static int ports_open;
2734 +static struct dma_pool *dma_pool;
2735 +
2736 +static struct {
2737 + int tx, txdone, rx, rxfree;
2738 +}queue_ids[2] = {{ HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE,
2739 + HSS0_PKT_RX_QUEUE, HSS0_PKT_RXFREE0_QUEUE },
2740 + { HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE,
2741 + HSS1_PKT_RX_QUEUE, HSS1_PKT_RXFREE0_QUEUE },
2742 +};
2743 +
2744 +
2745 +static inline struct port* dev_to_port(struct net_device *dev)
2746 +{
2747 + return dev_to_hdlc(dev)->priv;
2748 +}
2749 +
2750 +
2751 +static inline void debug_pkt(struct net_device *dev, const char *func,
2752 + u8 *data, int len)
2753 +{
2754 +#if DEBUG_PKT_BYTES
2755 + int i;
2756 +
2757 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
2758 + for (i = 0; i < len; i++) {
2759 + if (i >= DEBUG_PKT_BYTES)
2760 + break;
2761 + printk("%s%02X", !(i % 4) ? " " : "", data[i]);
2762 + }
2763 + printk("\n");
2764 +#endif
2765 +}
2766 +
2767 +
2768 +static inline void debug_desc(u32 phys, struct desc *desc)
2769 +{
2770 +#if DEBUG_DESC
2771 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
2772 + phys, desc->next, desc->buf_len, desc->pkt_len,
2773 + desc->data, desc->status, desc->error_count);
2774 +#endif
2775 +}
2776 +
2777 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
2778 +{
2779 +#if DEBUG_QUEUES
2780 + static struct {
2781 + int queue;
2782 + char *name;
2783 + } names[] = {
2784 + { HSS0_PKT_TX0_QUEUE, "TX#0 " },
2785 + { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
2786 + { HSS0_PKT_RX_QUEUE, "RX#0 " },
2787 + { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
2788 + { HSS1_PKT_TX0_QUEUE, "TX#1 " },
2789 + { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
2790 + { HSS1_PKT_RX_QUEUE, "RX#1 " },
2791 + { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
2792 + };
2793 + int i;
2794 +
2795 + for (i = 0; i < ARRAY_SIZE(names); i++)
2796 + if (names[i].queue == queue)
2797 + break;
2798 +
2799 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
2800 + i < ARRAY_SIZE(names) ? names[i].name : "",
2801 + is_get ? "->" : "<-", phys);
2802 +#endif
2803 +}
2804 +
2805 +static inline u32 queue_get_entry(unsigned int queue)
2806 +{
2807 + u32 phys = qmgr_get_entry(queue);
2808 + debug_queue(queue, 1, phys);
2809 + return phys;
2810 +}
2811 +
2812 +static inline int queue_get_desc(unsigned int queue, struct port *port,
2813 + int is_tx)
2814 +{
2815 + u32 phys, tab_phys, n_desc;
2816 + struct desc *tab;
2817 +
2818 + if (!(phys = queue_get_entry(queue)))
2819 + return -1;
2820 +
2821 + BUG_ON(phys & 0x1F);
2822 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
2823 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
2824 + n_desc = (phys - tab_phys) / sizeof(struct desc);
2825 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
2826 + debug_desc(phys, &tab[n_desc]);
2827 + BUG_ON(tab[n_desc].next);
2828 + return n_desc;
2829 +}
2830 +
2831 +static inline void queue_put_desc(unsigned int queue, u32 phys,
2832 + struct desc *desc)
2833 +{
2834 + debug_queue(queue, 0, phys);
2835 + debug_desc(phys, desc);
2836 + BUG_ON(phys & 0x1F);
2837 + qmgr_put_entry(queue, phys);
2838 + BUG_ON(qmgr_stat_overflow(queue));
2839 +}
2840 +
2841 +
2842 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
2843 +{
2844 +#ifdef __ARMEB__
2845 + dma_unmap_single(&port->netdev->dev, desc->data,
2846 + desc->buf_len, DMA_TO_DEVICE);
2847 +#else
2848 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
2849 + ALIGN((desc->data & 3) + desc->buf_len, 4),
2850 + DMA_TO_DEVICE);
2851 +#endif
2852 +}
2853 +
2854 +
2855 +static void hss_set_carrier(void *pdev, int carrier)
2856 +{
2857 + struct net_device *dev = pdev;
2858 + if (carrier)
2859 + netif_carrier_on(dev);
2860 + else
2861 + netif_carrier_off(dev);
2862 +}
2863 +
2864 +static void hss_rx_irq(void *pdev)
2865 +{
2866 + struct net_device *dev = pdev;
2867 + struct port *port = dev_to_port(dev);
2868 +
2869 +#if DEBUG_RX
2870 + printk(KERN_DEBUG "%s: hss_rx_irq\n", dev->name);
2871 +#endif
2872 + qmgr_disable_irq(queue_ids[port->id].rx);
2873 + netif_rx_schedule(dev);
2874 +}
2875 +
2876 +static int hss_poll(struct net_device *dev, int *budget)
2877 +{
2878 + struct port *port = dev_to_port(dev);
2879 + unsigned int rxq = queue_ids[port->id].rx;
2880 + unsigned int rxfreeq = queue_ids[port->id].rxfree;
2881 + struct net_device_stats *stats = hdlc_stats(dev);
2882 + int quota = dev->quota, received = 0;
2883 +
2884 +#if DEBUG_RX
2885 + printk(KERN_DEBUG "%s: hss_poll\n", dev->name);
2886 +#endif
2887 +
2888 + while (quota) {
2889 + struct sk_buff *skb;
2890 + struct desc *desc;
2891 + int n;
2892 +#ifdef __ARMEB__
2893 + struct sk_buff *temp;
2894 + u32 phys;
2895 +#endif
2896 +
2897 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
2898 + dev->quota -= received; /* No packet received */
2899 + *budget -= received;
2900 + received = 0;
2901 +#if DEBUG_RX
2902 + printk(KERN_DEBUG "%s: hss_poll netif_rx_complete\n",
2903 + dev->name);
2904 +#endif
2905 + netif_rx_complete(dev);
2906 + qmgr_enable_irq(rxq);
2907 + if (!qmgr_stat_empty(rxq) &&
2908 + netif_rx_reschedule(dev, 0)) {
2909 +#if DEBUG_RX
2910 + printk(KERN_DEBUG "%s: hss_poll"
2911 + " netif_rx_reschedule successed\n",
2912 + dev->name);
2913 +#endif
2914 + qmgr_disable_irq(rxq);
2915 + continue;
2916 + }
2917 +#if DEBUG_RX
2918 + printk(KERN_DEBUG "%s: hss_poll all done\n",
2919 + dev->name);
2920 +#endif
2921 + return 0; /* all work done */
2922 + }
2923 +
2924 + desc = rx_desc_ptr(port, n);
2925 +
2926 + if (desc->error_count) /* FIXME - remove printk */
2927 + printk(KERN_DEBUG "%s: hss_poll status 0x%02X errors"
2928 + " %u\n", dev->name, desc->status,
2929 + desc->error_count);
2930 +
2931 + skb = NULL;
2932 + switch (desc->status) {
2933 + case 0:
2934 +#ifdef __ARMEB__
2935 + if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
2936 + phys = dma_map_single(&dev->dev, skb->data,
2937 + RX_SIZE,
2938 + DMA_FROM_DEVICE);
2939 + if (dma_mapping_error(phys)) {
2940 + dev_kfree_skb(skb);
2941 + skb = NULL;
2942 + }
2943 + }
2944 +#else
2945 + skb = netdev_alloc_skb(dev, desc->pkt_len);
2946 +#endif
2947 + if (!skb)
2948 + stats->rx_dropped++;
2949 + break;
2950 + case ERR_HDLC_ALIGN:
2951 + case ERR_HDLC_ABORT:
2952 + stats->rx_frame_errors++;
2953 + stats->rx_errors++;
2954 + break;
2955 + case ERR_HDLC_FCS:
2956 + stats->rx_crc_errors++;
2957 + stats->rx_errors++;
2958 + break;
2959 + case ERR_HDLC_TOO_LONG:
2960 + stats->rx_length_errors++;
2961 + stats->rx_errors++;
2962 + break;
2963 + default: /* FIXME - remove printk */
2964 + printk(KERN_ERR "%s: hss_poll(): status 0x%02X errors"
2965 + " %u\n", dev->name, desc->status,
2966 + desc->error_count);
2967 + stats->rx_errors++;
2968 + }
2969 +
2970 + if (!skb) {
2971 + /* put the desc back on RX-ready queue */
2972 + desc->buf_len = RX_SIZE;
2973 + desc->pkt_len = desc->status = 0;
2974 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
2975 + continue;
2976 + }
2977 +
2978 + /* process received frame */
2979 +#ifdef __ARMEB__
2980 + temp = skb;
2981 + skb = port->rx_buff_tab[n];
2982 + dma_unmap_single(&dev->dev, desc->data,
2983 + RX_SIZE, DMA_FROM_DEVICE);
2984 +#else
2985 + dma_sync_single(&dev->dev, desc->data,
2986 + RX_SIZE, DMA_FROM_DEVICE);
2987 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
2988 + ALIGN(desc->pkt_len, 4) / 4);
2989 +#endif
2990 + skb_put(skb, desc->pkt_len);
2991 +
2992 + debug_pkt(dev, "hss_poll", skb->data, skb->len);
2993 +
2994 + skb->protocol = hdlc_type_trans(skb, dev);
2995 + dev->last_rx = jiffies;
2996 + stats->rx_packets++;
2997 + stats->rx_bytes += skb->len;
2998 + netif_receive_skb(skb);
2999 +
3000 + /* put the new buffer on RX-free queue */
3001 +#ifdef __ARMEB__
3002 + port->rx_buff_tab[n] = temp;
3003 + desc->data = phys;
3004 +#endif
3005 + desc->buf_len = RX_SIZE;
3006 + desc->pkt_len = 0;
3007 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
3008 + quota--;
3009 + received++;
3010 + }
3011 + dev->quota -= received;
3012 + *budget -= received;
3013 +#if DEBUG_RX
3014 + printk(KERN_DEBUG "hss_poll(): end, not all work done\n");
3015 +#endif
3016 + return 1; /* not all work done */
3017 +}
3018 +
3019 +
3020 +static void hss_txdone_irq(void *pdev)
3021 +{
3022 + struct net_device *dev = pdev;
3023 + struct port *port = dev_to_port(dev);
3024 + struct net_device_stats *stats = hdlc_stats(dev);
3025 + int n_desc;
3026 +
3027 +#if DEBUG_TX
3028 + printk(KERN_DEBUG DRV_NAME ": hss_txdone_irq\n");
3029 +#endif
3030 + while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
3031 + port, 1)) >= 0) {
3032 + struct desc *desc;
3033 + int start;
3034 +
3035 + desc = tx_desc_ptr(port, n_desc);
3036 +
3037 + stats->tx_packets++;
3038 + stats->tx_bytes += desc->pkt_len;
3039 +
3040 + dma_unmap_tx(port, desc);
3041 +#if DEBUG_TX
3042 + printk(KERN_DEBUG "%s: hss_txdone_irq free %p\n",
3043 + port->netdev->name, port->tx_buff_tab[n_desc]);
3044 +#endif
3045 + free_buffer_irq(port->tx_buff_tab[n_desc]);
3046 + port->tx_buff_tab[n_desc] = NULL;
3047 +
3048 + start = qmgr_stat_empty(port->plat->txreadyq);
3049 + queue_put_desc(port->plat->txreadyq,
3050 + tx_desc_phys(port, n_desc), desc);
3051 + if (start) {
3052 +#if DEBUG_TX
3053 + printk(KERN_DEBUG "%s: hss_txdone_irq xmit ready\n",
3054 + port->netdev->name);
3055 +#endif
3056 + netif_wake_queue(port->netdev);
3057 + }
3058 + }
3059 +}
3060 +
3061 +static int hss_xmit(struct sk_buff *skb, struct net_device *dev)
3062 +{
3063 + struct port *port = dev_to_port(dev);
3064 + struct net_device_stats *stats = hdlc_stats(dev);
3065 + unsigned int txreadyq = port->plat->txreadyq;
3066 + int len, offset, bytes, n;
3067 + void *mem;
3068 + u32 phys;
3069 + struct desc *desc;
3070 +
3071 +#if DEBUG_TX
3072 + printk(KERN_DEBUG "%s: hss_xmit\n", dev->name);
3073 +#endif
3074 +
3075 + if (unlikely(skb->len > HDLC_MAX_MRU)) {
3076 + dev_kfree_skb(skb);
3077 + stats->tx_errors++;
3078 + return NETDEV_TX_OK;
3079 + }
3080 +
3081 + debug_pkt(dev, "hss_xmit", skb->data, skb->len);
3082 +
3083 + len = skb->len;
3084 +#ifdef __ARMEB__
3085 + offset = 0; /* no need to keep alignment */
3086 + bytes = len;
3087 + mem = skb->data;
3088 +#else
3089 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
3090 + bytes = ALIGN(offset + len, 4);
3091 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
3092 + dev_kfree_skb(skb);
3093 + stats->tx_dropped++;
3094 + return NETDEV_TX_OK;
3095 + }
3096 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
3097 + dev_kfree_skb(skb);
3098 +#endif
3099 +
3100 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
3101 + if (dma_mapping_error(phys)) {
3102 +#ifdef __ARMEB__
3103 + dev_kfree_skb(skb);
3104 +#else
3105 + kfree(mem);
3106 +#endif
3107 + stats->tx_dropped++;
3108 + return NETDEV_TX_OK;
3109 + }
3110 +
3111 + n = queue_get_desc(txreadyq, port, 1);
3112 + BUG_ON(n < 0);
3113 + desc = tx_desc_ptr(port, n);
3114 +
3115 +#ifdef __ARMEB__
3116 + port->tx_buff_tab[n] = skb;
3117 +#else
3118 + port->tx_buff_tab[n] = mem;
3119 +#endif
3120 + desc->data = phys + offset;
3121 + desc->buf_len = desc->pkt_len = len;
3122 +
3123 + wmb();
3124 + queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
3125 + dev->trans_start = jiffies;
3126 +
3127 + if (qmgr_stat_empty(txreadyq)) {
3128 +#if DEBUG_TX
3129 + printk(KERN_DEBUG "%s: hss_xmit queue full\n", dev->name);
3130 +#endif
3131 + netif_stop_queue(dev);
3132 + /* we could miss TX ready interrupt */
3133 + if (!qmgr_stat_empty(txreadyq)) {
3134 +#if DEBUG_TX
3135 + printk(KERN_DEBUG "%s: hss_xmit ready again\n",
3136 + dev->name);
3137 +#endif
3138 + netif_wake_queue(dev);
3139 + }
3140 + }
3141 +
3142 +#if DEBUG_TX
3143 + printk(KERN_DEBUG "%s: hss_xmit end\n", dev->name);
3144 +#endif
3145 + return NETDEV_TX_OK;
3146 +}
3147 +
3148 +
3149 +static int request_queues(struct port *port)
3150 +{
3151 + int err;
3152 +
3153 + err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
3154 + if (err)
3155 + return err;
3156 +
3157 + err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
3158 + if (err)
3159 + goto rel_rxfree;
3160 +
3161 + err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
3162 + if (err)
3163 + goto rel_rx;
3164 +
3165 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
3166 + if (err)
3167 + goto rel_tx;
3168 +
3169 + err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
3170 + if (err)
3171 + goto rel_txready;
3172 + return 0;
3173 +
3174 +rel_txready:
3175 + qmgr_release_queue(port->plat->txreadyq);
3176 +rel_tx:
3177 + qmgr_release_queue(queue_ids[port->id].tx);
3178 +rel_rx:
3179 + qmgr_release_queue(queue_ids[port->id].rx);
3180 +rel_rxfree:
3181 + qmgr_release_queue(queue_ids[port->id].rxfree);
3182 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
3183 + port->netdev->name);
3184 + return err;
3185 +}
3186 +
3187 +static void release_queues(struct port *port)
3188 +{
3189 + qmgr_release_queue(queue_ids[port->id].rxfree);
3190 + qmgr_release_queue(queue_ids[port->id].rx);
3191 + qmgr_release_queue(queue_ids[port->id].txdone);
3192 + qmgr_release_queue(queue_ids[port->id].tx);
3193 + qmgr_release_queue(port->plat->txreadyq);
3194 +}
3195 +
3196 +static int init_queues(struct port *port)
3197 +{
3198 + int i;
3199 +
3200 + if (!ports_open)
3201 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
3202 + POOL_ALLOC_SIZE, 32, 0)))
3203 + return -ENOMEM;
3204 +
3205 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
3206 + &port->desc_tab_phys)))
3207 + return -ENOMEM;
3208 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
3209 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
3210 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
3211 +
3212 + /* Setup RX buffers */
3213 + for (i = 0; i < RX_DESCS; i++) {
3214 + struct desc *desc = rx_desc_ptr(port, i);
3215 + buffer_t *buff;
3216 + void *data;
3217 +#ifdef __ARMEB__
3218 + if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
3219 + return -ENOMEM;
3220 + data = buff->data;
3221 +#else
3222 + if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
3223 + return -ENOMEM;
3224 + data = buff;
3225 +#endif
3226 + desc->buf_len = RX_SIZE;
3227 + desc->data = dma_map_single(&port->netdev->dev, data,
3228 + RX_SIZE, DMA_FROM_DEVICE);
3229 + if (dma_mapping_error(desc->data)) {
3230 + free_buffer(buff);
3231 + return -EIO;
3232 + }
3233 + port->rx_buff_tab[i] = buff;
3234 + }
3235 +
3236 + return 0;
3237 +}
3238 +
3239 +static void destroy_queues(struct port *port)
3240 +{
3241 + int i;
3242 +
3243 + if (port->desc_tab) {
3244 + for (i = 0; i < RX_DESCS; i++) {
3245 + struct desc *desc = rx_desc_ptr(port, i);
3246 + buffer_t *buff = port->rx_buff_tab[i];
3247 + if (buff) {
3248 + dma_unmap_single(&port->netdev->dev,
3249 + desc->data, RX_SIZE,
3250 + DMA_FROM_DEVICE);
3251 + free_buffer(buff);
3252 + }
3253 + }
3254 + for (i = 0; i < TX_DESCS; i++) {
3255 + struct desc *desc = tx_desc_ptr(port, i);
3256 + buffer_t *buff = port->tx_buff_tab[i];
3257 + if (buff) {
3258 + dma_unmap_tx(port, desc);
3259 + free_buffer(buff);
3260 + }
3261 + }
3262 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
3263 + port->desc_tab = NULL;
3264 + }
3265 +
3266 + if (!ports_open && dma_pool) {
3267 + dma_pool_destroy(dma_pool);
3268 + dma_pool = NULL;
3269 + }
3270 +}
3271 +
3272 +static int hss_open(struct net_device *dev)
3273 +{
3274 + struct port *port = dev_to_port(dev);
3275 + struct npe *npe = port->npe;
3276 + struct msg msg;
3277 + int i, err;
3278 +
3279 + if (!npe_running(npe)) {
3280 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
3281 + if (err)
3282 + return err;
3283 + }
3284 +
3285 + if ((err = hdlc_open(dev)) != 0)
3286 + return err;
3287 +
3288 + if (port->plat->open)
3289 + if ((err = port->plat->open(port->id, port->netdev,
3290 + hss_set_carrier)) != 0)
3291 + goto err_hdlc_close;
3292 +
3293 + /* HSS main configuration */
3294 + memset(&msg, 0, sizeof(msg));
3295 + msg.cmd = PORT_CONFIG_WRITE;
3296 + msg.hss_port = port->id;
3297 + msg.index = 0; /* offset in HSS config */
3298 +
3299 + msg.data32 = PCR_FRM_PULSE_DISABLED |
3300 + PCR_SOF_NO_FBIT |
3301 + PCR_MSB_ENDIAN |
3302 + PCR_TX_DATA_ENABLE;
3303 +
3304 + if (port->settings.clock_type == CLOCK_INT)
3305 + msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
3306 +
3307 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_PCR") != 0))
3308 + goto err_plat_close; /* 0: TX PCR */
3309 +
3310 + msg.index = 4;
3311 + msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
3312 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_PCR") != 0))
3313 + goto err_plat_close; /* 4: RX PCR */
3314 +
3315 + msg.index = 8;
3316 + msg.data32 = (port->settings.loopback ? CCR_LOOPBACK : 0) |
3317 + (port->id ? CCR_SECOND_HSS : 0);
3318 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CORE_CR") != 0))
3319 + goto err_plat_close; /* 8: Core CR */
3320 +
3321 + msg.index = 12;
3322 + msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
3323 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CLK_CR") != 0))
3324 + goto err_plat_close; /* 12: CLK CR */
3325 +
3326 + msg.data32 = (FRAME_SYNC_OFFSET << 16) | (FRAME_SYNC_SIZE - 1);
3327 + msg.index = 16;
3328 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_FCR") != 0))
3329 + goto err_plat_close; /* 16: TX FCR */
3330 +
3331 + msg.index = 20;
3332 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_FCR") != 0))
3333 + goto err_plat_close; /* 20: RX FCR */
3334 +
3335 + msg.data32 = 0; /* Fill LUT with HDLC timeslots */
3336 + for (i = 0; i < 32 / HSS_LUT_BITS; i++)
3337 + msg.data32 |= TDMMAP_HDLC << (HSS_LUT_BITS * i);
3338 +
3339 + for (i = 0; i < 2 /* TX and RX */ * HSS_TIMESLOTS * HSS_LUT_BITS / 8;
3340 + i += 4) {
3341 + msg.index = 24 + i; /* 24 - 55: TX LUT, 56 - 87: RX LUT */
3342 + if ((err = npe_send_message(npe, &msg, "HSS_SET_LUT") != 0))
3343 + goto err_plat_close;
3344 + }
3345 +
3346 + /* HDLC mode configuration */
3347 + memset(&msg, 0, sizeof(msg));
3348 + msg.cmd = PKT_NUM_PIPES_WRITE;
3349 + msg.hss_port = port->id;
3350 + msg.data8a = PKT_NUM_PIPES;
3351 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_PIPES") != 0))
3352 + goto err_plat_close;
3353 +
3354 + memset(&msg, 0, sizeof(msg));
3355 + msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
3356 + msg.hss_port = port->id;
3357 + msg.data8a = PKT_PIPE_FIFO_SIZEW;
3358 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_FIFO") != 0))
3359 + goto err_plat_close;
3360 +
3361 + memset(&msg, 0, sizeof(msg));
3362 + msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
3363 + msg.hss_port = port->id;
3364 + msg.data32 = 0x7F7F7F7F;
3365 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_IDLE") != 0))
3366 + goto err_plat_close;
3367 +
3368 + memset(&msg, 0, sizeof(msg));
3369 + msg.cmd = PORT_CONFIG_LOAD;
3370 + msg.hss_port = port->id;
3371 + if ((err = npe_send_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
3372 + goto err_plat_close;
3373 + if ((err = npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
3374 + goto err_plat_close;
3375 +
3376 + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
3377 + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
3378 + printk(KERN_DEBUG "%s: unexpected message received in"
3379 + " response to HSS_LOAD_CONFIG\n", npe_name(npe));
3380 + err = EIO;
3381 + goto err_plat_close;
3382 + }
3383 +
3384 + memset(&msg, 0, sizeof(msg));
3385 + msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
3386 + msg.hss_port = port->id;
3387 + msg.data8a = port->hdlc_cfg; /* rx_cfg */
3388 + msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
3389 + if ((err = npe_send_message(npe, &msg, "HSS_SET_HDLC_CFG") != 0))
3390 + goto err_plat_close;
3391 +
3392 + memset(&msg, 0, sizeof(msg));
3393 + msg.cmd = PKT_PIPE_MODE_WRITE;
3394 + msg.hss_port = port->id;
3395 + msg.data8a = NPE_PKT_MODE_HDLC;
3396 + /* msg.data8b = inv_mask */
3397 + /* msg.data8c = or_mask */
3398 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_MODE") != 0))
3399 + goto err_plat_close;
3400 +
3401 + memset(&msg, 0, sizeof(msg));
3402 + msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
3403 + msg.hss_port = port->id;
3404 + msg.data16a = HDLC_MAX_MRU;
3405 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_RX_SIZE") != 0))
3406 + goto err_plat_close;
3407 +
3408 + if ((err = request_queues(port)) != 0)
3409 + goto err_plat_close;
3410 +
3411 + if ((err = init_queues(port)) != 0)
3412 + goto err_destroy_queues;
3413 +
3414 + memset(&msg, 0, sizeof(msg));
3415 + msg.cmd = PKT_PIPE_FLOW_ENABLE;
3416 + msg.hss_port = port->id;
3417 + if ((err = npe_send_message(npe, &msg, "HSS_ENABLE_PKT_PIPE") != 0))
3418 + goto err_destroy_queues;
3419 +
3420 + /* Populate queues with buffers, no failure after this point */
3421 + for (i = 0; i < TX_DESCS; i++)
3422 + queue_put_desc(port->plat->txreadyq,
3423 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
3424 +
3425 + for (i = 0; i < RX_DESCS; i++)
3426 + queue_put_desc(queue_ids[port->id].rxfree,
3427 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
3428 +
3429 + netif_start_queue(dev);
3430 +
3431 + qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
3432 + hss_rx_irq, dev);
3433 +
3434 + qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
3435 + hss_txdone_irq, dev);
3436 + qmgr_enable_irq(queue_ids[port->id].txdone);
3437 +
3438 + ports_open++;
3439 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
3440 + return 0;
3441 +
3442 +err_destroy_queues:
3443 + destroy_queues(port);
3444 + release_queues(port);
3445 +err_plat_close:
3446 + if (port->plat->close)
3447 + port->plat->close(port->id, port->netdev);
3448 +err_hdlc_close:
3449 + hdlc_close(dev);
3450 + return err;
3451 +}
3452 +
3453 +static int hss_close(struct net_device *dev)
3454 +{
3455 + struct port *port = dev_to_port(dev);
3456 + struct npe *npe = port->npe;
3457 + struct msg msg;
3458 + int buffs = RX_DESCS; /* allocated RX buffers */
3459 + int i;
3460 +
3461 + ports_open--;
3462 + qmgr_disable_irq(queue_ids[port->id].rx);
3463 + netif_stop_queue(dev);
3464 +
3465 + memset(&msg, 0, sizeof(msg));
3466 + msg.cmd = PKT_PIPE_FLOW_DISABLE;
3467 + msg.hss_port = port->id;
3468 + if (npe_send_message(npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
3469 + printk(KERN_CRIT "HSS-%i: unable to stop HDLC flow\n",
3470 + port->id);
3471 + /* The upper level would ignore the error anyway */
3472 + }
3473 +
3474 + while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
3475 + buffs--;
3476 + while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
3477 + buffs--;
3478 +
3479 + if (buffs)
3480 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
3481 + " left in NPE\n", dev->name, buffs);
3482 +
3483 + buffs = TX_DESCS;
3484 + while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
3485 + buffs--; /* cancel TX */
3486 +
3487 + i = 0;
3488 + do {
3489 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
3490 + buffs--;
3491 + if (!buffs)
3492 + break;
3493 + } while (++i < MAX_CLOSE_WAIT);
3494 +
3495 + if (buffs)
3496 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
3497 + "left in NPE\n", dev->name, buffs);
3498 +#if DEBUG_CLOSE
3499 + if (!buffs)
3500 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
3501 +#endif
3502 + qmgr_disable_irq(queue_ids[port->id].txdone);
3503 + destroy_queues(port);
3504 + release_queues(port);
3505 +
3506 + if (port->plat->close)
3507 + port->plat->close(port->id, port->netdev);
3508 + hdlc_close(dev);
3509 + return 0;
3510 +}
3511 +
3512 +
3513 +static int hss_attach(struct net_device *dev, unsigned short encoding,
3514 + unsigned short parity)
3515 +{
3516 + struct port *port = dev_to_port(dev);
3517 +
3518 + if (encoding != ENCODING_NRZ)
3519 + return -EINVAL;
3520 +
3521 + switch(parity) {
3522 + case PARITY_CRC16_PR1_CCITT:
3523 + port->hdlc_cfg = 0;
3524 + return 0;
3525 +
3526 + case PARITY_CRC32_PR1_CCITT:
3527 + port->hdlc_cfg = PKT_HDLC_CRC_32;
3528 + return 0;
3529 +
3530 + default:
3531 + return -EINVAL;
3532 + }
3533 +}
3534 +
3535 +
3536 +static int hss_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3537 +{
3538 + const size_t size = sizeof(sync_serial_settings);
3539 + sync_serial_settings new_line;
3540 + int clk;
3541 + sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
3542 + struct port *port = dev_to_port(dev);
3543 +
3544 + if (cmd != SIOCWANDEV)
3545 + return hdlc_ioctl(dev, ifr, cmd);
3546 +
3547 + switch(ifr->ifr_settings.type) {
3548 + case IF_GET_IFACE:
3549 + ifr->ifr_settings.type = IF_IFACE_V35;
3550 + if (ifr->ifr_settings.size < size) {
3551 + ifr->ifr_settings.size = size; /* data size wanted */
3552 + return -ENOBUFS;
3553 + }
3554 + if (copy_to_user(line, &port->settings, size))
3555 + return -EFAULT;
3556 + return 0;
3557 +
3558 + case IF_IFACE_SYNC_SERIAL:
3559 + case IF_IFACE_V35:
3560 + if(!capable(CAP_NET_ADMIN))
3561 + return -EPERM;
3562 + if (dev->flags & IFF_UP)
3563 + return -EBUSY; /* Cannot change parameters when open */
3564 +
3565 + if (copy_from_user(&new_line, line, size))
3566 + return -EFAULT;
3567 +
3568 + clk = new_line.clock_type;
3569 + if (port->plat->set_clock)
3570 + clk = port->plat->set_clock(port->id, clk);
3571 +
3572 + if (clk != CLOCK_EXT && clk != CLOCK_INT)
3573 + return -EINVAL; /* No such clock setting */
3574 +
3575 + if (new_line.loopback != 0 && new_line.loopback != 1)
3576 + return -EINVAL;
3577 +
3578 + memcpy(&port->settings, &new_line, size); /* Update settings */
3579 + return 0;
3580 +
3581 + default:
3582 + return hdlc_ioctl(dev, ifr, cmd);
3583 + }
3584 +}
3585 +
3586 +
3587 +static int __devinit hss_init_one(struct platform_device *pdev)
3588 +{
3589 + struct port *port;
3590 + struct net_device *dev;
3591 + hdlc_device *hdlc;
3592 + int err;
3593 +
3594 + if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
3595 + return -ENOMEM;
3596 + platform_set_drvdata(pdev, port);
3597 + port->id = pdev->id;
3598 +
3599 + if ((port->npe = npe_request(0)) == NULL) {
3600 + err = -ENOSYS;
3601 + goto err_free;
3602 + }
3603 +
3604 + port->plat = pdev->dev.platform_data;
3605 + if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
3606 + err = -ENOMEM;
3607 + goto err_plat;
3608 + }
3609 +
3610 + SET_MODULE_OWNER(net);
3611 + SET_NETDEV_DEV(dev, &pdev->dev);
3612 + hdlc = dev_to_hdlc(dev);
3613 + hdlc->attach = hss_attach;
3614 + hdlc->xmit = hss_xmit;
3615 + dev->open = hss_open;
3616 + dev->poll = hss_poll;
3617 + dev->stop = hss_close;
3618 + dev->do_ioctl = hss_ioctl;
3619 + dev->weight = 16;
3620 + dev->tx_queue_len = 100;
3621 + port->settings.clock_type = CLOCK_EXT;
3622 + port->settings.clock_rate = 2048000;
3623 +
3624 + if (register_hdlc_device(dev)) {
3625 + printk(KERN_ERR "HSS-%i: unable to register HDLC device\n",
3626 + port->id);
3627 + err = -ENOBUFS;
3628 + goto err_free_netdev;
3629 + }
3630 + printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
3631 + return 0;
3632 +
3633 +err_free_netdev:
3634 + free_netdev(dev);
3635 +err_plat:
3636 + npe_release(port->npe);
3637 + platform_set_drvdata(pdev, NULL);
3638 +err_free:
3639 + kfree(port);
3640 + return err;
3641 +}
3642 +
3643 +static int __devexit hss_remove_one(struct platform_device *pdev)
3644 +{
3645 + struct port *port = platform_get_drvdata(pdev);
3646 +
3647 + unregister_hdlc_device(port->netdev);
3648 + free_netdev(port->netdev);
3649 + npe_release(port->npe);
3650 + platform_set_drvdata(pdev, NULL);
3651 + kfree(port);
3652 + return 0;
3653 +}
3654 +
3655 +static struct platform_driver drv = {
3656 + .driver.name = DRV_NAME,
3657 + .probe = hss_init_one,
3658 + .remove = hss_remove_one,
3659 +};
3660 +
3661 +static int __init hss_init_module(void)
3662 +{
3663 + if ((ixp4xx_read_fuses() & (IXP4XX_FUSE_HDLC | IXP4XX_FUSE_HSS)) !=
3664 + (IXP4XX_FUSE_HDLC | IXP4XX_FUSE_HSS))
3665 + return -ENOSYS;
3666 + return platform_driver_register(&drv);
3667 +}
3668 +
3669 +static void __exit hss_cleanup_module(void)
3670 +{
3671 + platform_driver_unregister(&drv);
3672 +}
3673 +
3674 +MODULE_AUTHOR("Krzysztof Halasa");
3675 +MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
3676 +MODULE_LICENSE("GPL v2");
3677 +module_init(hss_init_module);
3678 +module_exit(hss_cleanup_module);
3679 diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/cpu.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/cpu.h
3680 --- linux-2.6.23/include/asm-arm/arch-ixp4xx/cpu.h 2007-10-09 22:31:38.000000000 +0200
3681 +++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/cpu.h 2007-10-22 19:20:22.000000000 +0200
3682 @@ -28,4 +28,19 @@
3683 #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
3684 IXP465_PROCESSOR_ID_VALUE)
3685
3686 +static inline u32 ixp4xx_read_fuses(void)
3687 +{
3688 + unsigned int fuses = ~*IXP4XX_EXP_CFG2;
3689 + fuses &= ~IXP4XX_FUSE_RESERVED;
3690 + if (!cpu_is_ixp46x())
3691 + fuses &= ~IXP4XX_FUSE_IXP46X_ONLY;
3692 +
3693 + return fuses;
3694 +}
3695 +
3696 +static inline void ixp4xx_write_fuses(u32 value)
3697 +{
3698 + *IXP4XX_EXP_CFG2 = ~value;
3699 +}
3700 +
3701 #endif /* _ASM_ARCH_CPU_H */
3702 diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/hardware.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/hardware.h
3703 --- linux-2.6.23/include/asm-arm/arch-ixp4xx/hardware.h 2007-10-09 22:31:38.000000000 +0200
3704 +++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/hardware.h 2007-10-22 19:20:22.000000000 +0200
3705 @@ -27,13 +27,13 @@
3706
3707 #define pcibios_assign_all_busses() 1
3708
3709 +/* Register locations and bits */
3710 +#include "ixp4xx-regs.h"
3711 +
3712 #ifndef __ASSEMBLER__
3713 #include <asm/arch/cpu.h>
3714 #endif
3715
3716 -/* Register locations and bits */
3717 -#include "ixp4xx-regs.h"
3718 -
3719 /* Platform helper functions and definitions */
3720 #include "platform.h"
3721
3722 diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3723 --- linux-2.6.23/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h 2007-10-09 22:31:38.000000000 +0200
3724 +++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h 2007-10-22 19:20:22.000000000 +0200
3725 @@ -607,4 +607,36 @@
3726
3727 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
3728
3729 +/* Fuse Bits of IXP_EXP_CFG2 */
3730 +#define IXP4XX_FUSE_RCOMP (1 << 0)
3731 +#define IXP4XX_FUSE_USB_DEVICE (1 << 1)
3732 +#define IXP4XX_FUSE_HASH (1 << 2)
3733 +#define IXP4XX_FUSE_AES (1 << 3)
3734 +#define IXP4XX_FUSE_DES (1 << 4)
3735 +#define IXP4XX_FUSE_HDLC (1 << 5)
3736 +#define IXP4XX_FUSE_AAL (1 << 6)
3737 +#define IXP4XX_FUSE_HSS (1 << 7)
3738 +#define IXP4XX_FUSE_UTOPIA (1 << 8)
3739 +#define IXP4XX_FUSE_NPEB_ETH0 (1 << 9)
3740 +#define IXP4XX_FUSE_NPEC_ETH (1 << 10)
3741 +#define IXP4XX_FUSE_RESET_NPEA (1 << 11)
3742 +#define IXP4XX_FUSE_RESET_NPEB (1 << 12)
3743 +#define IXP4XX_FUSE_RESET_NPEC (1 << 13)
3744 +#define IXP4XX_FUSE_PCI (1 << 14)
3745 +#define IXP4XX_FUSE_ECC_TIMESYNC (1 << 15)
3746 +#define IXP4XX_FUSE_UTOPIA_PHY_LIMIT (3 << 16)
3747 +#define IXP4XX_FUSE_USB_HOST (1 << 18)
3748 +#define IXP4XX_FUSE_NPEA_ETH (1 << 19)
3749 +#define IXP4XX_FUSE_NPEB_ETH_1_TO_3 (1 << 20)
3750 +#define IXP4XX_FUSE_RSA (1 << 21)
3751 +#define IXP4XX_FUSE_XSCALE_MAX_FREQ (3 << 22)
3752 +#define IXP4XX_FUSE_RESERVED (0xFF << 24)
3753 +
3754 +#define IXP4XX_FUSE_IXP46X_ONLY (IXP4XX_FUSE_ECC_TIMESYNC | \
3755 + IXP4XX_FUSE_USB_HOST | \
3756 + IXP4XX_FUSE_NPEA_ETH | \
3757 + IXP4XX_FUSE_NPEB_ETH_1_TO_3 | \
3758 + IXP4XX_FUSE_RSA | \
3759 + IXP4XX_FUSE_XSCALE_MAX_FREQ)
3760 +
3761 #endif
3762 diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/npe.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/npe.h
3763 --- linux-2.6.23/include/asm-arm/arch-ixp4xx/npe.h 1970-01-01 01:00:00.000000000 +0100
3764 +++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/npe.h 2007-10-22 19:20:22.000000000 +0200
3765 @@ -0,0 +1,41 @@
3766 +#ifndef __IXP4XX_NPE_H
3767 +#define __IXP4XX_NPE_H
3768 +
3769 +#include <linux/etherdevice.h>
3770 +#include <linux/kernel.h>
3771 +#include <asm/io.h>
3772 +
3773 +extern const char *npe_names[];
3774 +
3775 +struct npe_regs {
3776 + u32 exec_addr, exec_data, exec_status_cmd, exec_count;
3777 + u32 action_points[4];
3778 + u32 watchpoint_fifo, watch_count;
3779 + u32 profile_count;
3780 + u32 messaging_status, messaging_control;
3781 + u32 mailbox_status, /*messaging_*/ in_out_fifo;
3782 +};
3783 +
3784 +struct npe {
3785 + struct resource *mem_res;
3786 + struct npe_regs __iomem *regs;
3787 + u32 regs_phys;
3788 + int id;
3789 + int valid;
3790 +};
3791 +
3792 +
3793 +static inline const char *npe_name(struct npe *npe)
3794 +{
3795 + return npe_names[npe->id];
3796 +}
3797 +
3798 +int npe_running(struct npe *npe);
3799 +int npe_send_message(struct npe *npe, const void *msg, const char *what);
3800 +int npe_recv_message(struct npe *npe, void *msg, const char *what);
3801 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
3802 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
3803 +struct npe *npe_request(int id);
3804 +void npe_release(struct npe *npe);
3805 +
3806 +#endif /* __IXP4XX_NPE_H */
3807 diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/platform.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/platform.h
3808 --- linux-2.6.23/include/asm-arm/arch-ixp4xx/platform.h 2007-10-09 22:31:38.000000000 +0200
3809 +++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/platform.h 2007-10-22 19:20:22.000000000 +0200
3810 @@ -77,8 +77,7 @@
3811
3812 /*
3813 * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
3814 - * used to
3815 - * Used as platform_data to provide GPIO pin information to the ixp42x
3816 + * used as platform_data to provide GPIO pin information to the ixp42x
3817 * I2C driver.
3818 */
3819 struct ixp4xx_i2c_pins {
3820 @@ -86,6 +85,27 @@
3821 unsigned long scl_pin;
3822 };
3823
3824 +#define IXP4XX_ETH_NPEA 0x00
3825 +#define IXP4XX_ETH_NPEB 0x10
3826 +#define IXP4XX_ETH_NPEC 0x20
3827 +
3828 +/* Information about built-in Ethernet MAC interfaces */
3829 +struct eth_plat_info {
3830 + u8 phy; /* MII PHY ID, 0 - 31 */
3831 + u8 rxq; /* configurable, currently 0 - 31 only */
3832 + u8 txreadyq;
3833 + u8 hwaddr[6];
3834 +};
3835 +
3836 +/* Information about built-in HSS (synchronous serial) interfaces */
3837 +struct hss_plat_info {
3838 + int (*set_clock)(int port, unsigned int clock_type);
3839 + int (*open)(int port, void *pdev,
3840 + void (*set_carrier_cb)(void *pdev, int carrier));
3841 + void (*close)(int port, void *pdev);
3842 + u8 txreadyq;
3843 +};
3844 +
3845 /*
3846 * This structure provide a means for the board setup code
3847 * to give information to th pata_ixp4xx driver. It is
3848 diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/qmgr.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/qmgr.h
3849 --- linux-2.6.23/include/asm-arm/arch-ixp4xx/qmgr.h 1970-01-01 01:00:00.000000000 +0100
3850 +++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/qmgr.h 2007-10-22 19:20:22.000000000 +0200
3851 @@ -0,0 +1,124 @@
3852 +/*
3853 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
3854 + *
3855 + * This program is free software; you can redistribute it and/or modify it
3856 + * under the terms of version 2 of the GNU General Public License
3857 + * as published by the Free Software Foundation.
3858 + */
3859 +
3860 +#ifndef IXP4XX_QMGR_H
3861 +#define IXP4XX_QMGR_H
3862 +
3863 +#include <linux/kernel.h>
3864 +#include <asm/io.h>
3865 +
3866 +#define HALF_QUEUES 32
3867 +#define QUEUES 64 /* only 32 lower queues currently supported */
3868 +#define MAX_QUEUE_LENGTH 4 /* in dwords */
3869 +
3870 +#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
3871 +#define QUEUE_STAT1_NEARLY_EMPTY 2
3872 +#define QUEUE_STAT1_NEARLY_FULL 4
3873 +#define QUEUE_STAT1_FULL 8
3874 +#define QUEUE_STAT2_UNDERFLOW 1
3875 +#define QUEUE_STAT2_OVERFLOW 2
3876 +
3877 +#define QUEUE_WATERMARK_0_ENTRIES 0
3878 +#define QUEUE_WATERMARK_1_ENTRY 1
3879 +#define QUEUE_WATERMARK_2_ENTRIES 2
3880 +#define QUEUE_WATERMARK_4_ENTRIES 3
3881 +#define QUEUE_WATERMARK_8_ENTRIES 4
3882 +#define QUEUE_WATERMARK_16_ENTRIES 5
3883 +#define QUEUE_WATERMARK_32_ENTRIES 6
3884 +#define QUEUE_WATERMARK_64_ENTRIES 7
3885 +
3886 +/* queue interrupt request conditions */
3887 +#define QUEUE_IRQ_SRC_EMPTY 0
3888 +#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
3889 +#define QUEUE_IRQ_SRC_NEARLY_FULL 2
3890 +#define QUEUE_IRQ_SRC_FULL 3
3891 +#define QUEUE_IRQ_SRC_NOT_EMPTY 4
3892 +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
3893 +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
3894 +#define QUEUE_IRQ_SRC_NOT_FULL 7
3895 +
3896 +struct qmgr_regs {
3897 + u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
3898 + u32 stat1[4]; /* 0x400 - 0x40F */
3899 + u32 stat2[2]; /* 0x410 - 0x417 */
3900 + u32 statne_h; /* 0x418 - queue nearly empty */
3901 + u32 statf_h; /* 0x41C - queue full */
3902 + u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
3903 + u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
3904 + u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
3905 + u32 reserved[1776];
3906 + u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
3907 +};
3908 +
3909 +extern struct qmgr_regs __iomem *qmgr_regs;
3910 +
3911 +void qmgr_set_irq(unsigned int queue, int src,
3912 + void (*handler)(void *pdev), void *pdev);
3913 +void qmgr_enable_irq(unsigned int queue);
3914 +void qmgr_disable_irq(unsigned int queue);
3915 +
3916 +/* request_ and release_queue() must be called from non-IRQ context */
3917 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
3918 + unsigned int nearly_empty_watermark,
3919 + unsigned int nearly_full_watermark);
3920 +void qmgr_release_queue(unsigned int queue);
3921 +
3922 +
3923 +static inline void qmgr_put_entry(unsigned int queue, u32 val)
3924 +{
3925 + __raw_writel(val, &qmgr_regs->acc[queue][0]);
3926 +}
3927 +
3928 +static inline u32 qmgr_get_entry(unsigned int queue)
3929 +{
3930 + return __raw_readl(&qmgr_regs->acc[queue][0]);
3931 +}
3932 +
3933 +static inline int qmgr_get_stat1(unsigned int queue)
3934 +{
3935 + return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
3936 + >> ((queue & 7) << 2)) & 0xF;
3937 +}
3938 +
3939 +static inline int qmgr_get_stat2(unsigned int queue)
3940 +{
3941 + return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
3942 + >> ((queue & 0xF) << 1)) & 0x3;
3943 +}
3944 +
3945 +static inline int qmgr_stat_empty(unsigned int queue)
3946 +{
3947 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
3948 +}
3949 +
3950 +static inline int qmgr_stat_nearly_empty(unsigned int queue)
3951 +{
3952 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
3953 +}
3954 +
3955 +static inline int qmgr_stat_nearly_full(unsigned int queue)
3956 +{
3957 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
3958 +}
3959 +
3960 +static inline int qmgr_stat_full(unsigned int queue)
3961 +{
3962 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
3963 +}
3964 +
3965 +static inline int qmgr_stat_underflow(unsigned int queue)
3966 +{
3967 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
3968 +}
3969 +
3970 +static inline int qmgr_stat_overflow(unsigned int queue)
3971 +{
3972 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
3973 +}
3974 +
3975 +#endif
3976 diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/uncompress.h
3977 --- linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-09 22:31:38.000000000 +0200
3978 +++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-22 19:20:22.000000000 +0200
3979 @@ -13,7 +13,8 @@
3980 #ifndef _ARCH_UNCOMPRESS_H_
3981 #define _ARCH_UNCOMPRESS_H_
3982
3983 -#include <asm/hardware.h>
3984 +#define __ASM_ARCH_HARDWARE_H__
3985 +#include "ixp4xx-regs.h"
3986 #include <asm/mach-types.h>
3987 #include <linux/serial_reg.h>
3988
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