0f9b5f43c38719e7be60b4f785bcd520ff53687a
[openwrt/openwrt.git] / target / linux / ixp4xx / patches-2.6.25 / 190-cambria_support.patch
1 --- a/arch/arm/mach-ixp4xx/Kconfig
2 +++ b/arch/arm/mach-ixp4xx/Kconfig
3 @@ -25,6 +25,14 @@
4 Avila Network Platform. For more information on this platform,
5 see <file:Documentation/arm/IXP4xx>.
6
7 +config MACH_CAMBRIA
8 + bool "Cambria"
9 + select PCI
10 + help
11 + Say 'Y' here if you want your kernel to support the Gateworks
12 + Cambria series. For more information on this platform,
13 + see <file:Documentation/arm/IXP4xx>.
14 +
15 config MACH_LOFT
16 bool "Loft"
17 depends on MACH_AVILA
18 @@ -200,7 +208,7 @@
19
20 config CPU_IXP43X
21 bool
22 - depends on MACH_KIXRP435
23 + depends on MACH_KIXRP435 || MACH_CAMBRIA
24 default y
25
26 config MACH_GTWX5715
27 --- a/arch/arm/mach-ixp4xx/Makefile
28 +++ b/arch/arm/mach-ixp4xx/Makefile
29 @@ -7,6 +7,7 @@
30
31 obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
32 obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
33 +obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o
34 obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
35 obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
36 obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
37 @@ -28,6 +29,7 @@
38
39 obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
40 obj-$(CONFIG_MACH_AVILA) += avila-setup.o
41 +obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o
42 obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
43 obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
44 obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
45 --- /dev/null
46 +++ b/arch/arm/mach-ixp4xx/cambria-pci.c
47 @@ -0,0 +1,74 @@
48 +/*
49 + * arch/arch/mach-ixp4xx/cambria-pci.c
50 + *
51 + * PCI setup routines for Gateworks Cambria series
52 + *
53 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
54 + *
55 + * based on coyote-pci.c:
56 + * Copyright (C) 2002 Jungo Software Technologies.
57 + * Copyright (C) 2003 MontaVista Softwrae, Inc.
58 + *
59 + * Maintainer: Imre Kaloz <kaloz@openwrt.org>
60 + *
61 + * This program is free software; you can redistribute it and/or modify
62 + * it under the terms of the GNU General Public License version 2 as
63 + * published by the Free Software Foundation.
64 + *
65 + */
66 +
67 +#include <linux/kernel.h>
68 +#include <linux/pci.h>
69 +#include <linux/init.h>
70 +#include <linux/irq.h>
71 +
72 +#include <asm/mach-types.h>
73 +#include <asm/hardware.h>
74 +#include <asm/irq.h>
75 +
76 +#include <asm/mach/pci.h>
77 +
78 +extern void ixp4xx_pci_preinit(void);
79 +extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
80 +extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
81 +
82 +void __init cambria_pci_preinit(void)
83 +{
84 + set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
85 + set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
86 + set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
87 + set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
88 +
89 + ixp4xx_pci_preinit();
90 +}
91 +
92 +static int __init cambria_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
93 +{
94 + if (slot == 1)
95 + return IRQ_IXP4XX_GPIO11;
96 + else if (slot == 2)
97 + return IRQ_IXP4XX_GPIO10;
98 + else if (slot == 3)
99 + return IRQ_IXP4XX_GPIO9;
100 + else if (slot == 4)
101 + return IRQ_IXP4XX_GPIO8;
102 + else return -1;
103 +}
104 +
105 +struct hw_pci cambria_pci __initdata = {
106 + .nr_controllers = 1,
107 + .preinit = cambria_pci_preinit,
108 + .swizzle = pci_std_swizzle,
109 + .setup = ixp4xx_setup,
110 + .scan = ixp4xx_scan_bus,
111 + .map_irq = cambria_map_irq,
112 +};
113 +
114 +int __init cambria_pci_init(void)
115 +{
116 + if (machine_is_cambria())
117 + pci_common_init(&cambria_pci);
118 + return 0;
119 +}
120 +
121 +subsys_initcall(cambria_pci_init);
122 --- /dev/null
123 +++ b/arch/arm/mach-ixp4xx/cambria-setup.c
124 @@ -0,0 +1,444 @@
125 +/*
126 + * arch/arm/mach-ixp4xx/cambria-setup.c
127 + *
128 + * Board setup for the Gateworks Cambria series
129 + *
130 + * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
131 + *
132 + * based on coyote-setup.c:
133 + * Copyright (C) 2003-2005 MontaVista Software, Inc.
134 + *
135 + * Author: Imre Kaloz <Kaloz@openwrt.org>
136 + */
137 +
138 +#include <linux/kernel.h>
139 +#include <linux/init.h>
140 +#include <linux/device.h>
141 +#include <linux/if_ether.h>
142 +#include <linux/socket.h>
143 +#include <linux/netdevice.h>
144 +#include <linux/serial.h>
145 +#include <linux/tty.h>
146 +#include <linux/serial_8250.h>
147 +#include <linux/slab.h>
148 +#ifdef CONFIG_SENSORS_EEPROM
149 +# include <linux/i2c.h>
150 +# include <linux/eeprom.h>
151 +#endif
152 +
153 +#include <linux/leds.h>
154 +#include <linux/i2c-gpio.h>
155 +#include <asm/types.h>
156 +#include <asm/setup.h>
157 +#include <asm/memory.h>
158 +#include <asm/hardware.h>
159 +#include <asm/irq.h>
160 +#include <asm/mach-types.h>
161 +#include <asm/mach/arch.h>
162 +#include <asm/mach/flash.h>
163 +
164 +struct cambria_board_info {
165 + unsigned char *model;
166 + void (* setup)(void);
167 +};
168 +
169 +static struct cambria_board_info *cambria_info __initdata;
170 +
171 +static struct flash_platform_data cambria_flash_data = {
172 + .map_name = "cfi_probe",
173 + .width = 2,
174 +};
175 +
176 +static struct resource cambria_flash_resource = {
177 + .flags = IORESOURCE_MEM,
178 +};
179 +
180 +static struct platform_device cambria_flash = {
181 + .name = "IXP4XX-Flash",
182 + .id = 0,
183 + .dev = {
184 + .platform_data = &cambria_flash_data,
185 + },
186 + .num_resources = 1,
187 + .resource = &cambria_flash_resource,
188 +};
189 +
190 +static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
191 + .sda_pin = 7,
192 + .scl_pin = 6,
193 +};
194 +
195 +static struct platform_device cambria_i2c_gpio = {
196 + .name = "i2c-gpio",
197 + .id = 0,
198 + .dev = {
199 + .platform_data = &cambria_i2c_gpio_data,
200 + },
201 +};
202 +
203 +static struct resource cambria_uart_resource = {
204 + .start = IXP4XX_UART1_BASE_PHYS,
205 + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
206 + .flags = IORESOURCE_MEM,
207 +};
208 +
209 +static struct plat_serial8250_port cambria_uart_data[] = {
210 + {
211 + .mapbase = IXP4XX_UART1_BASE_PHYS,
212 + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
213 + .irq = IRQ_IXP4XX_UART1,
214 + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
215 + .iotype = UPIO_MEM,
216 + .regshift = 2,
217 + .uartclk = IXP4XX_UART_XTAL,
218 + },
219 + { },
220 +};
221 +
222 +static struct platform_device cambria_uart = {
223 + .name = "serial8250",
224 + .id = PLAT8250_DEV_PLATFORM,
225 + .dev = {
226 + .platform_data = cambria_uart_data,
227 + },
228 + .num_resources = 1,
229 + .resource = &cambria_uart_resource,
230 +};
231 +
232 +static struct resource cambria_pata_resources[] = {
233 + {
234 + .flags = IORESOURCE_MEM
235 + },
236 + {
237 + .flags = IORESOURCE_MEM,
238 + },
239 + {
240 + .name = "intrq",
241 + .start = IRQ_IXP4XX_GPIO12,
242 + .end = IRQ_IXP4XX_GPIO12,
243 + .flags = IORESOURCE_IRQ,
244 + },
245 +};
246 +
247 +static struct ixp4xx_pata_data cambria_pata_data = {
248 + .cs0_bits = 0xbfff3c03,
249 + .cs1_bits = 0xbfff3c03,
250 +};
251 +
252 +static struct platform_device cambria_pata = {
253 + .name = "pata_ixp4xx_cf",
254 + .id = 0,
255 + .dev.platform_data = &cambria_pata_data,
256 + .num_resources = ARRAY_SIZE(cambria_pata_resources),
257 + .resource = cambria_pata_resources,
258 +};
259 +
260 +static struct eth_plat_info cambria_npec_data = {
261 + .phy = 2,
262 + .rxq = 4,
263 + .txreadyq = 21,
264 +};
265 +
266 +static struct eth_plat_info cambria_npea_data = {
267 + .phy = 1,
268 + .rxq = 2,
269 + .txreadyq = 19,
270 +};
271 +
272 +static struct platform_device cambria_npec_device = {
273 + .name = "ixp4xx_eth",
274 + .id = IXP4XX_ETH_NPEC,
275 + .dev.platform_data = &cambria_npec_data,
276 +};
277 +
278 +static struct platform_device cambria_npea_device = {
279 + .name = "ixp4xx_eth",
280 + .id = IXP4XX_ETH_NPEA,
281 + .dev.platform_data = &cambria_npea_data,
282 +};
283 +
284 +static struct gpio_led cambria_gpio_leds[] = {
285 + {
286 + .name = "user", /* green led */
287 + .gpio = 5,
288 + .active_low = 1,
289 + }
290 +};
291 +
292 +static struct gpio_led_platform_data cambria_gpio_leds_data = {
293 + .num_leds = 1,
294 + .leds = cambria_gpio_leds,
295 +};
296 +
297 +static struct platform_device cambria_gpio_leds_device = {
298 + .name = "leds-gpio",
299 + .id = -1,
300 + .dev.platform_data = &cambria_gpio_leds_data,
301 +};
302 +
303 +
304 +static struct latch_led cambria_latch_leds[] = {
305 + {
306 + .name = "ledA", /* green led */
307 + .bit = 0,
308 + },
309 + {
310 + .name = "ledB", /* green led */
311 + .bit = 1,
312 + },
313 + {
314 + .name = "ledC", /* green led */
315 + .bit = 2,
316 + },
317 + {
318 + .name = "ledD", /* green led */
319 + .bit = 3,
320 + },
321 + {
322 + .name = "ledE", /* green led */
323 + .bit = 4,
324 + },
325 + {
326 + .name = "ledF", /* green led */
327 + .bit = 5,
328 + },
329 + {
330 + .name = "ledG", /* green led */
331 + .bit = 6,
332 + },
333 + {
334 + .name = "ledH", /* green led */
335 + .bit = 7,
336 + }
337 +};
338 +
339 +static struct latch_led_platform_data cambria_latch_leds_data = {
340 + .num_leds = 8,
341 + .leds = cambria_latch_leds,
342 + .mem = 0x53F40000,
343 +};
344 +
345 +static struct platform_device cambria_latch_leds_device = {
346 + .name = "leds-latch",
347 + .id = -1,
348 + .dev.platform_data = &cambria_latch_leds_data,
349 +};
350 +
351 +static struct resource cambria_usb0_resources[] = {
352 + {
353 + .start = 0xCD000000,
354 + .end = 0xCD000300,
355 + .flags = IORESOURCE_MEM,
356 + },
357 + {
358 + .start = 32,
359 + .flags = IORESOURCE_IRQ,
360 + },
361 +};
362 +
363 +static struct resource cambria_usb1_resources[] = {
364 + {
365 + .start = 0xCE000000,
366 + .end = 0xCE000300,
367 + .flags = IORESOURCE_MEM,
368 + },
369 + {
370 + .start = 33,
371 + .flags = IORESOURCE_IRQ,
372 + },
373 +};
374 +
375 +static u64 ehci_dma_mask = ~(u32)0;
376 +
377 +static struct platform_device cambria_usb0_device = {
378 + .name = "ixp4xx-ehci",
379 + .id = 0,
380 + .resource = cambria_usb0_resources,
381 + .num_resources = ARRAY_SIZE(cambria_usb0_resources),
382 + .dev = {
383 + .dma_mask = &ehci_dma_mask,
384 + .coherent_dma_mask = 0xffffffff,
385 + },
386 +};
387 +
388 +static struct platform_device cambria_usb1_device = {
389 + .name = "ixp4xx-ehci",
390 + .id = 1,
391 + .resource = cambria_usb1_resources,
392 + .num_resources = ARRAY_SIZE(cambria_usb1_resources),
393 + .dev = {
394 + .dma_mask = &ehci_dma_mask,
395 + .coherent_dma_mask = 0xffffffff,
396 + },
397 +};
398 +
399 +static struct platform_device *cambria_devices[] __initdata = {
400 + &cambria_i2c_gpio,
401 + &cambria_flash,
402 + &cambria_uart,
403 +};
404 +
405 +static void __init cambria_gw23xx_setup(void)
406 +{
407 + platform_device_register(&cambria_npec_device);
408 + platform_device_register(&cambria_npea_device);
409 +}
410 +
411 +#ifdef CONFIG_SENSORS_EEPROM
412 +static void __init cambria_gw2350_setup(void)
413 +{
414 + platform_device_register(&cambria_npec_device);
415 + platform_device_register(&cambria_npea_device);
416 +
417 + platform_device_register(&cambria_usb0_device);
418 + platform_device_register(&cambria_usb1_device);
419 +
420 + platform_device_register(&cambria_gpio_leds_device);
421 +}
422 +
423 +static void __init cambria_gw2358_setup(void)
424 +{
425 + platform_device_register(&cambria_npec_device);
426 + platform_device_register(&cambria_npea_device);
427 +
428 + platform_device_register(&cambria_usb0_device);
429 + platform_device_register(&cambria_usb1_device);
430 +
431 + platform_device_register(&cambria_pata);
432 +
433 + platform_device_register(&cambria_latch_leds_device);
434 +}
435 +
436 +static struct cambria_board_info cambria_boards[] __initdata = {
437 + {
438 + .model = "GW2350",
439 + .setup = cambria_gw2350_setup,
440 + }, {
441 + .model = "GW2358",
442 + .setup = cambria_gw2358_setup,
443 + }
444 +};
445 +
446 +static struct cambria_board_info * __init cambria_find_board_info(char *model)
447 +{
448 + int i;
449 +
450 + for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) {
451 + struct cambria_board_info *info = &cambria_boards[i];
452 + if (strncmp(info->model, model, strlen(info->model)) == 0)
453 + return info;
454 + }
455 +
456 + return NULL;
457 +}
458 +
459 +struct cambria_eeprom_header {
460 + unsigned char mac0[ETH_ALEN];
461 + unsigned char mac1[ETH_ALEN];
462 + unsigned char res0[4];
463 + unsigned char magic[2];
464 + unsigned char config[14];
465 + unsigned char model[16];
466 +};
467 +
468 +static int __init cambria_eeprom_notify(struct notifier_block *self,
469 + unsigned long event, void *t)
470 +{
471 + struct eeprom_data *ee = t;
472 + struct cambria_eeprom_header hdr;
473 +
474 + if (cambria_info)
475 + return NOTIFY_DONE;
476 +
477 + /* The eeprom is at address 0x51 */
478 + if (event != EEPROM_REGISTER || ee->client.addr != 0x51)
479 + return NOTIFY_DONE;
480 +
481 + ee->attr->read(&ee->client.dev.kobj, ee->attr, (char *)&hdr,
482 + 0, sizeof(hdr));
483 +
484 + if (hdr.magic[0] != 'G' || hdr.magic[1] != 'W')
485 + return NOTIFY_DONE;
486 +
487 + memcpy(&cambria_npec_data.hwaddr, hdr.mac0, ETH_ALEN);
488 + memcpy(&cambria_npea_data.hwaddr, hdr.mac1, ETH_ALEN);
489 +
490 + cambria_info = cambria_find_board_info(hdr.model);
491 +
492 + return NOTIFY_OK;
493 +}
494 +
495 +static struct notifier_block cambria_eeprom_notifier __initdata = {
496 + .notifier_call = cambria_eeprom_notify
497 +};
498 +
499 +static void __init cambria_register_eeprom_notifier(void)
500 +{
501 + register_eeprom_notifier(&cambria_eeprom_notifier);
502 +}
503 +
504 +static void __init cambria_unregister_eeprom_notifier(void)
505 +{
506 + unregister_eeprom_notifier(&cambria_eeprom_notifier);
507 +}
508 +#else /* CONFIG_SENSORS_EEPROM */
509 +static inline void cambria_register_eeprom_notifier(void) {};
510 +static inline void cambria_unregister_eeprom_notifier(void) {};
511 +#endif /* CONFIG_SENSORS_EEPROM */
512 +
513 +static void __init cambria_init(void)
514 +{
515 + ixp4xx_sys_init();
516 +
517 + cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
518 + cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
519 +
520 + *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
521 + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
522 +
523 + platform_add_devices(cambria_devices, ARRAY_SIZE(cambria_devices));
524 +
525 + cambria_pata_resources[0].start = 0x53e00000;
526 + cambria_pata_resources[0].end = 0x53e3ffff;
527 +
528 + cambria_pata_resources[1].start = 0x53e40000;
529 + cambria_pata_resources[1].end = 0x53e7ffff;
530 +
531 + cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
532 + cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
533 +
534 + cambria_register_eeprom_notifier();
535 +}
536 +
537 +static int __init cambria_model_setup(void)
538 +{
539 + if (!machine_is_cambria())
540 + return 0;
541 +
542 + if (cambria_info) {
543 + printk(KERN_DEBUG "Running on Gateworks Cambria %s\n",
544 + cambria_info->model);
545 + cambria_info->setup();
546 + } else {
547 + printk(KERN_INFO "Unknown/missing Cambria model number"
548 + " -- defaults will be used\n");
549 + cambria_gw23xx_setup();
550 + }
551 +
552 + cambria_unregister_eeprom_notifier();
553 + return 0;
554 +}
555 +late_initcall(cambria_model_setup);
556 +
557 +#ifdef CONFIG_MACH_CAMBRIA
558 +MACHINE_START(CAMBRIA, "Gateworks Cambria series")
559 + /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
560 + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
561 + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
562 + .map_io = ixp4xx_map_io,
563 + .init_irq = ixp4xx_init_irq,
564 + .timer = &ixp4xx_timer,
565 + .boot_params = 0x0100,
566 + .init_machine = cambria_init,
567 +MACHINE_END
568 +#endif
569 --- a/include/asm-arm/arch-ixp4xx/hardware.h
570 +++ b/include/asm-arm/arch-ixp4xx/hardware.h
571 @@ -18,7 +18,7 @@
572 #define __ASM_ARCH_HARDWARE_H__
573
574 #define PCIBIOS_MIN_IO 0x00001000
575 -#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
576 +#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x48000000 : 0x48000000)
577
578 /*
579 * We override the standard dma-mask routines for bouncing.