uboot-lantiq: fix boot of images larger than 8MB
[openwrt/openwrt.git] / target / linux / ixp4xx / patches-3.18 / 185-mi424wr_support.patch
1 --- a/arch/arm/configs/ixp4xx_defconfig
2 +++ b/arch/arm/configs/ixp4xx_defconfig
3 @@ -26,6 +26,7 @@ CONFIG_MACH_NAS100D=y
4 CONFIG_MACH_DSMG600=y
5 CONFIG_MACH_FSG=y
6 CONFIG_MACH_GTWX5715=y
7 +CONFIG_MACH_MI424WR=y
8 CONFIG_IXP4XX_QMGR=y
9 CONFIG_IXP4XX_NPE=y
10 # CONFIG_ARM_THUMB is not set
11 --- a/arch/arm/mach-ixp4xx/Kconfig
12 +++ b/arch/arm/mach-ixp4xx/Kconfig
13 @@ -258,6 +258,13 @@ config MACH_MIC256
14 Say 'Y' here if you want your kernel to support the MIC256
15 board from OMICRON electronics GmbH.
16
17 +config MACH_MI424WR
18 + bool "Actiontec MI424WR"
19 + depends on ARCH_IXP4XX
20 + select PCI
21 + help
22 + Add support for the Actiontec MI424-WR.
23 +
24 comment "IXP4xx Options"
25
26 config IXP4XX_INDIRECT_PCI
27 --- a/arch/arm/mach-ixp4xx/Makefile
28 +++ b/arch/arm/mach-ixp4xx/Makefile
29 @@ -25,6 +25,7 @@ obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixd
30 obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
31 obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
32 obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
33 +obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o
34
35 obj-y += common.o
36
37 @@ -51,6 +52,7 @@ obj-$(CONFIG_MACH_COMPEXWP18) += compex4
38 obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
39 obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
40 obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
41 +obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o
42
43 obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
44 obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
45 --- /dev/null
46 +++ b/arch/arm/mach-ixp4xx/mi424wr-pci.c
47 @@ -0,0 +1,70 @@
48 +/*
49 + * arch/arm/mach-ixp4xx/mi424wr-pci.c
50 + *
51 + * Actiontec MI424WR board-level PCI initialization
52 + *
53 + * Copyright (C) 2008 Jose Vasconcellos
54 + *
55 + * Maintainer: Jose Vasconcellos <jvasco@verizon.net>
56 + *
57 + * This program is free software; you can redistribute it and/or modify
58 + * it under the terms of the GNU General Public License version 2 as
59 + * published by the Free Software Foundation.
60 + *
61 + */
62 +
63 +#include <linux/kernel.h>
64 +#include <linux/pci.h>
65 +#include <linux/init.h>
66 +#include <linux/irq.h>
67 +
68 +#include <asm/mach-types.h>
69 +#include <asm/mach/pci.h>
70 +
71 +/* PCI controller GPIO to IRQ pin mappings
72 + * This information was obtained from Actiontec's GPL release.
73 + *
74 + * INTA INTB
75 + * SLOT 13 8 6
76 + * SLOT 14 7 8
77 + * SLOT 15 6 7
78 + */
79 +
80 +void __init mi424wr_pci_preinit(void)
81 +{
82 + irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
83 + irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
84 + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
85 +
86 + ixp4xx_pci_preinit();
87 +}
88 +
89 +static int __init mi424wr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
90 +{
91 + if (slot == 13)
92 + return IRQ_IXP4XX_GPIO8;
93 + if (slot == 14)
94 + return IRQ_IXP4XX_GPIO7;
95 + if (slot == 15)
96 + return IRQ_IXP4XX_GPIO6;
97 +
98 + return -1;
99 +}
100 +
101 +struct hw_pci mi424wr_pci __initdata = {
102 + .nr_controllers = 1,
103 + .preinit = mi424wr_pci_preinit,
104 + .ops = &ixp4xx_ops,
105 + .setup = ixp4xx_setup,
106 + .map_irq = mi424wr_map_irq,
107 +};
108 +
109 +int __init mi424wr_pci_init(void)
110 +{
111 + if (machine_is_mi424wr())
112 + pci_common_init(&mi424wr_pci);
113 + return 0;
114 +}
115 +
116 +subsys_initcall(mi424wr_pci_init);
117 +
118 --- /dev/null
119 +++ b/arch/arm/mach-ixp4xx/mi424wr-setup.c
120 @@ -0,0 +1,387 @@
121 +/*
122 + * arch/arm/mach-ixp4xx/mi424wr-setup.c
123 + *
124 + * Actiontec MI424-WR board setup
125 + * Copyright (c) 2008 Jose Vasconcellos
126 + *
127 + * Based on Gemtek GTWX5715 by
128 + * Copyright (C) 2004 George T. Joseph
129 + * Derived from Coyote
130 + *
131 + * This program is free software; you can redistribute it and/or
132 + * modify it under the terms of the GNU General Public License
133 + * as published by the Free Software Foundation; either version 2
134 + * of the License, or (at your option) any later version.
135 + *
136 + * This program is distributed in the hope that it will be useful,
137 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
138 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
139 + * GNU General Public License for more details.
140 + *
141 + * You should have received a copy of the GNU General Public License
142 + * along with this program; if not, write to the Free Software
143 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
144 + *
145 + */
146 +
147 +#include <linux/init.h>
148 +#include <linux/device.h>
149 +#include <linux/serial.h>
150 +#include <linux/serial_8250.h>
151 +#include <linux/types.h>
152 +#include <linux/memory.h>
153 +#include <linux/leds.h>
154 +#include <linux/spi/spi_gpio_old.h>
155 +#include <linux/dma-mapping.h>
156 +
157 +#include <asm/setup.h>
158 +#include <asm/system_info.h>
159 +#include <asm/irq.h>
160 +#include <asm/io.h>
161 +#include <asm/mach-types.h>
162 +#include <asm/mach/arch.h>
163 +#include <asm/mach/flash.h>
164 +
165 +/*
166 + * GPIO 2,3,4 and 9 are hard wired to the Micrel/Kendin KS8995M Switch
167 + * and operate as an SPI type interface. The details of the interface
168 + * are available on Kendin/Micrel's web site.
169 + */
170 +
171 +#define MI424WR_KSSPI_SELECT 9
172 +#define MI424WR_KSSPI_TXD 4
173 +#define MI424WR_KSSPI_CLOCK 2
174 +#define MI424WR_KSSPI_RXD 3
175 +
176 +/*
177 + * The "reset" button is wired to GPIO 10.
178 + * The GPIO is brought "low" when the button is pushed.
179 + */
180 +
181 +#define MI424WR_BUTTON_GPIO 10
182 +#define MI424WR_BUTTON_IRQ IRQ_IXP4XX_GPIO10
183 +
184 +#define MI424WR_MOCA_WAN_LED 11
185 +
186 +/* Latch on CS1 - taken from Actiontec's 2.4 source code
187 + *
188 + * default latch value
189 + * 0 - power alarm led (red) 0 (off)
190 + * 1 - power led (green) 0 (off)
191 + * 2 - wireless led (green) 1 (off)
192 + * 3 - no internet led (red) 0 (off)
193 + * 4 - internet ok led (green) 0 (off)
194 + * 5 - moca LAN 0 (off)
195 + * 6 - WAN alarm led (red) 0 (off)
196 + * 7 - PCI reset 1 (not reset)
197 + * 8 - IP phone 1 led (green) 1 (off)
198 + * 9 - IP phone 2 led (green) 1 (off)
199 + * 10 - VOIP ready led (green) 1 (off)
200 + * 11 - PSTN relay 1 control 0 (PSTN)
201 + * 12 - PSTN relay 1 control 0 (PSTN)
202 + * 13 - N/A
203 + * 14 - N/A
204 + * 15 - N/A
205 + */
206 +
207 +#define MI424WR_LATCH_MASK 0x04
208 +#define MI424WR_LATCH_DEFAULT 0x1f86
209 +
210 +#define MI424WR_LATCH_ALARM_LED 0x00
211 +#define MI424WR_LATCH_POWER_LED 0x01
212 +#define MI424WR_LATCH_WIRELESS_LED 0x02
213 +#define MI424WR_LATCH_INET_DOWN_LED 0x03
214 +#define MI424WR_LATCH_INET_OK_LED 0x04
215 +#define MI424WR_LATCH_MOCA_LAN_LED 0x05
216 +#define MI424WR_LATCH_WAN_ALARM_LED 0x06
217 +#define MI424WR_LATCH_PCI_RESET 0x07
218 +#define MI424WR_LATCH_PHONE1_LED 0x08
219 +#define MI424WR_LATCH_PHONE2_LED 0x09
220 +#define MI424WR_LATCH_VOIP_LED 0x10
221 +#define MI424WR_LATCH_PSTN_RELAY1 0x11
222 +#define MI424WR_LATCH_PSTN_RELAY2 0x12
223 +
224 +/* initialize CS1 to default timings, Intel style, 16-bit bus */
225 +#define MI424WR_CS1_CONFIG 0x80000002
226 +
227 +/* Define both UARTs but they are not easily accessible.
228 + */
229 +
230 +static struct resource mi424wr_uart_resources[] = {
231 + {
232 + .start = IXP4XX_UART1_BASE_PHYS,
233 + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
234 + .flags = IORESOURCE_MEM,
235 + },
236 + {
237 + .start = IXP4XX_UART2_BASE_PHYS,
238 + .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
239 + .flags = IORESOURCE_MEM,
240 + }
241 +};
242 +
243 +
244 +static struct plat_serial8250_port mi424wr_uart_platform_data[] = {
245 + {
246 + .mapbase = IXP4XX_UART1_BASE_PHYS,
247 + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
248 + .irq = IRQ_IXP4XX_UART1,
249 + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
250 + .iotype = UPIO_MEM,
251 + .regshift = 2,
252 + .uartclk = IXP4XX_UART_XTAL,
253 + },
254 + {
255 + .mapbase = IXP4XX_UART2_BASE_PHYS,
256 + .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
257 + .irq = IRQ_IXP4XX_UART2,
258 + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
259 + .iotype = UPIO_MEM,
260 + .regshift = 2,
261 + .uartclk = IXP4XX_UART_XTAL,
262 + },
263 + { },
264 +};
265 +
266 +static struct platform_device mi424wr_uart_device = {
267 + .name = "serial8250",
268 + .id = PLAT8250_DEV_PLATFORM,
269 + .dev.platform_data = mi424wr_uart_platform_data,
270 + .num_resources = ARRAY_SIZE(mi424wr_uart_resources),
271 + .resource = mi424wr_uart_resources,
272 +};
273 +
274 +static struct flash_platform_data mi424wr_flash_data = {
275 + .map_name = "cfi_probe",
276 + .width = 2,
277 +};
278 +
279 +static struct resource mi424wr_flash_resource = {
280 + .flags = IORESOURCE_MEM,
281 +};
282 +
283 +static struct platform_device mi424wr_flash = {
284 + .name = "IXP4XX-Flash",
285 + .id = 0,
286 + .dev.platform_data = &mi424wr_flash_data,
287 + .num_resources = 1,
288 + .resource = &mi424wr_flash_resource,
289 +};
290 +
291 +static int mi424wr_spi_boardinfo_setup(struct spi_board_info *bi,
292 + struct spi_master *master, void *data)
293 +{
294 +
295 + strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias));
296 +
297 + bi->max_speed_hz = 5000000 /* Hz */;
298 + bi->bus_num = master->bus_num;
299 + bi->mode = SPI_MODE_0;
300 +
301 + return 0;
302 +}
303 +
304 +static struct spi_gpio_platform_data mi424wr_spi_bus_data = {
305 + .pin_cs = MI424WR_KSSPI_SELECT,
306 + .pin_clk = MI424WR_KSSPI_CLOCK,
307 + .pin_miso = MI424WR_KSSPI_RXD,
308 + .pin_mosi = MI424WR_KSSPI_TXD,
309 + .cs_activelow = 1,
310 + .no_spi_delay = 1,
311 + .boardinfo_setup = mi424wr_spi_boardinfo_setup,
312 +};
313 +
314 +static struct gpio_led mi424wr_gpio_led[] = {
315 + {
316 + .name = "moca-wan", /* green led */
317 + .gpio = MI424WR_MOCA_WAN_LED,
318 + .active_low = 0,
319 + }
320 +};
321 +
322 +static struct gpio_led_platform_data mi424wr_gpio_leds_data = {
323 + .num_leds = 1,
324 + .leds = mi424wr_gpio_led,
325 +};
326 +
327 +static struct platform_device mi424wr_gpio_leds = {
328 + .name = "leds-gpio",
329 + .id = -1,
330 + .dev.platform_data = &mi424wr_gpio_leds_data,
331 +};
332 +
333 +static uint16_t latch_value = MI424WR_LATCH_DEFAULT;
334 +static uint16_t __iomem *iobase;
335 +
336 +static void mi424wr_latch_set_led(u8 bit, enum led_brightness value)
337 +{
338 +
339 + if (((MI424WR_LATCH_MASK >> bit) & 1) ^ (value == LED_OFF))
340 + latch_value &= ~(0x1 << bit);
341 + else
342 + latch_value |= (0x1 << bit);
343 +
344 + __raw_writew(latch_value, iobase);
345 +
346 +}
347 +
348 +static struct latch_led mi424wr_latch_led[] = {
349 + {
350 + .name = "power-alarm",
351 + .bit = MI424WR_LATCH_ALARM_LED,
352 + },
353 + {
354 + .name = "power-ok",
355 + .bit = MI424WR_LATCH_POWER_LED,
356 + },
357 + {
358 + .name = "wireless", /* green led */
359 + .bit = MI424WR_LATCH_WIRELESS_LED,
360 + },
361 + {
362 + .name = "inet-down", /* red led */
363 + .bit = MI424WR_LATCH_INET_DOWN_LED,
364 + },
365 + {
366 + .name = "inet-up", /* green led */
367 + .bit = MI424WR_LATCH_INET_OK_LED,
368 + },
369 + {
370 + .name = "moca-lan", /* green led */
371 + .bit = MI424WR_LATCH_MOCA_LAN_LED,
372 + },
373 + {
374 + .name = "wan-alarm", /* red led */
375 + .bit = MI424WR_LATCH_WAN_ALARM_LED,
376 + }
377 +};
378 +
379 +static struct latch_led_platform_data mi424wr_latch_leds_data = {
380 + .num_leds = ARRAY_SIZE(mi424wr_latch_led),
381 + .mem = 0x51000000,
382 + .leds = mi424wr_latch_led,
383 + .set_led = mi424wr_latch_set_led,
384 +};
385 +
386 +static struct platform_device mi424wr_latch_leds = {
387 + .name = "leds-latch",
388 + .id = -1,
389 + .dev.platform_data = &mi424wr_latch_leds_data,
390 +};
391 +
392 +static struct platform_device mi424wr_spi_bus = {
393 + .name = "spi-gpio",
394 + .id = 0,
395 + .dev.platform_data = &mi424wr_spi_bus_data,
396 +};
397 +
398 +static struct eth_plat_info mi424wr_wan_data = {
399 + .phy = 17, /* KS8721 */
400 + .rxq = 3,
401 + .txreadyq = 20,
402 +};
403 +
404 +static struct eth_plat_info mi424wr_lan_data = {
405 + .phy = IXP4XX_ETH_PHY_MAX_ADDR,
406 + .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
407 + .rxq = 4,
408 + .txreadyq = 21,
409 +};
410 +
411 +static struct platform_device mi424wr_npe_devices[] = {
412 + {
413 + .name = "ixp4xx_eth",
414 + .id = IXP4XX_ETH_NPEC,
415 + .dev.platform_data = &mi424wr_lan_data,
416 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
417 + }, {
418 + .name = "ixp4xx_eth",
419 + .id = IXP4XX_ETH_NPEB,
420 + .dev.platform_data = &mi424wr_wan_data,
421 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
422 + }
423 +};
424 +
425 +static struct eth_plat_info mi424wr_wanD_data = {
426 + .phy = 5,
427 + .rxq = 4,
428 + .txreadyq = 21,
429 +};
430 +
431 +static struct eth_plat_info mi424wr_lanD_data = {
432 + .phy = IXP4XX_ETH_PHY_MAX_ADDR,
433 + .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
434 + .rxq = 3,
435 + .txreadyq = 20,
436 +};
437 +
438 +static struct platform_device mi424wr_npeD_devices[] = {
439 + {
440 + .name = "ixp4xx_eth",
441 + .id = IXP4XX_ETH_NPEB,
442 + .dev.platform_data = &mi424wr_lanD_data,
443 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
444 + }, {
445 + .name = "ixp4xx_eth",
446 + .id = IXP4XX_ETH_NPEC,
447 + .dev.platform_data = &mi424wr_wanD_data,
448 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
449 + }
450 +};
451 +
452 +static struct platform_device *mi424wr_devices[] __initdata = {
453 + &mi424wr_uart_device,
454 + &mi424wr_flash,
455 + &mi424wr_gpio_leds,
456 + &mi424wr_latch_leds,
457 + &mi424wr_spi_bus,
458 +};
459 +
460 +static void __init mi424wr_init(void)
461 +{
462 + ixp4xx_sys_init();
463 +
464 + mi424wr_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
465 + mi424wr_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1;
466 +
467 + *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
468 + *IXP4XX_EXP_CS1 = MI424WR_CS1_CONFIG;
469 +
470 + /* configure button as input
471 + */
472 + gpio_line_config(MI424WR_BUTTON_GPIO, IXP4XX_GPIO_IN);
473 +
474 + /* Initialize LEDs and enables PCI bus.
475 + */
476 + iobase = ioremap_nocache(IXP4XX_EXP_BUS_BASE(1), 0x1000);
477 + __raw_writew(latch_value, iobase);
478 +
479 + platform_add_devices(mi424wr_devices, ARRAY_SIZE(mi424wr_devices));
480 +
481 + /* Need to figure out how to detect revD.
482 + * Look for a revision argument sent by redboot.
483 + */
484 +#define revD 4
485 + if (system_rev == revD) {
486 + platform_device_register(&mi424wr_npeD_devices[0]);
487 + platform_device_register(&mi424wr_npeD_devices[1]);
488 + } else {
489 + platform_device_register(&mi424wr_npe_devices[0]);
490 + platform_device_register(&mi424wr_npe_devices[1]);
491 + }
492 +}
493 +
494 +
495 +MACHINE_START(MI424WR, "Actiontec MI424WR")
496 + /* Maintainer: Jose Vasconcellos */
497 + .map_io = ixp4xx_map_io,
498 + .init_irq = ixp4xx_init_irq,
499 + .init_time = ixp4xx_timer_init,
500 + .atag_offset = 0x0100,
501 + .init_machine = mi424wr_init,
502 +#if defined(CONFIG_PCI)
503 + .dma_zone_size = SZ_64M,
504 +#endif
505 + .restart = ixp4xx_restart,
506 +MACHINE_END
507 +