lantiq: Switch to the new SPI driver
[openwrt/openwrt.git] / target / linux / lantiq / dts / EASY80920.dtsi
1 /include/ "vr9.dtsi"
2
3 / {
4 chosen {
5 bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
6
7 leds {
8 boot = &power;
9 failsafe = &power;
10 running = &power;
11
12 usb = &usb1;
13 usb2 = &usb2;
14 };
15 };
16
17 memory@0 {
18 reg = <0x0 0x4000000>;
19 };
20
21 fpi@10000000 {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "lantiq,fpi", "simple-bus";
25 ranges = <0x0 0x10000000 0xEEFFFFF>;
26 reg = <0x10000000 0xEF00000>;
27
28 localbus@0 {
29 #address-cells = <2>;
30 #size-cells = <1>;
31 compatible = "lantiq,localbus", "simple-bus";
32
33 };
34
35 gpio: pinmux@E100B10 {
36 compatible = "lantiq,pinctrl-xr9";
37 pinctrl-names = "default";
38 pinctrl-0 = <&state_default>;
39
40 interrupt-parent = <&icu0>;
41 interrupts = <166 135 66 40 41 42 38>;
42
43 #gpio-cells = <2>;
44 gpio-controller;
45 reg = <0xE100B10 0xA0>;
46
47 state_default: pinmux {
48 exin3 {
49 lantiq,groups = "exin3";
50 lantiq,function = "exin";
51 };
52 stp {
53 lantiq,groups = "stp";
54 lantiq,function = "stp";
55 };
56 nand {
57 lantiq,groups = "nand cle", "nand ale",
58 "nand rd", "nand rdy";
59 lantiq,function = "ebu";
60 };
61 mdio {
62 lantiq,groups = "mdio";
63 lantiq,function = "mdio";
64 };
65 pci {
66 lantiq,groups = "gnt1", "req1";
67 lantiq,function = "pci";
68 };
69 conf_out {
70 lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
71 "io4", "io5", "io6", /* stp */
72 "io21",
73 "io33";
74 lantiq,open-drain;
75 lantiq,pull = <0>;
76 lantiq,output = <1>;
77 };
78 pcie-rst {
79 lantiq,pins = "io38";
80 lantiq,pull = <0>;
81 lantiq,output = <1>;
82 };
83 conf_in {
84 lantiq,pins = "io39", /* exin3 */
85 "io48"; /* nand rdy */
86 lantiq,pull = <2>;
87 };
88 };
89 pins_spi_default: pins_spi_default {
90 spi_in {
91 lantiq,groups = "spi_di";
92 lantiq,function = "spi";
93 };
94 spi_out {
95 lantiq,groups = "spi_do", "spi_clk",
96 "spi_cs4";
97 lantiq,function = "spi";
98 lantiq,output = <1>;
99 };
100 };
101 };
102
103 eth@E108000 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 compatible = "lantiq,xrx200-net";
107 reg = < 0xE108000 0x3000 /* switch */
108 0xE10B100 0x70 /* mdio */
109 0xE10B1D8 0x30 /* mii */
110 0xE10B308 0x30 /* pmac */
111 >;
112 interrupt-parent = <&icu0>;
113 interrupts = <73 72>;
114
115 lan: interface@0 {
116 compatible = "lantiq,xrx200-pdi";
117 #address-cells = <1>;
118 #size-cells = <0>;
119 reg = <0>;
120 mac-address = [ 00 11 22 33 44 55 ];
121
122 ethernet@0 {
123 compatible = "lantiq,xrx200-pdi-port";
124 reg = <0>;
125 phy-mode = "rgmii";
126 phy-handle = <&phy0>;
127 };
128 ethernet@1 {
129 compatible = "lantiq,xrx200-pdi-port";
130 reg = <1>;
131 phy-mode = "rgmii";
132 phy-handle = <&phy1>;
133 };
134 ethernet@2 {
135 compatible = "lantiq,xrx200-pdi-port";
136 reg = <2>;
137 phy-mode = "gmii";
138 phy-handle = <&phy11>;
139 };
140 };
141
142 wan: interface@1 {
143 compatible = "lantiq,xrx200-pdi";
144 #address-cells = <1>;
145 #size-cells = <0>;
146 reg = <1>;
147 mac-address = [ 00 11 22 33 44 56 ];
148 lantiq,wan;
149 ethernet@5 {
150 compatible = "lantiq,xrx200-pdi-port";
151 reg = <5>;
152 phy-mode = "rgmii";
153 phy-handle = <&phy5>;
154 };
155 };
156
157 test: interface@2 {
158 compatible = "lantiq,xrx200-pdi";
159 #address-cells = <1>;
160 #size-cells = <0>;
161 reg = <2>;
162 mac-address = [ 00 11 22 33 44 57 ];
163 ethernet@4 {
164 compatible = "lantiq,xrx200-pdi-port";
165 reg = <4>;
166 phynmode0 = "gmii";
167 phy-handle = <&phy13>;
168 };
169 };
170
171 mdio@0 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "lantiq,xrx200-mdio";
175 phy0: ethernet-phy@0 {
176 reg = <0x0>;
177 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
178 };
179 phy1: ethernet-phy@1 {
180 reg = <0x1>;
181 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
182 };
183 phy5: ethernet-phy@5 {
184 reg = <0x5>;
185 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
186 };
187 phy11: ethernet-phy@11 {
188 reg = <0x11>;
189 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
190 };
191 phy13: ethernet-phy@13 {
192 reg = <0x13>;
193 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
194 };
195 };
196 };
197
198 stp: stp@E100BB0 {
199 compatible = "lantiq,gpio-stp-xway";
200 reg = <0xE100BB0 0x40>;
201 #gpio-cells = <2>;
202 gpio-controller;
203
204 lantiq,shadow = <0xffff>;
205 lantiq,groups = <0x7>;
206 lantiq,dsl = <0x3>;
207 lantiq,phy1 = <0x7>;
208 lantiq,phy2 = <0x7>;
209 /* lantiq,rising; */
210 };
211
212 ifxhcd@E101000 {
213 status = "okay";
214 gpios = <&gpio 33 0>;
215 lantiq,portmask = <0x3>;
216 };
217
218 pci@E105400 {
219 #address-cells = <3>;
220 #size-cells = <2>;
221 #interrupt-cells = <1>;
222 compatible = "lantiq,pci-xway1";
223 bus-range = <0x0 0x0>;
224 ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
225 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
226 reg = <0x7000000 0x8000 /* config space */
227 0xE105400 0x400>; /* pci bridge */
228 lantiq,bus-clock = <33333333>;
229 /*lantiq,external-clock;*/
230 lantiq,delay-hi = <0>; /* 0ns delay */
231 lantiq,delay-lo = <0>; /* 0.0ns delay */
232 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
233 interrupt-map = <
234 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
235 >;
236 gpios-reset = <&gpio 21 0>;
237 req-mask = <0x1>; /* GNT1 */
238 };
239 };
240
241 gphy-xrx200 {
242 compatible = "lantiq,phy-xrx200";
243 firmware = "lantiq/vr9_phy11g_a2x.bin";
244 phys = [ 00 01 ];
245 };
246
247 gpio-keys-polled {
248 compatible = "gpio-keys-polled";
249 #address-cells = <1>;
250 #size-cells = <0>;
251 poll-interval = <100>;
252 /* reset {
253 label = "reset";
254 gpios = <&gpio 7 1>;
255 linux,code = <0x198>;
256 };*/
257 paging {
258 label = "paging";
259 gpios = <&gpio 11 1>;
260 linux,code = <0x100>;
261 };
262 };
263
264 gpio-leds {
265 compatible = "gpio-leds";
266
267 power: power {
268 label = "easy80920:green:power";
269 gpios = <&stp 9 0>;
270 default-state = "keep";
271 };
272 warning {
273 label = "easy80920:green:warning";
274 gpios = <&stp 22 0>;
275 };
276 fxs1 {
277 label = "easy80920:green:fxs1";
278 gpios = <&stp 21 0>;
279 };
280 fxs2 {
281 label = "easy80920:green:fxs2";
282 gpios = <&stp 20 0>;
283 };
284 fxo {
285 label = "easy80920:green:fxo";
286 gpios = <&stp 19 0>;
287 };
288 usb1: usb1 {
289 label = "easy80920:green:usb1";
290 gpios = <&stp 18 0>;
291 };
292 usb2: usb2 {
293 label = "easy80920:green:usb2";
294 gpios = <&stp 15 0>;
295 };
296 sd {
297 label = "easy80920:green:sd";
298 gpios = <&stp 14 0>;
299 };
300 wps {
301 label = "easy80920:green:wps";
302 gpios = <&stp 12 0>;
303 };
304 };
305 };
306
307 &spi {
308 pinctrl-names = "default";
309 pinctrl-0 = <&pins_spi_default>;
310
311 status = "ok";
312
313 m25p80@4 {
314 #address-cells = <1>;
315 #size-cells = <1>;
316 compatible = "jedec,spi-nor";
317 reg = <4 0>;
318 spi-max-frequency = <1000000>;
319
320 partition@0 {
321 reg = <0x0 0x20000>;
322 label = "SPI (RO) U-Boot Image";
323 read-only;
324 };
325
326 partition@20000 {
327 reg = <0x20000 0x10000>;
328 label = "ENV_MAC";
329 read-only;
330 };
331
332 partition@30000 {
333 reg = <0x30000 0x10000>;
334 label = "DPF";
335 read-only;
336 };
337
338 partition@40000 {
339 reg = <0x40000 0x10000>;
340 label = "NVRAM";
341 read-only;
342 };
343
344 partition@500000 {
345 reg = <0x50000 0x003a0000>;
346 label = "kernel";
347 };
348 };
349 };