target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4
   5 / {
   6         compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9";
   7
   8         chosen {
   9                 bootargs = "console=ttyLTQ0,115200";
  10         };
  11
  12         aliases {
  13                 led-boot = &power;
  14                 led-failsafe = &power;
  15                 led-running = &power;
  16
  17                 led-usb = &usb1;
  18                 led-usb2 = &usb2;
  19         };
  20
  21         memory@0 {
  22                 reg = <0x0 0x4000000>;
  23         };
  24
  25         fpi@10000000 {
  26                 gpio: pinmux@E100B10 {
  27                         pinctrl-names = "default";
  28                         pinctrl-0 = <&state_default>;
  29
  30                         state_default: pinmux {
  31                                 exin3 {
  32                                         lantiq,groups = "exin3";
  33                                         lantiq,function = "exin";
  34                                 };
  35                                 stp {
  36                                         lantiq,groups = "stp";
  37                                         lantiq,function = "stp";
  38                                 };
  39                                 nand {
  40                                         lantiq,groups = "nand cle", "nand ale",
  41                                                         "nand rd", "nand rdy";
  42                                         lantiq,function = "ebu";
  43                                 };
  44                                 mdio {
  45                                         lantiq,groups = "mdio";
  46                                         lantiq,function = "mdio";
  47                                 };
  48                                 pci {
  49                                         lantiq,groups = "gnt1", "req1";
  50                                         lantiq,function = "pci";
  51                                 };
  52                                 conf_out {
  53                                         lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
  54                                                         "io4", "io5", "io6", /* stp */
  55                                                         "io21",
  56                                                         "io33";
  57                                         lantiq,open-drain;
  58                                         lantiq,pull = <0>;
  59                                         lantiq,output = <1>;
  60                                 };
  61                                 pcie-rst {
  62                                         lantiq,pins = "io38";
  63                                         lantiq,pull = <0>;
  64                                         lantiq,output = <1>;
  65                                 };
  66                                 conf_in {
  67                                         lantiq,pins = "io39", /* exin3 */
  68                                                         "io48"; /* nand rdy */
  69                                         lantiq,pull = <2>;
  70                                 };
  71                         };
  72                         pins_spi_default: pins_spi_default {
  73                                 spi_in {
  74                                         lantiq,groups = "spi_di";
  75                                         lantiq,function = "spi";
  76                                 };
  77                                 spi_out {
  78                                         lantiq,groups = "spi_do", "spi_clk",
  79                                                 "spi_cs4";
  80                                         lantiq,function = "spi";
  81                                         lantiq,output = <1>;
  82                                 };
  83                         };
  84                 };
  85
  86                 stp: stp@E100BB0 {
  87                         compatible = "lantiq,gpio-stp-xway";
  88                         reg = <0xE100BB0 0x40>;
  89                         #gpio-cells = <2>;
  90                         gpio-controller;
  91
  92                         lantiq,shadow = <0xffff>;
  93                         lantiq,groups = <0x7>;
  94                         lantiq,dsl = <0x3>;
  95                         lantiq,phy1 = <0x7>;
  96                         lantiq,phy2 = <0x7>;
  97                         /* lantiq,rising; */
  98                 };
  99
 100                 ifxhcd@E101000 {
 101                         status = "okay";
 102                         gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
 103                         lantiq,portmask = <0x3>;
 104                 };
 105         };
 106
 107         gphy-xrx200 {
 108                 compatible = "lantiq,phy-xrx200";
 109                 firmware1 = "lantiq/xrx200_phy11g_a14.bin";
 110                 firmware2 = "lantiq/xrx200_phy11g_a22.bin";
 111                 phys = [ 00 01 ];
 112         };
 113
 114         gpio-keys-polled {
 115                 compatible = "gpio-keys-polled";
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118                 poll-interval = <100>;
 119 /*              reset {
 120                         label = "reset";
 121                         gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
 122                         linux,code = <KEY_RESTART>;
 123                 };*/
 124                 paging {
 125                         label = "paging";
 126                         gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
 127                         linux,code = <KEY_PHONE>;
 128                 };
 129         };
 130
 131         gpio-leds {
 132                 compatible = "gpio-leds";
 133
 134                 power: power {
 135                         label = "easy80920:green:power";
 136                         gpios = <&stp 9 GPIO_ACTIVE_HIGH>;
 137                         default-state = "keep";
 138                 };
 139                 warning {
 140                         label = "easy80920:green:warning";
 141                         gpios = <&stp 22 GPIO_ACTIVE_HIGH>;
 142                 };
 143                 fxs1 {
 144                         label = "easy80920:green:fxs1";
 145                         gpios = <&stp 21 GPIO_ACTIVE_HIGH>;
 146                 };
 147                 fxs2 {
 148                         label = "easy80920:green:fxs2";
 149                         gpios = <&stp 20 GPIO_ACTIVE_HIGH>;
 150                 };
 151                 fxo {
 152                         label = "easy80920:green:fxo";
 153                         gpios = <&stp 19 GPIO_ACTIVE_HIGH>;
 154                 };
 155                 usb1: usb1 {
 156                         label = "easy80920:green:usb1";
 157                         gpios = <&stp 18 GPIO_ACTIVE_HIGH>;
 158                 };
 159                 usb2: usb2 {
 160                         label = "easy80920:green:usb2";
 161                         gpios = <&stp 15 GPIO_ACTIVE_HIGH>;
 162                 };
 163                 sd {
 164                         label = "easy80920:green:sd";
 165                         gpios = <&stp 14 GPIO_ACTIVE_HIGH>;
 166                 };
 167                 wps {
 168                         label = "easy80920:green:wps";
 169                         gpios = <&stp 12 GPIO_ACTIVE_HIGH>;
 170                 };
 171         };
 172 };
 173
 174 &spi {
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pins_spi_default>;
 177
 178         status = "ok";
 179
 180         m25p80@4 {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 compatible = "jedec,spi-nor";
 184                 reg = <4 0>;
 185                 spi-max-frequency = <1000000>;
 186
 187                 partitions {
 188                         compatible = "fixed-partitions";
 189                         #address-cells = <1>;
 190                         #size-cells = <1>;
 191
 192                         partition@0 {
 193                                 reg = <0x0 0x20000>;
 194                                 label = "SPI (RO) U-Boot Image";
 195                                 read-only;
 196                         };
 197
 198                         partition@20000 {
 199                                 reg = <0x20000 0x10000>;
 200                                 label = "ENV_MAC";
 201                                 read-only;
 202                         };
 203
 204                         partition@30000 {
 205                                 reg = <0x30000 0x10000>;
 206                                 label = "DPF";
 207                                 read-only;
 208                         };
 209
 210                         partition@40000 {
 211                                 reg = <0x40000 0x10000>;
 212                                 label = "NVRAM";
 213                                 read-only;
 214                         };
 215
 216                         partition@500000 {
 217                                 reg = <0x50000 0x003a0000>;
 218                                 label = "kernel";
 219                         };
 220                 };
 221         };
 222 };
 223
 224 &eth0 {
 225         lan: interface@0 {
 226                 compatible = "lantiq,xrx200-pdi";
 227                 #address-cells = <1>;
 228                 #size-cells = <0>;
 229                 reg = <0>;
 230                 lantiq,switch;
 231
 232                 ethernet@4 {
 233                         compatible = "lantiq,xrx200-pdi-port";
 234                         reg = <4>;
 235                         phy-mode = "gmii";
 236                         phy-handle = <&phy13>;
 237                 };
 238                 ethernet@2 {
 239                         compatible = "lantiq,xrx200-pdi-port";
 240                         reg = <2>;
 241                         phy-mode = "gmii";
 242                         phy-handle = <&phy11>;
 243                 };
 244                 ethernet@1 {
 245                         compatible = "lantiq,xrx200-pdi-port";
 246                         reg = <1>;
 247                         phy-mode = "rgmii";
 248                         phy-handle = <&phy1>;
 249                 };
 250                 ethernet@0 {
 251                         compatible = "lantiq,xrx200-pdi-port";
 252                         reg = <0>;
 253                         phy-mode = "rgmii";
 254                         phy-handle = <&phy0>;
 255                 };
 256         };
 257
 258         wan: interface@1 {
 259                 compatible = "lantiq,xrx200-pdi";
 260                 #address-cells = <1>;
 261                 #size-cells = <0>;
 262                 reg = <1>;
 263                 lantiq,wan;
 264
 265                 ethernet@5 {
 266                         compatible = "lantiq,xrx200-pdi-port";
 267                         reg = <5>;
 268                         phy-mode = "rgmii";
 269                         phy-handle = <&phy5>;
 270                 };
 271         };
 272
 273         mdio@0 {
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 compatible = "lantiq,xrx200-mdio";
 277                 phy0: ethernet-phy@0 {
 278                         reg = <0x0>;
 279                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 280                 };
 281                 phy1: ethernet-phy@1 {
 282                         reg = <0x1>;
 283                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 284                 };
 285                 phy5: ethernet-phy@5 {
 286                         reg = <0x5>;
 287                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 288                 };
 289                 phy11: ethernet-phy@11 {
 290                         reg = <0x11>;
 291                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 292                 };
 293                 phy13: ethernet-phy@13 {
 294                         reg = <0x13>;
 295                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 296                 };
 297         };
 298 };