* fixes spi flash for ar9
[openwrt/openwrt.git] / target / linux / lantiq / patches-2.6.39 / 410-spi2.patch
1 From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2 Date: Thu, 3 Mar 2011 17:15:30 +0000 (+0100)
3 Subject: SPI: lantiq: Add driver for Lantiq SoC SPI controller
4 X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=653c95b8b9066c9c6ac08bd64d0ceee439e9fd90;hp=3d21b04682ae8eb1c1965aba39d1796e8c5ad84b
5
6 SPI: lantiq: Add driver for Lantiq SoC SPI controller
7
8 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 ---
10
11 --- a/drivers/spi/Kconfig
12 +++ b/drivers/spi/Kconfig
13 @@ -193,6 +193,14 @@
14 This enables using the Freescale i.MX SPI controllers in master
15 mode.
16
17 +config SPI_LANTIQ
18 + tristate "Lantiq SoC SPI controller"
19 + depends on SOC_TYPE_XWAY
20 + select SPI_BITBANG
21 + help
22 + This driver supports the Lantiq SoC SPI controller in master
23 + mode.
24 +
25 config SPI_LM70_LLP
26 tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
27 depends on PARPORT && EXPERIMENTAL
28 --- a/drivers/spi/Makefile
29 +++ b/drivers/spi/Makefile
30 @@ -26,6 +26,7 @@
31 obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
32 obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o
33 obj-$(CONFIG_SPI_IMX) += spi_imx.o
34 +obj-$(CONFIG_SPI_LANTIQ) += spi_lantiq.o
35 obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
36 obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
37 obj-$(CONFIG_SPI_PXA2XX_PCI) += pxa2xx_spi_pci.o
38 --- /dev/null
39 +++ b/drivers/spi/spi_lantiq.c
40 @@ -0,0 +1,1062 @@
41 +/*
42 + * Lantiq SoC SPI controller
43 + *
44 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
45 + *
46 + * This program is free software; you can distribute it and/or modify it
47 + * under the terms of the GNU General Public License (Version 2) as
48 + * published by the Free Software Foundation.
49 + */
50 +
51 +#include <linux/init.h>
52 +#include <linux/module.h>
53 +#include <linux/workqueue.h>
54 +#include <linux/platform_device.h>
55 +#include <linux/io.h>
56 +#include <linux/sched.h>
57 +#include <linux/delay.h>
58 +#include <linux/interrupt.h>
59 +#include <linux/completion.h>
60 +#include <linux/spinlock.h>
61 +#include <linux/err.h>
62 +#include <linux/clk.h>
63 +#include <linux/gpio.h>
64 +#include <linux/spi/spi.h>
65 +#include <linux/spi/spi_bitbang.h>
66 +
67 +#include <lantiq_soc.h>
68 +#include <lantiq_platform.h>
69 +
70 +#define LTQ_SPI_CLC 0x00 /* Clock control */
71 +#define LTQ_SPI_PISEL 0x04 /* Port input select */
72 +#define LTQ_SPI_ID 0x08 /* Identification */
73 +#define LTQ_SPI_CON 0x10 /* Control */
74 +#define LTQ_SPI_STAT 0x14 /* Status */
75 +#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */
76 +#define LTQ_SPI_TB 0x20 /* Transmit buffer */
77 +#define LTQ_SPI_RB 0x24 /* Receive buffer */
78 +#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */
79 +#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */
80 +#define LTQ_SPI_FSTAT 0x38 /* FIFO status */
81 +#define LTQ_SPI_BRT 0x40 /* Baudrate timer */
82 +#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */
83 +#define LTQ_SPI_SFCON 0x60 /* Serial frame control */
84 +#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */
85 +#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */
86 +#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */
87 +#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */
88 +#define LTQ_SPI_RXREQ 0x80 /* Receive request */
89 +#define LTQ_SPI_RXCNT 0x84 /* Receive count */
90 +#define LTQ_SPI_DMACON 0xEC /* DMA control */
91 +#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */
92 +#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */
93 +#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */
94 +
95 +#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */
96 +#define LTQ_SPI_CLC_SMC_MASK 0xFF
97 +#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */
98 +#define LTQ_SPI_CLC_RMC_MASK 0xFF
99 +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
100 +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
101 +
102 +#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */
103 +#define LTQ_SPI_ID_TXFS_MASK 0x3F
104 +#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */
105 +#define LTQ_SPI_ID_RXFS_MASK 0x3F
106 +#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */
107 +#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */
108 +
109 +#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */
110 +#define LTQ_SPI_CON_BM_MASK 0x1F
111 +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
112 +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
113 +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
114 +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
115 +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
116 +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
117 +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
118 +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
119 +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
120 +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
121 +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
122 +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */
123 +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
124 +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
125 +
126 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
127 +#define LTQ_SPI_STAT_RXBV_SHIFT 28
128 +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
129 +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
130 +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
131 +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
132 +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
133 +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
134 +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
135 +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
136 +
137 +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
138 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
139 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
140 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
141 +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
142 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
143 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
144 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
145 +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
146 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
147 +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
148 +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
149 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
150 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
151 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
152 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
153 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50
154 +
155 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */
156 +#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F
157 +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
158 +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
159 +
160 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */
161 +#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F
162 +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
163 +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
164 +
165 +#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f
166 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0
167 +#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f
168 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8
169 +
170 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8
171 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0
172 +
173 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8
174 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0
175 +
176 +#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */
177 +#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */
178 +
179 +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
180 +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
181 +#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */
182 +#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */
183 +#define LTQ_SPI_IRNEN_ALL 0xF
184 +
185 +/* Hard-wired GPIOs used by SPI controller */
186 +#define LTQ_SPI_GPIO_DI 16
187 +#define LTQ_SPI_GPIO_DO 17
188 +#define LTQ_SPI_GPIO_CLK 18
189 +
190 +struct ltq_spi {
191 + struct spi_bitbang bitbang;
192 + struct completion done;
193 + spinlock_t lock;
194 +
195 + struct device *dev;
196 + void __iomem *base;
197 + struct clk *clk;
198 +
199 + int status;
200 + int irq[3];
201 +
202 + const u8 *tx;
203 + u8 *rx;
204 + u32 tx_cnt;
205 + u32 rx_cnt;
206 + u32 len;
207 + struct spi_transfer *curr_transfer;
208 +
209 + u32 (*get_tx) (struct ltq_spi *);
210 +
211 + u16 txfs;
212 + u16 rxfs;
213 + unsigned dma_support:1;
214 + unsigned cfg_mode:1;
215 +
216 +};
217 +
218 +struct ltq_spi_controller_state {
219 + void (*cs_activate) (struct spi_device *);
220 + void (*cs_deactivate) (struct spi_device *);
221 +};
222 +
223 +struct ltq_spi_irq_map {
224 + char *name;
225 + irq_handler_t handler;
226 +};
227 +
228 +struct ltq_spi_cs_gpio_map {
229 + unsigned gpio;
230 + unsigned altsel0;
231 + unsigned altsel1;
232 +};
233 +
234 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
235 +{
236 + return spi_master_get_devdata(spi->master);
237 +}
238 +
239 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
240 +{
241 + return ioread32be(hw->base + reg);
242 +}
243 +
244 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
245 +{
246 + iowrite32be(val, hw->base + reg);
247 +}
248 +
249 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
250 +{
251 + u32 val;
252 +
253 + val = ltq_spi_reg_read(hw, reg);
254 + val |= bits;
255 + ltq_spi_reg_write(hw, val, reg);
256 +}
257 +
258 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
259 +{
260 + u32 val;
261 +
262 + val = ltq_spi_reg_read(hw, reg);
263 + val &= ~bits;
264 + ltq_spi_reg_write(hw, val, reg);
265 +}
266 +
267 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
268 +{
269 + u32 clc;
270 +
271 + /* Power-up mdule */
272 + ltq_pmu_enable(PMU_SPI);
273 +
274 + /*
275 + * Set clock divider for run mode to 1 to
276 + * run at same frequency as FPI bus
277 + */
278 + clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
279 + ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
280 +}
281 +
282 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
283 +{
284 + /* Set clock divider to 0 and set module disable bit */
285 + ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
286 +
287 + /* Power-down mdule */
288 + ltq_pmu_disable(PMU_SPI);
289 +}
290 +
291 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
292 +{
293 + u32 val;
294 +
295 + /*
296 + * Enable and flush FIFOs. Set interrupt trigger level to
297 + * half of FIFO count implemented in hardware.
298 + */
299 + if (hw->txfs > 1) {
300 + val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
301 + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
302 + ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
303 + }
304 +
305 + if (hw->rxfs > 1) {
306 + val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
307 + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
308 + ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
309 + }
310 +}
311 +
312 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
313 +{
314 + u32 stat;
315 + unsigned long timeout;
316 +
317 + timeout = jiffies + msecs_to_jiffies(200);
318 +
319 + do {
320 + stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
321 + if (!(stat & LTQ_SPI_STAT_BSY))
322 + return 0;
323 +
324 + cond_resched();
325 + } while (!time_after_eq(jiffies, timeout));
326 +
327 + dev_err(hw->dev, "SPI wait ready timed out\n");
328 +
329 + return -ETIMEDOUT;
330 +}
331 +
332 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
333 +{
334 + if (hw->cfg_mode)
335 + return;
336 +
337 + /*
338 + * Putting the SPI module in config mode is only safe if no
339 + * transfer is in progress as indicated by busy flag STATE.BSY.
340 + */
341 + if (ltq_spi_wait_ready(hw)) {
342 + ltq_spi_reset_fifos(hw);
343 + hw->status = -ETIMEDOUT;
344 + }
345 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
346 +
347 + hw->cfg_mode = 1;
348 +}
349 +
350 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
351 +{
352 + if (!hw->cfg_mode)
353 + return;
354 +
355 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
356 +
357 + hw->cfg_mode = 0;
358 +}
359 +
360 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
361 +{
362 + const u8 *tx = hw->tx;
363 + u32 data = *tx++;
364 +
365 + hw->tx_cnt++;
366 + hw->tx++;
367 +
368 + return data;
369 +}
370 +
371 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
372 +{
373 + const u16 *tx = (u16 *) hw->tx;
374 + u32 data = *tx++;
375 +
376 + hw->tx_cnt += 2;
377 + hw->tx += 2;
378 +
379 + return data;
380 +}
381 +
382 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
383 +{
384 + const u32 *tx = (u32 *) hw->tx;
385 + u32 data = *tx++;
386 +
387 + hw->tx_cnt += 4;
388 + hw->tx += 4;
389 +
390 + return data;
391 +}
392 +
393 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
394 +{
395 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
396 + u32 bm;
397 + u8 bits_per_word = spi->bits_per_word;
398 +
399 + /*
400 + * Use either default value of SPI device or value
401 + * from current transfer.
402 + */
403 + if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
404 + bits_per_word = hw->curr_transfer->bits_per_word;
405 +
406 + if (bits_per_word <= 8)
407 + hw->get_tx = ltq_spi_tx_word_u8;
408 + else if (bits_per_word <= 16)
409 + hw->get_tx = ltq_spi_tx_word_u16;
410 + else if (bits_per_word <= 32)
411 + hw->get_tx = ltq_spi_tx_word_u32;
412 +
413 + /* CON.BM value = bits_per_word - 1 */
414 + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
415 +
416 + ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
417 + LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
418 + ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
419 +}
420 +
421 +static void ltq_spi_speed_set(struct spi_device *spi)
422 +{
423 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
424 + u32 br, max_speed_hz, spi_clk;
425 + u32 speed_hz = spi->max_speed_hz;
426 +
427 + /*
428 + * Use either default value of SPI device or value
429 + * from current transfer.
430 + */
431 + if (hw->curr_transfer && hw->curr_transfer->speed_hz)
432 + speed_hz = hw->curr_transfer->speed_hz;
433 +
434 + /*
435 + * SPI module clock is derived from FPI bus clock dependent on
436 + * divider value in CLC.RMS which is always set to 1.
437 + */
438 + spi_clk = clk_get_rate(hw->clk);
439 +
440 + /*
441 + * Maximum SPI clock frequency in master mode is half of
442 + * SPI module clock frequency. Maximum reload value of
443 + * baudrate generator BR is 2^16.
444 + */
445 + max_speed_hz = spi_clk / 2;
446 + if (speed_hz >= max_speed_hz)
447 + br = 0;
448 + else
449 + br = (max_speed_hz / speed_hz) - 1;
450 +
451 + if (br > 0xFFFF)
452 + br = 0xFFFF;
453 +
454 + ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
455 +}
456 +
457 +static void ltq_spi_clockmode_set(struct spi_device *spi)
458 +{
459 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
460 + u32 con;
461 +
462 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
463 +
464 + /*
465 + * SPI mode mapping in CON register:
466 + * Mode CPOL CPHA CON.PO CON.PH
467 + * 0 0 0 0 1
468 + * 1 0 1 0 0
469 + * 2 1 0 1 1
470 + * 3 1 1 1 0
471 + */
472 + if (spi->mode & SPI_CPHA)
473 + con &= ~LTQ_SPI_CON_PH;
474 + else
475 + con |= LTQ_SPI_CON_PH;
476 +
477 + if (spi->mode & SPI_CPOL)
478 + con |= LTQ_SPI_CON_PO;
479 + else
480 + con &= ~LTQ_SPI_CON_PO;
481 +
482 + /* Set heading control */
483 + if (spi->mode & SPI_LSB_FIRST)
484 + con &= ~LTQ_SPI_CON_HB;
485 + else
486 + con |= LTQ_SPI_CON_HB;
487 +
488 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
489 +}
490 +
491 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
492 +{
493 + u32 con;
494 +
495 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
496 +
497 + if (t) {
498 + if (t->tx_buf && t->rx_buf) {
499 + con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
500 + } else if (t->rx_buf) {
501 + con &= ~LTQ_SPI_CON_RXOFF;
502 + con |= LTQ_SPI_CON_TXOFF;
503 + } else if (t->tx_buf) {
504 + con &= ~LTQ_SPI_CON_TXOFF;
505 + con |= LTQ_SPI_CON_RXOFF;
506 + }
507 + } else
508 + con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
509 +
510 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
511 +}
512 +
513 +static void ltq_spi_gpio_cs_activate(struct spi_device *spi)
514 +{
515 + struct ltq_spi_controller_data *cdata = spi->controller_data;
516 + int val = spi->mode & SPI_CS_HIGH ? 1 : 0;
517 +
518 + gpio_set_value(cdata->gpio, val);
519 +}
520 +
521 +static void ltq_spi_gpio_cs_deactivate(struct spi_device *spi)
522 +{
523 + struct ltq_spi_controller_data *cdata = spi->controller_data;
524 + int val = spi->mode & SPI_CS_HIGH ? 0 : 1;
525 +
526 + gpio_set_value(cdata->gpio, val);
527 +}
528 +
529 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
530 +{
531 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
532 + u32 fgpo;
533 +
534 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
535 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
536 +}
537 +
538 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
539 +{
540 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
541 + u32 fgpo;
542 +
543 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
544 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
545 +}
546 +
547 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
548 +{
549 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
550 + struct ltq_spi_controller_state *cstate = spi->controller_state;
551 +
552 + switch (cs) {
553 + case BITBANG_CS_ACTIVE:
554 + ltq_spi_bits_per_word_set(spi);
555 + ltq_spi_speed_set(spi);
556 + ltq_spi_clockmode_set(spi);
557 + ltq_spi_run_mode_set(hw);
558 +
559 + cstate->cs_activate(spi);
560 + break;
561 +
562 + case BITBANG_CS_INACTIVE:
563 + cstate->cs_deactivate(spi);
564 +
565 + ltq_spi_config_mode_set(hw);
566 +
567 + break;
568 + }
569 +}
570 +
571 +static int ltq_spi_setup_transfer(struct spi_device *spi,
572 + struct spi_transfer *t)
573 +{
574 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
575 + u8 bits_per_word = spi->bits_per_word;
576 +
577 + hw->curr_transfer = t;
578 +
579 + if (t && t->bits_per_word)
580 + bits_per_word = t->bits_per_word;
581 +
582 + if (bits_per_word > 32)
583 + return -EINVAL;
584 +
585 + ltq_spi_config_mode_set(hw);
586 +
587 + return 0;
588 +}
589 +
590 +static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = {
591 + { 15, 1, 0 },
592 + { 22, 1, 0 },
593 + { 13, 0, 1 },
594 + { 10, 0, 1 },
595 + { 9, 0, 1 },
596 + { 11, 1, 1 },
597 +};
598 +
599 +static int ltq_spi_setup(struct spi_device *spi)
600 +{
601 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
602 + struct ltq_spi_controller_data *cdata = spi->controller_data;
603 + struct ltq_spi_controller_state *cstate;
604 + u32 gpocon, fgpo;
605 + int ret;
606 +
607 + /* Set default word length to 8 if not set */
608 + if (!spi->bits_per_word)
609 + spi->bits_per_word = 8;
610 +
611 + if (spi->bits_per_word > 32)
612 + return -EINVAL;
613 +
614 + if (!spi->controller_state) {
615 + cstate = kzalloc(sizeof(struct ltq_spi_controller_state),
616 + GFP_KERNEL);
617 + if (!cstate)
618 + return -ENOMEM;
619 +
620 + spi->controller_state = cstate;
621 + } else
622 + return 0;
623 +
624 + /*
625 + * Up to six GPIOs can be connected to the SPI module
626 + * via GPIO alternate function to control the chip select lines.
627 + * For more flexibility in board layout this driver can also control
628 + * the CS lines via GPIO API. If GPIOs should be used, board setup code
629 + * have to register the SPI device with struct ltq_spi_controller_data
630 + * attached.
631 + */
632 + if (cdata && cdata->gpio) {
633 + ret = gpio_request(cdata->gpio, "spi-cs");
634 + if (ret)
635 + return -EBUSY;
636 +
637 + ret = spi->mode & SPI_CS_HIGH ? 0 : 1;
638 + gpio_direction_output(cdata->gpio, ret);
639 +
640 + cstate->cs_activate = ltq_spi_gpio_cs_activate;
641 + cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate;
642 + } else {
643 + ret = ltq_gpio_request(ltq_spi_cs[spi->chip_select].gpio,
644 + ltq_spi_cs[spi->chip_select].altsel0,
645 + ltq_spi_cs[spi->chip_select].altsel1,
646 + 1, "spi-cs");
647 + if (ret)
648 + return -EBUSY;
649 +
650 + gpocon = (1 << (spi->chip_select +
651 + LTQ_SPI_GPOCON_ISCSBN_SHIFT));
652 +
653 + if (spi->mode & SPI_CS_HIGH)
654 + gpocon |= (1 << spi->chip_select);
655 +
656 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
657 +
658 + ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
659 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
660 +
661 + cstate->cs_activate = ltq_spi_internal_cs_activate;
662 + cstate->cs_deactivate = ltq_spi_internal_cs_deactivate;
663 + }
664 +
665 + return 0;
666 +}
667 +
668 +static void ltq_spi_cleanup(struct spi_device *spi)
669 +{
670 + struct ltq_spi_controller_data *cdata = spi->controller_data;
671 + struct ltq_spi_controller_state *cstate = spi->controller_state;
672 + unsigned gpio;
673 +
674 + if (cdata && cdata->gpio)
675 + gpio = cdata->gpio;
676 + else
677 + gpio = ltq_spi_cs[spi->chip_select].gpio;
678 +
679 + gpio_free(gpio);
680 + kfree(cstate);
681 +}
682 +
683 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
684 +{
685 + u32 fstat, data;
686 + u16 fifo_space;
687 +
688 + /* Determine how much FIFOs are free for TX data */
689 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
690 + fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
691 + LTQ_SPI_FSTAT_TXFFL_MASK);
692 +
693 + if (!fifo_space)
694 + return;
695 +
696 + while (hw->tx_cnt < hw->len && fifo_space) {
697 + data = hw->get_tx(hw);
698 + ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
699 + fifo_space--;
700 + }
701 +}
702 +
703 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
704 +{
705 + u32 fstat, data, *rx32;
706 + u16 fifo_fill;
707 + u8 rxbv, shift, *rx8;
708 +
709 + /* Determine how much FIFOs are filled with RX data */
710 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
711 + fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
712 + & LTQ_SPI_FSTAT_RXFFL_MASK);
713 +
714 + if (!fifo_fill)
715 + return;
716 +
717 + /*
718 + * The 32 bit FIFO is always used completely independent from the
719 + * bits_per_word value. Thus four bytes have to be read at once
720 + * per FIFO.
721 + */
722 + rx32 = (u32 *) hw->rx;
723 + while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
724 + *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
725 + hw->rx_cnt += 4;
726 + hw->rx += 4;
727 + fifo_fill--;
728 + }
729 +
730 + /*
731 + * If there are remaining bytes, read byte count from STAT.RXBV
732 + * register and read the data byte-wise.
733 + */
734 + while (fifo_fill && hw->rx_cnt < hw->len) {
735 + rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
736 + LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
737 + data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
738 +
739 + shift = (rxbv - 1) * 8;
740 + rx8 = hw->rx;
741 +
742 + while (rxbv) {
743 + *rx8++ = (data >> shift) & 0xFF;
744 + rxbv--;
745 + shift -= 8;
746 + hw->rx_cnt++;
747 + hw->rx++;
748 + }
749 +
750 + fifo_fill--;
751 + }
752 +}
753 +
754 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
755 +{
756 + u32 rxreq, rxreq_max, rxtodo;
757 +
758 + rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
759 +
760 + /*
761 + * In RX-only mode the serial clock is activated only after writing
762 + * the expected amount of RX bytes into RXREQ register.
763 + * To avoid receive overflows at high clocks it is better to request
764 + * only the amount of bytes that fits into all FIFOs. This value
765 + * depends on the FIFO size implemented in hardware.
766 + */
767 + rxreq = hw->len - hw->rx_cnt;
768 + rxreq_max = hw->rxfs << 2;
769 + rxreq = min(rxreq_max, rxreq);
770 +
771 + if (!rxtodo && rxreq)
772 + ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
773 +}
774 +
775 +static inline void ltq_spi_complete(struct ltq_spi *hw)
776 +{
777 + complete(&hw->done);
778 +}
779 +
780 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
781 +{
782 + struct ltq_spi *hw = data;
783 + unsigned long flags;
784 + int completed = 0;
785 +
786 + spin_lock_irqsave(&hw->lock, flags);
787 +
788 + if (hw->tx_cnt < hw->len)
789 + ltq_spi_txfifo_write(hw);
790 +
791 + if (hw->tx_cnt == hw->len)
792 + completed = 1;
793 +
794 + spin_unlock_irqrestore(&hw->lock, flags);
795 +
796 + if (completed)
797 + ltq_spi_complete(hw);
798 +
799 + return IRQ_HANDLED;
800 +}
801 +
802 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
803 +{
804 + struct ltq_spi *hw = data;
805 + unsigned long flags;
806 + int completed = 0;
807 +
808 + spin_lock_irqsave(&hw->lock, flags);
809 +
810 + if (hw->rx_cnt < hw->len) {
811 + ltq_spi_rxfifo_read(hw);
812 +
813 + if (hw->tx && hw->tx_cnt < hw->len)
814 + ltq_spi_txfifo_write(hw);
815 + }
816 +
817 + if (hw->rx_cnt == hw->len)
818 + completed = 1;
819 + else if (!hw->tx)
820 + ltq_spi_rxreq_set(hw);
821 +
822 + spin_unlock_irqrestore(&hw->lock, flags);
823 +
824 + if (completed)
825 + ltq_spi_complete(hw);
826 +
827 + return IRQ_HANDLED;
828 +}
829 +
830 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
831 +{
832 + struct ltq_spi *hw = data;
833 + unsigned long flags;
834 +
835 + spin_lock_irqsave(&hw->lock, flags);
836 +
837 + /* Disable all interrupts */
838 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
839 +
840 + /* Clear all error flags */
841 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
842 +
843 + /* Flush FIFOs */
844 + ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
845 + ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
846 +
847 + hw->status = -EIO;
848 + spin_unlock_irqrestore(&hw->lock, flags);
849 +
850 + ltq_spi_complete(hw);
851 +
852 + return IRQ_HANDLED;
853 +}
854 +
855 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
856 +{
857 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
858 + u32 irq_flags = 0;
859 +
860 + hw->tx = t->tx_buf;
861 + hw->rx = t->rx_buf;
862 + hw->len = t->len;
863 + hw->tx_cnt = 0;
864 + hw->rx_cnt = 0;
865 + hw->status = 0;
866 + INIT_COMPLETION(hw->done);
867 +
868 + ltq_spi_xmit_set(hw, t);
869 +
870 + /* Enable error interrupts */
871 + ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
872 +
873 + if (hw->tx) {
874 + /* Initially fill TX FIFO with as much data as possible */
875 + ltq_spi_txfifo_write(hw);
876 + irq_flags |= LTQ_SPI_IRNEN_T;
877 +
878 + /* Always enable RX interrupt in Full Duplex mode */
879 + if (hw->rx)
880 + irq_flags |= LTQ_SPI_IRNEN_R;
881 + } else if (hw->rx) {
882 + /* Start RX clock */
883 + ltq_spi_rxreq_set(hw);
884 +
885 + /* Enable RX interrupt to receive data from RX FIFOs */
886 + irq_flags |= LTQ_SPI_IRNEN_R;
887 + }
888 +
889 + /* Enable TX or RX interrupts */
890 + ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
891 + wait_for_completion_interruptible(&hw->done);
892 +
893 + /* Disable all interrupts */
894 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
895 +
896 + /*
897 + * Return length of current transfer for bitbang utility code if
898 + * no errors occured during transmission.
899 + */
900 + if (!hw->status)
901 + hw->status = hw->len;
902 +
903 + return hw->status;
904 +}
905 +
906 +static const struct ltq_spi_irq_map ltq_spi_irqs[] = {
907 + { "spi_tx", ltq_spi_tx_irq },
908 + { "spi_rx", ltq_spi_rx_irq },
909 + { "spi_err", ltq_spi_err_irq },
910 +};
911 +
912 +static int __init ltq_spi_probe(struct platform_device *pdev)
913 +{
914 + struct spi_master *master;
915 + struct resource *r;
916 + struct ltq_spi *hw;
917 + struct ltq_spi_platform_data *pdata = pdev->dev.platform_data;
918 + int ret, i;
919 + u32 data, id;
920 +
921 + master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
922 + if (!master) {
923 + dev_err(&pdev->dev, "spi_alloc_master\n");
924 + ret = -ENOMEM;
925 + goto err;
926 + }
927 +
928 + hw = spi_master_get_devdata(master);
929 +
930 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
931 + if (r == NULL) {
932 + dev_err(&pdev->dev, "platform_get_resource\n");
933 + ret = -ENOENT;
934 + goto err_master;
935 + }
936 +
937 + r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
938 + pdev->name);
939 + if (!r) {
940 + dev_err(&pdev->dev, "devm_request_mem_region\n");
941 + ret = -ENXIO;
942 + goto err_master;
943 + }
944 +
945 + hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
946 + if (!hw->base) {
947 + dev_err(&pdev->dev, "devm_ioremap_nocache\n");
948 + ret = -ENXIO;
949 + goto err_master;
950 + }
951 +
952 + hw->clk = clk_get(&pdev->dev, "fpi");
953 + if (IS_ERR(hw->clk)) {
954 + dev_err(&pdev->dev, "clk_get\n");
955 + ret = PTR_ERR(hw->clk);
956 + goto err_master;
957 + }
958 +
959 + memset(hw->irq, 0, sizeof(hw->irq));
960 + for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
961 + ret = platform_get_irq_byname(pdev, ltq_spi_irqs[i].name);
962 + if (0 > ret) {
963 + dev_err(&pdev->dev, "platform_get_irq_byname\n");
964 + goto err_irq;
965 + }
966 +
967 + hw->irq[i] = ret;
968 + ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
969 + 0, ltq_spi_irqs[i].name, hw);
970 + if (ret) {
971 + dev_err(&pdev->dev, "request_irq\n");
972 + goto err_irq;
973 + }
974 + }
975 +
976 + hw->bitbang.master = spi_master_get(master);
977 + hw->bitbang.chipselect = ltq_spi_chipselect;
978 + hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
979 + hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
980 +
981 + master->bus_num = pdev->id;
982 + master->num_chipselect = pdata->num_chipselect;
983 + master->setup = ltq_spi_setup;
984 + master->cleanup = ltq_spi_cleanup;
985 +
986 + hw->dev = &pdev->dev;
987 + init_completion(&hw->done);
988 + spin_lock_init(&hw->lock);
989 +
990 + /* Set GPIO alternate functions to SPI */
991 + ltq_gpio_request(LTQ_SPI_GPIO_DI, 1, 0, 0, "spi-di");
992 + ltq_gpio_request(LTQ_SPI_GPIO_DO, 1, 0, 1, "spi-do");
993 + ltq_gpio_request(LTQ_SPI_GPIO_CLK, 1, 0, 1, "spi-clk");
994 +
995 + ltq_spi_hw_enable(hw);
996 +
997 + /* Read module capabilities */
998 + id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
999 + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1000 + hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1001 + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
1002 +
1003 + ltq_spi_config_mode_set(hw);
1004 +
1005 + /* Enable error checking, disable TX/RX, set idle value high */
1006 + data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
1007 + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
1008 + LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
1009 + ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
1010 +
1011 + /* Enable master mode and clear error flags */
1012 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
1013 + LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
1014 +
1015 + /* Reset GPIO/CS registers */
1016 + ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
1017 + ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
1018 +
1019 + /* Enable and flush FIFOs */
1020 + ltq_spi_reset_fifos(hw);
1021 +
1022 + ret = spi_bitbang_start(&hw->bitbang);
1023 + if (ret) {
1024 + dev_err(&pdev->dev, "spi_bitbang_start\n");
1025 + goto err_bitbang;
1026 + }
1027 +
1028 + platform_set_drvdata(pdev, hw);
1029 +
1030 + pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
1031 + id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
1032 +
1033 + return 0;
1034 +
1035 +err_bitbang:
1036 + ltq_spi_hw_disable(hw);
1037 +
1038 +err_irq:
1039 + clk_put(hw->clk);
1040 +
1041 + for (; i > 0; i--)
1042 + free_irq(hw->irq[i], hw);
1043 +
1044 +err_master:
1045 + spi_master_put(master);
1046 +
1047 +err:
1048 + return ret;
1049 +}
1050 +
1051 +static int __exit ltq_spi_remove(struct platform_device *pdev)
1052 +{
1053 + struct ltq_spi *hw = platform_get_drvdata(pdev);
1054 + int ret, i;
1055 +
1056 + ret = spi_bitbang_stop(&hw->bitbang);
1057 + if (ret)
1058 + return ret;
1059 +
1060 + platform_set_drvdata(pdev, NULL);
1061 +
1062 + ltq_spi_config_mode_set(hw);
1063 + ltq_spi_hw_disable(hw);
1064 +
1065 + for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
1066 + if (0 < hw->irq[i])
1067 + free_irq(hw->irq[i], hw);
1068 +
1069 + gpio_free(LTQ_SPI_GPIO_DI);
1070 + gpio_free(LTQ_SPI_GPIO_DO);
1071 + gpio_free(LTQ_SPI_GPIO_CLK);
1072 +
1073 + clk_put(hw->clk);
1074 + spi_master_put(hw->bitbang.master);
1075 +
1076 + return 0;
1077 +}
1078 +
1079 +static struct platform_driver ltq_spi_driver = {
1080 + .driver = {
1081 + .name = "ltq-spi",
1082 + .owner = THIS_MODULE,
1083 + },
1084 + .remove = __exit_p(ltq_spi_remove),
1085 +};
1086 +
1087 +static int __init ltq_spi_init(void)
1088 +{
1089 + return platform_driver_probe(&ltq_spi_driver, ltq_spi_probe);
1090 +}
1091 +module_init(ltq_spi_init);
1092 +
1093 +static void __exit ltq_spi_exit(void)
1094 +{
1095 + platform_driver_unregister(&ltq_spi_driver);
1096 +}
1097 +module_exit(ltq_spi_exit);
1098 +
1099 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1100 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1101 +MODULE_LICENSE("GPL");
1102 +MODULE_ALIAS("platform:ltq-spi");