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lantiq: add ath9k led pin support
[openwrt/openwrt.git] / target / linux / lantiq / patches-3.10 / 0010-MIPS-lantiq-wifi-and-ethernet-eeprom-handling.patch
1 From 591a9bdde1fa9aa6f1c6132ea04771bb1dcd6180 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 13 Mar 2013 10:02:58 +0100
4 Subject: [PATCH 18/22] owrt: lantiq: wifi and ethernet eeprom handling
5
6 ---
7 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h | 6 +
8 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
9 arch/mips/lantiq/xway/Makefile | 3 +
10 arch/mips/lantiq/xway/ath_eep.c | 248 ++++++++++++++++++++
11 arch/mips/lantiq/xway/eth_mac.c | 76 ++++++
12 arch/mips/lantiq/xway/pci-ath-fixup.c | 109 +++++++++
13 arch/mips/lantiq/xway/rt_eep.c | 60 +++++
14 arch/mips/pci/pci-lantiq.c | 2 +-
15 8 files changed, 506 insertions(+), 1 deletion(-)
16 create mode 100644 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
17 create mode 100644 arch/mips/lantiq/xway/ath_eep.c
18 create mode 100644 arch/mips/lantiq/xway/eth_mac.c
19 create mode 100644 arch/mips/lantiq/xway/pci-ath-fixup.c
20 create mode 100644 arch/mips/lantiq/xway/rt_eep.c
21
22 Index: linux-3.10.49/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
23 ===================================================================
24 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
25 +++ linux-3.10.49/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h 2014-09-07 17:34:26.488234696 +0200
26 @@ -0,0 +1,6 @@
27 +#ifndef _PCI_ATH_FIXUP
28 +#define _PCI_ATH_FIXUP
29 +
30 +void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init;
31 +
32 +#endif /* _PCI_ATH_FIXUP */
33 Index: linux-3.10.49/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
34 ===================================================================
35 --- linux-3.10.49.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 2014-07-18 00:58:15.000000000 +0200
36 +++ linux-3.10.49/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 2014-09-07 17:34:26.488234696 +0200
37 @@ -90,5 +90,8 @@
38 extern void ltq_pmu_enable(unsigned int module);
39 extern void ltq_pmu_disable(unsigned int module);
40
41 +/* allow the ethernet driver to load a flash mapped mac addr */
42 +const u8* ltq_get_eth_mac(void);
43 +
44 #endif /* CONFIG_SOC_TYPE_XWAY */
45 #endif /* _LTQ_XWAY_H__ */
46 Index: linux-3.10.49/arch/mips/lantiq/xway/Makefile
47 ===================================================================
48 --- linux-3.10.49.orig/arch/mips/lantiq/xway/Makefile 2014-09-07 17:34:26.448234696 +0200
49 +++ linux-3.10.49/arch/mips/lantiq/xway/Makefile 2014-09-07 17:41:10.740227820 +0200
50 @@ -2,4 +2,7 @@
51
52 obj-y += vmmc.o
53
54 +obj-y += eth_mac.o
55 +obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o
56 +
57 obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
58 Index: linux-3.10.49/arch/mips/lantiq/xway/ath_eep.c
59 ===================================================================
60 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
61 +++ linux-3.10.49/arch/mips/lantiq/xway/ath_eep.c 2014-09-07 17:41:03.184227948 +0200
62 @@ -0,0 +1,282 @@
63 +/*
64 + * Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
65 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
66 + * Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
67 + * Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
68 + * Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
69 + *
70 + * This program is free software; you can redistribute it and/or modify it
71 + * under the terms of the GNU General Public License version 2 as published
72 + * by the Free Software Foundation.
73 + */
74 +
75 +#include <linux/init.h>
76 +#include <linux/module.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/etherdevice.h>
79 +#include <linux/ath5k_platform.h>
80 +#include <linux/ath9k_platform.h>
81 +#include <linux/pci.h>
82 +#include <linux/err.h>
83 +#include <linux/mtd/mtd.h>
84 +#include <pci-ath-fixup.h>
85 +#include <lantiq_soc.h>
86 +
87 +extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
88 +struct ath5k_platform_data ath5k_pdata;
89 +struct ath9k_platform_data ath9k_pdata = {
90 + .led_pin = -1,
91 +};
92 +static u8 athxk_eeprom_mac[6];
93 +
94 +static int ath9k_pci_plat_dev_init(struct pci_dev *dev)
95 +{
96 + dev->dev.platform_data = &ath9k_pdata;
97 + return 0;
98 +}
99 +
100 +static int ath9k_eep_load;
101 +int __init of_ath9k_eeprom_probe(struct platform_device *pdev)
102 +{
103 + struct device_node *np = pdev->dev.of_node, *mtd_np;
104 + struct resource *eep_res, *mac_res = NULL;
105 + void __iomem *eep, *mac;
106 + int mac_offset, led_pin;
107 + u32 mac_inc = 0, pci_slot = 0;
108 + int i;
109 + struct mtd_info *the_mtd;
110 + size_t flash_readlen;
111 + const __be32 *list;
112 + const char *part;
113 + phandle phandle;
114 +
115 + if ((list = of_get_property(np, "ath,eep-flash", &i)) && i == 2 *
116 + sizeof(*list) && (phandle = be32_to_cpup(list++)) &&
117 + (mtd_np = of_find_node_by_phandle(phandle)) && ((part =
118 + of_get_property(mtd_np, "label", NULL)) || (part =
119 + mtd_np->name)) && (the_mtd = get_mtd_device_nm(part))
120 + != ERR_PTR(-ENODEV)) {
121 + i = mtd_read(the_mtd, be32_to_cpup(list),
122 + ATH9K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen,
123 + (void *) ath9k_pdata.eeprom_data);
124 + if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
125 + size_t mac_readlen;
126 + mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
127 + (void *) athxk_eeprom_mac);
128 + }
129 + put_mtd_device(the_mtd);
130 + if ((sizeof(ath9k_pdata.eeprom_data) != flash_readlen) || i) {
131 + dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
132 + return -ENODEV;
133 + }
134 + } else {
135 + eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
136 + mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
137 +
138 + if (!eep_res) {
139 + dev_err(&pdev->dev, "failed to load eeprom address\n");
140 + return -ENODEV;
141 + }
142 + if (resource_size(eep_res) != ATH9K_PLAT_EEP_MAX_WORDS << 1) {
143 + dev_err(&pdev->dev, "eeprom has an invalid size\n");
144 + return -EINVAL;
145 + }
146 +
147 + eep = ioremap(eep_res->start, resource_size(eep_res));
148 + memcpy_fromio(ath9k_pdata.eeprom_data, eep,
149 + ATH9K_PLAT_EEP_MAX_WORDS << 1);
150 + }
151 +
152 + if (of_find_property(np, "ath,eep-swap", NULL))
153 + for (i = 0; i < ATH9K_PLAT_EEP_MAX_WORDS; i++)
154 + ath9k_pdata.eeprom_data[i] = swab16(ath9k_pdata.eeprom_data[i]);
155 +
156 + if (of_find_property(np, "ath,eep-endian", NULL)) {
157 + ath9k_pdata.endian_check = true;
158 +
159 + dev_info(&pdev->dev, "endian check enabled.\n");
160 + }
161 +
162 + if (!is_valid_ether_addr(athxk_eeprom_mac)) {
163 + if (mac_res) {
164 + if (resource_size(mac_res) != 6) {
165 + dev_err(&pdev->dev, "mac has an invalid size\n");
166 + return -EINVAL;
167 + }
168 + mac = ioremap(mac_res->start, resource_size(mac_res));
169 + memcpy_fromio(athxk_eeprom_mac, mac, 6);
170 + } else if (ltq_get_eth_mac()) {
171 + memcpy(athxk_eeprom_mac, ltq_get_eth_mac(), 6);
172 + }
173 + }
174 + if (!is_valid_ether_addr(athxk_eeprom_mac)) {
175 + dev_warn(&pdev->dev, "using random mac\n");
176 + random_ether_addr(athxk_eeprom_mac);
177 + }
178 +
179 + if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
180 + athxk_eeprom_mac[5] += mac_inc;
181 +
182 + ath9k_pdata.macaddr = athxk_eeprom_mac;
183 + ltq_pci_plat_dev_init = ath9k_pci_plat_dev_init;
184 +
185 + if (!of_property_read_u32(np, "ath,pci-slot", &pci_slot)) {
186 + ltq_pci_ath_fixup(pci_slot, ath9k_pdata.eeprom_data);
187 +
188 + dev_info(&pdev->dev, "pci slot: %u\n", pci_slot);
189 + if (ath9k_eep_load) {
190 + struct pci_dev *d = NULL;
191 + while ((d = pci_get_device(PCI_VENDOR_ID_ATHEROS,
192 + PCI_ANY_ID, d)) != NULL)
193 + pci_fixup_device(pci_fixup_early, d);
194 + }
195 +
196 + }
197 +
198 + if (!of_property_read_u32(np, "ath,led-pin", &led_pin)) {
199 + ath9k_pdata.led_pin = led_pin;
200 + dev_info(&pdev->dev, "using led pin %d.\n", led_pin);
201 + }
202 +
203 + dev_info(&pdev->dev, "loaded ath9k eeprom\n");
204 +
205 + return 0;
206 +}
207 +
208 +static struct of_device_id ath9k_eeprom_ids[] = {
209 + { .compatible = "ath9k,eeprom" },
210 + { }
211 +};
212 +
213 +static struct platform_driver ath9k_eeprom_driver = {
214 + .driver = {
215 + .name = "ath9k,eeprom",
216 + .owner = THIS_MODULE,
217 + .of_match_table = of_match_ptr(ath9k_eeprom_ids),
218 + },
219 +};
220 +
221 +static int __init of_ath9k_eeprom_init(void)
222 +{
223 + int ret = platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe);
224 +
225 + if (ret)
226 + ath9k_eep_load = 1;
227 +
228 + return ret;
229 +}
230 +
231 +static int __init of_ath9k_eeprom_init_late(void)
232 +{
233 + if (!ath9k_eep_load)
234 + return 0;
235 + return platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe);
236 +}
237 +late_initcall(of_ath9k_eeprom_init_late);
238 +subsys_initcall(of_ath9k_eeprom_init);
239 +
240 +
241 +static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
242 +{
243 + dev->dev.platform_data = &ath5k_pdata;
244 + return 0;
245 +}
246 +
247 +int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
248 +{
249 + struct device_node *np = pdev->dev.of_node, *mtd_np;
250 + struct resource *eep_res, *mac_res = NULL;
251 + void __iomem *eep, *mac;
252 + int mac_offset;
253 + u32 mac_inc = 0;
254 + int i;
255 + struct mtd_info *the_mtd;
256 + size_t flash_readlen;
257 + const __be32 *list;
258 + const char *part;
259 + phandle phandle;
260 +
261 + if ((list = of_get_property(np, "ath,eep-flash", &i)) && i == 2 *
262 + sizeof(*list) && (phandle = be32_to_cpup(list++)) &&
263 + (mtd_np = of_find_node_by_phandle(phandle)) && ((part =
264 + of_get_property(mtd_np, "label", NULL)) || (part =
265 + mtd_np->name)) && (the_mtd = get_mtd_device_nm(part))
266 + != ERR_PTR(-ENODEV)) {
267 + i = mtd_read(the_mtd, be32_to_cpup(list),
268 + ATH5K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen,
269 + (void *) ath5k_pdata.eeprom_data);
270 + put_mtd_device(the_mtd);
271 + if ((sizeof(ATH5K_PLAT_EEP_MAX_WORDS << 1) != flash_readlen)
272 + || i) {
273 + dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
274 + return -ENODEV;
275 + }
276 + } else {
277 + eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
278 + mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
279 +
280 + if (!eep_res) {
281 + dev_err(&pdev->dev, "failed to load eeprom address\n");
282 + return -ENODEV;
283 + }
284 + if (resource_size(eep_res) != ATH5K_PLAT_EEP_MAX_WORDS << 1) {
285 + dev_err(&pdev->dev, "eeprom has an invalid size\n");
286 + return -EINVAL;
287 + }
288 +
289 + eep = ioremap(eep_res->start, resource_size(eep_res));
290 + ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1,
291 + GFP_KERNEL);
292 + memcpy_fromio(ath5k_pdata.eeprom_data, eep,
293 + ATH5K_PLAT_EEP_MAX_WORDS << 1);
294 + }
295 +
296 + if (of_find_property(np, "ath,eep-swap", NULL))
297 + for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
298 + ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
299 +
300 + if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
301 + memcpy_fromio(athxk_eeprom_mac, (void*) ath5k_pdata.eeprom_data + mac_offset, 6);
302 + } else if (mac_res) {
303 + if (resource_size(mac_res) != 6) {
304 + dev_err(&pdev->dev, "mac has an invalid size\n");
305 + return -EINVAL;
306 + }
307 + mac = ioremap(mac_res->start, resource_size(mac_res));
308 + memcpy_fromio(athxk_eeprom_mac, mac, 6);
309 + } else if (ltq_get_eth_mac())
310 + memcpy(athxk_eeprom_mac, ltq_get_eth_mac(), 6);
311 + else {
312 + dev_warn(&pdev->dev, "using random mac\n");
313 + random_ether_addr(athxk_eeprom_mac);
314 + }
315 +
316 + if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
317 + athxk_eeprom_mac[5] += mac_inc;
318 +
319 + ath5k_pdata.macaddr = athxk_eeprom_mac;
320 + ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
321 +
322 + dev_info(&pdev->dev, "loaded ath5k eeprom\n");
323 +
324 + return 0;
325 +}
326 +
327 +static struct of_device_id ath5k_eeprom_ids[] = {
328 + { .compatible = "ath5k,eeprom" },
329 + { }
330 +};
331 +
332 +static struct platform_driver ath5k_eeprom_driver = {
333 + .driver = {
334 + .name = "ath5k,eeprom",
335 + .owner = THIS_MODULE,
336 + .of_match_table = of_match_ptr(ath5k_eeprom_ids),
337 + },
338 +};
339 +
340 +static int __init of_ath5k_eeprom_init(void)
341 +{
342 + return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
343 +}
344 +device_initcall(of_ath5k_eeprom_init);
345 Index: linux-3.10.49/arch/mips/lantiq/xway/eth_mac.c
346 ===================================================================
347 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
348 +++ linux-3.10.49/arch/mips/lantiq/xway/eth_mac.c 2014-09-07 17:34:26.488234696 +0200
349 @@ -0,0 +1,76 @@
350 +/*
351 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
352 + *
353 + * This program is free software; you can redistribute it and/or modify it
354 + * under the terms of the GNU General Public License version 2 as published
355 + * by the Free Software Foundation.
356 + */
357 +
358 +#include <linux/init.h>
359 +#include <linux/module.h>
360 +#include <linux/of_platform.h>
361 +#include <linux/if_ether.h>
362 +
363 +static u8 eth_mac[6];
364 +static int eth_mac_set;
365 +
366 +const u8* ltq_get_eth_mac(void)
367 +{
368 + return eth_mac;
369 +}
370 +
371 +static int __init setup_ethaddr(char *str)
372 +{
373 + eth_mac_set = mac_pton(str, eth_mac);
374 + return !eth_mac_set;
375 +}
376 +__setup("ethaddr=", setup_ethaddr);
377 +
378 +int __init of_eth_mac_probe(struct platform_device *pdev)
379 +{
380 + struct device_node *np = pdev->dev.of_node;
381 + struct resource *mac_res;
382 + void __iomem *mac;
383 + u32 mac_inc = 0;
384 +
385 + if (eth_mac_set) {
386 + dev_err(&pdev->dev, "mac was already set by bootloader\n");
387 + return -EINVAL;
388 + }
389 + mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
390 +
391 + if (!mac_res) {
392 + dev_err(&pdev->dev, "failed to load mac\n");
393 + return -EINVAL;
394 + }
395 + if (resource_size(mac_res) != 6) {
396 + dev_err(&pdev->dev, "mac has an invalid size\n");
397 + return -EINVAL;
398 + }
399 + mac = ioremap(mac_res->start, resource_size(mac_res));
400 + memcpy_fromio(eth_mac, mac, 6);
401 +
402 + if (!of_property_read_u32(np, "mac-increment", &mac_inc))
403 + eth_mac[5] += mac_inc;
404 +
405 + return 0;
406 +}
407 +
408 +static struct of_device_id eth_mac_ids[] = {
409 + { .compatible = "lantiq,eth-mac" },
410 + { /* sentinel */ }
411 +};
412 +
413 +static struct platform_driver eth_mac_driver = {
414 + .driver = {
415 + .name = "lantiq,eth-mac",
416 + .owner = THIS_MODULE,
417 + .of_match_table = of_match_ptr(eth_mac_ids),
418 + },
419 +};
420 +
421 +static int __init of_eth_mac_init(void)
422 +{
423 + return platform_driver_probe(&eth_mac_driver, of_eth_mac_probe);
424 +}
425 +device_initcall(of_eth_mac_init);
426 Index: linux-3.10.49/arch/mips/lantiq/xway/pci-ath-fixup.c
427 ===================================================================
428 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
429 +++ linux-3.10.49/arch/mips/lantiq/xway/pci-ath-fixup.c 2014-09-07 17:34:26.488234696 +0200
430 @@ -0,0 +1,109 @@
431 +/*
432 + * Atheros AP94 reference board PCI initialization
433 + *
434 + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
435 + *
436 + * This program is free software; you can redistribute it and/or modify it
437 + * under the terms of the GNU General Public License version 2 as published
438 + * by the Free Software Foundation.
439 + */
440 +
441 +#include <linux/pci.h>
442 +#include <linux/init.h>
443 +#include <linux/delay.h>
444 +#include <lantiq_soc.h>
445 +
446 +#define LTQ_PCI_MEM_BASE 0x18000000
447 +
448 +struct ath_fixup {
449 + u16 *cal_data;
450 + unsigned slot;
451 +};
452 +
453 +static int ath_num_fixups;
454 +static struct ath_fixup ath_fixups[2];
455 +
456 +static void ath_pci_fixup(struct pci_dev *dev)
457 +{
458 + void __iomem *mem;
459 + u16 *cal_data = NULL;
460 + u16 cmd;
461 + u32 bar0;
462 + u32 val;
463 + unsigned i;
464 +
465 + for (i = 0; i < ath_num_fixups; i++) {
466 + if (ath_fixups[i].cal_data == NULL)
467 + continue;
468 +
469 + if (ath_fixups[i].slot != PCI_SLOT(dev->devfn))
470 + continue;
471 +
472 + cal_data = ath_fixups[i].cal_data;
473 + break;
474 + }
475 +
476 + if (cal_data == NULL)
477 + return;
478 +
479 + if (*cal_data != 0xa55a) {
480 + pr_err("pci %s: invalid calibration data\n", pci_name(dev));
481 + return;
482 + }
483 +
484 + pr_info("pci %s: fixup device configuration\n", pci_name(dev));
485 +
486 + mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000);
487 + if (!mem) {
488 + pr_err("pci %s: ioremap error\n", pci_name(dev));
489 + return;
490 + }
491 +
492 + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
493 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE);
494 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
495 + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
496 + pci_write_config_word(dev, PCI_COMMAND, cmd);
497 +
498 + /* set pointer to first reg address */
499 + cal_data += 3;
500 + while (*cal_data != 0xffff) {
501 + u32 reg;
502 + reg = *cal_data++;
503 + val = *cal_data++;
504 + val |= (*cal_data++) << 16;
505 +
506 + ltq_w32(swab32(val), mem + reg);
507 + udelay(100);
508 + }
509 +
510 + pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
511 + dev->vendor = val & 0xffff;
512 + dev->device = (val >> 16) & 0xffff;
513 +
514 + pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
515 + dev->revision = val & 0xff;
516 + dev->class = val >> 8; /* upper 3 bytes */
517 +
518 + pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n",
519 + pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class);
520 +
521 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
522 + cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
523 + pci_write_config_word(dev, PCI_COMMAND, cmd);
524 +
525 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
526 +
527 + iounmap(mem);
528 +}
529 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup);
530 +
531 +void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data)
532 +{
533 + if (ath_num_fixups >= ARRAY_SIZE(ath_fixups))
534 + return;
535 +
536 + ath_fixups[ath_num_fixups].slot = slot;
537 + ath_fixups[ath_num_fixups].cal_data = cal_data;
538 + ath_num_fixups++;
539 +}
540 Index: linux-3.10.49/arch/mips/lantiq/xway/rt_eep.c
541 ===================================================================
542 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
543 +++ linux-3.10.49/arch/mips/lantiq/xway/rt_eep.c 2014-09-07 17:34:26.488234696 +0200
544 @@ -0,0 +1,60 @@
545 +/*
546 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
547 + *
548 + * This program is free software; you can redistribute it and/or modify it
549 + * under the terms of the GNU General Public License version 2 as published
550 + * by the Free Software Foundation.
551 + */
552 +
553 +#include <linux/init.h>
554 +#include <linux/module.h>
555 +#include <linux/pci.h>
556 +#include <linux/platform_device.h>
557 +#include <linux/rt2x00_platform.h>
558 +
559 +extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
560 +static struct rt2x00_platform_data rt2x00_pdata;
561 +
562 +static int rt2x00_pci_plat_dev_init(struct pci_dev *dev)
563 +{
564 + dev->dev.platform_data = &rt2x00_pdata;
565 + return 0;
566 +}
567 +
568 +int __init of_ralink_eeprom_probe(struct platform_device *pdev)
569 +{
570 + struct device_node *np = pdev->dev.of_node;
571 + const char *eeprom;
572 +
573 + if (of_property_read_string(np, "ralink,eeprom", &eeprom)) {
574 + dev_err(&pdev->dev, "failed to load eeprom filename\n");
575 + return 0;
576 + }
577 +
578 + rt2x00_pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL);
579 +// rt2x00_pdata.mac_address = mac;
580 + ltq_pci_plat_dev_init = rt2x00_pci_plat_dev_init;
581 +
582 + dev_info(&pdev->dev, "using %s as eeprom\n", eeprom);
583 +
584 + return 0;
585 +}
586 +
587 +static struct of_device_id ralink_eeprom_ids[] = {
588 + { .compatible = "ralink,eeprom" },
589 + { }
590 +};
591 +
592 +static struct platform_driver ralink_eeprom_driver = {
593 + .driver = {
594 + .name = "ralink,eeprom",
595 + .owner = THIS_MODULE,
596 + .of_match_table = of_match_ptr(ralink_eeprom_ids),
597 + },
598 +};
599 +
600 +static int __init of_ralink_eeprom_init(void)
601 +{
602 + return platform_driver_probe(&ralink_eeprom_driver, of_ralink_eeprom_probe);
603 +}
604 +device_initcall(of_ralink_eeprom_init);
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