target/linux/lantiq/patches-3.14/0018-MTD-nand-lots-of-xrx200-fixes.patch

   1 From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 9 Sep 2014 23:12:15 +0200
   4 Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/mtd/nand/xway_nand.c |   63 ++++++++++++++++++++++++++++++++++++++++++
   9  1 file changed, 63 insertions(+)
  10
  11 --- a/drivers/mtd/nand/xway_nand.c
  12 +++ b/drivers/mtd/nand/xway_nand.c
  13 @@ -54,8 +54,27 @@
  14  #define NAND_CON_CSMUX         (1 << 1)
  15  #define NAND_CON_NANDM         1
  16
  17 +#define DANUBE_PCI_REG32( addr )    (*(volatile u32 *)(addr))
  18 +#define PCI_CR_PR_OFFSET           (KSEG1+0x1E105400)
  19 +#define PCI_CR_PC_ARB              (PCI_CR_PR_OFFSET + 0x0080)
  20 +
  21  static u32 xway_latchcmd;
  22
  23 +/*
  24 + * req_mask provides a mechanism to prevent interference between
  25 + * nand and pci (probably only relevant for the BT Home Hub 2B).
  26 + * Setting it causes the corresponding pci req pins to be masked
  27 + * during nand access, and also moves ebu locking from the read/write
  28 + * functions to the chip select function to ensure that the whole
  29 + * operation runs with interrupts disabled.
  30 + * In addition it switches on some extra waiting in xway_cmd_ctrl().
  31 + * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
  32 + * which in turn seems to be necessary for the nor chip to be recognised
  33 + * reliably, on a board (Home Hub 2B again) which has both nor and nand.
  34 + */
  35 +
  36 +static __be32 req_mask = 0;
  37 +
  38  static void xway_reset_chip(struct nand_chip *chip)
  39  {
  40         unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
  41 @@ -86,12 +105,24 @@ static void xway_select_chip(struct mtd_
  42         case -1:
  43                 ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
  44                 ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
  45 +
  46 +               if (req_mask) {
  47 +                       /* Unmask all external PCI request */
  48 +                       DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
  49 +               }
  50                 spin_unlock_irqrestore(&ebu_lock, csflags);
  51 +
  52                 break;
  53         case 0:
  54                 spin_lock_irqsave(&ebu_lock, csflags);
  55 +               if (req_mask) {
  56 +                       /* Mask all external PCI request */
  57 +                       DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
  58 +               }
  59 +
  60                 ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
  61                 ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
  62 +
  63                 break;
  64         default:
  65                 BUG();
  66 @@ -103,6 +134,12 @@ static void xway_cmd_ctrl(struct mtd_inf
  67         struct nand_chip *this = mtd->priv;
  68         unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
  69
  70 +       if (req_mask) {
  71 +               if (cmd != NAND_CMD_STATUS)
  72 +                       ltq_ebu_w32(EBU_NAND_WAIT, 0); /* Clear nand ready */
  73 +       }
  74 +
  75 +
  76         if (ctrl & NAND_CTRL_CHANGE) {
  77                 if (ctrl & NAND_CLE)
  78                         xway_latchcmd = NAND_WRITE_CMD;
  79 @@ -115,6 +152,24 @@ static void xway_cmd_ctrl(struct mtd_inf
  80                 while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
  81                         ;
  82         }
  83 +
  84 +       if (req_mask) {
  85 +              /*
  86 +               * program and erase have their own busy handlers
  87 +               * status and sequential in needs no delay
  88 +               */
  89 +               switch (cmd) {
  90 +                       case NAND_CMD_ERASE1:
  91 +                       case NAND_CMD_SEQIN:
  92 +                       case NAND_CMD_STATUS:
  93 +                       case NAND_CMD_READID:
  94 +                       return;
  95 +               }
  96 +
  97 +               /* wait until command is processed */
  98 +               while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
  99 +                       ;
 100 +       }
 101  }
 102
 103  static int xway_dev_ready(struct mtd_info *mtd)
 104 @@ -157,6 +212,8 @@ static int xway_nand_probe(struct platfo
 105  {
 106         struct nand_chip *this = platform_get_drvdata(pdev);
 107         unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
 108 +       const __be32 *req_mask_ptr = of_get_property(pdev->dev.of_node,
 109 +                                       "req-mask", NULL);
 110         const __be32 *cs = of_get_property(pdev->dev.of_node,
 111                                         "lantiq,cs", NULL);
 112         u32 cs_flag = 0;
 113 @@ -165,6 +222,12 @@ static int xway_nand_probe(struct platfo
 114         if (cs && (*cs == 1))
 115                 cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
 116
 117 +       /*
 118 +        * Load the PCI req lines to mask from the device tree. If the
 119 +        * property is not present, setting req_mask to 0 disables masking.
 120 +        */
 121 +       req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
 122 +
 123         /* setup the EBU to run in NAND mode on our base addr */
 124         ltq_ebu_w32(CPHYSADDR(nandaddr)
 125                 | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);