target/linux/lantiq/patches-3.14/0028-SPI-MIPS-lantiq-adds-spi-xway.patch

   1 From 855c99aff4c1fb440a679cc8481947daf95643b8 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 13 Mar 2013 09:29:37 +0100
   4 Subject: [PATCH 28/31] SPI: MIPS: lantiq: adds spi-xway
   5
   6 This patch adds support for the SPI core found on several Lantiq SoCs.
   7 The Driver has been runtime tested in combination with m25p80 Flash Devices
   8 on Amazon_SE and VR9.
   9
  10 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 ---
  13  drivers/spi/Kconfig    |    8 +
  14  drivers/spi/Makefile   |    1 +
  15  drivers/spi/spi-xway.c |  977 ++++++++++++++++++++++++++++++++++++++++++++++++
  16  3 files changed, 986 insertions(+)
  17  create mode 100644 drivers/spi/spi-xway.c
  18
  19 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
  20 index 581ee2a..b2cd93c 100644
  21 --- a/drivers/spi/Kconfig
  22 +++ b/drivers/spi/Kconfig
  23 @@ -527,6 +527,14 @@ config SPI_NUC900
  24         help
  25           SPI driver for Nuvoton NUC900 series ARM SoCs
  26
  27 +config SPI_XWAY
  28 +       tristate "Lantiq XWAY SPI controller"
  29 +       depends on LANTIQ && SOC_TYPE_XWAY
  30 +       select SPI_BITBANG
  31 +       help
  32 +         This driver supports the Lantiq SoC SPI controller in master
  33 +         mode.
  34 +
  35  #
  36  # Add new SPI master controllers in alphabetical order above this line
  37  #
  38 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
  39 index 95af48d..82d3799 100644
  40 --- a/drivers/spi/Makefile
  41 +++ b/drivers/spi/Makefile
  42 @@ -79,3 +79,4 @@ obj-$(CONFIG_SPI_TOPCLIFF_PCH)                += spi-topcliff-pch.o
  43  obj-$(CONFIG_SPI_TXX9)                 += spi-txx9.o
  44  obj-$(CONFIG_SPI_XCOMM)                += spi-xcomm.o
  45  obj-$(CONFIG_SPI_XILINX)               += spi-xilinx.o
  46 +obj-$(CONFIG_SPI_XWAY)                 += spi-xway.o
  47 diff --git a/drivers/spi/spi-xway.c b/drivers/spi/spi-xway.c
  48 new file mode 100644
  49 index 0000000..61532e3
  50 --- /dev/null
  51 +++ b/drivers/spi/spi-xway.c
  52 @@ -0,0 +1,977 @@
  53 +/*
  54 + * Lantiq SoC SPI controller
  55 + *
  56 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  57 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
  58 + *
  59 + * This program is free software; you can distribute it and/or modify it
  60 + * under the terms of the GNU General Public License (Version 2) as
  61 + * published by the Free Software Foundation.
  62 + */
  63 +
  64 +#include <linux/init.h>
  65 +#include <linux/module.h>
  66 +#include <linux/workqueue.h>
  67 +#include <linux/platform_device.h>
  68 +#include <linux/io.h>
  69 +#include <linux/sched.h>
  70 +#include <linux/delay.h>
  71 +#include <linux/interrupt.h>
  72 +#include <linux/completion.h>
  73 +#include <linux/spinlock.h>
  74 +#include <linux/err.h>
  75 +#include <linux/clk.h>
  76 +#include <linux/spi/spi.h>
  77 +#include <linux/spi/spi_bitbang.h>
  78 +#include <linux/of_irq.h>
  79 +
  80 +#include <lantiq_soc.h>
  81 +
  82 +#define LTQ_SPI_CLC            0x00    /* Clock control */
  83 +#define LTQ_SPI_PISEL          0x04    /* Port input select */
  84 +#define LTQ_SPI_ID             0x08    /* Identification */
  85 +#define LTQ_SPI_CON            0x10    /* Control */
  86 +#define LTQ_SPI_STAT           0x14    /* Status */
  87 +#define LTQ_SPI_WHBSTATE       0x18    /* Write HW modified state */
  88 +#define LTQ_SPI_TB             0x20    /* Transmit buffer */
  89 +#define LTQ_SPI_RB             0x24    /* Receive buffer */
  90 +#define LTQ_SPI_RXFCON         0x30    /* Receive FIFO control */
  91 +#define LTQ_SPI_TXFCON         0x34    /* Transmit FIFO control */
  92 +#define LTQ_SPI_FSTAT          0x38    /* FIFO status */
  93 +#define LTQ_SPI_BRT            0x40    /* Baudrate timer */
  94 +#define LTQ_SPI_BRSTAT         0x44    /* Baudrate timer status */
  95 +#define LTQ_SPI_SFCON          0x60    /* Serial frame control */
  96 +#define LTQ_SPI_SFSTAT         0x64    /* Serial frame status */
  97 +#define LTQ_SPI_GPOCON         0x70    /* General purpose output control */
  98 +#define LTQ_SPI_GPOSTAT                0x74    /* General purpose output status */
  99 +#define LTQ_SPI_FGPO           0x78    /* Forced general purpose output */
 100 +#define LTQ_SPI_RXREQ          0x80    /* Receive request */
 101 +#define LTQ_SPI_RXCNT          0x84    /* Receive count */
 102 +#define LTQ_SPI_DMACON         0xEC    /* DMA control */
 103 +#define LTQ_SPI_IRNEN          0xF4    /* Interrupt node enable */
 104 +#define LTQ_SPI_IRNICR         0xF8    /* Interrupt node interrupt capture */
 105 +#define LTQ_SPI_IRNCR          0xFC    /* Interrupt node control */
 106 +
 107 +#define LTQ_SPI_CLC_SMC_SHIFT  16      /* Clock divider for sleep mode */
 108 +#define LTQ_SPI_CLC_SMC_MASK   0xFF
 109 +#define LTQ_SPI_CLC_RMC_SHIFT  8       /* Clock divider for normal run mode */
 110 +#define LTQ_SPI_CLC_RMC_MASK   0xFF
 111 +#define LTQ_SPI_CLC_DISS       BIT(1)  /* Disable status bit */
 112 +#define LTQ_SPI_CLC_DISR       BIT(0)  /* Disable request bit */
 113 +
 114 +#define LTQ_SPI_ID_TXFS_SHIFT  24      /* Implemented TX FIFO size */
 115 +#define LTQ_SPI_ID_TXFS_MASK   0x3F
 116 +#define LTQ_SPI_ID_RXFS_SHIFT  16      /* Implemented RX FIFO size */
 117 +#define LTQ_SPI_ID_RXFS_MASK   0x3F
 118 +#define LTQ_SPI_ID_REV_MASK    0x1F    /* Hardware revision number */
 119 +#define LTQ_SPI_ID_CFG         BIT(5)  /* DMA interface support */
 120 +
 121 +#define LTQ_SPI_CON_BM_SHIFT   16      /* Data width selection */
 122 +#define LTQ_SPI_CON_BM_MASK    0x1F
 123 +#define LTQ_SPI_CON_EM         BIT(24) /* Echo mode */
 124 +#define LTQ_SPI_CON_IDLE       BIT(23) /* Idle bit value */
 125 +#define LTQ_SPI_CON_ENBV       BIT(22) /* Enable byte valid control */
 126 +#define LTQ_SPI_CON_RUEN       BIT(12) /* Receive underflow error enable */
 127 +#define LTQ_SPI_CON_TUEN       BIT(11) /* Transmit underflow error enable */
 128 +#define LTQ_SPI_CON_AEN                BIT(10) /* Abort error enable */
 129 +#define LTQ_SPI_CON_REN                BIT(9)  /* Receive overflow error enable */
 130 +#define LTQ_SPI_CON_TEN                BIT(8)  /* Transmit overflow error enable */
 131 +#define LTQ_SPI_CON_LB         BIT(7)  /* Loopback control */
 132 +#define LTQ_SPI_CON_PO         BIT(6)  /* Clock polarity control */
 133 +#define LTQ_SPI_CON_PH         BIT(5)  /* Clock phase control */
 134 +#define LTQ_SPI_CON_HB         BIT(4)  /* Heading control */
 135 +#define LTQ_SPI_CON_RXOFF      BIT(1)  /* Switch receiver off */
 136 +#define LTQ_SPI_CON_TXOFF      BIT(0)  /* Switch transmitter off */
 137 +
 138 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
 139 +#define LTQ_SPI_STAT_RXBV_SHIFT        28
 140 +#define LTQ_SPI_STAT_BSY       BIT(13) /* Busy flag */
 141 +#define LTQ_SPI_STAT_RUE       BIT(12) /* Receive underflow error flag */
 142 +#define LTQ_SPI_STAT_TUE       BIT(11) /* Transmit underflow error flag */
 143 +#define LTQ_SPI_STAT_AE                BIT(10) /* Abort error flag */
 144 +#define LTQ_SPI_STAT_RE                BIT(9)  /* Receive error flag */
 145 +#define LTQ_SPI_STAT_TE                BIT(8)  /* Transmit error flag */
 146 +#define LTQ_SPI_STAT_MS                BIT(1)  /* Master/slave select bit */
 147 +#define LTQ_SPI_STAT_EN                BIT(0)  /* Enable bit */
 148 +
 149 +#define LTQ_SPI_WHBSTATE_SETTUE        BIT(15) /* Set transmit underflow error flag */
 150 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
 151 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
 152 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
 153 +#define LTQ_SPI_WHBSTATE_CLRTUE        BIT(11) /* Clear transmit underflow error
 154 +                                               flag */
 155 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
 156 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9)  /* Clear receive error flag */
 157 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8)  /* Clear transmit error flag */
 158 +#define LTQ_SPI_WHBSTATE_SETME BIT(7)  /* Set mode error flag */
 159 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6)  /* Clear mode error flag */
 160 +#define LTQ_SPI_WHBSTATE_SETRUE        BIT(5)  /* Set receive underflow error flag */
 161 +#define LTQ_SPI_WHBSTATE_CLRRUE        BIT(4)  /* Clear receive underflow error flag */
 162 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3)  /* Set master select bit */
 163 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2)  /* Clear master select bit */
 164 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1)  /* Set enable bit (operational mode) */
 165 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0)  /* Clear enable bit (config mode */
 166 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS    0x0F50
 167 +
 168 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT    8 /* FIFO interrupt trigger level */
 169 +#define LTQ_SPI_RXFCON_RXFITL_MASK     0x3F
 170 +#define LTQ_SPI_RXFCON_RXFLU           BIT(1)  /* FIFO flush */
 171 +#define LTQ_SPI_RXFCON_RXFEN           BIT(0)  /* FIFO enable */
 172 +
 173 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT    8 /* FIFO interrupt trigger level */
 174 +#define LTQ_SPI_TXFCON_TXFITL_MASK     0x3F
 175 +#define LTQ_SPI_TXFCON_TXFLU           BIT(1)  /* FIFO flush */
 176 +#define LTQ_SPI_TXFCON_TXFEN           BIT(0)  /* FIFO enable */
 177 +
 178 +#define LTQ_SPI_FSTAT_RXFFL_MASK       0x3f
 179 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT      0
 180 +#define LTQ_SPI_FSTAT_TXFFL_MASK       0x3f
 181 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT      8
 182 +
 183 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT    8
 184 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT   0
 185 +
 186 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT     8
 187 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT     0
 188 +
 189 +#define LTQ_SPI_RXREQ_RXCNT_MASK       0xFFFF  /* Receive count value */
 190 +#define LTQ_SPI_RXCNT_TODO_MASK                0xFFFF  /* Recevie to-do value */
 191 +
 192 +#define LTQ_SPI_IRNEN_F                BIT(3)  /* Frame end interrupt request */
 193 +#define LTQ_SPI_IRNEN_E                BIT(2)  /* Error end interrupt request */
 194 +#define LTQ_SPI_IRNEN_T                BIT(1)  /* Transmit end interrupt request */
 195 +#define LTQ_SPI_IRNEN_R                BIT(0)  /* Receive end interrupt request */
 196 +#define LTQ_SPI_IRNEN_ALL      0xF
 197 +
 198 +struct ltq_spi {
 199 +       struct spi_bitbang      bitbang;
 200 +       struct completion       done;
 201 +       spinlock_t              lock;
 202 +
 203 +       struct device           *dev;
 204 +       void __iomem            *base;
 205 +       struct clk              *fpiclk;
 206 +       struct clk              *spiclk;
 207 +
 208 +       int                     status;
 209 +       int                     irq[3];
 210 +
 211 +       const u8                *tx;
 212 +       u8                      *rx;
 213 +       u32                     tx_cnt;
 214 +       u32                     rx_cnt;
 215 +       u32                     len;
 216 +       struct spi_transfer     *curr_transfer;
 217 +
 218 +       u32 (*get_tx) (struct ltq_spi *);
 219 +
 220 +       u16                     txfs;
 221 +       u16                     rxfs;
 222 +       unsigned                dma_support:1;
 223 +       unsigned                cfg_mode:1;
 224 +};
 225 +
 226 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
 227 +{
 228 +       return spi_master_get_devdata(spi->master);
 229 +}
 230 +
 231 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
 232 +{
 233 +       return ioread32be(hw->base + reg);
 234 +}
 235 +
 236 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
 237 +{
 238 +       iowrite32be(val, hw->base + reg);
 239 +}
 240 +
 241 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
 242 +{
 243 +       u32 val;
 244 +
 245 +       val = ltq_spi_reg_read(hw, reg);
 246 +       val |= bits;
 247 +       ltq_spi_reg_write(hw, val, reg);
 248 +}
 249 +
 250 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
 251 +{
 252 +       u32 val;
 253 +
 254 +       val = ltq_spi_reg_read(hw, reg);
 255 +       val &= ~bits;
 256 +       ltq_spi_reg_write(hw, val, reg);
 257 +}
 258 +
 259 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
 260 +{
 261 +       u32 clc;
 262 +
 263 +       /* Power-up module */
 264 +       clk_enable(hw->spiclk);
 265 +
 266 +       /*
 267 +        * Set clock divider for run mode to 1 to
 268 +        * run at same frequency as FPI bus
 269 +        */
 270 +       clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
 271 +       ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
 272 +}
 273 +
 274 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
 275 +{
 276 +       /* Set clock divider to 0 and set module disable bit */
 277 +       ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
 278 +
 279 +       /* Power-down module */
 280 +       clk_disable(hw->spiclk);
 281 +}
 282 +
 283 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
 284 +{
 285 +       u32 val;
 286 +
 287 +       /*
 288 +        * Enable and flush FIFOs. Set interrupt trigger level to
 289 +        * half of FIFO count implemented in hardware.
 290 +        */
 291 +       if (hw->txfs > 1) {
 292 +               val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
 293 +               val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
 294 +               ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
 295 +       }
 296 +
 297 +       if (hw->rxfs > 1) {
 298 +               val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
 299 +               val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
 300 +               ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
 301 +       }
 302 +}
 303 +
 304 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
 305 +{
 306 +       u32 stat;
 307 +       unsigned long timeout;
 308 +
 309 +       timeout = jiffies + msecs_to_jiffies(200);
 310 +
 311 +       do {
 312 +               stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
 313 +               if (!(stat & LTQ_SPI_STAT_BSY))
 314 +                       return 0;
 315 +
 316 +               cond_resched();
 317 +       } while (!time_after_eq(jiffies, timeout));
 318 +
 319 +       dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat);
 320 +
 321 +       return -ETIMEDOUT;
 322 +}
 323 +
 324 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
 325 +{
 326 +       if (hw->cfg_mode)
 327 +               return;
 328 +
 329 +       /*
 330 +        * Putting the SPI module in config mode is only safe if no
 331 +        * transfer is in progress as indicated by busy flag STATE.BSY.
 332 +        */
 333 +       if (ltq_spi_wait_ready(hw)) {
 334 +               ltq_spi_reset_fifos(hw);
 335 +               hw->status = -ETIMEDOUT;
 336 +       }
 337 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
 338 +
 339 +       hw->cfg_mode = 1;
 340 +}
 341 +
 342 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
 343 +{
 344 +       if (!hw->cfg_mode)
 345 +               return;
 346 +
 347 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
 348 +
 349 +       hw->cfg_mode = 0;
 350 +}
 351 +
 352 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
 353 +{
 354 +       const u8 *tx = hw->tx;
 355 +       u32 data = *tx++;
 356 +
 357 +       hw->tx_cnt++;
 358 +       hw->tx++;
 359 +
 360 +       return data;
 361 +}
 362 +
 363 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
 364 +{
 365 +       const u16 *tx = (u16 *) hw->tx;
 366 +       u32 data = *tx++;
 367 +
 368 +       hw->tx_cnt += 2;
 369 +       hw->tx += 2;
 370 +
 371 +       return data;
 372 +}
 373 +
 374 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
 375 +{
 376 +       const u32 *tx = (u32 *) hw->tx;
 377 +       u32 data = *tx++;
 378 +
 379 +       hw->tx_cnt += 4;
 380 +       hw->tx += 4;
 381 +
 382 +       return data;
 383 +}
 384 +
 385 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
 386 +{
 387 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 388 +       u32 bm;
 389 +       u8 bits_per_word = spi->bits_per_word;
 390 +
 391 +       /*
 392 +        * Use either default value of SPI device or value
 393 +        * from current transfer.
 394 +        */
 395 +       if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
 396 +               bits_per_word = hw->curr_transfer->bits_per_word;
 397 +
 398 +       if (bits_per_word <= 8)
 399 +               hw->get_tx = ltq_spi_tx_word_u8;
 400 +       else if (bits_per_word <= 16)
 401 +               hw->get_tx = ltq_spi_tx_word_u16;
 402 +       else if (bits_per_word <= 32)
 403 +               hw->get_tx = ltq_spi_tx_word_u32;
 404 +
 405 +       /* CON.BM value = bits_per_word - 1 */
 406 +       bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
 407 +
 408 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
 409 +                            LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
 410 +       ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
 411 +}
 412 +
 413 +static void ltq_spi_speed_set(struct spi_device *spi)
 414 +{
 415 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 416 +       u32 br, max_speed_hz, spi_clk;
 417 +       u32 speed_hz = spi->max_speed_hz;
 418 +
 419 +       /*
 420 +        * Use either default value of SPI device or value
 421 +        * from current transfer.
 422 +        */
 423 +       if (hw->curr_transfer && hw->curr_transfer->speed_hz)
 424 +               speed_hz = hw->curr_transfer->speed_hz;
 425 +
 426 +       /*
 427 +        * SPI module clock is derived from FPI bus clock dependent on
 428 +        * divider value in CLC.RMS which is always set to 1.
 429 +        */
 430 +       spi_clk = clk_get_rate(hw->fpiclk);
 431 +
 432 +       /*
 433 +        * Maximum SPI clock frequency in master mode is half of
 434 +        * SPI module clock frequency. Maximum reload value of
 435 +        * baudrate generator BR is 2^16.
 436 +        */
 437 +       max_speed_hz = spi_clk / 2;
 438 +       if (speed_hz >= max_speed_hz)
 439 +               br = 0;
 440 +       else
 441 +               br = (max_speed_hz / speed_hz) - 1;
 442 +
 443 +       if (br > 0xFFFF)
 444 +               br = 0xFFFF;
 445 +
 446 +       ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
 447 +}
 448 +
 449 +static void ltq_spi_clockmode_set(struct spi_device *spi)
 450 +{
 451 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 452 +       u32 con;
 453 +
 454 +       con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
 455 +
 456 +       /*
 457 +        * SPI mode mapping in CON register:
 458 +        * Mode CPOL CPHA CON.PO CON.PH
 459 +        *  0    0    0      0      1
 460 +        *  1    0    1      0      0
 461 +        *  2    1    0      1      1
 462 +        *  3    1    1      1      0
 463 +        */
 464 +       if (spi->mode & SPI_CPHA)
 465 +               con &= ~LTQ_SPI_CON_PH;
 466 +       else
 467 +               con |= LTQ_SPI_CON_PH;
 468 +
 469 +       if (spi->mode & SPI_CPOL)
 470 +               con |= LTQ_SPI_CON_PO;
 471 +       else
 472 +               con &= ~LTQ_SPI_CON_PO;
 473 +
 474 +       /* Set heading control */
 475 +       if (spi->mode & SPI_LSB_FIRST)
 476 +               con &= ~LTQ_SPI_CON_HB;
 477 +       else
 478 +               con |= LTQ_SPI_CON_HB;
 479 +
 480 +       ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
 481 +}
 482 +
 483 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
 484 +{
 485 +       u32 con;
 486 +
 487 +       con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
 488 +
 489 +       if (t) {
 490 +               if (t->tx_buf && t->rx_buf) {
 491 +                       con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
 492 +               } else if (t->rx_buf) {
 493 +                       con &= ~LTQ_SPI_CON_RXOFF;
 494 +                       con |= LTQ_SPI_CON_TXOFF;
 495 +               } else if (t->tx_buf) {
 496 +                       con &= ~LTQ_SPI_CON_TXOFF;
 497 +                       con |= LTQ_SPI_CON_RXOFF;
 498 +               }
 499 +       } else
 500 +               con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
 501 +
 502 +       ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
 503 +}
 504 +
 505 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
 506 +{
 507 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 508 +       u32 fgpo;
 509 +
 510 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
 511 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 512 +}
 513 +
 514 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
 515 +{
 516 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 517 +       u32 fgpo;
 518 +
 519 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
 520 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 521 +}
 522 +
 523 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
 524 +{
 525 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 526 +
 527 +       switch (cs) {
 528 +       case BITBANG_CS_ACTIVE:
 529 +               ltq_spi_bits_per_word_set(spi);
 530 +               ltq_spi_speed_set(spi);
 531 +               ltq_spi_clockmode_set(spi);
 532 +               ltq_spi_run_mode_set(hw);
 533 +               ltq_spi_internal_cs_activate(spi);
 534 +               break;
 535 +
 536 +       case BITBANG_CS_INACTIVE:
 537 +               ltq_spi_internal_cs_deactivate(spi);
 538 +               ltq_spi_config_mode_set(hw);
 539 +               break;
 540 +       }
 541 +}
 542 +
 543 +static int ltq_spi_setup_transfer(struct spi_device *spi,
 544 +                                 struct spi_transfer *t)
 545 +{
 546 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 547 +       u8 bits_per_word = spi->bits_per_word;
 548 +
 549 +       hw->curr_transfer = t;
 550 +
 551 +       if (t && t->bits_per_word)
 552 +               bits_per_word = t->bits_per_word;
 553 +
 554 +       if (bits_per_word > 32)
 555 +               return -EINVAL;
 556 +
 557 +       ltq_spi_config_mode_set(hw);
 558 +
 559 +       return 0;
 560 +}
 561 +
 562 +static int ltq_spi_setup(struct spi_device *spi)
 563 +{
 564 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 565 +       u32 gpocon, fgpo;
 566 +
 567 +       /* Set default word length to 8 if not set */
 568 +       if (!spi->bits_per_word)
 569 +               spi->bits_per_word = 8;
 570 +
 571 +       if (spi->bits_per_word > 32)
 572 +               return -EINVAL;
 573 +
 574 +       /*
 575 +        * Up to six GPIOs can be connected to the SPI module
 576 +        * via GPIO alternate function to control the chip select lines.
 577 +        */
 578 +       gpocon = (1 << (spi->chip_select +
 579 +                       LTQ_SPI_GPOCON_ISCSBN_SHIFT));
 580 +
 581 +       if (spi->mode & SPI_CS_HIGH)
 582 +               gpocon |= (1 << spi->chip_select);
 583 +
 584 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
 585 +
 586 +       ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
 587 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 588 +
 589 +       return 0;
 590 +}
 591 +
 592 +static void ltq_spi_cleanup(struct spi_device *spi)
 593 +{
 594 +
 595 +}
 596 +
 597 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
 598 +{
 599 +       u32 fstat, data;
 600 +       u16 fifo_space;
 601 +
 602 +       /* Determine how much FIFOs are free for TX data */
 603 +       fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
 604 +       fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
 605 +                                       LTQ_SPI_FSTAT_TXFFL_MASK);
 606 +
 607 +       if (!fifo_space)
 608 +               return;
 609 +
 610 +       while (hw->tx_cnt < hw->len && fifo_space) {
 611 +               data = hw->get_tx(hw);
 612 +               ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
 613 +               fifo_space--;
 614 +       }
 615 +}
 616 +
 617 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
 618 +{
 619 +       u32 fstat, data, *rx32;
 620 +       u16 fifo_fill;
 621 +       u8 rxbv, shift, *rx8;
 622 +
 623 +       /* Determine how much FIFOs are filled with RX data */
 624 +       fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
 625 +       fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
 626 +                       & LTQ_SPI_FSTAT_RXFFL_MASK);
 627 +
 628 +       if (!fifo_fill)
 629 +               return;
 630 +
 631 +       /*
 632 +        * The 32 bit FIFO is always used completely independent from the
 633 +        * bits_per_word value. Thus four bytes have to be read at once
 634 +        * per FIFO.
 635 +        */
 636 +       rx32 = (u32 *) hw->rx;
 637 +       while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
 638 +               *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
 639 +               hw->rx_cnt += 4;
 640 +               hw->rx += 4;
 641 +               fifo_fill--;
 642 +       }
 643 +
 644 +       /*
 645 +        * If there are remaining bytes, read byte count from STAT.RXBV
 646 +        * register and read the data byte-wise.
 647 +        */
 648 +       while (fifo_fill && hw->rx_cnt < hw->len) {
 649 +               rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
 650 +                       LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
 651 +               data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
 652 +
 653 +               shift = (rxbv - 1) * 8;
 654 +               rx8 = hw->rx;
 655 +
 656 +               while (rxbv) {
 657 +                       *rx8++ = (data >> shift) & 0xFF;
 658 +                       rxbv--;
 659 +                       shift -= 8;
 660 +                       hw->rx_cnt++;
 661 +                       hw->rx++;
 662 +               }
 663 +
 664 +               fifo_fill--;
 665 +       }
 666 +}
 667 +
 668 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
 669 +{
 670 +       u32 rxreq, rxreq_max, rxtodo;
 671 +
 672 +       rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
 673 +
 674 +       /*
 675 +        * In RX-only mode the serial clock is activated only after writing
 676 +        * the expected amount of RX bytes into RXREQ register.
 677 +        * To avoid receive overflows at high clocks it is better to request
 678 +        * only the amount of bytes that fits into all FIFOs. This value
 679 +        * depends on the FIFO size implemented in hardware.
 680 +        */
 681 +       rxreq = hw->len - hw->rx_cnt;
 682 +       rxreq_max = hw->rxfs << 2;
 683 +       rxreq = min(rxreq_max, rxreq);
 684 +
 685 +       if (!rxtodo && rxreq)
 686 +               ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
 687 +}
 688 +
 689 +static inline void ltq_spi_complete(struct ltq_spi *hw)
 690 +{
 691 +       complete(&hw->done);
 692 +}
 693 +
 694 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
 695 +{
 696 +       struct ltq_spi *hw = data;
 697 +       unsigned long flags;
 698 +       int completed = 0;
 699 +
 700 +       spin_lock_irqsave(&hw->lock, flags);
 701 +
 702 +       if (hw->tx_cnt < hw->len)
 703 +               ltq_spi_txfifo_write(hw);
 704 +
 705 +       if (hw->tx_cnt == hw->len)
 706 +               completed = 1;
 707 +
 708 +       spin_unlock_irqrestore(&hw->lock, flags);
 709 +
 710 +       if (completed)
 711 +               ltq_spi_complete(hw);
 712 +
 713 +       return IRQ_HANDLED;
 714 +}
 715 +
 716 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
 717 +{
 718 +       struct ltq_spi *hw = data;
 719 +       unsigned long flags;
 720 +       int completed = 0;
 721 +
 722 +       spin_lock_irqsave(&hw->lock, flags);
 723 +
 724 +       if (hw->rx_cnt < hw->len) {
 725 +               ltq_spi_rxfifo_read(hw);
 726 +
 727 +               if (hw->tx && hw->tx_cnt < hw->len)
 728 +                       ltq_spi_txfifo_write(hw);
 729 +       }
 730 +
 731 +       if (hw->rx_cnt == hw->len)
 732 +               completed = 1;
 733 +       else if (!hw->tx)
 734 +               ltq_spi_rxreq_set(hw);
 735 +
 736 +       spin_unlock_irqrestore(&hw->lock, flags);
 737 +
 738 +       if (completed)
 739 +               ltq_spi_complete(hw);
 740 +
 741 +       return IRQ_HANDLED;
 742 +}
 743 +
 744 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
 745 +{
 746 +       struct ltq_spi *hw = data;
 747 +       unsigned long flags;
 748 +
 749 +       spin_lock_irqsave(&hw->lock, flags);
 750 +
 751 +       /* Disable all interrupts */
 752 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
 753 +
 754 +       /* Clear all error flags */
 755 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
 756 +
 757 +       /* Flush FIFOs */
 758 +       ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
 759 +       ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
 760 +
 761 +       hw->status = -EIO;
 762 +       spin_unlock_irqrestore(&hw->lock, flags);
 763 +
 764 +       ltq_spi_complete(hw);
 765 +
 766 +       return IRQ_HANDLED;
 767 +}
 768 +
 769 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 770 +{
 771 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 772 +       u32 irq_flags = 0;
 773 +
 774 +       hw->tx = t->tx_buf;
 775 +       hw->rx = t->rx_buf;
 776 +       hw->len = t->len;
 777 +       hw->tx_cnt = 0;
 778 +       hw->rx_cnt = 0;
 779 +       hw->status = 0;
 780 +       INIT_COMPLETION(hw->done);
 781 +
 782 +       ltq_spi_xmit_set(hw, t);
 783 +
 784 +       /* Enable error interrupts */
 785 +       ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
 786 +
 787 +       if (hw->tx) {
 788 +               /* Initially fill TX FIFO with as much data as possible */
 789 +               ltq_spi_txfifo_write(hw);
 790 +               irq_flags |= LTQ_SPI_IRNEN_T;
 791 +
 792 +               /* Always enable RX interrupt in Full Duplex mode */
 793 +               if (hw->rx)
 794 +                       irq_flags |= LTQ_SPI_IRNEN_R;
 795 +       } else if (hw->rx) {
 796 +               /* Start RX clock */
 797 +               ltq_spi_rxreq_set(hw);
 798 +
 799 +               /* Enable RX interrupt to receive data from RX FIFOs */
 800 +               irq_flags |= LTQ_SPI_IRNEN_R;
 801 +       }
 802 +
 803 +       /* Enable TX or RX interrupts */
 804 +       ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
 805 +       wait_for_completion_interruptible(&hw->done);
 806 +
 807 +       /* Disable all interrupts */
 808 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
 809 +
 810 +       /*
 811 +        * Return length of current transfer for bitbang utility code if
 812 +        * no errors occured during transmission.
 813 +        */
 814 +       if (!hw->status)
 815 +               hw->status = hw->len;
 816 +
 817 +       return hw->status;
 818 +}
 819 +
 820 +static const struct ltq_spi_irq_map {
 821 +       char *name;
 822 +       irq_handler_t handler;
 823 +} ltq_spi_irqs[] = {
 824 +       { "spi_rx", ltq_spi_rx_irq },
 825 +       { "spi_tx", ltq_spi_tx_irq },
 826 +       { "spi_err", ltq_spi_err_irq },
 827 +};
 828 +
 829 +static int ltq_spi_probe(struct platform_device *pdev)
 830 +{
 831 +       struct resource irqres[3];
 832 +       struct spi_master *master;
 833 +       struct resource *r;
 834 +       struct ltq_spi *hw;
 835 +       int ret, i;
 836 +       u32 data, id;
 837 +
 838 +       if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 3) != 3) {
 839 +               dev_err(&pdev->dev, "IRQ settings missing in device tree\n");
 840 +               return -EINVAL;
 841 +       }
 842 +
 843 +       master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
 844 +       if (!master) {
 845 +               dev_err(&pdev->dev, "spi_alloc_master\n");
 846 +               ret = -ENOMEM;
 847 +               goto err;
 848 +       }
 849 +
 850 +       hw = spi_master_get_devdata(master);
 851 +
 852 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 853 +       if (r == NULL) {
 854 +               dev_err(&pdev->dev, "platform_get_resource\n");
 855 +               ret = -ENOENT;
 856 +               goto err_master;
 857 +       }
 858 +
 859 +       r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 860 +                       pdev->name);
 861 +       if (!r) {
 862 +               dev_err(&pdev->dev, "failed to request memory region\n");
 863 +               ret = -ENXIO;
 864 +               goto err_master;
 865 +       }
 866 +
 867 +       hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
 868 +       if (!hw->base) {
 869 +               dev_err(&pdev->dev, "failed to remap memory region\n");
 870 +               ret = -ENXIO;
 871 +               goto err_master;
 872 +       }
 873 +
 874 +       memset(hw->irq, 0, sizeof(hw->irq));
 875 +       for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
 876 +               hw->irq[i] = irqres[i].start;
 877 +               ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
 878 +                                 0, ltq_spi_irqs[i].name, hw);
 879 +               if (ret) {
 880 +                       dev_err(&pdev->dev, "failed to request %s irq (%d)\n",
 881 +                                       ltq_spi_irqs[i].name, hw->irq[i]);
 882 +                       goto err_irq;
 883 +               }
 884 +       }
 885 +
 886 +       hw->fpiclk = clk_get_fpi();
 887 +       if (IS_ERR(hw->fpiclk)) {
 888 +               dev_err(&pdev->dev, "failed to get fpi clock\n");
 889 +               ret = PTR_ERR(hw->fpiclk);
 890 +               goto err_clk;
 891 +       }
 892 +
 893 +       hw->spiclk = clk_get(&pdev->dev, NULL);
 894 +       if (IS_ERR(hw->spiclk)) {
 895 +               dev_err(&pdev->dev, "failed to get spi clock gate\n");
 896 +               ret = PTR_ERR(hw->spiclk);
 897 +               goto err_clk;
 898 +       }
 899 +
 900 +       hw->bitbang.master = spi_master_get(master);
 901 +       hw->bitbang.chipselect = ltq_spi_chipselect;
 902 +       hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
 903 +       hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
 904 +
 905 +       if (of_machine_is_compatible("lantiq,ase"))
 906 +               master->num_chipselect = 3;
 907 +       else
 908 +               master->num_chipselect = 6;
 909 +       master->bus_num = pdev->id;
 910 +       master->setup = ltq_spi_setup;
 911 +       master->cleanup = ltq_spi_cleanup;
 912 +       master->dev.of_node = pdev->dev.of_node;
 913 +
 914 +       hw->dev = &pdev->dev;
 915 +       init_completion(&hw->done);
 916 +       spin_lock_init(&hw->lock);
 917 +
 918 +       ltq_spi_hw_enable(hw);
 919 +
 920 +       /* Read module capabilities */
 921 +       id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
 922 +       hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
 923 +       hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
 924 +       hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
 925 +
 926 +       ltq_spi_config_mode_set(hw);
 927 +
 928 +       /* Enable error checking, disable TX/RX, set idle value high */
 929 +       data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
 930 +           LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
 931 +           LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
 932 +       ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
 933 +
 934 +       /* Enable master mode and clear error flags */
 935 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
 936 +                         LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
 937 +
 938 +       /* Reset GPIO/CS registers */
 939 +       ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
 940 +       ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
 941 +
 942 +       /* Enable and flush FIFOs */
 943 +       ltq_spi_reset_fifos(hw);
 944 +
 945 +       ret = spi_bitbang_start(&hw->bitbang);
 946 +       if (ret) {
 947 +               dev_err(&pdev->dev, "spi_bitbang_start failed\n");
 948 +               goto err_bitbang;
 949 +       }
 950 +
 951 +       platform_set_drvdata(pdev, hw);
 952 +
 953 +       pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
 954 +               id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
 955 +
 956 +       return 0;
 957 +
 958 +err_bitbang:
 959 +       ltq_spi_hw_disable(hw);
 960 +
 961 +err_clk:
 962 +       if (hw->fpiclk)
 963 +               clk_put(hw->fpiclk);
 964 +       if (hw->spiclk)
 965 +               clk_put(hw->spiclk);
 966 +
 967 +err_irq:
 968 +       clk_put(hw->fpiclk);
 969 +
 970 +       for (; i > 0; i--)
 971 +               free_irq(hw->irq[i], hw);
 972 +
 973 +err_master:
 974 +       spi_master_put(master);
 975 +
 976 +err:
 977 +       return ret;
 978 +}
 979 +
 980 +static int ltq_spi_remove(struct platform_device *pdev)
 981 +{
 982 +       struct ltq_spi *hw = platform_get_drvdata(pdev);
 983 +       int ret, i;
 984 +
 985 +       ret = spi_bitbang_stop(&hw->bitbang);
 986 +       if (ret)
 987 +               return ret;
 988 +
 989 +       platform_set_drvdata(pdev, NULL);
 990 +
 991 +       ltq_spi_config_mode_set(hw);
 992 +       ltq_spi_hw_disable(hw);
 993 +
 994 +       for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
 995 +               if (0 < hw->irq[i])
 996 +                       free_irq(hw->irq[i], hw);
 997 +
 998 +       if (hw->fpiclk)
 999 +               clk_put(hw->fpiclk);
1000 +       if (hw->spiclk)
1001 +               clk_put(hw->spiclk);
1002 +
1003 +       spi_master_put(hw->bitbang.master);
1004 +
1005 +       return 0;
1006 +}
1007 +
1008 +static const struct of_device_id ltq_spi_match[] = {
1009 +       { .compatible = "lantiq,spi-xway" },
1010 +       {},
1011 +};
1012 +MODULE_DEVICE_TABLE(of, ltq_spi_match);
1013 +
1014 +static struct platform_driver ltq_spi_driver = {
1015 +       .probe = ltq_spi_probe,
1016 +       .remove = ltq_spi_remove,
1017 +       .driver = {
1018 +               .name = "spi-xway",
1019 +               .owner = THIS_MODULE,
1020 +               .of_match_table = ltq_spi_match,
1021 +       },
1022 +};
1023 +
1024 +module_platform_driver(ltq_spi_driver);
1025 +
1026 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1027 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1028 +MODULE_LICENSE("GPL");
1029 +MODULE_ALIAS("platform:spi-xway");
1030 --
1031 1.7.10.4
1032