ed00b343368dfb9d6a0b9b853dc85d0519762133
[openwrt/openwrt.git] / target / linux / lantiq / patches-3.18 / 0033-SPI-MIPS-lantiq-adds-spi-xway.patch
1 From e75df4f96373e5d16f8ca13aa031e54cdcfeda62 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 13 Mar 2013 09:29:37 +0100
4 Subject: [PATCH 33/36] SPI: MIPS: lantiq: adds spi-xway
5
6 This patch adds support for the SPI core found on several Lantiq SoCs.
7 The Driver has been runtime tested in combination with m25p80 Flash Devices
8 on Amazon_SE and VR9.
9
10 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
11 Signed-off-by: John Crispin <blogic@openwrt.org>
12 ---
13 drivers/spi/Kconfig | 8 +
14 drivers/spi/Makefile | 1 +
15 drivers/spi/spi-xway.c | 977 ++++++++++++++++++++++++++++++++++++++++++++++++
16 3 files changed, 986 insertions(+)
17 create mode 100644 drivers/spi/spi-xway.c
18
19 --- a/drivers/spi/Kconfig
20 +++ b/drivers/spi/Kconfig
21 @@ -597,6 +597,14 @@ config SPI_NUC900
22 help
23 SPI driver for Nuvoton NUC900 series ARM SoCs
24
25 +config SPI_XWAY
26 + tristate "Lantiq XWAY SPI controller"
27 + depends on LANTIQ && SOC_TYPE_XWAY
28 + select SPI_BITBANG
29 + help
30 + This driver supports the Lantiq SoC SPI controller in master
31 + mode.
32 +
33 #
34 # Add new SPI master controllers in alphabetical order above this line
35 #
36 --- a/drivers/spi/Makefile
37 +++ b/drivers/spi/Makefile
38 @@ -86,3 +86,4 @@ obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
39 obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
40 obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
41 obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
42 +obj-$(CONFIG_SPI_XWAY) += spi-xway.o
43 --- /dev/null
44 +++ b/drivers/spi/spi-xway.c
45 @@ -0,0 +1,975 @@
46 +/*
47 + * Lantiq SoC SPI controller
48 + *
49 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
50 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
51 + *
52 + * This program is free software; you can distribute it and/or modify it
53 + * under the terms of the GNU General Public License (Version 2) as
54 + * published by the Free Software Foundation.
55 + */
56 +
57 +#include <linux/init.h>
58 +#include <linux/module.h>
59 +#include <linux/workqueue.h>
60 +#include <linux/platform_device.h>
61 +#include <linux/io.h>
62 +#include <linux/sched.h>
63 +#include <linux/delay.h>
64 +#include <linux/interrupt.h>
65 +#include <linux/completion.h>
66 +#include <linux/spinlock.h>
67 +#include <linux/err.h>
68 +#include <linux/clk.h>
69 +#include <linux/spi/spi.h>
70 +#include <linux/spi/spi_bitbang.h>
71 +#include <linux/of_irq.h>
72 +
73 +#include <lantiq_soc.h>
74 +
75 +#define LTQ_SPI_CLC 0x00 /* Clock control */
76 +#define LTQ_SPI_PISEL 0x04 /* Port input select */
77 +#define LTQ_SPI_ID 0x08 /* Identification */
78 +#define LTQ_SPI_CON 0x10 /* Control */
79 +#define LTQ_SPI_STAT 0x14 /* Status */
80 +#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */
81 +#define LTQ_SPI_TB 0x20 /* Transmit buffer */
82 +#define LTQ_SPI_RB 0x24 /* Receive buffer */
83 +#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */
84 +#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */
85 +#define LTQ_SPI_FSTAT 0x38 /* FIFO status */
86 +#define LTQ_SPI_BRT 0x40 /* Baudrate timer */
87 +#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */
88 +#define LTQ_SPI_SFCON 0x60 /* Serial frame control */
89 +#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */
90 +#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */
91 +#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */
92 +#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */
93 +#define LTQ_SPI_RXREQ 0x80 /* Receive request */
94 +#define LTQ_SPI_RXCNT 0x84 /* Receive count */
95 +#define LTQ_SPI_DMACON 0xEC /* DMA control */
96 +#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */
97 +#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */
98 +#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */
99 +
100 +#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */
101 +#define LTQ_SPI_CLC_SMC_MASK 0xFF
102 +#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */
103 +#define LTQ_SPI_CLC_RMC_MASK 0xFF
104 +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
105 +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
106 +
107 +#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */
108 +#define LTQ_SPI_ID_TXFS_MASK 0x3F
109 +#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */
110 +#define LTQ_SPI_ID_RXFS_MASK 0x3F
111 +#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */
112 +#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */
113 +
114 +#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */
115 +#define LTQ_SPI_CON_BM_MASK 0x1F
116 +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
117 +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
118 +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
119 +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
120 +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
121 +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
122 +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
123 +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
124 +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
125 +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
126 +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
127 +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */
128 +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
129 +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
130 +
131 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
132 +#define LTQ_SPI_STAT_RXBV_SHIFT 28
133 +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
134 +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
135 +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
136 +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
137 +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
138 +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
139 +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
140 +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
141 +
142 +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
143 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
144 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
145 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
146 +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error
147 + flag */
148 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
149 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
150 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
151 +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
152 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
153 +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
154 +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
155 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
156 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
157 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
158 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
159 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50
160 +
161 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */
162 +#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F
163 +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
164 +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
165 +
166 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */
167 +#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F
168 +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
169 +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
170 +
171 +#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f
172 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0
173 +#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f
174 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8
175 +
176 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8
177 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0
178 +
179 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8
180 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0
181 +
182 +#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */
183 +#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */
184 +
185 +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
186 +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
187 +#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */
188 +#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */
189 +#define LTQ_SPI_IRNEN_ALL 0xF
190 +
191 +struct ltq_spi {
192 + struct spi_bitbang bitbang;
193 + struct completion done;
194 + spinlock_t lock;
195 +
196 + struct device *dev;
197 + void __iomem *base;
198 + struct clk *fpiclk;
199 + struct clk *spiclk;
200 +
201 + int status;
202 + int irq[3];
203 +
204 + const u8 *tx;
205 + u8 *rx;
206 + u32 tx_cnt;
207 + u32 rx_cnt;
208 + u32 len;
209 + struct spi_transfer *curr_transfer;
210 +
211 + u32 (*get_tx) (struct ltq_spi *);
212 +
213 + u16 txfs;
214 + u16 rxfs;
215 + unsigned dma_support:1;
216 + unsigned cfg_mode:1;
217 +};
218 +
219 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
220 +{
221 + return spi_master_get_devdata(spi->master);
222 +}
223 +
224 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
225 +{
226 + return ioread32be(hw->base + reg);
227 +}
228 +
229 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
230 +{
231 + iowrite32be(val, hw->base + reg);
232 +}
233 +
234 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
235 +{
236 + u32 val;
237 +
238 + val = ltq_spi_reg_read(hw, reg);
239 + val |= bits;
240 + ltq_spi_reg_write(hw, val, reg);
241 +}
242 +
243 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
244 +{
245 + u32 val;
246 +
247 + val = ltq_spi_reg_read(hw, reg);
248 + val &= ~bits;
249 + ltq_spi_reg_write(hw, val, reg);
250 +}
251 +
252 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
253 +{
254 + u32 clc;
255 +
256 + /* Power-up module */
257 + clk_enable(hw->spiclk);
258 +
259 + /*
260 + * Set clock divider for run mode to 1 to
261 + * run at same frequency as FPI bus
262 + */
263 + clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
264 + ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
265 +}
266 +
267 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
268 +{
269 + /* Set clock divider to 0 and set module disable bit */
270 + ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
271 +
272 + /* Power-down module */
273 + clk_disable(hw->spiclk);
274 +}
275 +
276 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
277 +{
278 + u32 val;
279 +
280 + /*
281 + * Enable and flush FIFOs. Set interrupt trigger level to
282 + * half of FIFO count implemented in hardware.
283 + */
284 + if (hw->txfs > 1) {
285 + val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
286 + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
287 + ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
288 + }
289 +
290 + if (hw->rxfs > 1) {
291 + val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
292 + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
293 + ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
294 + }
295 +}
296 +
297 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
298 +{
299 + u32 stat;
300 + unsigned long timeout;
301 +
302 + timeout = jiffies + msecs_to_jiffies(200);
303 +
304 + do {
305 + stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
306 + if (!(stat & LTQ_SPI_STAT_BSY))
307 + return 0;
308 +
309 + cond_resched();
310 + } while (!time_after_eq(jiffies, timeout));
311 +
312 + dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat);
313 +
314 + return -ETIMEDOUT;
315 +}
316 +
317 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
318 +{
319 + if (hw->cfg_mode)
320 + return;
321 +
322 + /*
323 + * Putting the SPI module in config mode is only safe if no
324 + * transfer is in progress as indicated by busy flag STATE.BSY.
325 + */
326 + if (ltq_spi_wait_ready(hw)) {
327 + ltq_spi_reset_fifos(hw);
328 + hw->status = -ETIMEDOUT;
329 + }
330 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
331 +
332 + hw->cfg_mode = 1;
333 +}
334 +
335 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
336 +{
337 + if (!hw->cfg_mode)
338 + return;
339 +
340 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
341 +
342 + hw->cfg_mode = 0;
343 +}
344 +
345 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
346 +{
347 + const u8 *tx = hw->tx;
348 + u32 data = *tx++;
349 +
350 + hw->tx_cnt++;
351 + hw->tx++;
352 +
353 + return data;
354 +}
355 +
356 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
357 +{
358 + const u16 *tx = (u16 *) hw->tx;
359 + u32 data = *tx++;
360 +
361 + hw->tx_cnt += 2;
362 + hw->tx += 2;
363 +
364 + return data;
365 +}
366 +
367 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
368 +{
369 + const u32 *tx = (u32 *) hw->tx;
370 + u32 data = *tx++;
371 +
372 + hw->tx_cnt += 4;
373 + hw->tx += 4;
374 +
375 + return data;
376 +}
377 +
378 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
379 +{
380 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
381 + u32 bm;
382 + u8 bits_per_word = spi->bits_per_word;
383 +
384 + /*
385 + * Use either default value of SPI device or value
386 + * from current transfer.
387 + */
388 + if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
389 + bits_per_word = hw->curr_transfer->bits_per_word;
390 +
391 + if (bits_per_word <= 8)
392 + hw->get_tx = ltq_spi_tx_word_u8;
393 + else if (bits_per_word <= 16)
394 + hw->get_tx = ltq_spi_tx_word_u16;
395 + else if (bits_per_word <= 32)
396 + hw->get_tx = ltq_spi_tx_word_u32;
397 +
398 + /* CON.BM value = bits_per_word - 1 */
399 + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
400 +
401 + ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
402 + LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
403 + ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
404 +}
405 +
406 +static void ltq_spi_speed_set(struct spi_device *spi)
407 +{
408 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
409 + u32 br, max_speed_hz, spi_clk;
410 + u32 speed_hz = spi->max_speed_hz;
411 +
412 + /*
413 + * Use either default value of SPI device or value
414 + * from current transfer.
415 + */
416 + if (hw->curr_transfer && hw->curr_transfer->speed_hz)
417 + speed_hz = hw->curr_transfer->speed_hz;
418 +
419 + /*
420 + * SPI module clock is derived from FPI bus clock dependent on
421 + * divider value in CLC.RMS which is always set to 1.
422 + */
423 + spi_clk = clk_get_rate(hw->fpiclk);
424 +
425 + /*
426 + * Maximum SPI clock frequency in master mode is half of
427 + * SPI module clock frequency. Maximum reload value of
428 + * baudrate generator BR is 2^16.
429 + */
430 + max_speed_hz = spi_clk / 2;
431 + if (speed_hz >= max_speed_hz)
432 + br = 0;
433 + else
434 + br = (max_speed_hz / speed_hz) - 1;
435 +
436 + if (br > 0xFFFF)
437 + br = 0xFFFF;
438 +
439 + ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
440 +}
441 +
442 +static void ltq_spi_clockmode_set(struct spi_device *spi)
443 +{
444 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
445 + u32 con;
446 +
447 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
448 +
449 + /*
450 + * SPI mode mapping in CON register:
451 + * Mode CPOL CPHA CON.PO CON.PH
452 + * 0 0 0 0 1
453 + * 1 0 1 0 0
454 + * 2 1 0 1 1
455 + * 3 1 1 1 0
456 + */
457 + if (spi->mode & SPI_CPHA)
458 + con &= ~LTQ_SPI_CON_PH;
459 + else
460 + con |= LTQ_SPI_CON_PH;
461 +
462 + if (spi->mode & SPI_CPOL)
463 + con |= LTQ_SPI_CON_PO;
464 + else
465 + con &= ~LTQ_SPI_CON_PO;
466 +
467 + /* Set heading control */
468 + if (spi->mode & SPI_LSB_FIRST)
469 + con &= ~LTQ_SPI_CON_HB;
470 + else
471 + con |= LTQ_SPI_CON_HB;
472 +
473 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
474 +}
475 +
476 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
477 +{
478 + u32 con;
479 +
480 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
481 +
482 + if (t) {
483 + if (t->tx_buf && t->rx_buf) {
484 + con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
485 + } else if (t->rx_buf) {
486 + con &= ~LTQ_SPI_CON_RXOFF;
487 + con |= LTQ_SPI_CON_TXOFF;
488 + } else if (t->tx_buf) {
489 + con &= ~LTQ_SPI_CON_TXOFF;
490 + con |= LTQ_SPI_CON_RXOFF;
491 + }
492 + } else
493 + con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
494 +
495 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
496 +}
497 +
498 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
499 +{
500 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
501 + u32 fgpo;
502 +
503 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
504 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
505 +}
506 +
507 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
508 +{
509 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
510 + u32 fgpo;
511 +
512 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
513 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
514 +}
515 +
516 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
517 +{
518 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
519 +
520 + switch (cs) {
521 + case BITBANG_CS_ACTIVE:
522 + ltq_spi_bits_per_word_set(spi);
523 + ltq_spi_speed_set(spi);
524 + ltq_spi_clockmode_set(spi);
525 + ltq_spi_run_mode_set(hw);
526 + ltq_spi_internal_cs_activate(spi);
527 + break;
528 +
529 + case BITBANG_CS_INACTIVE:
530 + ltq_spi_internal_cs_deactivate(spi);
531 + ltq_spi_config_mode_set(hw);
532 + break;
533 + }
534 +}
535 +
536 +static int ltq_spi_setup_transfer(struct spi_device *spi,
537 + struct spi_transfer *t)
538 +{
539 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
540 + u8 bits_per_word = spi->bits_per_word;
541 +
542 + hw->curr_transfer = t;
543 +
544 + if (t && t->bits_per_word)
545 + bits_per_word = t->bits_per_word;
546 +
547 + if (bits_per_word > 32)
548 + return -EINVAL;
549 +
550 + ltq_spi_config_mode_set(hw);
551 +
552 + return 0;
553 +}
554 +
555 +static int ltq_spi_setup(struct spi_device *spi)
556 +{
557 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
558 + u32 gpocon, fgpo;
559 +
560 + /* Set default word length to 8 if not set */
561 + if (!spi->bits_per_word)
562 + spi->bits_per_word = 8;
563 +
564 + if (spi->bits_per_word > 32)
565 + return -EINVAL;
566 +
567 + /*
568 + * Up to six GPIOs can be connected to the SPI module
569 + * via GPIO alternate function to control the chip select lines.
570 + */
571 + gpocon = (1 << (spi->chip_select +
572 + LTQ_SPI_GPOCON_ISCSBN_SHIFT));
573 +
574 + if (spi->mode & SPI_CS_HIGH)
575 + gpocon |= (1 << spi->chip_select);
576 +
577 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
578 +
579 + ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
580 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
581 +
582 + return 0;
583 +}
584 +
585 +static void ltq_spi_cleanup(struct spi_device *spi)
586 +{
587 +
588 +}
589 +
590 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
591 +{
592 + u32 fstat, data;
593 + u16 fifo_space;
594 +
595 + /* Determine how much FIFOs are free for TX data */
596 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
597 + fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
598 + LTQ_SPI_FSTAT_TXFFL_MASK);
599 +
600 + if (!fifo_space)
601 + return;
602 +
603 + while (hw->tx_cnt < hw->len && fifo_space) {
604 + data = hw->get_tx(hw);
605 + ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
606 + fifo_space--;
607 + }
608 +}
609 +
610 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
611 +{
612 + u32 fstat, data, *rx32;
613 + u16 fifo_fill;
614 + u8 rxbv, shift, *rx8;
615 +
616 + /* Determine how much FIFOs are filled with RX data */
617 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
618 + fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
619 + & LTQ_SPI_FSTAT_RXFFL_MASK);
620 +
621 + if (!fifo_fill)
622 + return;
623 +
624 + /*
625 + * The 32 bit FIFO is always used completely independent from the
626 + * bits_per_word value. Thus four bytes have to be read at once
627 + * per FIFO.
628 + */
629 + rx32 = (u32 *) hw->rx;
630 + while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
631 + *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
632 + hw->rx_cnt += 4;
633 + hw->rx += 4;
634 + fifo_fill--;
635 + }
636 +
637 + /*
638 + * If there are remaining bytes, read byte count from STAT.RXBV
639 + * register and read the data byte-wise.
640 + */
641 + while (fifo_fill && hw->rx_cnt < hw->len) {
642 + rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
643 + LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
644 + data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
645 +
646 + shift = (rxbv - 1) * 8;
647 + rx8 = hw->rx;
648 +
649 + while (rxbv) {
650 + *rx8++ = (data >> shift) & 0xFF;
651 + rxbv--;
652 + shift -= 8;
653 + hw->rx_cnt++;
654 + hw->rx++;
655 + }
656 +
657 + fifo_fill--;
658 + }
659 +}
660 +
661 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
662 +{
663 + u32 rxreq, rxreq_max, rxtodo;
664 +
665 + rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
666 +
667 + /*
668 + * In RX-only mode the serial clock is activated only after writing
669 + * the expected amount of RX bytes into RXREQ register.
670 + * To avoid receive overflows at high clocks it is better to request
671 + * only the amount of bytes that fits into all FIFOs. This value
672 + * depends on the FIFO size implemented in hardware.
673 + */
674 + rxreq = hw->len - hw->rx_cnt;
675 + rxreq_max = hw->rxfs << 2;
676 + rxreq = min(rxreq_max, rxreq);
677 +
678 + if (!rxtodo && rxreq)
679 + ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
680 +}
681 +
682 +static inline void ltq_spi_complete(struct ltq_spi *hw)
683 +{
684 + complete(&hw->done);
685 +}
686 +
687 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
688 +{
689 + struct ltq_spi *hw = data;
690 + unsigned long flags;
691 + int completed = 0;
692 +
693 + spin_lock_irqsave(&hw->lock, flags);
694 +
695 + if (hw->tx_cnt < hw->len)
696 + ltq_spi_txfifo_write(hw);
697 +
698 + if (hw->tx_cnt == hw->len)
699 + completed = 1;
700 +
701 + spin_unlock_irqrestore(&hw->lock, flags);
702 +
703 + if (completed)
704 + ltq_spi_complete(hw);
705 +
706 + return IRQ_HANDLED;
707 +}
708 +
709 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
710 +{
711 + struct ltq_spi *hw = data;
712 + unsigned long flags;
713 + int completed = 0;
714 +
715 + spin_lock_irqsave(&hw->lock, flags);
716 +
717 + if (hw->rx_cnt < hw->len) {
718 + ltq_spi_rxfifo_read(hw);
719 +
720 + if (hw->tx && hw->tx_cnt < hw->len)
721 + ltq_spi_txfifo_write(hw);
722 + }
723 +
724 + if (hw->rx_cnt == hw->len)
725 + completed = 1;
726 + else if (!hw->tx)
727 + ltq_spi_rxreq_set(hw);
728 +
729 + spin_unlock_irqrestore(&hw->lock, flags);
730 +
731 + if (completed)
732 + ltq_spi_complete(hw);
733 +
734 + return IRQ_HANDLED;
735 +}
736 +
737 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
738 +{
739 + struct ltq_spi *hw = data;
740 + unsigned long flags;
741 +
742 + spin_lock_irqsave(&hw->lock, flags);
743 +
744 + /* Disable all interrupts */
745 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
746 +
747 + /* Clear all error flags */
748 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
749 +
750 + /* Flush FIFOs */
751 + ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
752 + ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
753 +
754 + hw->status = -EIO;
755 + spin_unlock_irqrestore(&hw->lock, flags);
756 +
757 + ltq_spi_complete(hw);
758 +
759 + return IRQ_HANDLED;
760 +}
761 +
762 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
763 +{
764 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
765 + u32 irq_flags = 0;
766 +
767 + hw->tx = t->tx_buf;
768 + hw->rx = t->rx_buf;
769 + hw->len = t->len;
770 + hw->tx_cnt = 0;
771 + hw->rx_cnt = 0;
772 + hw->status = 0;
773 + init_completion(&hw->done);
774 +
775 + ltq_spi_xmit_set(hw, t);
776 +
777 + /* Enable error interrupts */
778 + ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
779 +
780 + if (hw->tx) {
781 + /* Initially fill TX FIFO with as much data as possible */
782 + ltq_spi_txfifo_write(hw);
783 + irq_flags |= LTQ_SPI_IRNEN_T;
784 +
785 + /* Always enable RX interrupt in Full Duplex mode */
786 + if (hw->rx)
787 + irq_flags |= LTQ_SPI_IRNEN_R;
788 + } else if (hw->rx) {
789 + /* Start RX clock */
790 + ltq_spi_rxreq_set(hw);
791 +
792 + /* Enable RX interrupt to receive data from RX FIFOs */
793 + irq_flags |= LTQ_SPI_IRNEN_R;
794 + }
795 +
796 + /* Enable TX or RX interrupts */
797 + ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
798 + wait_for_completion_interruptible(&hw->done);
799 +
800 + /* Disable all interrupts */
801 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
802 +
803 + /*
804 + * Return length of current transfer for bitbang utility code if
805 + * no errors occured during transmission.
806 + */
807 + if (!hw->status)
808 + hw->status = hw->len;
809 +
810 + return hw->status;
811 +}
812 +
813 +static const struct ltq_spi_irq_map {
814 + char *name;
815 + irq_handler_t handler;
816 +} ltq_spi_irqs[] = {
817 + { "spi_rx", ltq_spi_rx_irq },
818 + { "spi_tx", ltq_spi_tx_irq },
819 + { "spi_err", ltq_spi_err_irq },
820 +};
821 +
822 +static int ltq_spi_probe(struct platform_device *pdev)
823 +{
824 + struct resource irqres[3];
825 + struct spi_master *master;
826 + struct resource *r;
827 + struct ltq_spi *hw;
828 + int ret, i;
829 + u32 data, id;
830 +
831 + if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 3) != 3) {
832 + dev_err(&pdev->dev, "IRQ settings missing in device tree\n");
833 + return -EINVAL;
834 + }
835 +
836 + master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
837 + if (!master) {
838 + dev_err(&pdev->dev, "spi_alloc_master\n");
839 + ret = -ENOMEM;
840 + goto err;
841 + }
842 +
843 + hw = spi_master_get_devdata(master);
844 +
845 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
846 + if (r == NULL) {
847 + dev_err(&pdev->dev, "platform_get_resource\n");
848 + ret = -ENOENT;
849 + goto err_master;
850 + }
851 +
852 + r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
853 + pdev->name);
854 + if (!r) {
855 + dev_err(&pdev->dev, "failed to request memory region\n");
856 + ret = -ENXIO;
857 + goto err_master;
858 + }
859 +
860 + hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
861 + if (!hw->base) {
862 + dev_err(&pdev->dev, "failed to remap memory region\n");
863 + ret = -ENXIO;
864 + goto err_master;
865 + }
866 +
867 + memset(hw->irq, 0, sizeof(hw->irq));
868 + for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
869 + hw->irq[i] = irqres[i].start;
870 + ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
871 + 0, ltq_spi_irqs[i].name, hw);
872 + if (ret) {
873 + dev_err(&pdev->dev, "failed to request %s irq (%d)\n",
874 + ltq_spi_irqs[i].name, hw->irq[i]);
875 + goto err_irq;
876 + }
877 + }
878 +
879 + hw->fpiclk = clk_get_fpi();
880 + if (IS_ERR(hw->fpiclk)) {
881 + dev_err(&pdev->dev, "failed to get fpi clock\n");
882 + ret = PTR_ERR(hw->fpiclk);
883 + goto err_clk;
884 + }
885 +
886 + hw->spiclk = clk_get(&pdev->dev, NULL);
887 + if (IS_ERR(hw->spiclk)) {
888 + dev_err(&pdev->dev, "failed to get spi clock gate\n");
889 + ret = PTR_ERR(hw->spiclk);
890 + goto err_clk;
891 + }
892 +
893 + hw->bitbang.master = spi_master_get(master);
894 + hw->bitbang.chipselect = ltq_spi_chipselect;
895 + hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
896 + hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
897 +
898 + if (of_machine_is_compatible("lantiq,ase"))
899 + master->num_chipselect = 3;
900 + else
901 + master->num_chipselect = 6;
902 + master->bus_num = pdev->id;
903 + master->setup = ltq_spi_setup;
904 + master->cleanup = ltq_spi_cleanup;
905 + master->dev.of_node = pdev->dev.of_node;
906 +
907 + hw->dev = &pdev->dev;
908 + init_completion(&hw->done);
909 + spin_lock_init(&hw->lock);
910 +
911 + ltq_spi_hw_enable(hw);
912 +
913 + /* Read module capabilities */
914 + id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
915 + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
916 + hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
917 + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
918 +
919 + ltq_spi_config_mode_set(hw);
920 +
921 + /* Enable error checking, disable TX/RX, set idle value high */
922 + data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
923 + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
924 + LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
925 + ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
926 +
927 + /* Enable master mode and clear error flags */
928 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
929 + LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
930 +
931 + /* Reset GPIO/CS registers */
932 + ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
933 + ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
934 +
935 + /* Enable and flush FIFOs */
936 + ltq_spi_reset_fifos(hw);
937 +
938 + ret = spi_bitbang_start(&hw->bitbang);
939 + if (ret) {
940 + dev_err(&pdev->dev, "spi_bitbang_start failed\n");
941 + goto err_bitbang;
942 + }
943 +
944 + platform_set_drvdata(pdev, hw);
945 +
946 + pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
947 + id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
948 +
949 + return 0;
950 +
951 +err_bitbang:
952 + ltq_spi_hw_disable(hw);
953 +
954 +err_clk:
955 + if (hw->fpiclk)
956 + clk_put(hw->fpiclk);
957 + if (hw->spiclk)
958 + clk_put(hw->spiclk);
959 +
960 +err_irq:
961 + clk_put(hw->fpiclk);
962 +
963 + for (; i > 0; i--)
964 + free_irq(hw->irq[i], hw);
965 +
966 +err_master:
967 + spi_master_put(master);
968 +
969 +err:
970 + return ret;
971 +}
972 +
973 +static int ltq_spi_remove(struct platform_device *pdev)
974 +{
975 + struct ltq_spi *hw = platform_get_drvdata(pdev);
976 + int i;
977 +
978 + spi_bitbang_stop(&hw->bitbang);
979 +
980 + platform_set_drvdata(pdev, NULL);
981 +
982 + ltq_spi_config_mode_set(hw);
983 + ltq_spi_hw_disable(hw);
984 +
985 + for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
986 + if (0 < hw->irq[i])
987 + free_irq(hw->irq[i], hw);
988 +
989 + if (hw->fpiclk)
990 + clk_put(hw->fpiclk);
991 + if (hw->spiclk)
992 + clk_put(hw->spiclk);
993 +
994 + spi_master_put(hw->bitbang.master);
995 +
996 + return 0;
997 +}
998 +
999 +static const struct of_device_id ltq_spi_match[] = {
1000 + { .compatible = "lantiq,spi-xway" },
1001 + {},
1002 +};
1003 +MODULE_DEVICE_TABLE(of, ltq_spi_match);
1004 +
1005 +static struct platform_driver ltq_spi_driver = {
1006 + .probe = ltq_spi_probe,
1007 + .remove = ltq_spi_remove,
1008 + .driver = {
1009 + .name = "spi-xway",
1010 + .owner = THIS_MODULE,
1011 + .of_match_table = ltq_spi_match,
1012 + },
1013 +};
1014 +
1015 +module_platform_driver(ltq_spi_driver);
1016 +
1017 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1018 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1019 +MODULE_LICENSE("GPL");
1020 +MODULE_ALIAS("platform:spi-xway");