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bump kernel to 3.2.12
[openwrt/openwrt.git] / target / linux / lantiq / patches-3.2 / 0005-MIPS-lantiq-reorganize-xway-code.patch
1 From cf7086d4c2f7caeccd019c0a57bf1566c72c13ee Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 10 Aug 2011 14:57:04 +0200
4 Subject: [PATCH 05/70] MIPS: lantiq: reorganize xway code
5
6 Inside the folder arch/mips/lantiq/xway, there were alot of small files with
7 lots of duplicated code. This patch adds a wrapper function for inserting and
8 requesting resources and unifies the small files into one bigger file.
9
10 This patch makes the xway code consistent with the falcon support added later
11 in this series.
12
13 Signed-off-by: John Crispin <blogic@openwrt.org>
14 ---
15 arch/mips/include/asm/mach-lantiq/lantiq.h | 14 +---
16 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 14 ++++
17 arch/mips/lantiq/clk.c | 25 +------
18 arch/mips/lantiq/devices.c | 30 ++------
19 arch/mips/lantiq/devices.h | 4 +
20 arch/mips/lantiq/prom.c | 51 +++++++++++--
21 arch/mips/lantiq/prom.h | 4 +
22 arch/mips/lantiq/xway/Makefile | 6 +-
23 arch/mips/lantiq/xway/devices.c | 42 ++---------
24 arch/mips/lantiq/xway/dma.c | 21 +----
25 arch/mips/lantiq/xway/ebu.c | 52 -------------
26 arch/mips/lantiq/xway/pmu.c | 69 -----------------
27 arch/mips/lantiq/xway/prom-ase.c | 9 ++
28 arch/mips/lantiq/xway/prom-xway.c | 10 +++
29 arch/mips/lantiq/xway/reset.c | 21 +----
30 arch/mips/lantiq/xway/setup-ase.c | 19 -----
31 arch/mips/lantiq/xway/setup-xway.c | 20 -----
32 arch/mips/lantiq/xway/sysctrl.c | 78 ++++++++++++++++++++
33 drivers/watchdog/lantiq_wdt.c | 2 +-
34 19 files changed, 199 insertions(+), 292 deletions(-)
35 delete mode 100644 arch/mips/lantiq/xway/ebu.c
36 delete mode 100644 arch/mips/lantiq/xway/pmu.c
37 delete mode 100644 arch/mips/lantiq/xway/setup-ase.c
38 delete mode 100644 arch/mips/lantiq/xway/setup-xway.c
39 create mode 100644 arch/mips/lantiq/xway/sysctrl.c
40
41 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
42 index ce2f029..66d7300 100644
43 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
44 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
45 @@ -9,6 +9,7 @@
46 #define _LANTIQ_H__
47
48 #include <linux/irq.h>
49 +#include <linux/ioport.h>
50
51 /* generic reg access functions */
52 #define ltq_r32(reg) __raw_readl(reg)
53 @@ -18,15 +19,6 @@
54 #define ltq_r8(reg) __raw_readb(reg)
55 #define ltq_w8(val, reg) __raw_writeb(val, reg)
56
57 -/* register access macros for EBU and CGU */
58 -#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
59 -#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
60 -#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
61 -#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
62 -
63 -extern __iomem void *ltq_ebu_membase;
64 -extern __iomem void *ltq_cgu_membase;
65 -
66 extern unsigned int ltq_get_cpu_ver(void);
67 extern unsigned int ltq_get_soc_type(void);
68
69 @@ -51,7 +43,9 @@ extern void ltq_enable_irq(struct irq_data *data);
70
71 /* find out what caused the last cpu reset */
72 extern int ltq_reset_cause(void);
73 -#define LTQ_RST_CAUSE_WDTRST 0x20
74 +
75 +/* helper for requesting and remapping resources */
76 +extern void __iomem *ltq_remap_resource(struct resource *res);
77
78 #define IOPORT_RESOURCE_START 0x10000000
79 #define IOPORT_RESOURCE_END 0xffffffff
80 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
81 index 8a3c6be..9b7ee366 100644
82 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
83 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
84 @@ -61,6 +61,8 @@
85 #define LTQ_CGU_BASE_ADDR 0x1F103000
86 #define LTQ_CGU_SIZE 0x1000
87
88 +#define CGU_EPHY 0x10
89 +
90 /* ICU - interrupt control unit */
91 #define LTQ_ICU_BASE_ADDR 0x1F880200
92 #define LTQ_ICU_SIZE 0x100
93 @@ -97,6 +99,8 @@
94 #define LTQ_WDT_BASE_ADDR 0x1F8803F0
95 #define LTQ_WDT_SIZE 0x10
96
97 +#define LTQ_RST_CAUSE_WDTRST 0x20
98 +
99 /* STP - serial to parallel conversion unit */
100 #define LTQ_STP_BASE_ADDR 0x1E100BB0
101 #define LTQ_STP_SIZE 0x40
102 @@ -121,11 +125,21 @@
103 #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
104 #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
105
106 +/* register access macros for EBU and CGU */
107 +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
108 +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
109 +#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
110 +#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
111 +
112 +extern __iomem void *ltq_ebu_membase;
113 +extern __iomem void *ltq_cgu_membase;
114 +
115 /* request a non-gpio and set the PIO config */
116 extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
117 unsigned int alt1, unsigned int dir, const char *name);
118 extern void ltq_pmu_enable(unsigned int module);
119 extern void ltq_pmu_disable(unsigned int module);
120 +extern void ltq_cgu_enable(unsigned int clk);
121
122 static inline int ltq_is_ar9(void)
123 {
124 diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
125 index 77ed70f..39eef7f 100644
126 --- a/arch/mips/lantiq/clk.c
127 +++ b/arch/mips/lantiq/clk.c
128 @@ -22,6 +22,7 @@
129 #include <lantiq_soc.h>
130
131 #include "clk.h"
132 +#include "prom.h"
133
134 struct clk {
135 const char *name;
136 @@ -46,16 +47,6 @@ static struct clk cpu_clk_generic[] = {
137 },
138 };
139
140 -static struct resource ltq_cgu_resource = {
141 - .name = "cgu",
142 - .start = LTQ_CGU_BASE_ADDR,
143 - .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1,
144 - .flags = IORESOURCE_MEM,
145 -};
146 -
147 -/* remapped clock register range */
148 -void __iomem *ltq_cgu_membase;
149 -
150 void clk_init(void)
151 {
152 cpu_clk = cpu_clk_generic;
153 @@ -133,21 +124,11 @@ void __init plat_time_init(void)
154 {
155 struct clk *clk;
156
157 - if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
158 - panic("Failed to insert cgu memory\n");
159 -
160 - if (request_mem_region(ltq_cgu_resource.start,
161 - resource_size(&ltq_cgu_resource), "cgu") < 0)
162 - panic("Failed to request cgu memory\n");
163 + ltq_soc_init();
164
165 - ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
166 - resource_size(&ltq_cgu_resource));
167 - if (!ltq_cgu_membase) {
168 - pr_err("Failed to remap cgu memory\n");
169 - unreachable();
170 - }
171 clk = clk_get(0, "cpu");
172 mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
173 write_c0_compare(read_c0_count());
174 + pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
175 clk_put(clk);
176 }
177 diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c
178 index de1cb2b..7193d78 100644
179 --- a/arch/mips/lantiq/devices.c
180 +++ b/arch/mips/lantiq/devices.c
181 @@ -27,12 +27,8 @@
182 #include "devices.h"
183
184 /* nor flash */
185 -static struct resource ltq_nor_resource = {
186 - .name = "nor",
187 - .start = LTQ_FLASH_START,
188 - .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1,
189 - .flags = IORESOURCE_MEM,
190 -};
191 +static struct resource ltq_nor_resource =
192 + MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX);
193
194 static struct platform_device ltq_nor = {
195 .name = "ltq_nor",
196 @@ -47,12 +43,8 @@ void __init ltq_register_nor(struct physmap_flash_data *data)
197 }
198
199 /* watchdog */
200 -static struct resource ltq_wdt_resource = {
201 - .name = "watchdog",
202 - .start = LTQ_WDT_BASE_ADDR,
203 - .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1,
204 - .flags = IORESOURCE_MEM,
205 -};
206 +static struct resource ltq_wdt_resource =
207 + MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE);
208
209 void __init ltq_register_wdt(void)
210 {
211 @@ -61,24 +53,14 @@ void __init ltq_register_wdt(void)
212
213 /* asc ports */
214 static struct resource ltq_asc0_resources[] = {
215 - {
216 - .name = "asc0",
217 - .start = LTQ_ASC0_BASE_ADDR,
218 - .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1,
219 - .flags = IORESOURCE_MEM,
220 - },
221 + MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE),
222 IRQ_RES(tx, LTQ_ASC_TIR(0)),
223 IRQ_RES(rx, LTQ_ASC_RIR(0)),
224 IRQ_RES(err, LTQ_ASC_EIR(0)),
225 };
226
227 static struct resource ltq_asc1_resources[] = {
228 - {
229 - .name = "asc1",
230 - .start = LTQ_ASC1_BASE_ADDR,
231 - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
232 - .flags = IORESOURCE_MEM,
233 - },
234 + MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
235 IRQ_RES(tx, LTQ_ASC_TIR(1)),
236 IRQ_RES(rx, LTQ_ASC_RIR(1)),
237 IRQ_RES(err, LTQ_ASC_EIR(1)),
238 diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h
239 index 2947bb1..a03c23f 100644
240 --- a/arch/mips/lantiq/devices.h
241 +++ b/arch/mips/lantiq/devices.h
242 @@ -14,6 +14,10 @@
243
244 #define IRQ_RES(resname, irq) \
245 {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ}
246 +#define MEM_RES(resname, adr_start, adr_size) \
247 + { .name = resname, .flags = IORESOURCE_MEM, \
248 + .start = ((adr_start) & ~KSEG1), \
249 + .end = ((adr_start + adr_size - 1) & ~KSEG1) }
250
251 extern void ltq_register_nor(struct physmap_flash_data *data);
252 extern void ltq_register_wdt(void);
253 diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
254 index e34fcfd..e3b1e25 100644
255 --- a/arch/mips/lantiq/prom.c
256 +++ b/arch/mips/lantiq/prom.c
257 @@ -16,6 +16,10 @@
258 #include "prom.h"
259 #include "clk.h"
260
261 +/* access to the ebu needs to be locked between different drivers */
262 +DEFINE_SPINLOCK(ebu_lock);
263 +EXPORT_SYMBOL_GPL(ebu_lock);
264 +
265 static struct ltq_soc_info soc_info;
266
267 unsigned int ltq_get_cpu_ver(void)
268 @@ -55,16 +59,51 @@ static void __init prom_init_cmdline(void)
269 }
270 }
271
272 -void __init prom_init(void)
273 +void __iomem *ltq_remap_resource(struct resource *res)
274 {
275 - struct clk *clk;
276 + __iomem void *ret = NULL;
277 + struct resource *lookup = lookup_resource(&iomem_resource, res->start);
278 +
279 + if (lookup && strcmp(lookup->name, res->name)) {
280 + pr_err("conflicting memory range %s\n", res->name);
281 + return NULL;
282 + }
283 + if (!lookup) {
284 + if (insert_resource(&iomem_resource, res) < 0) {
285 + pr_err("Failed to insert %s memory\n", res->name);
286 + return NULL;
287 + }
288 + }
289 + if (request_mem_region(res->start,
290 + resource_size(res), res->name) < 0) {
291 + pr_err("Failed to request %s memory\n", res->name);
292 + goto err_res;
293 + }
294
295 + ret = ioremap_nocache(res->start, resource_size(res));
296 + if (!ret)
297 + goto err_mem;
298 +
299 + pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n",
300 + res->start, res->end, res->name);
301 + return ret;
302 +
303 +err_mem:
304 + panic("Failed to remap %s memory\n", res->name);
305 + release_mem_region(res->start, resource_size(res));
306 +
307 +err_res:
308 + release_resource(res);
309 + return NULL;
310 +}
311 +EXPORT_SYMBOL(ltq_remap_resource);
312 +
313 +void __init prom_init(void)
314 +{
315 ltq_soc_detect(&soc_info);
316 clk_init();
317 - clk = clk_get(0, "cpu");
318 - snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d",
319 - soc_info.name, soc_info.rev);
320 - clk_put(clk);
321 + snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
322 + soc_info.name, soc_info.rev_type);
323 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
324 pr_info("SoC: %s\n", soc_info.sys_type);
325 prom_init_cmdline();
326 diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h
327 index b4229d9..51dba1b 100644
328 --- a/arch/mips/lantiq/prom.h
329 +++ b/arch/mips/lantiq/prom.h
330 @@ -9,17 +9,21 @@
331 #ifndef _LTQ_PROM_H__
332 #define _LTQ_PROM_H__
333
334 +#define LTQ_SYS_REV_LEN 0x10
335 #define LTQ_SYS_TYPE_LEN 0x100
336
337 struct ltq_soc_info {
338 unsigned char *name;
339 unsigned int rev;
340 + unsigned char rev_type[LTQ_SYS_REV_LEN];
341 + unsigned int srev;
342 unsigned int partnum;
343 unsigned int type;
344 unsigned char sys_type[LTQ_SYS_TYPE_LEN];
345 };
346
347 extern void ltq_soc_detect(struct ltq_soc_info *i);
348 +extern void ltq_soc_init(void);
349 extern void ltq_soc_setup(void);
350
351 #endif
352 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
353 index c517f2e..6678402 100644
354 --- a/arch/mips/lantiq/xway/Makefile
355 +++ b/arch/mips/lantiq/xway/Makefile
356 @@ -1,7 +1,7 @@
357 -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
358 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
359
360 -obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
361 -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
362 +obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
363 +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
364
365 obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
366 obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
367 diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
368 index d614aa7..f97e565 100644
369 --- a/arch/mips/lantiq/xway/devices.c
370 +++ b/arch/mips/lantiq/xway/devices.c
371 @@ -31,22 +31,9 @@
372
373 /* gpio */
374 static struct resource ltq_gpio_resource[] = {
375 - {
376 - .name = "gpio0",
377 - .start = LTQ_GPIO0_BASE_ADDR,
378 - .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1,
379 - .flags = IORESOURCE_MEM,
380 - }, {
381 - .name = "gpio1",
382 - .start = LTQ_GPIO1_BASE_ADDR,
383 - .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1,
384 - .flags = IORESOURCE_MEM,
385 - }, {
386 - .name = "gpio2",
387 - .start = LTQ_GPIO2_BASE_ADDR,
388 - .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1,
389 - .flags = IORESOURCE_MEM,
390 - }
391 + MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
392 + MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
393 + MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
394 };
395
396 void __init ltq_register_gpio(void)
397 @@ -64,12 +51,8 @@ void __init ltq_register_gpio(void)
398 }
399
400 /* serial to parallel conversion */
401 -static struct resource ltq_stp_resource = {
402 - .name = "stp",
403 - .start = LTQ_STP_BASE_ADDR,
404 - .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1,
405 - .flags = IORESOURCE_MEM,
406 -};
407 +static struct resource ltq_stp_resource =
408 + MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE);
409
410 void __init ltq_register_gpio_stp(void)
411 {
412 @@ -78,12 +61,7 @@ void __init ltq_register_gpio_stp(void)
413
414 /* asc ports - amazon se has its own serial mapping */
415 static struct resource ltq_ase_asc_resources[] = {
416 - {
417 - .name = "asc0",
418 - .start = LTQ_ASC1_BASE_ADDR,
419 - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
420 - .flags = IORESOURCE_MEM,
421 - },
422 + MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
423 IRQ_RES(tx, LTQ_ASC_ASE_TIR),
424 IRQ_RES(rx, LTQ_ASC_ASE_RIR),
425 IRQ_RES(err, LTQ_ASC_ASE_EIR),
426 @@ -96,12 +74,8 @@ void __init ltq_register_ase_asc(void)
427 }
428
429 /* ethernet */
430 -static struct resource ltq_etop_resources = {
431 - .name = "etop",
432 - .start = LTQ_ETOP_BASE_ADDR,
433 - .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
434 - .flags = IORESOURCE_MEM,
435 -};
436 +static struct resource ltq_etop_resources =
437 + MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE);
438
439 static struct platform_device ltq_etop = {
440 .name = "ltq_etop",
441 diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
442 index cbb6ae5..60cd11f 100644
443 --- a/arch/mips/lantiq/xway/dma.c
444 +++ b/arch/mips/lantiq/xway/dma.c
445 @@ -24,6 +24,8 @@
446 #include <lantiq_soc.h>
447 #include <xway_dma.h>
448
449 +#include "../devices.h"
450 +
451 #define LTQ_DMA_CTRL 0x10
452 #define LTQ_DMA_CPOLL 0x14
453 #define LTQ_DMA_CS 0x18
454 @@ -55,12 +57,8 @@
455 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
456 ltq_dma_membase + (z))
457
458 -static struct resource ltq_dma_resource = {
459 - .name = "dma",
460 - .start = LTQ_DMA_BASE_ADDR,
461 - .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
462 - .flags = IORESOURCE_MEM,
463 -};
464 +static struct resource ltq_dma_resource =
465 + MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE);
466
467 static void __iomem *ltq_dma_membase;
468
469 @@ -220,17 +218,8 @@ ltq_dma_init(void)
470 {
471 int i;
472
473 - /* insert and request the memory region */
474 - if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0)
475 - panic("Failed to insert dma memory\n");
476 -
477 - if (request_mem_region(ltq_dma_resource.start,
478 - resource_size(&ltq_dma_resource), "dma") < 0)
479 - panic("Failed to request dma memory\n");
480 -
481 /* remap dma register range */
482 - ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
483 - resource_size(&ltq_dma_resource));
484 + ltq_dma_membase = ltq_remap_resource(&ltq_dma_resource);
485 if (!ltq_dma_membase)
486 panic("Failed to remap dma memory\n");
487
488 diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
489 deleted file mode 100644
490 index 033b318..0000000
491 --- a/arch/mips/lantiq/xway/ebu.c
492 +++ /dev/null
493 @@ -1,52 +0,0 @@
494 -/*
495 - * This program is free software; you can redistribute it and/or modify it
496 - * under the terms of the GNU General Public License version 2 as published
497 - * by the Free Software Foundation.
498 - *
499 - * EBU - the external bus unit attaches PCI, NOR and NAND
500 - *
501 - * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
502 - */
503 -
504 -#include <linux/kernel.h>
505 -#include <linux/module.h>
506 -#include <linux/ioport.h>
507 -
508 -#include <lantiq_soc.h>
509 -
510 -/* all access to the ebu must be locked */
511 -DEFINE_SPINLOCK(ebu_lock);
512 -EXPORT_SYMBOL_GPL(ebu_lock);
513 -
514 -static struct resource ltq_ebu_resource = {
515 - .name = "ebu",
516 - .start = LTQ_EBU_BASE_ADDR,
517 - .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1,
518 - .flags = IORESOURCE_MEM,
519 -};
520 -
521 -/* remapped base addr of the clock unit and external bus unit */
522 -void __iomem *ltq_ebu_membase;
523 -
524 -static int __init lantiq_ebu_init(void)
525 -{
526 - /* insert and request the memory region */
527 - if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
528 - panic("Failed to insert ebu memory\n");
529 -
530 - if (request_mem_region(ltq_ebu_resource.start,
531 - resource_size(&ltq_ebu_resource), "ebu") < 0)
532 - panic("Failed to request ebu memory\n");
533 -
534 - /* remap ebu register range */
535 - ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
536 - resource_size(&ltq_ebu_resource));
537 - if (!ltq_ebu_membase)
538 - panic("Failed to remap ebu memory\n");
539 -
540 - /* make sure to unprotect the memory region where flash is located */
541 - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
542 - return 0;
543 -}
544 -
545 -postcore_initcall(lantiq_ebu_init);
546 diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
547 deleted file mode 100644
548 index 39f0d26..0000000
549 --- a/arch/mips/lantiq/xway/pmu.c
550 +++ /dev/null
551 @@ -1,69 +0,0 @@
552 -/*
553 - * This program is free software; you can redistribute it and/or modify it
554 - * under the terms of the GNU General Public License version 2 as published
555 - * by the Free Software Foundation.
556 - *
557 - * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
558 - */
559 -
560 -#include <linux/kernel.h>
561 -#include <linux/module.h>
562 -#include <linux/ioport.h>
563 -
564 -#include <lantiq_soc.h>
565 -
566 -/* PMU - the power management unit allows us to turn part of the core
567 - * on and off
568 - */
569 -
570 -/* the enable / disable registers */
571 -#define LTQ_PMU_PWDCR 0x1C
572 -#define LTQ_PMU_PWDSR 0x20
573 -
574 -#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
575 -#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
576 -
577 -static struct resource ltq_pmu_resource = {
578 - .name = "pmu",
579 - .start = LTQ_PMU_BASE_ADDR,
580 - .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1,
581 - .flags = IORESOURCE_MEM,
582 -};
583 -
584 -static void __iomem *ltq_pmu_membase;
585 -
586 -void ltq_pmu_enable(unsigned int module)
587 -{
588 - int err = 1000000;
589 -
590 - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
591 - do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
592 -
593 - if (!err)
594 - panic("activating PMU module failed!\n");
595 -}
596 -EXPORT_SYMBOL(ltq_pmu_enable);
597 -
598 -void ltq_pmu_disable(unsigned int module)
599 -{
600 - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
601 -}
602 -EXPORT_SYMBOL(ltq_pmu_disable);
603 -
604 -int __init ltq_pmu_init(void)
605 -{
606 - if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
607 - panic("Failed to insert pmu memory\n");
608 -
609 - if (request_mem_region(ltq_pmu_resource.start,
610 - resource_size(&ltq_pmu_resource), "pmu") < 0)
611 - panic("Failed to request pmu memory\n");
612 -
613 - ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
614 - resource_size(&ltq_pmu_resource));
615 - if (!ltq_pmu_membase)
616 - panic("Failed to remap pmu memory\n");
617 - return 0;
618 -}
619 -
620 -core_initcall(ltq_pmu_init);
621 diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
622 index ae4959a..3f86a3b 100644
623 --- a/arch/mips/lantiq/xway/prom-ase.c
624 +++ b/arch/mips/lantiq/xway/prom-ase.c
625 @@ -13,6 +13,7 @@
626
627 #include <lantiq_soc.h>
628
629 +#include "devices.h"
630 #include "../prom.h"
631
632 #define SOC_AMAZON_SE "Amazon_SE"
633 @@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
634 {
635 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
636 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
637 + sprintf(i->rev_type, "1.%d", i->rev);
638 switch (i->partnum) {
639 case SOC_ID_AMAZON_SE:
640 i->name = SOC_AMAZON_SE;
641 @@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
642 break;
643 }
644 }
645 +
646 +void __init ltq_soc_setup(void)
647 +{
648 + ltq_register_ase_asc();
649 + ltq_register_gpio();
650 + ltq_register_wdt();
651 +}
652 diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
653 index 2228133..d823a92 100644
654 --- a/arch/mips/lantiq/xway/prom-xway.c
655 +++ b/arch/mips/lantiq/xway/prom-xway.c
656 @@ -13,6 +13,7 @@
657
658 #include <lantiq_soc.h>
659
660 +#include "devices.h"
661 #include "../prom.h"
662
663 #define SOC_DANUBE "Danube"
664 @@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
665 {
666 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
667 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
668 + sprintf(i->rev_type, "1.%d", i->rev);
669 switch (i->partnum) {
670 case SOC_ID_DANUBE1:
671 case SOC_ID_DANUBE2:
672 @@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
673 break;
674 }
675 }
676 +
677 +void __init ltq_soc_setup(void)
678 +{
679 + ltq_register_asc(0);
680 + ltq_register_asc(1);
681 + ltq_register_gpio();
682 + ltq_register_wdt();
683 +}
684 diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
685 index 3d41f0b..ca2212a 100644
686 --- a/arch/mips/lantiq/xway/reset.c
687 +++ b/arch/mips/lantiq/xway/reset.c
688 @@ -15,6 +15,8 @@
689
690 #include <lantiq_soc.h>
691
692 +#include "../devices.h"
693 +
694 #define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y))
695 #define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x))
696
697 @@ -25,12 +27,8 @@
698 #define LTQ_RCU_RST_STAT 0x0014
699 #define LTQ_RCU_STAT_SHIFT 26
700
701 -static struct resource ltq_rcu_resource = {
702 - .name = "rcu",
703 - .start = LTQ_RCU_BASE_ADDR,
704 - .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1,
705 - .flags = IORESOURCE_MEM,
706 -};
707 +static struct resource ltq_rcu_resource =
708 + MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE);
709
710 /* remapped base addr of the reset control unit */
711 static void __iomem *ltq_rcu_membase;
712 @@ -67,17 +65,8 @@ static void ltq_machine_power_off(void)
713
714 static int __init mips_reboot_setup(void)
715 {
716 - /* insert and request the memory region */
717 - if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0)
718 - panic("Failed to insert rcu memory\n");
719 -
720 - if (request_mem_region(ltq_rcu_resource.start,
721 - resource_size(&ltq_rcu_resource), "rcu") < 0)
722 - panic("Failed to request rcu memory\n");
723 -
724 /* remap rcu register range */
725 - ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
726 - resource_size(&ltq_rcu_resource));
727 + ltq_rcu_membase = ltq_remap_resource(&ltq_rcu_resource);
728 if (!ltq_rcu_membase)
729 panic("Failed to remap rcu memory\n");
730
731 diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c
732 deleted file mode 100644
733 index f6f3267..0000000
734 --- a/arch/mips/lantiq/xway/setup-ase.c
735 +++ /dev/null
736 @@ -1,19 +0,0 @@
737 -/*
738 - * This program is free software; you can redistribute it and/or modify it
739 - * under the terms of the GNU General Public License version 2 as published
740 - * by the Free Software Foundation.
741 - *
742 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
743 - */
744 -
745 -#include <lantiq_soc.h>
746 -
747 -#include "../prom.h"
748 -#include "devices.h"
749 -
750 -void __init ltq_soc_setup(void)
751 -{
752 - ltq_register_ase_asc();
753 - ltq_register_gpio();
754 - ltq_register_wdt();
755 -}
756 diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c
757 deleted file mode 100644
758 index c292f64..0000000
759 --- a/arch/mips/lantiq/xway/setup-xway.c
760 +++ /dev/null
761 @@ -1,20 +0,0 @@
762 -/*
763 - * This program is free software; you can redistribute it and/or modify it
764 - * under the terms of the GNU General Public License version 2 as published
765 - * by the Free Software Foundation.
766 - *
767 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
768 - */
769 -
770 -#include <lantiq_soc.h>
771 -
772 -#include "../prom.h"
773 -#include "devices.h"
774 -
775 -void __init ltq_soc_setup(void)
776 -{
777 - ltq_register_asc(0);
778 - ltq_register_asc(1);
779 - ltq_register_gpio();
780 - ltq_register_wdt();
781 -}
782 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
783 new file mode 100644
784 index 0000000..8fd13a1
785 --- /dev/null
786 +++ b/arch/mips/lantiq/xway/sysctrl.c
787 @@ -0,0 +1,78 @@
788 +/*
789 + * This program is free software; you can redistribute it and/or modify it
790 + * under the terms of the GNU General Public License version 2 as published
791 + * by the Free Software Foundation.
792 + *
793 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
794 + */
795 +
796 +#include <linux/ioport.h>
797 +#include <linux/export.h>
798 +
799 +#include <lantiq_soc.h>
800 +
801 +#include "../devices.h"
802 +
803 +/* clock control register */
804 +#define LTQ_CGU_IFCCR 0x0018
805 +
806 +/* the enable / disable registers */
807 +#define LTQ_PMU_PWDCR 0x1C
808 +#define LTQ_PMU_PWDSR 0x20
809 +
810 +#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
811 +#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
812 +
813 +static struct resource ltq_cgu_resource =
814 + MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE);
815 +
816 +static struct resource ltq_pmu_resource =
817 + MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE);
818 +
819 +static struct resource ltq_ebu_resource =
820 + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
821 +
822 +void __iomem *ltq_cgu_membase;
823 +void __iomem *ltq_ebu_membase;
824 +static void __iomem *ltq_pmu_membase;
825 +
826 +void ltq_cgu_enable(unsigned int clk)
827 +{
828 + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR);
829 +}
830 +
831 +void ltq_pmu_enable(unsigned int module)
832 +{
833 + int err = 1000000;
834 +
835 + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
836 + do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
837 +
838 + if (!err)
839 + panic("activating PMU module failed!\n");
840 +}
841 +EXPORT_SYMBOL(ltq_pmu_enable);
842 +
843 +void ltq_pmu_disable(unsigned int module)
844 +{
845 + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
846 +}
847 +EXPORT_SYMBOL(ltq_pmu_disable);
848 +
849 +void __init ltq_soc_init(void)
850 +{
851 + ltq_pmu_membase = ltq_remap_resource(&ltq_pmu_resource);
852 + if (!ltq_pmu_membase)
853 + panic("Failed to remap pmu memory\n");
854 +
855 + ltq_cgu_membase = ltq_remap_resource(&ltq_cgu_resource);
856 + if (!ltq_cgu_membase)
857 + panic("Failed to remap cgu memory\n");
858 +
859 + ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_resource);
860 + if (!ltq_ebu_membase)
861 + panic("Failed to remap ebu memory\n");
862 +
863 + /* make sure to unprotect the memory region where flash is located */
864 + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
865 +}
866 diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
867 index 102aed0..179bf98 100644
868 --- a/drivers/watchdog/lantiq_wdt.c
869 +++ b/drivers/watchdog/lantiq_wdt.c
870 @@ -16,7 +16,7 @@
871 #include <linux/clk.h>
872 #include <linux/io.h>
873
874 -#include <lantiq.h>
875 +#include <lantiq_soc.h>
876
877 /* Section 3.4 of the datasheet
878 * The password sequence protects the WDT control register from unintended
879 --
880 1.7.7.1
881
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