target/linux/lantiq/patches-3.7/0109-GPIO-MIPS-add-gpio-driver-for-falcon-SoC.patch

   1 From d4911be1cc44c8d3ca72b03d5da13f792d4a02d2 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 23 Jun 2012 15:32:33 +0200
   4 Subject: [PATCH 109/123] GPIO: MIPS: add gpio driver for falcon SoC
   5
   6 Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
   7 up to 32 pads. The GPIO blocks have a per pin IRQs.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  11 Cc: linux-kernel@vger.kernel.org
  12 ---
  13  drivers/gpio/Kconfig       |    5 +
  14  drivers/gpio/Makefile      |    1 +
  15  drivers/gpio/gpio-falcon.c |  349 ++++++++++++++++++++++++++++++++++++++++++++
  16  3 files changed, 355 insertions(+)
  17  create mode 100644 drivers/gpio/gpio-falcon.c
  18
  19 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
  20 index 47150f5..0647e07 100644
  21 --- a/drivers/gpio/Kconfig
  22 +++ b/drivers/gpio/Kconfig
  23 @@ -114,6 +114,11 @@ config GPIO_EP93XX
  24         depends on ARCH_EP93XX
  25         select GPIO_GENERIC
  26
  27 +config GPIO_FALCON
  28 +       def_bool y
  29 +       depends on MIPS && SOC_FALCON
  30 +       select GPIO_GENERIC
  31 +
  32  config GPIO_MM_LANTIQ
  33         bool "Lantiq Memory mapped GPIOs"
  34         depends on LANTIQ && SOC_XWAY
  35 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
  36 index 9aeed67..2a9e4a2 100644
  37 --- a/drivers/gpio/Makefile
  38 +++ b/drivers/gpio/Makefile
  39 @@ -21,6 +21,7 @@ obj-$(CONFIG_GPIO_DA9052)     += gpio-da9052.o
  40  obj-$(CONFIG_ARCH_DAVINCI)     += gpio-davinci.o
  41  obj-$(CONFIG_GPIO_EM)          += gpio-em.o
  42  obj-$(CONFIG_GPIO_EP93XX)      += gpio-ep93xx.o
  43 +obj-$(CONFIG_GPIO_FALCON)      += gpio-falcon.o
  44  obj-$(CONFIG_GPIO_GE_FPGA)     += gpio-ge.o
  45  obj-$(CONFIG_GPIO_ICH)         += gpio-ich.o
  46  obj-$(CONFIG_GPIO_IT8761E)     += gpio-it8761e.o
  47 diff --git a/drivers/gpio/gpio-falcon.c b/drivers/gpio/gpio-falcon.c
  48 new file mode 100644
  49 index 0000000..ae8b55d
  50 --- /dev/null
  51 +++ b/drivers/gpio/gpio-falcon.c
  52 @@ -0,0 +1,349 @@
  53 +/*
  54 + *  This program is free software; you can redistribute it and/or modify it
  55 + *  under the terms of the GNU General Public License version 2 as published
  56 + *  by the Free Software Foundation.
  57 + *
  58 + *  Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
  59 + *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
  60 + */
  61 +
  62 +#include <linux/gpio.h>
  63 +#include <linux/interrupt.h>
  64 +#include <linux/slab.h>
  65 +#include <linux/export.h>
  66 +#include <linux/err.h>
  67 +#include <linux/module.h>
  68 +#include <linux/of.h>
  69 +#include <linux/of_irq.h>
  70 +#include <linux/pinctrl/pinctrl.h>
  71 +#include <linux/pinctrl/consumer.h>
  72 +#include <linux/platform_device.h>
  73 +
  74 +#include <lantiq_soc.h>
  75 +
  76 +/* Data Output Register */
  77 +#define GPIO_OUT            0x00000000
  78 +/* Data Input Register */
  79 +#define GPIO_IN             0x00000004
  80 +/* Direction Register */
  81 +#define GPIO_DIR            0x00000008
  82 +/* External Interrupt Control Register 0 */
  83 +#define GPIO_EXINTCR0       0x00000018
  84 +/* External Interrupt Control Register 1 */
  85 +#define GPIO_EXINTCR1       0x0000001C
  86 +/* IRN Capture Register */
  87 +#define GPIO_IRNCR          0x00000020
  88 +/* IRN Interrupt Configuration Register */
  89 +#define GPIO_IRNCFG            0x0000002C
  90 +/* IRN Interrupt Enable Set Register */
  91 +#define GPIO_IRNRNSET       0x00000030
  92 +/* IRN Interrupt Enable Clear Register */
  93 +#define GPIO_IRNENCLR       0x00000034
  94 +/* Output Set Register */
  95 +#define GPIO_OUTSET         0x00000040
  96 +/* Output Cler Register */
  97 +#define GPIO_OUTCLR         0x00000044
  98 +/* Direction Clear Register */
  99 +#define GPIO_DIRSET         0x00000048
 100 +/* Direction Set Register */
 101 +#define GPIO_DIRCLR         0x0000004C
 102 +
 103 +/* turn a gpio_chip into a falcon_gpio_port */
 104 +#define ctop(c)                container_of(c, struct falcon_gpio_port, gpio_chip)
 105 +/* turn a irq_data into a falcon_gpio_port */
 106 +#define itop(i)                ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
 107 +
 108 +#define port_r32(p, reg)       ltq_r32(p->port + reg)
 109 +#define port_w32(p, val, reg)  ltq_w32(val, p->port + reg)
 110 +#define port_w32_mask(p, clear, set, reg) \
 111 +               port_w32(p, (port_r32(p, reg) & ~(clear)) | (set), reg)
 112 +
 113 +#define MAX_PORTS              5
 114 +#define PINS_PER_PORT          32
 115 +
 116 +struct falcon_gpio_port {
 117 +       struct gpio_chip gpio_chip;
 118 +       void __iomem *port;
 119 +       unsigned int irq_base;
 120 +       unsigned int chained_irq;
 121 +       struct clk *clk;
 122 +       char name[6];
 123 +};
 124 +
 125 +static int falcon_gpio_direction_input(struct gpio_chip *chip,
 126 +                                       unsigned int offset)
 127 +{
 128 +       port_w32(ctop(chip), 1 << offset, GPIO_DIRCLR);
 129 +
 130 +       return 0;
 131 +}
 132 +
 133 +static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset,
 134 +                                       int value)
 135 +{
 136 +       if (value)
 137 +               port_w32(ctop(chip), 1 << offset, GPIO_OUTSET);
 138 +       else
 139 +               port_w32(ctop(chip), 1 << offset, GPIO_OUTCLR);
 140 +}
 141 +
 142 +static int falcon_gpio_direction_output(struct gpio_chip *chip,
 143 +                                       unsigned int offset, int value)
 144 +{
 145 +       falcon_gpio_set(chip, offset, value);
 146 +       port_w32(ctop(chip), 1 << offset, GPIO_DIRSET);
 147 +
 148 +       return 0;
 149 +}
 150 +
 151 +static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
 152 +{
 153 +       if ((port_r32(ctop(chip), GPIO_DIR) >> offset) & 1)
 154 +               return (port_r32(ctop(chip), GPIO_OUT) >> offset) & 1;
 155 +       else
 156 +               return (port_r32(ctop(chip), GPIO_IN) >> offset) & 1;
 157 +}
 158 +
 159 +static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
 160 +{
 161 +       int gpio = chip->base + offset;
 162 +
 163 +       return pinctrl_request_gpio(gpio);
 164 +}
 165 +
 166 +static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
 167 +{
 168 +       int gpio = chip->base + offset;
 169 +
 170 +       pinctrl_free_gpio(gpio);
 171 +}
 172 +
 173 +static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 174 +{
 175 +       return ctop(chip)->irq_base + offset;
 176 +}
 177 +
 178 +static void falcon_gpio_disable_irq(struct irq_data *d)
 179 +{
 180 +       unsigned int offset = d->irq - itop(d)->irq_base;
 181 +
 182 +       port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
 183 +}
 184 +
 185 +static void falcon_gpio_enable_irq(struct irq_data *d)
 186 +{
 187 +       unsigned int offset = d->irq - itop(d)->irq_base;
 188 +
 189 +       port_w32(itop(d), 1 << offset, GPIO_IRNRNSET);
 190 +}
 191 +
 192 +static void falcon_gpio_ack_irq(struct irq_data *d)
 193 +{
 194 +       unsigned int offset = d->irq - itop(d)->irq_base;
 195 +
 196 +       port_w32(itop(d), 1 << offset, GPIO_IRNCR);
 197 +}
 198 +
 199 +static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
 200 +{
 201 +       unsigned int offset = d->irq - itop(d)->irq_base;
 202 +
 203 +       port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
 204 +       port_w32(itop(d), 1 << offset, GPIO_IRNCR);
 205 +}
 206 +
 207 +static struct irq_chip falcon_gpio_irq_chip;
 208 +static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
 209 +{
 210 +       unsigned int offset = d->irq - itop(d)->irq_base;
 211 +       unsigned int mask = 1 << offset;
 212 +
 213 +       if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
 214 +               return 0;
 215 +
 216 +       if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
 217 +               /* level triggered */
 218 +               port_w32_mask(itop(d), 0, mask, GPIO_IRNCFG);
 219 +               irq_set_chip_and_handler_name(d->irq,
 220 +                       &falcon_gpio_irq_chip, handle_level_irq, "mux");
 221 +       } else {
 222 +               /* edge triggered */
 223 +               port_w32_mask(itop(d), mask, 0, GPIO_IRNCFG);
 224 +               irq_set_chip_and_handler_name(d->irq,
 225 +                       &falcon_gpio_irq_chip, handle_simple_irq, "mux");
 226 +       }
 227 +
 228 +       if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 229 +               port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
 230 +               port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR1);
 231 +       } else {
 232 +               if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
 233 +                       /* positive logic: rising edge, high level */
 234 +                       port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
 235 +               else
 236 +                       /* negative logic: falling edge, low level */
 237 +                       port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR0);
 238 +               port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR1);
 239 +       }
 240 +
 241 +       return gpio_direction_input(itop(d)->gpio_chip.base + offset);
 242 +}
 243 +
 244 +static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 245 +{
 246 +       struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
 247 +       unsigned long irncr;
 248 +       int offset;
 249 +
 250 +       /* acknowledge interrupt */
 251 +       irncr = port_r32(gpio_port, GPIO_IRNCR);
 252 +       port_w32(gpio_port, irncr, GPIO_IRNCR);
 253 +
 254 +       desc->irq_data.chip->irq_ack(&desc->irq_data);
 255 +
 256 +       for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
 257 +               generic_handle_irq(gpio_port->irq_base + offset);
 258 +}
 259 +
 260 +static int falcon_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 261 +                               irq_hw_number_t hw)
 262 +{
 263 +       struct falcon_gpio_port *port = d->host_data;
 264 +
 265 +       irq_set_chip_and_handler_name(irq, &falcon_gpio_irq_chip,
 266 +                       handle_simple_irq, "mux");
 267 +       irq_set_chip_data(irq, port);
 268 +
 269 +       /* set to negative logic (falling edge, low level) */
 270 +       port_w32_mask(port, 0, 1 << hw, GPIO_EXINTCR0);
 271 +       return 0;
 272 +}
 273 +
 274 +static struct irq_chip falcon_gpio_irq_chip = {
 275 +       .name = "gpio_irq_mux",
 276 +       .irq_mask = falcon_gpio_disable_irq,
 277 +       .irq_unmask = falcon_gpio_enable_irq,
 278 +       .irq_ack = falcon_gpio_ack_irq,
 279 +       .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
 280 +       .irq_set_type = falcon_gpio_irq_type,
 281 +};
 282 +
 283 +static const struct irq_domain_ops irq_domain_ops = {
 284 +       .xlate = irq_domain_xlate_onetwocell,
 285 +       .map = falcon_gpio_irq_map,
 286 +};
 287 +
 288 +static struct irqaction gpio_cascade = {
 289 +       .handler = no_action,
 290 +       .flags = IRQF_DISABLED,
 291 +       .name = "gpio_cascade",
 292 +};
 293 +
 294 +static int falcon_gpio_probe(struct platform_device *pdev)
 295 +{
 296 +       struct pinctrl_gpio_range *gpio_range;
 297 +       struct device_node *node = pdev->dev.of_node;
 298 +       const __be32 *bank = of_get_property(node, "lantiq,bank", NULL);
 299 +       struct falcon_gpio_port *gpio_port;
 300 +       struct resource *gpiores, irqres;
 301 +       int ret, size;
 302 +
 303 +       if (!bank || *bank >= MAX_PORTS)
 304 +               return -ENODEV;
 305 +
 306 +       size = pinctrl_falcon_get_range_size(*bank);
 307 +       if (size < 1) {
 308 +               dev_err(&pdev->dev, "pad not loaded for bank %d\n", *bank);
 309 +               return size;
 310 +       }
 311 +
 312 +       gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 313 +       if (!gpiores)
 314 +               return -ENODEV;
 315 +
 316 +       gpio_range = devm_kzalloc(&pdev->dev, sizeof(struct pinctrl_gpio_range),
 317 +                               GFP_KERNEL);
 318 +       if (!gpio_range)
 319 +               return -ENOMEM;
 320 +
 321 +       gpio_port = devm_kzalloc(&pdev->dev, sizeof(struct falcon_gpio_port),
 322 +                               GFP_KERNEL);
 323 +       if (!gpio_port)
 324 +               return -ENOMEM;
 325 +       snprintf(gpio_port->name, 6, "gpio%d", *bank);
 326 +       gpio_port->gpio_chip.label = gpio_port->name;
 327 +       gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
 328 +       gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
 329 +       gpio_port->gpio_chip.get = falcon_gpio_get;
 330 +       gpio_port->gpio_chip.set = falcon_gpio_set;
 331 +       gpio_port->gpio_chip.request = falcon_gpio_request;
 332 +       gpio_port->gpio_chip.free = falcon_gpio_free;
 333 +       gpio_port->gpio_chip.base = -1;
 334 +       gpio_port->gpio_chip.ngpio = size;
 335 +       gpio_port->gpio_chip.dev = &pdev->dev;
 336 +
 337 +       gpio_port->port = devm_request_and_ioremap(&pdev->dev, gpiores);
 338 +       if (!gpio_port->port) {
 339 +               dev_err(&pdev->dev, "Could not map io ranges\n");
 340 +               return -ENOMEM;
 341 +       }
 342 +
 343 +       gpio_port->clk = clk_get(&pdev->dev, NULL);
 344 +       if (IS_ERR(gpio_port->clk)) {
 345 +               dev_err(&pdev->dev, "Could not get clock\n");
 346 +               return PTR_ERR(gpio_port->clk);
 347 +       }
 348 +       clk_enable(gpio_port->clk);
 349 +
 350 +       if (of_irq_to_resource_table(node, &irqres, 1) == 1) {
 351 +               gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * *bank);
 352 +               gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
 353 +               gpio_port->chained_irq = irqres.start;
 354 +               irq_domain_add_legacy(node, size, gpio_port->irq_base, 0,
 355 +                                       &irq_domain_ops, gpio_port);
 356 +               setup_irq(irqres.start, &gpio_cascade);
 357 +               irq_set_handler_data(irqres.start, gpio_port);
 358 +               irq_set_chained_handler(irqres.start, falcon_gpio_irq_handler);
 359 +       }
 360 +
 361 +       ret = gpiochip_add(&gpio_port->gpio_chip);
 362 +       if (!ret)
 363 +               platform_set_drvdata(pdev, gpio_port);
 364 +
 365 +       gpio_range->name = "FALCON GPIO";
 366 +       gpio_range->id = *bank;
 367 +       gpio_range->base = gpio_port->gpio_chip.base;
 368 +       gpio_range->npins = gpio_port->gpio_chip.ngpio;
 369 +       gpio_range->gc = &gpio_port->gpio_chip;
 370 +       pinctrl_falcon_add_gpio_range(gpio_range);
 371 +
 372 +       return ret;
 373 +}
 374 +
 375 +static const struct of_device_id falcon_gpio_match[] = {
 376 +       { .compatible = "lantiq,gpio-falcon" },
 377 +       {},
 378 +};
 379 +MODULE_DEVICE_TABLE(of, falcon_gpio_match);
 380 +
 381 +static struct platform_driver falcon_gpio_driver = {
 382 +       .probe = falcon_gpio_probe,
 383 +       .driver = {
 384 +               .name = "gpio-falcon",
 385 +               .owner = THIS_MODULE,
 386 +               .of_match_table = falcon_gpio_match,
 387 +       },
 388 +};
 389 +
 390 +int __init falcon_gpio_init(void)
 391 +{
 392 +       int ret;
 393 +
 394 +       pr_info("FALC(tm) ON GPIO Driver, (C) 2012 Lantiq Deutschland Gmbh\n");
 395 +       ret = platform_driver_register(&falcon_gpio_driver);
 396 +       if (ret)
 397 +               pr_err("falcon_gpio: Error registering platform driver!");
 398 +       return ret;
 399 +}
 400 +
 401 +subsys_initcall(falcon_gpio_init);
 402 --
 403 1.7.10.4
 404