08e6b648111c80f469006c54f85189d14fa942cc
[openwrt/openwrt.git] / target / linux / lantiq / patches-4.1 / 0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
1 From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 7 Aug 2014 18:15:36 +0200
4 Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/net/phy/Kconfig | 5 +
9 drivers/net/phy/Makefile | 1 +
10 drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 237 insertions(+)
12 create mode 100644 drivers/net/phy/lantiq.c
13
14 --- a/drivers/net/phy/Kconfig
15 +++ b/drivers/net/phy/Kconfig
16 @@ -165,6 +165,11 @@ config RTL8306_PHY
17 tristate "Driver for Realtek RTL8306S switches"
18 select SWCONFIG
19
20 +config LANTIQ_PHY
21 + tristate "Driver for Lantiq PHYs"
22 + ---help---
23 + Supports the 11G and 22E PHYs.
24 +
25 config FIXED_PHY
26 tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
27 depends on PHYLIB
28 --- a/drivers/net/phy/Makefile
29 +++ b/drivers/net/phy/Makefile
30 @@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
31 obj-$(CONFIG_DP83640_PHY) += dp83640.o
32 obj-$(CONFIG_STE10XP) += ste10Xp.o
33 obj-$(CONFIG_MICREL_PHY) += micrel.o
34 +obj-$(CONFIG_LANTIQ_PHY) += lantiq.o
35 obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
36 obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
37 obj-$(CONFIG_AT803X_PHY) += at803x.o
38 --- /dev/null
39 +++ b/drivers/net/phy/lantiq.c
40 @@ -0,0 +1,231 @@
41 +/*
42 + * This program is free software; you can redistribute it and/or modify
43 + * it under the terms of the GNU General Public License as published by
44 + * the Free Software Foundation; either version 2 of the License, or
45 + * (at your option) any later version.
46 + *
47 + * This program is distributed in the hope that it will be useful,
48 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
49 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50 + * GNU General Public License for more details.
51 + *
52 + * You should have received a copy of the GNU General Public License
53 + * along with this program; if not, write to the Free Software
54 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
55 + *
56 + * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
57 + */
58 +
59 +#include <linux/module.h>
60 +#include <linux/phy.h>
61 +
62 +#define MII_MMDCTRL 0x0d
63 +#define MII_MMDDATA 0x0e
64 +
65 +#define MII_VR9_11G_IMASK 0x19 /* interrupt mask */
66 +#define MII_VR9_11G_ISTAT 0x1a /* interrupt status */
67 +
68 +#define INT_VR9_11G_WOL BIT(15) /* Wake-On-LAN */
69 +#define INT_VR9_11G_ANE BIT(11) /* Auto-Neg error */
70 +#define INT_VR9_11G_ANC BIT(10) /* Auto-Neg complete */
71 +#define INT_VR9_11G_ADSC BIT(5) /* Link auto-downspeed detect */
72 +#define INT_VR9_11G_DXMC BIT(2) /* Duplex mode change */
73 +#define INT_VR9_11G_LSPC BIT(1) /* Link speed change */
74 +#define INT_VR9_11G_LSTC BIT(0) /* Link state change */
75 +#define INT_VR9_11G_MASK (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
76 +
77 +#define ADVERTISED_MPD BIT(10) /* Multi-port device */
78 +
79 +#define MMD_DEVAD 0x1f
80 +#define MMD_ACTYPE_SHIFT 14
81 +#define MMD_ACTYPE_ADDRESS (0 << MMD_ACTYPE_SHIFT)
82 +#define MMD_ACTYPE_DATA (1 << MMD_ACTYPE_SHIFT)
83 +#define MMD_ACTYPE_DATA_PI (2 << MMD_ACTYPE_SHIFT)
84 +#define MMD_ACTYPE_DATA_PIWR (3 << MMD_ACTYPE_SHIFT)
85 +
86 +static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
87 + u16 regnum)
88 +{
89 + phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
90 + phy_write(phydev, MII_MMDDATA, regnum);
91 + phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
92 +
93 + return phy_read(phydev, MII_MMDDATA);
94 +}
95 +
96 +static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
97 + u16 regnum, u16 val)
98 +{
99 + phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
100 + phy_write(phydev, MII_MMDDATA, regnum);
101 + phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
102 + phy_write(phydev, MII_MMDDATA, val);
103 +
104 + return 0;
105 +}
106 +
107 +static int vr9_gphy_config_init(struct phy_device *phydev)
108 +{
109 + int err;
110 +
111 + dev_dbg(&phydev->dev, "%s\n", __func__);
112 +
113 + /* Mask all interrupts */
114 + err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
115 + if (err)
116 + return err;
117 +
118 + /* Clear all pending interrupts */
119 + phy_read(phydev, MII_VR9_11G_ISTAT);
120 +
121 + vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5);
122 + vr9_gphy_mmd_write(phydev, 0x1e1, 0x67);
123 + vr9_gphy_mmd_write(phydev, 0x1e2, 0x42);
124 + vr9_gphy_mmd_write(phydev, 0x1e3, 0x10);
125 + vr9_gphy_mmd_write(phydev, 0x1e4, 0x70);
126 + vr9_gphy_mmd_write(phydev, 0x1e5, 0x03);
127 + vr9_gphy_mmd_write(phydev, 0x1e6, 0x20);
128 + vr9_gphy_mmd_write(phydev, 0x1e7, 0x00);
129 + vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);
130 + vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);
131 +
132 + return 0;
133 +}
134 +
135 +static int vr9_gphy_config_aneg(struct phy_device *phydev)
136 +{
137 + int reg, err;
138 +
139 + /* Advertise as multi-port device */
140 + reg = phy_read(phydev, MII_CTRL1000);
141 + reg |= ADVERTISED_MPD;
142 + err = phy_write(phydev, MII_CTRL1000, reg);
143 + if (err)
144 + return err;
145 +
146 + return genphy_config_aneg(phydev);
147 +}
148 +
149 +static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
150 +{
151 + int reg;
152 +
153 + /*
154 + * Possible IRQ numbers:
155 + * - IM3_IRL18 for GPHY0
156 + * - IM3_IRL17 for GPHY1
157 + *
158 + * Due to a silicon bug IRQ lines are not really independent from
159 + * each other. Sometimes the two lines are driven at the same time
160 + * if only one GPHY core raises the interrupt.
161 + */
162 +
163 + reg = phy_read(phydev, MII_VR9_11G_ISTAT);
164 +
165 + return (reg < 0) ? reg : 0;
166 +}
167 +
168 +static int vr9_gphy_did_interrupt(struct phy_device *phydev)
169 +{
170 + int reg;
171 +
172 + reg = phy_read(phydev, MII_VR9_11G_ISTAT);
173 +
174 + return reg > 0;
175 +}
176 +
177 +static int vr9_gphy_config_intr(struct phy_device *phydev)
178 +{
179 + int err;
180 +
181 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
182 + err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
183 + else
184 + err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
185 +
186 + return err;
187 +}
188 +
189 +static struct phy_driver lantiq_phy[] = {
190 + {
191 + .phy_id = 0xd565a400,
192 + .phy_id_mask = 0xfffffff8,
193 + .name = "Lantiq XWAY PEF7071",
194 + .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
195 + .flags = 0, /*PHY_HAS_INTERRUPT,*/
196 + .config_init = vr9_gphy_config_init,
197 + .config_aneg = vr9_gphy_config_aneg,
198 + .read_status = genphy_read_status,
199 + .ack_interrupt = vr9_gphy_ack_interrupt,
200 + .did_interrupt = vr9_gphy_did_interrupt,
201 + .config_intr = vr9_gphy_config_intr,
202 + .driver = { .owner = THIS_MODULE },
203 + }, {
204 + .phy_id = 0x030260D0,
205 + .phy_id_mask = 0xfffffff0,
206 + .name = "Lantiq XWAY VR9 GPHY 11G v1.3",
207 + .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
208 + .flags = 0, /*PHY_HAS_INTERRUPT,*/
209 + .config_init = vr9_gphy_config_init,
210 + .config_aneg = vr9_gphy_config_aneg,
211 + .read_status = genphy_read_status,
212 + .ack_interrupt = vr9_gphy_ack_interrupt,
213 + .did_interrupt = vr9_gphy_did_interrupt,
214 + .config_intr = vr9_gphy_config_intr,
215 + .driver = { .owner = THIS_MODULE },
216 + }, {
217 + .phy_id = 0xd565a408,
218 + .phy_id_mask = 0xfffffff8,
219 + .name = "Lantiq XWAY VR9 GPHY 11G v1.4",
220 + .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
221 + .flags = 0, /*PHY_HAS_INTERRUPT,*/
222 + .config_init = vr9_gphy_config_init,
223 + .config_aneg = vr9_gphy_config_aneg,
224 + .read_status = genphy_read_status,
225 + .ack_interrupt = vr9_gphy_ack_interrupt,
226 + .did_interrupt = vr9_gphy_did_interrupt,
227 + .config_intr = vr9_gphy_config_intr,
228 + .driver = { .owner = THIS_MODULE },
229 + }, {
230 + .phy_id = 0xd565a418,
231 + .phy_id_mask = 0xfffffff8,
232 + .name = "Lantiq XWAY XRX PHY22F v1.4",
233 + .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
234 + .flags = 0, /*PHY_HAS_INTERRUPT,*/
235 + .config_init = vr9_gphy_config_init,
236 + .config_aneg = vr9_gphy_config_aneg,
237 + .read_status = genphy_read_status,
238 + .ack_interrupt = vr9_gphy_ack_interrupt,
239 + .did_interrupt = vr9_gphy_did_interrupt,
240 + .config_intr = vr9_gphy_config_intr,
241 + .driver = { .owner = THIS_MODULE },
242 + },
243 +};
244 +
245 +static int __init ltq_phy_init(void)
246 +{
247 + int i;
248 +
249 + for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) {
250 + int err = phy_driver_register(&lantiq_phy[i]);
251 + if (err)
252 + pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name);
253 + }
254 +
255 + return 0;
256 +}
257 +
258 +static void __exit ltq_phy_exit(void)
259 +{
260 + int i;
261 +
262 + for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++)
263 + phy_driver_unregister(&lantiq_phy[i]);
264 +}
265 +
266 +module_init(ltq_phy_init);
267 +module_exit(ltq_phy_exit);
268 +
269 +MODULE_DESCRIPTION("Lantiq PHY drivers");
270 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
271 +MODULE_LICENSE("GPL");