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lantiq: kernel 4.14: copy patches, config and dts files
[openwrt/openwrt.git] / target / linux / lantiq / patches-4.14 / 0004-MIPS-lantiq-add-atm-hack.patch
1 From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Aug 2012 10:27:25 +0200
4 Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
9 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
10 arch/mips/lantiq/irq.c | 2 +
11 arch/mips/mm/cache.c | 2 +
12 include/uapi/linux/atm.h | 6 +
13 net/atm/common.c | 6 +
14 net/atm/proc.c | 2 +-
15 7 files changed, 416 insertions(+), 1 deletion(-)
16 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
17 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
18
19 --- /dev/null
20 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
21 @@ -0,0 +1,196 @@
22 +/******************************************************************************
23 +**
24 +** FILE NAME : ifx_atm.h
25 +** PROJECT : UEIP
26 +** MODULES : ATM
27 +**
28 +** DATE : 17 Jun 2009
29 +** AUTHOR : Xu Liang
30 +** DESCRIPTION : Global ATM driver header file
31 +** COPYRIGHT : Copyright (c) 2006
32 +** Infineon Technologies AG
33 +** Am Campeon 1-12, 85579 Neubiberg, Germany
34 +**
35 +** This program is free software; you can redistribute it and/or modify
36 +** it under the terms of the GNU General Public License as published by
37 +** the Free Software Foundation; either version 2 of the License, or
38 +** (at your option) any later version.
39 +**
40 +** HISTORY
41 +** $Date $Author $Comment
42 +** 07 JUL 2009 Xu Liang Init Version
43 +*******************************************************************************/
44 +
45 +#ifndef IFX_ATM_H
46 +#define IFX_ATM_H
47 +
48 +
49 +
50 +/*!
51 + \defgroup IFX_ATM UEIP Project - ATM driver module
52 + \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
53 + */
54 +
55 +/*!
56 + \defgroup IFX_ATM_IOCTL IOCTL Commands
57 + \ingroup IFX_ATM
58 + \brief IOCTL Commands used by user application.
59 + */
60 +
61 +/*!
62 + \defgroup IFX_ATM_STRUCT Structures
63 + \ingroup IFX_ATM
64 + \brief Structures used by user application.
65 + */
66 +
67 +/*!
68 + \file ifx_atm.h
69 + \ingroup IFX_ATM
70 + \brief ATM driver header file
71 + */
72 +
73 +
74 +
75 +/*
76 + * ####################################
77 + * Definition
78 + * ####################################
79 + */
80 +
81 +/*!
82 + \addtogroup IFX_ATM_STRUCT
83 + */
84 +/*@{*/
85 +
86 +/*
87 + * ATM MIB
88 + */
89 +
90 +/*!
91 + \struct atm_cell_ifEntry_t
92 + \brief Structure used for Cell Level MIB Counters.
93 +
94 + User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
95 + */
96 +typedef struct {
97 + __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
98 + __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
99 + __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
100 + __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
101 + __u32 ifInErrors; /*!< counter of error ingress cells */
102 + __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
103 + __u32 ifOutErrors; /*!< counter of error egress cells */
104 +} atm_cell_ifEntry_t;
105 +
106 +/*!
107 + \struct atm_aal5_ifEntry_t
108 + \brief Structure used for AAL5 Frame Level MIB Counters.
109 +
110 + User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
111 + */
112 +typedef struct {
113 + __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
114 + __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
115 + __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
116 + __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
117 + __u32 ifInUcastPkts; /*!< counter of ingress packets */
118 + __u32 ifOutUcastPkts; /*!< counter of egress packets */
119 + __u32 ifInErrors; /*!< counter of error ingress packets */
120 + __u32 ifInDiscards; /*!< counter of dropped ingress packets */
121 + __u32 ifOutErros; /*!< counter of error egress packets */
122 + __u32 ifOutDiscards; /*!< counter of dropped egress packets */
123 +} atm_aal5_ifEntry_t;
124 +
125 +/*!
126 + \struct atm_aal5_vcc_t
127 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
128 +
129 + This structure is a part of structure "atm_aal5_vcc_x_t".
130 + */
131 +typedef struct {
132 + __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
133 + __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
134 + __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
135 +} atm_aal5_vcc_t;
136 +
137 +/*!
138 + \struct atm_aal5_vcc_x_t
139 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
140 +
141 + User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
142 + */
143 +typedef struct {
144 + int vpi; /*!< VPI of the VCC to get MIB counters */
145 + int vci; /*!< VCI of the VCC to get MIB counters */
146 + atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
147 +} atm_aal5_vcc_x_t;
148 +
149 +/*@}*/
150 +
151 +
152 +
153 +/*
154 + * ####################################
155 + * IOCTL
156 + * ####################################
157 + */
158 +
159 +/*!
160 + \addtogroup IFX_ATM_IOCTL
161 + */
162 +/*@{*/
163 +
164 +/*
165 + * ioctl Command
166 + */
167 +/*!
168 + \brief ATM IOCTL Magic Number
169 + */
170 +#define PPE_ATM_IOC_MAGIC 'o'
171 +/*!
172 + \brief ATM IOCTL Command - Get Cell Level MIB Counters
173 +
174 + This command is obsolete. User can get cell level MIB from DSL API.
175 + This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
176 + */
177 +#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
178 +/*!
179 + \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
180 +
181 + Get AAL5 packet counters.
182 + This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
183 + */
184 +#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
185 +/*!
186 + \brief ATM IOCTL Command - Get Per PVC MIB Counters
187 +
188 + Get AAL5 packet counters for each PVC.
189 + This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
190 + */
191 +#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
192 +/*!
193 + \brief Total Number of ATM IOCTL Commands
194 + */
195 +#define PPE_ATM_IOC_MAXNR 3
196 +
197 +/*@}*/
198 +
199 +
200 +
201 +/*
202 + * ####################################
203 + * API
204 + * ####################################
205 + */
206 +
207 +#ifdef __KERNEL__
208 +struct port_cell_info {
209 + unsigned int port_num;
210 + unsigned int tx_link_rate[2];
211 +};
212 +#endif
213 +
214 +
215 +
216 +#endif // IFX_ATM_H
217 +
218 --- /dev/null
219 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
220 @@ -0,0 +1,203 @@
221 +/******************************************************************************
222 +**
223 +** FILE NAME : ifx_ptm.h
224 +** PROJECT : UEIP
225 +** MODULES : PTM
226 +**
227 +** DATE : 17 Jun 2009
228 +** AUTHOR : Xu Liang
229 +** DESCRIPTION : Global PTM driver header file
230 +** COPYRIGHT : Copyright (c) 2006
231 +** Infineon Technologies AG
232 +** Am Campeon 1-12, 85579 Neubiberg, Germany
233 +**
234 +** This program is free software; you can redistribute it and/or modify
235 +** it under the terms of the GNU General Public License as published by
236 +** the Free Software Foundation; either version 2 of the License, or
237 +** (at your option) any later version.
238 +**
239 +** HISTORY
240 +** $Date $Author $Comment
241 +** 07 JUL 2009 Xu Liang Init Version
242 +*******************************************************************************/
243 +
244 +#ifndef IFX_PTM_H
245 +#define IFX_PTM_H
246 +
247 +
248 +
249 +/*!
250 + \defgroup IFX_PTM UEIP Project - PTM driver module
251 + \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
252 + */
253 +
254 +/*!
255 + \defgroup IFX_PTM_IOCTL IOCTL Commands
256 + \ingroup IFX_PTM
257 + \brief IOCTL Commands used by user application.
258 + */
259 +
260 +/*!
261 + \defgroup IFX_PTM_STRUCT Structures
262 + \ingroup IFX_PTM
263 + \brief Structures used by user application.
264 + */
265 +
266 +/*!
267 + \file ifx_ptm.h
268 + \ingroup IFX_PTM
269 + \brief PTM driver header file
270 + */
271 +
272 +
273 +
274 +/*
275 + * ####################################
276 + * Definition
277 + * ####################################
278 + */
279 +
280 +
281 +
282 +/*
283 + * ####################################
284 + * IOCTL
285 + * ####################################
286 + */
287 +
288 +/*!
289 + \addtogroup IFX_PTM_IOCTL
290 + */
291 +/*@{*/
292 +
293 +/*
294 + * ioctl Command
295 + */
296 +/*!
297 + \brief PTM IOCTL Command - Get codeword MIB counters.
298 +
299 + This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
300 + */
301 +#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
302 +/*!
303 + \brief PTM IOCTL Command - Get packet MIB counters.
304 +
305 + This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
306 + */
307 +#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
308 +/*!
309 + \brief PTM IOCTL Command - Get firmware configuration (CRC).
310 +
311 + This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
312 + */
313 +#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
314 +/*!
315 + \brief PTM IOCTL Command - Set firmware configuration (CRC).
316 +
317 + This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
318 + */
319 +#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
320 +/*!
321 + \brief PTM IOCTL Command - Program priority value to TX queue mapping.
322 +
323 + This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
324 + */
325 +#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
326 +
327 +/*@}*/
328 +
329 +
330 +/*!
331 + \addtogroup IFX_PTM_STRUCT
332 + */
333 +/*@{*/
334 +
335 +/*
336 + * ioctl Data Type
337 + */
338 +
339 +/*!
340 + \typedef PTM_CW_IF_ENTRY_T
341 + \brief Wrapping of structure "ptm_cw_ifEntry_t".
342 + */
343 +/*!
344 + \struct ptm_cw_ifEntry_t
345 + \brief Structure used for CodeWord level MIB counters.
346 + */
347 +typedef struct ptm_cw_ifEntry_t {
348 + uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
349 + uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
350 + uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
351 + uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
352 + uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
353 +} PTM_CW_IF_ENTRY_T;
354 +
355 +/*!
356 + \typedef PTM_FRAME_MIB_T
357 + \brief Wrapping of structure "ptm_frame_mib_t".
358 + */
359 +/*!
360 + \struct ptm_frame_mib_t
361 + \brief Structure used for packet level MIB counters.
362 + */
363 +typedef struct ptm_frame_mib_t {
364 + uint32_t RxCorrect; /*!< output, number of ingress packet */
365 + uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
366 + uint32_t RxDropped; /*!< output, number of dropped ingress packet */
367 + uint32_t TxSend; /*!< output, number of egress packet */
368 +} PTM_FRAME_MIB_T;
369 +
370 +/*!
371 + \typedef IFX_PTM_CFG_T
372 + \brief Wrapping of structure "ptm_cfg_t".
373 + */
374 +/*!
375 + \struct ptm_cfg_t
376 + \brief Structure used for ETH/TC CRC configuration.
377 + */
378 +typedef struct ptm_cfg_t {
379 + uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
380 + uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
381 + uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
382 + uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
383 + uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
384 + uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
385 + uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
386 +} IFX_PTM_CFG_T;
387 +
388 +/*!
389 + \typedef IFX_PTM_PRIO_Q_MAP_T
390 + \brief Wrapping of structure "ppe_prio_q_map".
391 + */
392 +/*!
393 + \struct ppe_prio_q_map
394 + \brief Structure used for Priority Value to TX Queue mapping.
395 + */
396 +typedef struct ppe_prio_q_map {
397 + int pkt_prio;
398 + int qid;
399 + int vpi; // ignored in eth interface
400 + int vci; // ignored in eth interface
401 +} IFX_PTM_PRIO_Q_MAP_T;
402 +
403 +/*@}*/
404 +
405 +
406 +
407 +/*
408 + * ####################################
409 + * API
410 + * ####################################
411 + */
412 +
413 +#ifdef __KERNEL__
414 +struct port_cell_info {
415 + unsigned int port_num;
416 + unsigned int tx_link_rate[2];
417 +};
418 +#endif
419 +
420 +
421 +
422 +#endif // IFX_PTM_H
423 +
424 --- a/arch/mips/lantiq/irq.c
425 +++ b/arch/mips/lantiq/irq.c
426 @@ -14,6 +14,7 @@
427 #include <linux/of_platform.h>
428 #include <linux/of_address.h>
429 #include <linux/of_irq.h>
430 +#include <linux/module.h>
431
432 #include <asm/bootinfo.h>
433 #include <asm/irq_cpu.h>
434 @@ -100,6 +101,7 @@ void ltq_mask_and_ack_irq(struct irq_dat
435 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
436 ltq_icu_w32(im, BIT(offset), isr);
437 }
438 +EXPORT_SYMBOL(ltq_mask_and_ack_irq);
439
440 static void ltq_ack_irq(struct irq_data *d)
441 {
442 --- a/arch/mips/mm/cache.c
443 +++ b/arch/mips/mm/cache.c
444 @@ -63,6 +63,8 @@ void (*_dma_cache_wback)(unsigned long s
445 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
446
447 EXPORT_SYMBOL(_dma_cache_wback_inv);
448 +EXPORT_SYMBOL(_dma_cache_wback);
449 +EXPORT_SYMBOL(_dma_cache_inv);
450
451 #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
452
453 --- a/include/uapi/linux/atm.h
454 +++ b/include/uapi/linux/atm.h
455 @@ -130,8 +130,14 @@
456 #define ATM_ABR 4
457 #define ATM_ANYCLASS 5 /* compatible with everything */
458
459 +#define ATM_VBR_NRT ATM_VBR
460 +#define ATM_VBR_RT 6
461 +#define ATM_UBR_PLUS 7
462 +#define ATM_GFR 8
463 +
464 #define ATM_MAX_PCR -1 /* maximum available PCR */
465
466 +
467 struct atm_trafprm {
468 unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
469 int max_pcr; /* maximum PCR in cells per second */
470 --- a/net/atm/common.c
471 +++ b/net/atm/common.c
472 @@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc
473 write_unlock_irq(&vcc_sklist_lock);
474 }
475
476 +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
477 +EXPORT_SYMBOL(ifx_atm_alloc_tx);
478 +
479 static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
480 {
481 struct sk_buff *skb;
482 struct sock *sk = sk_atm(vcc);
483
484 + if (ifx_atm_alloc_tx != NULL)
485 + return ifx_atm_alloc_tx(vcc, size);
486 +
487 if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
488 pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
489 sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
490 --- a/net/atm/proc.c
491 +++ b/net/atm/proc.c
492 @@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil
493 static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
494 {
495 static const char *const class_name[] = {
496 - "off", "UBR", "CBR", "VBR", "ABR"};
497 + "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
498 static const char *const aal_name[] = {
499 "---", "1", "2", "3/4", /* 0- 3 */
500 "???", "5", "???", "???", /* 4- 7 */
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