target/linux/lantiq/patches-4.14/0023-NET-PHY-add-led-support-for-intel-xway.patch

   1 From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 7 Aug 2014 18:15:36 +0200
   4 Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/phy/Kconfig  |    5 +
   9  drivers/net/phy/Makefile |    1 +
  10  drivers/net/phy/lantiq.c |  231 ++++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 237 insertions(+)
  12  create mode 100644 drivers/net/phy/lantiq.c
  13
  14 --- a/drivers/net/phy/intel-xway.c
  15 +++ b/drivers/net/phy/intel-xway.c
  16 @@ -152,6 +152,51 @@
  17  #define PHY_ID_PHY11G_VR9              0xD565A409
  18  #define PHY_ID_PHY22F_VR9              0xD565A419
  19
  20 +#if IS_ENABLED(CONFIG_OF_MDIO)
  21 +static int vr9_gphy_of_reg_init(struct phy_device *phydev)
  22 +{
  23 +       u32 tmp;
  24 +
  25 +       /* store the led values if one was passed by the devicetree */
  26 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp))
  27 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp);
  28 +
  29 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp))
  30 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp);
  31 +
  32 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp))
  33 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp);
  34 +
  35 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp))
  36 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp);
  37 +
  38 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp))
  39 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp);
  40 +
  41 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp))
  42 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp);
  43 +
  44 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp))
  45 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H,  tmp);
  46 +
  47 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp))
  48 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
  49 +
  50 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp))
  51 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);
  52 +
  53 +       if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp))
  54 +               phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
  55 +
  56 +       return 0;
  57 +}
  58 +#else
  59 +static int vr9_gphy_of_reg_init(struct phy_device *phydev)
  60 +{
  61 +       return 0;
  62 +}
  63 +#endif /* CONFIG_OF_MDIO */
  64 +
  65  static int xway_gphy_config_init(struct phy_device *phydev)
  66  {
  67         int err;
  68 @@ -190,6 +235,7 @@ static int xway_gphy_config_init(struct
  69         phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh);
  70         phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl);
  71
  72 +       vr9_gphy_of_reg_init(phydev);
  73         return 0;
  74  }
  75
  76 --- /dev/null
  77 +++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
  78 @@ -0,0 +1,216 @@
  79 +Lanitq PHY binding
  80 +============================================
  81 +
  82 +This devicetree binding controls the lantiq ethernet phys led functionality.
  83 +
  84 +Example:
  85 +       mdio@0 {
  86 +               #address-cells = <1>;
  87 +               #size-cells = <0>;
  88 +               compatible = "lantiq,xrx200-mdio";
  89 +                       phy5: ethernet-phy@5 {
  90 +                       reg = <0x1>;
  91 +                       compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  92 +               };
  93 +               phy11: ethernet-phy@11 {
  94 +                       reg = <0x11>;
  95 +                       compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
  96 +                       lantiq,led2h = <0x00>;
  97 +                       lantiq,led2l = <0x03>;
  98 +               };
  99 +               phy12: ethernet-phy@12 {
 100 +                       reg = <0x12>;
 101 +                       compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
 102 +                       lantiq,led1h = <0x00>;
 103 +                       lantiq,led1l = <0x03>;
 104 +               };
 105 +               phy13: ethernet-phy@13 {
 106 +                       reg = <0x13>;
 107 +                       compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
 108 +                       lantiq,led2h = <0x00>;
 109 +                       lantiq,led2l = <0x03>;
 110 +               };
 111 +               phy14: ethernet-phy@14 {
 112 +                       reg = <0x14>;
 113 +                       compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
 114 +                       lantiq,led1h = <0x00>;
 115 +                       lantiq,led1l = <0x03>;
 116 +               };
 117 +       };
 118 +
 119 +Register Description
 120 +============================================
 121 +
 122 +LEDCH:
 123 +
 124 +Name   Hardware Reset Value
 125 +LEDCH  0x00C5
 126 +
 127 +| 15 |    |    |    |    |    |    |  8 |
 128 +=========================================
 129 +|              RES                     |
 130 +=========================================
 131 +
 132 +|  7 |    |    |    |    |    |    |  0 |
 133 +=========================================
 134 +|   FBF   |   SBF   |RES |     NACS     |
 135 +=========================================
 136 +
 137 +Field  Bits    Type    Description
 138 +FBF    7:6     RW      Fast Blink Frequency
 139 +                       ---
 140 +                       0x0 (00b) F02HZ 2 Hz blinking frequency
 141 +                       0x1 (01b) F04HZ 4 Hz blinking frequency
 142 +                       0x2 (10b) F08HZ 8 Hz blinking frequency
 143 +                       0x3 (11b) F16HZ 16 Hz blinking frequency
 144 +
 145 +SBF    5:4     RW      Slow Blink Frequency
 146 +                       ---
 147 +                       0x0 (00b) F02HZ 2 Hz blinking frequency
 148 +                       0x1 (01b) F04HZ 4 Hz blinking frequency
 149 +                       0x2 (10b) F08HZ 8 Hz blinking frequency
 150 +                       0x3 (11b) F16HZ 16 Hz blinking frequency
 151 +
 152 +NACS   2:0     RW      Inverse of Scan Function
 153 +                       ---
 154 +                       0x0 (000b) NONE No Function
 155 +                       0x1 (001b) LINK Complex function enabled when link is up
 156 +                       0x2 (010b) PDOWN Complex function enabled when device is powered-down
 157 +                       0x3 (011b) EEE Complex function enabled when device is in EEE mode
 158 +                       0x4 (100b) ANEG Complex function enabled when auto-negotiation is running
 159 +                       0x5 (101b) ABIST Complex function enabled when analog self-test is running
 160 +                       0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running
 161 +                       0x7 (111b) TEST Complex function enabled when test mode is running
 162 +
 163 +LEDCL:
 164 +
 165 +Name   Hardware Reset Value
 166 +LEDCL  0x0067
 167 +
 168 +| 15 |    |    |    |    |    |    |  8 |
 169 +=========================================
 170 +|              RES                     |
 171 +=========================================
 172 +
 173 +|  7 |    |    |    |    |    |    |  0 |
 174 +=========================================
 175 +|RES |     SCAN     |RES |    CBLINK    |
 176 +=========================================
 177 +
 178 +Field  Bits    Type    Description
 179 +SCAN   6:4     RW      Complex Scan Configuration
 180 +                       ---
 181 +                       000 B NONE No Function
 182 +                       001 B LINK Complex function enabled when link is up
 183 +                       010 B PDOWN Complex function enabled when device is powered-down
 184 +                       011 B EEE Complex function enabled when device is in EEE mode
 185 +                       100 B ANEG Complex function enabled when auto-negotiation is running
 186 +                       101 B ABIST Complex function enabled when analog self-test is running
 187 +                       110 B CDIAG Complex function enabled when cable diagnostics are running
 188 +                       111 B TEST Complex function enabled when test mode is running
 189 +
 190 +CBLINK 2:0     RW      Complex Blinking Configuration
 191 +                       ---
 192 +                       000 B NONE No Function
 193 +                       001 B LINK Complex function enabled when link is up
 194 +                       010 B PDOWN Complex function enabled when device is powered-down
 195 +                       011 B EEE Complex function enabled when device is in EEE mode
 196 +                       100 B ANEG Complex function enabled when auto-negotiation is running
 197 +                       101 B ABIST Complex function enabled when analog self-test is running
 198 +                       110 B CDIAG Complex function enabled when cable diagnostics are running
 199 +                       111 B TEST Complex function enabled when test mode is running
 200 +
 201 +LEDxH:
 202 +
 203 +Name   Hardware Reset Value
 204 +LED0H  0x0070
 205 +LED1H  0x0020
 206 +LED2H  0x0040
 207 +LED3H  0x0040
 208 +
 209 +| 15 |    |    |    |    |    |    |  8 |
 210 +=========================================
 211 +|              RES                     |
 212 +=========================================
 213 +
 214 +|  7 |    |    |    |    |    |    |  0 |
 215 +=========================================
 216 +|        CON        |       BLINKF      |
 217 +=========================================
 218 +
 219 +Field  Bits    Type    Description
 220 +CON    7:4     RW      Constant On Configuration
 221 +                       ---
 222 +                       0x0 (0000b) NONE LED does not light up constantly
 223 +                       0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s
 224 +                       0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s
 225 +                       0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s
 226 +                       0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s
 227 +                       0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s
 228 +                       0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s
 229 +                       0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s
 230 +                       0x8 (1000b) PDOWN LED is on when device is powered-down
 231 +                       0x9 (1001b) EEE LED is on when device is in EEE mode
 232 +                       0xA (1010b) ANEG LED is on when auto-negotiation is running
 233 +                       0xB (1011b) ABIST LED is on when analog self-test is running
 234 +                       0xC (1100b) CDIAG LED is on when cable diagnostics are running
 235 +
 236 +BLINKF 3:0     RW      Fast Blinking Configuration
 237 +                       ---
 238 +                       0x0 (0000b) NONE No Blinking
 239 +                       0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
 240 +                       0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
 241 +                       0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
 242 +                       0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
 243 +                       0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
 244 +                       0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
 245 +                       0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
 246 +                       0x8 (1000b) PDOWN Blink when device is powered-down
 247 +                       0x9 (1001b) EEE Blink when device is in EEE mode
 248 +                       0xA (1010b) ANEG Blink when auto-negotiation is running
 249 +                       0xB (1011b) ABIST Blink when analog self-test is running
 250 +                       0xC (1100b) CDIAG Blink when cable diagnostics are running
 251 +
 252 +LEDxL:
 253 +
 254 +Name   Hardware Reset Value
 255 +LED0L  0x0003
 256 +LED1L  0x0000
 257 +LED2L  0x0000
 258 +LED3L  0x0020
 259 +
 260 +| 15 |    |    |    |    |    |    |  8 |
 261 +=========================================
 262 +|              RES                     |
 263 +=========================================
 264 +
 265 +|  7 |    |    |    |    |    |    |  0 |
 266 +=========================================
 267 +|      BLINKS       |       PULSE       |
 268 +=========================================
 269 +
 270 +Field  Bits    Type    Description
 271 +BLINKS 7:4     RW      Slow Blinkin Configuration
 272 +                       ---
 273 +                       0x0 (0000b) NONE No Blinking
 274 +                       0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
 275 +                       0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
 276 +                       0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
 277 +                       0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
 278 +                       0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
 279 +                       0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
 280 +                       0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
 281 +                       0x8 (1000b) PDOWN Blink when device is powered-down
 282 +                       0x9 (1001b) EEE Blink when device is in EEE mode
 283 +                       0xA (1010b) ANEG Blink when auto-negotiation is running
 284 +                       0xB (1011b) ABIST Blink when analog self-test is running
 285 +                       0xC (1100b) CDIAG Blink when cable diagnostics are runningning
 286 +
 287 +PULSE  3:0     RW      Pulsing Configuration
 288 +                       The pulse field is a mask field by which certain events can be combined
 289 +                       ---
 290 +                       0x0 (0000b) NONE No pulsing
 291 +                       0x1 (0001b) TXACT Transmit activity
 292 +                       0x2 (0010b) RXACT Receive activity
 293 +                       0x4 (0100b) COL Collision
 294 +                       0x8 (1000b) RES Reserved