target/linux/lantiq/patches-4.14/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch

   1 From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Fri, 6 Jan 2017 17:55:24 +0100
   4 Subject: [PATCH 2/2] usb: dwc2:  add support for other Lantiq SoCs
   5
   6 The size of the internal RAM of the DesignWare USB controller changed
   7 between the different Lantiq SoCs. We have the following sizes:
   8
   9 Amazon + Danube: 8 KByte
  10 Amazon SE + arx100: 2 KByte
  11 xrx200 + xrx300: 2.5 KByte
  12
  13 For Danube SoC we do not provide the params and let the driver decide
  14 to use sane defaults, for the Amazon SE and arx100 we use small fifos
  15 and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
  16 The auto detection of max_transfer_size and max_packet_count should
  17 work, so remove it.
  18
  19 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
  20 ---
  21  drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------
  22  1 file changed, 39 insertions(+), 7 deletions(-)
  23
  24 --- a/drivers/usb/dwc2/params.c
  25 +++ b/drivers/usb/dwc2/params.c
  26 @@ -83,7 +83,14 @@ static void dwc2_set_rk_params(struct dw
  27                 GAHBCFG_HBSTLEN_SHIFT;
  28  }
  29
  30 -static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
  31 +static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg)
  32 +{
  33 +       struct dwc2_core_params *p = &hsotg->params;
  34 +
  35 +       p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  36 +}
  37 +
  38 +static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg)
  39  {
  40         struct dwc2_core_params *p = &hsotg->params;
  41
  42 @@ -91,12 +98,20 @@ static void dwc2_set_ltq_params(struct d
  43         p->host_rx_fifo_size = 288;
  44         p->host_nperio_tx_fifo_size = 128;
  45         p->host_perio_tx_fifo_size = 96;
  46 -       p->max_transfer_size = 65535;
  47 -       p->max_packet_count = 511;
  48         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  49                 GAHBCFG_HBSTLEN_SHIFT;
  50  }
  51
  52 +static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg)
  53 +{
  54 +       struct dwc2_core_params *p = &hsotg->params;
  55 +
  56 +       p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  57 +       p->host_rx_fifo_size = 288;
  58 +       p->host_nperio_tx_fifo_size = 128;
  59 +       p->host_perio_tx_fifo_size = 136;
  60 +}
  61 +
  62  static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
  63  {
  64         struct dwc2_core_params *p = &hsotg->params;
  65 @@ -140,8 +155,11 @@ const struct of_device_id dwc2_of_match_
  66         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
  67         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
  68         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
  69 -       { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
  70 -       { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
  71 +       { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },
  72 +       { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },
  73 +       { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },
  74 +       { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },
  75 +       { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },
  76         { .compatible = "snps,dwc2" },
  77         { .compatible = "samsung,s3c6400-hsotg" },
  78         { .compatible = "amlogic,meson8-usb",