target/linux/lantiq/patches-4.9/0065-MIPS-lantiq-improve-USB-initialization.patch

   1 From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Fri, 6 Jan 2017 17:40:12 +0100
   4 Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
   5
   6 This adds code to initialize the USB controller and PHY also on Danube,
   7 Amazon SE and AR10. This code is based on the Vendor driver from
   8 different UGW versions and compared to the hardware documentation.
   9
  10 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
  11 ---
  12  arch/mips/lantiq/xway/reset.c   | 120 ++++++++++++++++++++++++++++++----------
  13  arch/mips/lantiq/xway/sysctrl.c |  20 +++++++
  14  2 files changed, 110 insertions(+), 30 deletions(-)
  15
  16 --- a/arch/mips/lantiq/xway/reset.c
  17 +++ b/arch/mips/lantiq/xway/reset.c
  18 @@ -72,6 +72,8 @@
  19  #define RCU_USBCFG_HDSEL_BIT   BIT(11)
  20  #define RCU_USBCFG_HOST_END_BIT        BIT(10)
  21  #define RCU_USBCFG_SLV_END_BIT BIT(9)
  22 +#define RCU_USBCFG_SLV_END_BIT_AR9     BIT(17)
  23 +
  24
  25  /* USB reset bits */
  26  #define RCU_USBRESET           0x0010
  27 @@ -85,6 +87,8 @@
  28
  29  #define RCU_CFG1A              0x0038
  30  #define RCU_CFG1B              0x003C
  31 +#define  RCU_CFG1_TX_PEE       BIT(0)
  32 +#define  RCU_CFG1_DIS_THR_SHIFT        15 /* Disconnect Threshold */
  33
  34  /* USB PMU devices */
  35  #define PMU_AHBM               BIT(15)
  36 @@ -306,38 +310,91 @@ static void ltq_usb_init(void)
  37         /* Power for USB cores 1 & 2 */
  38         ltq_pmu_enable(PMU_AHBM);
  39         ltq_pmu_enable(PMU_USB0);
  40 -       ltq_pmu_enable(PMU_USB1);
  41
  42 -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
  43 -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
  44 +       if (of_machine_is_compatible("lantiq,ar10") ||
  45 +           of_machine_is_compatible("lantiq,grx390") ||
  46 +           of_machine_is_compatible("lantiq,ar9") ||
  47 +           of_machine_is_compatible("lantiq,vr9"))
  48 +               ltq_pmu_enable(PMU_USB1);
  49 +
  50 +       if (of_machine_is_compatible("lantiq,vr9") ||
  51 +           of_machine_is_compatible("lantiq,ar10")) {
  52 +               ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | RCU_CFG1_TX_PEE |
  53 +                           7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1A);
  54 +               ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | RCU_CFG1_TX_PEE |
  55 +                           7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1B);
  56 +       }
  57
  58         /* Enable USB PHY power for cores 1 & 2 */
  59         ltq_pmu_enable(PMU_USB0_P);
  60 -       ltq_pmu_enable(PMU_USB1_P);
  61 +       if (of_machine_is_compatible("lantiq,ar10") ||
  62 +           of_machine_is_compatible("lantiq,grx390") ||
  63 +           of_machine_is_compatible("lantiq,ar9") ||
  64 +           of_machine_is_compatible("lantiq,vr9"))
  65 +               ltq_pmu_enable(PMU_USB1_P);
  66 +
  67 +       if (of_machine_is_compatible("lantiq,ase") ||
  68 +           of_machine_is_compatible("lantiq,danube")) {
  69 +               /* Configure cores to host mode */
  70 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
  71 +                       RCU_USB1CFG);
  72 +
  73 +               /* Select DMA endianness (Host-endian: big-endian) */
  74 +               ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
  75 +                       | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
  76 +       }
  77 +
  78 +       if (of_machine_is_compatible("lantiq,ar9")) {
  79 +               /* Configure cores to host mode */
  80 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
  81 +                       RCU_USB1CFG);
  82 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
  83 +                       RCU_USB2CFG);
  84 +
  85 +               /* Select DMA endianness (Host-endian: big-endian) */
  86 +               ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
  87 +                       | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
  88 +               ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
  89 +                       | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
  90 +       }
  91 +
  92 +       if (of_machine_is_compatible("lantiq,vr9") ||
  93 +           of_machine_is_compatible("lantiq,ar10")) {
  94 +               /* Configure cores to host mode */
  95 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
  96 +                       RCU_USB1CFG);
  97 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
  98 +                       RCU_USB2CFG);
  99 +
 100 +               /* Select DMA endianness (Host-endian: big-endian) */
 101 +               ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
 102 +                       | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
 103 +               ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
 104 +                       | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
 105 +       }
 106 +
 107 +       if (of_machine_is_compatible("lantiq,ar9")) {
 108 +               /* Hard reset USB state machines */
 109 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
 110 +                          | USBRESET_BIT | BIT(28), RCU_USBRESET);
 111 +               udelay(50 * 1000);
 112 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
 113 +                           & ~(USBRESET_BIT | BIT(28)), RCU_USBRESET);
 114 +       } else {
 115 +               /* Hard reset USB state machines */
 116 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
 117 +               udelay(50 * 1000);
 118 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
 119 +       }
 120
 121 -       /* Configure cores to host mode */
 122 -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
 123 -               RCU_USB1CFG);
 124 -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
 125 -               RCU_USB2CFG);
 126 -
 127 -       /* Select DMA endianness (Host-endian: big-endian) */
 128 -       ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
 129 -               | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
 130 -       ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
 131 -               | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
 132 -
 133 -       /* Hard reset USB state machines */
 134 -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
 135 -       udelay(50 * 1000);
 136 -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
 137 -
 138 -       /* Soft reset USB state machines */
 139 -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
 140 -               | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
 141 -       udelay(50 * 1000);
 142 -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
 143 -               & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
 144 +       if (of_machine_is_compatible("lantiq,vr9")) {
 145 +               /* Soft reset USB state machines */
 146 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
 147 +                       | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
 148 +               udelay(50 * 1000);
 149 +               ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
 150 +                       & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
 151 +       }
 152  }
 153
 154  static int __init mips_reboot_setup(void)
 155 @@ -363,8 +420,11 @@ static int __init mips_reboot_setup(void
 156         if (!ltq_rcu_membase)
 157                 panic("Failed to remap core memory");
 158
 159 -       if (of_machine_is_compatible("lantiq,ar9") ||
 160 -           of_machine_is_compatible("lantiq,vr9"))
 161 +       if (of_machine_is_compatible("lantiq,danube") ||
 162 +           of_machine_is_compatible("lantiq,ase") ||
 163 +           of_machine_is_compatible("lantiq,ar9") ||
 164 +           of_machine_is_compatible("lantiq,vr9") ||
 165 +           of_machine_is_compatible("lantiq,ar10"))
 166                 ltq_usb_init();
 167
 168         if (of_machine_is_compatible("lantiq,vr9"))
 169 --- a/arch/mips/lantiq/xway/sysctrl.c
 170 +++ b/arch/mips/lantiq/xway/sysctrl.c
 171 @@ -254,6 +254,25 @@ static void pmu_disable(struct clk *clk)
 172                 pr_warn("deactivating PMU module failed!");
 173  }
 174
 175 +static void usb_set_clock(void)
 176 +{
 177 +       unsigned int val = ltq_cgu_r32(ifccr);
 178 +
 179 +       if (of_machine_is_compatible("lantiq,ar10") ||
 180 +           of_machine_is_compatible("lantiq,grx390")) {
 181 +               val &= ~0x03; /* XTAL divided by 3 */
 182 +       } else if (of_machine_is_compatible("lantiq,ar9") ||
 183 +                  of_machine_is_compatible("lantiq,vr9")) {
 184 +               /* TODO: this depends on the XTAL frequency */
 185 +               val |= 0x03; /* XTAL divided by 3 */
 186 +       } else if (of_machine_is_compatible("lantiq,ase")) {
 187 +               val |= 0x20; /* from XTAL */
 188 +       } else if (of_machine_is_compatible("lantiq,danube")) {
 189 +               val |= 0x30; /* 12 MHz, generated from 36 MHz */
 190 +       }
 191 +       ltq_cgu_w32(val, ifccr);
 192 +}
 193 +
 194  /* the pci enable helper */
 195  static int pci_enable(struct clk *clk)
 196  {
 197 @@ -608,4 +627,5 @@ void __init ltq_soc_init(void)
 198
 199         if (of_machine_is_compatible("lantiq,vr9"))
 200                 xbar_fpi_burst_disable();
 201 +       usb_set_clock();
 202  }