target/linux/lantiq/patches-4.9/0091-spi-lantiq-ssc-add-support-for-Lantiq-SSC-SPI-controller.patch

   1 --- /dev/null
   2 +++ b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
   3 @@ -0,0 +1,29 @@
   4 +Lantiq Synchronous Serial Controller (SSC) SPI master driver
   5 +
   6 +Required properties:
   7 +- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
   8 +- #address-cells: see spi-bus.txt
   9 +- #size-cells: see spi-bus.txt
  10 +- reg: address and length of the spi master registers
  11 +- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
  12 +
  13 +
  14 +Optional properties:
  15 +- clocks: spi clock phandle
  16 +- num-cs: see spi-bus.txt, set to 8 if unset
  17 +- base-cs: the number of the first chip select, set to 1 if unset.
  18 +
  19 +Example:
  20 +
  21 +
  22 +spi: spi@E100800 {
  23 +       compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
  24 +       reg = <0xE100800 0x100>;
  25 +       interrupt-parent = <&icu0>;
  26 +       interrupts = <22 23 24>;
  27 +       interrupt-names = "spi_rx", "spi_tx", "spi_err";
  28 +       #address-cells = <1>;
  29 +       #size-cells = <1>;
  30 +       num-cs = <6>;
  31 +       base-cs = <1>;
  32 +};
  33 --- a/drivers/spi/Kconfig
  34 +++ b/drivers/spi/Kconfig
  35 @@ -403,6 +403,14 @@ config SPI_NUC900
  36         help
  37           SPI driver for Nuvoton NUC900 series ARM SoCs
  38
  39 +config SPI_LANTIQ_SSC
  40 +       tristate "Lantiq SSC SPI controller"
  41 +       depends on LANTIQ
  42 +       help
  43 +         This driver supports the Lantiq SSC SPI controller in master
  44 +         mode. This controller is found on Intel (former Lantiq) SoCs like
  45 +         the Danube, Falcon, xRX200, xRX300.
  46 +
  47  config SPI_OC_TINY
  48         tristate "OpenCores tiny SPI"
  49         depends on GPIOLIB || COMPILE_TEST
  50 --- a/drivers/spi/Makefile
  51 +++ b/drivers/spi/Makefile
  52 @@ -47,6 +47,7 @@ obj-$(CONFIG_SPI_FSL_SPI)             += spi-fsl-sp
  53  obj-$(CONFIG_SPI_GPIO)                 += spi-gpio.o
  54  obj-$(CONFIG_SPI_IMG_SPFI)             += spi-img-spfi.o
  55  obj-$(CONFIG_SPI_IMX)                  += spi-imx.o
  56 +obj-$(CONFIG_SPI_LANTIQ_SSC)           += spi-lantiq-ssc.o
  57  obj-$(CONFIG_SPI_JCORE)                        += spi-jcore.o
  58  obj-$(CONFIG_SPI_LM70_LLP)             += spi-lm70llp.o
  59  obj-$(CONFIG_SPI_LP8841_RTC)           += spi-lp8841-rtc.o
  60 --- /dev/null
  61 +++ b/drivers/spi/spi-lantiq-ssc.c
  62 @@ -0,0 +1,952 @@
  63 +/*
  64 + * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  65 + * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
  66 + *
  67 + * This program is free software; you can distribute it and/or modify it
  68 + * under the terms of the GNU General Public License (Version 2) as
  69 + * published by the Free Software Foundation.
  70 + */
  71 +
  72 +#include <linux/kernel.h>
  73 +#include <linux/module.h>
  74 +#include <linux/of_device.h>
  75 +#include <linux/clk.h>
  76 +#include <linux/io.h>
  77 +#include <linux/delay.h>
  78 +#include <linux/interrupt.h>
  79 +#include <linux/sched.h>
  80 +#include <linux/completion.h>
  81 +#include <linux/spinlock.h>
  82 +#include <linux/err.h>
  83 +#include <linux/gpio.h>
  84 +#include <linux/pm_runtime.h>
  85 +#include <linux/spi/spi.h>
  86 +
  87 +#include <lantiq_soc.h>
  88 +
  89 +#define SPI_RX_IRQ_NAME                "spi_rx"
  90 +#define SPI_TX_IRQ_NAME                "spi_tx"
  91 +#define SPI_ERR_IRQ_NAME       "spi_err"
  92 +#define SPI_FRM_IRQ_NAME       "spi_frm"
  93 +
  94 +#define SPI_CLC                        0x00
  95 +#define SPI_PISEL              0x04
  96 +#define SPI_ID                 0x08
  97 +#define SPI_CON                        0x10
  98 +#define SPI_STAT               0x14
  99 +#define SPI_WHBSTATE           0x18
 100 +#define SPI_TB                 0x20
 101 +#define SPI_RB                 0x24
 102 +#define SPI_RXFCON             0x30
 103 +#define SPI_TXFCON             0x34
 104 +#define SPI_FSTAT              0x38
 105 +#define SPI_BRT                        0x40
 106 +#define SPI_BRSTAT             0x44
 107 +#define SPI_SFCON              0x60
 108 +#define SPI_SFSTAT             0x64
 109 +#define SPI_GPOCON             0x70
 110 +#define SPI_GPOSTAT            0x74
 111 +#define SPI_FPGO               0x78
 112 +#define SPI_RXREQ              0x80
 113 +#define SPI_RXCNT              0x84
 114 +#define SPI_DMACON             0xec
 115 +#define SPI_IRNEN              0xf4
 116 +#define SPI_IRNICR             0xf8
 117 +#define SPI_IRNCR              0xfc
 118 +
 119 +#define SPI_CLC_SMC_S          16      /* Clock divider for sleep mode */
 120 +#define SPI_CLC_SMC_M          (0xFF << SPI_CLC_SMC_S)
 121 +#define SPI_CLC_RMC_S          8       /* Clock divider for normal run mode */
 122 +#define SPI_CLC_RMC_M          (0xFF << SPI_CLC_RMC_S)
 123 +#define SPI_CLC_DISS           BIT(1)  /* Disable status bit */
 124 +#define SPI_CLC_DISR           BIT(0)  /* Disable request bit */
 125 +
 126 +#define SPI_ID_TXFS_S          24      /* Implemented TX FIFO size */
 127 +#define SPI_ID_TXFS_M          (0x3F << SPI_ID_TXFS_S)
 128 +#define SPI_ID_RXFS_S          16      /* Implemented RX FIFO size */
 129 +#define SPI_ID_RXFS_M          (0x3F << SPI_ID_RXFS_S)
 130 +#define SPI_ID_MOD_S           8       /* Module ID */
 131 +#define SPI_ID_MOD_M           (0xff << SPI_ID_MOD_S)
 132 +#define SPI_ID_CFG_S           5       /* DMA interface support */
 133 +#define SPI_ID_CFG_M           (1 << SPI_ID_CFG_S)
 134 +#define SPI_ID_REV_M           0x1F    /* Hardware revision number */
 135 +
 136 +#define SPI_CON_BM_S           16      /* Data width selection */
 137 +#define SPI_CON_BM_M           (0x1F << SPI_CON_BM_S)
 138 +#define SPI_CON_EM             BIT(24) /* Echo mode */
 139 +#define SPI_CON_IDLE           BIT(23) /* Idle bit value */
 140 +#define SPI_CON_ENBV           BIT(22) /* Enable byte valid control */
 141 +#define SPI_CON_RUEN           BIT(12) /* Receive underflow error enable */
 142 +#define SPI_CON_TUEN           BIT(11) /* Transmit underflow error enable */
 143 +#define SPI_CON_AEN            BIT(10) /* Abort error enable */
 144 +#define SPI_CON_REN            BIT(9)  /* Receive overflow error enable */
 145 +#define SPI_CON_TEN            BIT(8)  /* Transmit overflow error enable */
 146 +#define SPI_CON_LB             BIT(7)  /* Loopback control */
 147 +#define SPI_CON_PO             BIT(6)  /* Clock polarity control */
 148 +#define SPI_CON_PH             BIT(5)  /* Clock phase control */
 149 +#define SPI_CON_HB             BIT(4)  /* Heading control */
 150 +#define SPI_CON_RXOFF          BIT(1)  /* Switch receiver off */
 151 +#define SPI_CON_TXOFF          BIT(0)  /* Switch transmitter off */
 152 +
 153 +#define SPI_STAT_RXBV_S                28
 154 +#define SPI_STAT_RXBV_M                (0x7 << SPI_STAT_RXBV_S)
 155 +#define SPI_STAT_BSY           BIT(13) /* Busy flag */
 156 +#define SPI_STAT_RUE           BIT(12) /* Receive underflow error flag */
 157 +#define SPI_STAT_TUE           BIT(11) /* Transmit underflow error flag */
 158 +#define SPI_STAT_AE            BIT(10) /* Abort error flag */
 159 +#define SPI_STAT_RE            BIT(9)  /* Receive error flag */
 160 +#define SPI_STAT_TE            BIT(8)  /* Transmit error flag */
 161 +#define SPI_STAT_ME            BIT(7)  /* Mode error flag */
 162 +#define SPI_STAT_MS            BIT(1)  /* Master/slave select bit */
 163 +#define SPI_STAT_EN            BIT(0)  /* Enable bit */
 164 +#define SPI_STAT_ERRORS                (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \
 165 +                                SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE)
 166 +
 167 +#define SPI_WHBSTATE_SETTUE    BIT(15) /* Set transmit underflow error flag */
 168 +#define SPI_WHBSTATE_SETAE     BIT(14) /* Set abort error flag */
 169 +#define SPI_WHBSTATE_SETRE     BIT(13) /* Set receive error flag */
 170 +#define SPI_WHBSTATE_SETTE     BIT(12) /* Set transmit error flag */
 171 +#define SPI_WHBSTATE_CLRTUE    BIT(11) /* Clear transmit underflow error flag */
 172 +#define SPI_WHBSTATE_CLRAE     BIT(10) /* Clear abort error flag */
 173 +#define SPI_WHBSTATE_CLRRE     BIT(9)  /* Clear receive error flag */
 174 +#define SPI_WHBSTATE_CLRTE     BIT(8)  /* Clear transmit error flag */
 175 +#define SPI_WHBSTATE_SETME     BIT(7)  /* Set mode error flag */
 176 +#define SPI_WHBSTATE_CLRME     BIT(6)  /* Clear mode error flag */
 177 +#define SPI_WHBSTATE_SETRUE    BIT(5)  /* Set receive underflow error flag */
 178 +#define SPI_WHBSTATE_CLRRUE    BIT(4)  /* Clear receive underflow error flag */
 179 +#define SPI_WHBSTATE_SETMS     BIT(3)  /* Set master select bit */
 180 +#define SPI_WHBSTATE_CLRMS     BIT(2)  /* Clear master select bit */
 181 +#define SPI_WHBSTATE_SETEN     BIT(1)  /* Set enable bit (operational mode) */
 182 +#define SPI_WHBSTATE_CLREN     BIT(0)  /* Clear enable bit (config mode */
 183 +#define SPI_WHBSTATE_CLR_ERRORS        (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \
 184 +                                SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \
 185 +                                SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE)
 186 +
 187 +#define SPI_RXFCON_RXFITL_S    8       /* FIFO interrupt trigger level */
 188 +#define SPI_RXFCON_RXFITL_M    (0x3F << SPI_RXFCON_RXFITL_S)
 189 +#define SPI_RXFCON_RXFLU       BIT(1)  /* FIFO flush */
 190 +#define SPI_RXFCON_RXFEN       BIT(0)  /* FIFO enable */
 191 +
 192 +#define SPI_TXFCON_TXFITL_S    8       /* FIFO interrupt trigger level */
 193 +#define SPI_TXFCON_TXFITL_M    (0x3F << SPI_TXFCON_TXFITL_S)
 194 +#define SPI_TXFCON_TXFLU       BIT(1)  /* FIFO flush */
 195 +#define SPI_TXFCON_TXFEN       BIT(0)  /* FIFO enable */
 196 +
 197 +#define SPI_FSTAT_RXFFL_S      0
 198 +#define SPI_FSTAT_RXFFL_M      (0x3f << SPI_FSTAT_RXFFL_S)
 199 +#define SPI_FSTAT_TXFFL_S      8
 200 +#define SPI_FSTAT_TXFFL_M      (0x3f << SPI_FSTAT_TXFFL_S)
 201 +
 202 +#define SPI_GPOCON_ISCSBN_S    8
 203 +#define SPI_GPOCON_INVOUTN_S   0
 204 +
 205 +#define SPI_FGPO_SETOUTN_S     8
 206 +#define SPI_FGPO_CLROUTN_S     0
 207 +
 208 +#define SPI_RXREQ_RXCNT_M      0xFFFF  /* Receive count value */
 209 +#define SPI_RXCNT_TODO_M       0xFFFF  /* Recevie to-do value */
 210 +
 211 +#define SPI_IRNEN_TFI          BIT(4)  /* TX finished interrupt */
 212 +#define SPI_IRNEN_F            BIT(3)  /* Frame end interrupt request */
 213 +#define SPI_IRNEN_E            BIT(2)  /* Error end interrupt request */
 214 +#define SPI_IRNEN_T_XWAY       BIT(1)  /* Transmit end interrupt request */
 215 +#define SPI_IRNEN_R_XWAY       BIT(0)  /* Receive end interrupt request */
 216 +#define SPI_IRNEN_R_XRX                BIT(1)  /* Transmit end interrupt request */
 217 +#define SPI_IRNEN_T_XRX                BIT(0)  /* Receive end interrupt request */
 218 +#define SPI_IRNEN_ALL          0x1F
 219 +
 220 +struct lantiq_ssc_hwcfg {
 221 +       unsigned int irnen_r;
 222 +       unsigned int irnen_t;
 223 +};
 224 +
 225 +struct lantiq_ssc_spi {
 226 +       struct spi_master               *master;
 227 +       struct device                   *dev;
 228 +       void __iomem                    *regbase;
 229 +       struct clk                      *spi_clk;
 230 +       struct clk                      *fpi_clk;
 231 +       const struct lantiq_ssc_hwcfg   *hwcfg;
 232 +
 233 +       spinlock_t                      lock;
 234 +
 235 +       const u8                        *tx;
 236 +       u8                              *rx;
 237 +       unsigned int                    tx_todo;
 238 +       unsigned int                    rx_todo;
 239 +       unsigned int                    bits_per_word;
 240 +       unsigned int                    speed_hz;
 241 +       int                             status;
 242 +       unsigned int                    tx_fifo_size;
 243 +       unsigned int                    rx_fifo_size;
 244 +       unsigned int                    base_cs;
 245 +};
 246 +
 247 +static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
 248 +{
 249 +       return __raw_readl(spi->regbase + reg);
 250 +}
 251 +
 252 +static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
 253 +                             u32 reg)
 254 +{
 255 +       __raw_writel(val, spi->regbase + reg);
 256 +}
 257 +
 258 +static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
 259 +                            u32 set, u32 reg)
 260 +{
 261 +       u32 val = __raw_readl(spi->regbase + reg);
 262 +
 263 +       val &= ~clr;
 264 +       val |= set;
 265 +       __raw_writel(val, spi->regbase + reg);
 266 +}
 267 +
 268 +static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
 269 +{
 270 +       u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
 271 +
 272 +       return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S;
 273 +}
 274 +
 275 +static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
 276 +{
 277 +       u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
 278 +
 279 +       return fstat & SPI_FSTAT_RXFFL_M;
 280 +}
 281 +
 282 +static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
 283 +{
 284 +       return spi->tx_fifo_size - tx_fifo_level(spi);
 285 +}
 286 +
 287 +static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
 288 +{
 289 +       u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S;
 290 +
 291 +       val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU;
 292 +       lantiq_ssc_writel(spi, val, SPI_RXFCON);
 293 +}
 294 +
 295 +static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
 296 +{
 297 +       u32 val = 1 << SPI_TXFCON_TXFITL_S;
 298 +
 299 +       val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU;
 300 +       lantiq_ssc_writel(spi, val, SPI_TXFCON);
 301 +}
 302 +
 303 +static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
 304 +{
 305 +       lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON);
 306 +}
 307 +
 308 +static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
 309 +{
 310 +       lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON);
 311 +}
 312 +
 313 +static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
 314 +{
 315 +       lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE);
 316 +}
 317 +
 318 +static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
 319 +{
 320 +       lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE);
 321 +}
 322 +
 323 +static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
 324 +                             unsigned int max_speed_hz)
 325 +{
 326 +       u32 spi_clk, brt;
 327 +
 328 +       /*
 329 +        * SPI module clock is derived from FPI bus clock dependent on
 330 +        * divider value in CLC.RMS which is always set to 1.
 331 +        *
 332 +        *                 f_SPI
 333 +        * baudrate = --------------
 334 +        *             2 * (BR + 1)
 335 +        */
 336 +       spi_clk = clk_get_rate(spi->fpi_clk) / 2;
 337 +
 338 +       if (max_speed_hz > spi_clk)
 339 +               brt = 0;
 340 +       else
 341 +               brt = spi_clk / max_speed_hz - 1;
 342 +
 343 +       if (brt > 0xFFFF)
 344 +               brt = 0xFFFF;
 345 +
 346 +       dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
 347 +               spi_clk, max_speed_hz, brt);
 348 +
 349 +       lantiq_ssc_writel(spi, brt, SPI_BRT);
 350 +}
 351 +
 352 +static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
 353 +                                  unsigned int bits_per_word)
 354 +{
 355 +       u32 bm;
 356 +
 357 +       /* CON.BM value = bits_per_word - 1 */
 358 +       bm = (bits_per_word - 1) << SPI_CON_BM_S;
 359 +
 360 +       lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON);
 361 +}
 362 +
 363 +static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
 364 +                               unsigned int mode)
 365 +{
 366 +       u32 con_set = 0, con_clr = 0;
 367 +
 368 +       /*
 369 +        * SPI mode mapping in CON register:
 370 +        * Mode CPOL CPHA CON.PO CON.PH
 371 +        *  0    0    0      0      1
 372 +        *  1    0    1      0      0
 373 +        *  2    1    0      1      1
 374 +        *  3    1    1      1      0
 375 +        */
 376 +       if (mode & SPI_CPHA)
 377 +               con_clr |= SPI_CON_PH;
 378 +       else
 379 +               con_set |= SPI_CON_PH;
 380 +
 381 +       if (mode & SPI_CPOL)
 382 +               con_set |= SPI_CON_PO | SPI_CON_IDLE;
 383 +       else
 384 +               con_clr |= SPI_CON_PO | SPI_CON_IDLE;
 385 +
 386 +       /* Set heading control */
 387 +       if (mode & SPI_LSB_FIRST)
 388 +               con_clr |= SPI_CON_HB;
 389 +       else
 390 +               con_set |= SPI_CON_HB;
 391 +
 392 +       /* Set loopback mode */
 393 +       if (mode & SPI_LOOP)
 394 +               con_set |= SPI_CON_LB;
 395 +       else
 396 +               con_clr |= SPI_CON_LB;
 397 +
 398 +       lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON);
 399 +}
 400 +
 401 +static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
 402 +{
 403 +       const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
 404 +
 405 +       /*
 406 +        * Set clock divider for run mode to 1 to
 407 +        * run at same frequency as FPI bus
 408 +        */
 409 +       lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC);
 410 +
 411 +       /* Put controller into config mode */
 412 +       hw_enter_config_mode(spi);
 413 +
 414 +       /* Clear error flags */
 415 +       lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
 416 +
 417 +       /* Enable error checking, disable TX/RX */
 418 +       lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN |
 419 +               SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
 420 +
 421 +       /* Setup default SPI mode */
 422 +       hw_setup_bits_per_word(spi, spi->bits_per_word);
 423 +       hw_setup_clock_mode(spi, SPI_MODE_0);
 424 +
 425 +       /* Enable master mode and clear error flags */
 426 +       lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS,
 427 +                              SPI_WHBSTATE);
 428 +
 429 +       /* Reset GPIO/CS registers */
 430 +       lantiq_ssc_writel(spi, 0, SPI_GPOCON);
 431 +       lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO);
 432 +
 433 +       /* Enable and flush FIFOs */
 434 +       rx_fifo_reset(spi);
 435 +       tx_fifo_reset(spi);
 436 +
 437 +       /* Enable interrupts */
 438 +       lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E,
 439 +                         SPI_IRNEN);
 440 +}
 441 +
 442 +static int lantiq_ssc_setup(struct spi_device *spidev)
 443 +{
 444 +       struct spi_master *master = spidev->master;
 445 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 446 +       unsigned int cs = spidev->chip_select;
 447 +       u32 gpocon;
 448 +
 449 +       /* GPIOs are used for CS */
 450 +       if (gpio_is_valid(spidev->cs_gpio))
 451 +               return 0;
 452 +
 453 +       dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
 454 +
 455 +       if (cs < spi->base_cs) {
 456 +               dev_err(spi->dev,
 457 +                       "chipselect %i too small (min %i)\n", cs, spi->base_cs);
 458 +               return -EINVAL;
 459 +       }
 460 +
 461 +       /* set GPO pin to CS mode */
 462 +       gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S);
 463 +
 464 +       /* invert GPO pin */
 465 +       if (spidev->mode & SPI_CS_HIGH)
 466 +               gpocon |= 1 << (cs - spi->base_cs);
 467 +
 468 +       lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON);
 469 +
 470 +       return 0;
 471 +}
 472 +
 473 +static int lantiq_ssc_prepare_message(struct spi_master *master,
 474 +                                     struct spi_message *message)
 475 +{
 476 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 477 +
 478 +       hw_enter_config_mode(spi);
 479 +       hw_setup_clock_mode(spi, message->spi->mode);
 480 +       hw_enter_active_mode(spi);
 481 +
 482 +       return 0;
 483 +}
 484 +
 485 +static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
 486 +                             struct spi_device *spidev, struct spi_transfer *t)
 487 +{
 488 +       unsigned int speed_hz = t->speed_hz;
 489 +       unsigned int bits_per_word = t->bits_per_word;
 490 +       u32 con;
 491 +
 492 +       if (bits_per_word != spi->bits_per_word ||
 493 +               speed_hz != spi->speed_hz) {
 494 +               hw_enter_config_mode(spi);
 495 +               hw_setup_speed_hz(spi, speed_hz);
 496 +               hw_setup_bits_per_word(spi, bits_per_word);
 497 +               hw_enter_active_mode(spi);
 498 +
 499 +               spi->speed_hz = speed_hz;
 500 +               spi->bits_per_word = bits_per_word;
 501 +       }
 502 +
 503 +       /* Configure transmitter and receiver */
 504 +       con = lantiq_ssc_readl(spi, SPI_CON);
 505 +       if (t->tx_buf)
 506 +               con &= ~SPI_CON_TXOFF;
 507 +       else
 508 +               con |= SPI_CON_TXOFF;
 509 +
 510 +       if (t->rx_buf)
 511 +               con &= ~SPI_CON_RXOFF;
 512 +       else
 513 +               con |= SPI_CON_RXOFF;
 514 +
 515 +       lantiq_ssc_writel(spi, con, SPI_CON);
 516 +}
 517 +
 518 +static int lantiq_ssc_unprepare_message(struct spi_master *master,
 519 +                                       struct spi_message *message)
 520 +{
 521 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 522 +
 523 +       /* Disable transmitter and receiver while idle */
 524 +       lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
 525 +
 526 +       return 0;
 527 +}
 528 +
 529 +static void tx_fifo_write(struct lantiq_ssc_spi *spi)
 530 +{
 531 +       const u8 *tx8;
 532 +       const u16 *tx16;
 533 +       const u32 *tx32;
 534 +       u32 data;
 535 +       unsigned int tx_free = tx_fifo_free(spi);
 536 +
 537 +       while (spi->tx_todo && tx_free) {
 538 +               switch (spi->bits_per_word) {
 539 +               case 2 ... 8:
 540 +                       tx8 = spi->tx;
 541 +                       data = *tx8;
 542 +                       spi->tx_todo--;
 543 +                       spi->tx++;
 544 +                       break;
 545 +               case 16:
 546 +                       tx16 = (u16 *) spi->tx;
 547 +                       data = *tx16;
 548 +                       spi->tx_todo -= 2;
 549 +                       spi->tx += 2;
 550 +                       break;
 551 +               case 32:
 552 +                       tx32 = (u32 *) spi->tx;
 553 +                       data = *tx32;
 554 +                       spi->tx_todo -= 4;
 555 +                       spi->tx += 4;
 556 +                       break;
 557 +               default:
 558 +                       WARN_ON(1);
 559 +                       data = 0;
 560 +                       break;
 561 +               }
 562 +
 563 +               lantiq_ssc_writel(spi, data, SPI_TB);
 564 +               tx_free--;
 565 +       }
 566 +}
 567 +
 568 +static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
 569 +{
 570 +       u8 *rx8;
 571 +       u16 *rx16;
 572 +       u32 *rx32;
 573 +       u32 data;
 574 +       unsigned int rx_fill = rx_fifo_level(spi);
 575 +
 576 +       while (rx_fill) {
 577 +               data = lantiq_ssc_readl(spi, SPI_RB);
 578 +
 579 +               switch (spi->bits_per_word) {
 580 +               case 2 ... 8:
 581 +                       rx8 = spi->rx;
 582 +                       *rx8 = data;
 583 +                       spi->rx_todo--;
 584 +                       spi->rx++;
 585 +                       break;
 586 +               case 16:
 587 +                       rx16 = (u16 *) spi->rx;
 588 +                       *rx16 = data;
 589 +                       spi->rx_todo -= 2;
 590 +                       spi->rx += 2;
 591 +                       break;
 592 +               case 32:
 593 +                       rx32 = (u32 *) spi->rx;
 594 +                       *rx32 = data;
 595 +                       spi->rx_todo -= 4;
 596 +                       spi->rx += 4;
 597 +                       break;
 598 +               default:
 599 +                       WARN_ON(1);
 600 +                       break;
 601 +               }
 602 +
 603 +               rx_fill--;
 604 +       }
 605 +}
 606 +
 607 +static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
 608 +{
 609 +       u32 data, *rx32;
 610 +       u8 *rx8;
 611 +       unsigned int rxbv, shift;
 612 +       unsigned int rx_fill = rx_fifo_level(spi);
 613 +
 614 +       /*
 615 +        * In RX-only mode the bits per word value is ignored by HW. A value
 616 +        * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
 617 +        * If remaining RX bytes are less than 4, the FIFO must be read
 618 +        * differently. The amount of received and valid bytes is indicated
 619 +        * by STAT.RXBV register value.
 620 +        */
 621 +       while (rx_fill) {
 622 +               if (spi->rx_todo < 4)  {
 623 +                       rxbv = (lantiq_ssc_readl(spi, SPI_STAT) &
 624 +                               SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S;
 625 +                       data = lantiq_ssc_readl(spi, SPI_RB);
 626 +
 627 +                       shift = (rxbv - 1) * 8;
 628 +                       rx8 = spi->rx;
 629 +
 630 +                       while (rxbv) {
 631 +                               *rx8++ = (data >> shift) & 0xFF;
 632 +                               rxbv--;
 633 +                               shift -= 8;
 634 +                               spi->rx_todo--;
 635 +                               spi->rx++;
 636 +                       }
 637 +               } else {
 638 +                       data = lantiq_ssc_readl(spi, SPI_RB);
 639 +                       rx32 = (u32 *) spi->rx;
 640 +
 641 +                       *rx32++ = data;
 642 +                       spi->rx_todo -= 4;
 643 +                       spi->rx += 4;
 644 +               }
 645 +               rx_fill--;
 646 +       }
 647 +}
 648 +
 649 +static void rx_request(struct lantiq_ssc_spi *spi)
 650 +{
 651 +       unsigned int rxreq, rxreq_max;
 652 +
 653 +       /*
 654 +        * To avoid receive overflows at high clocks it is better to request
 655 +        * only the amount of bytes that fits into all FIFOs. This value
 656 +        * depends on the FIFO size implemented in hardware.
 657 +        */
 658 +       rxreq = spi->rx_todo;
 659 +       rxreq_max = spi->rx_fifo_size * 4;
 660 +       if (rxreq > rxreq_max)
 661 +               rxreq = rxreq_max;
 662 +
 663 +       lantiq_ssc_writel(spi, rxreq, SPI_RXREQ);
 664 +}
 665 +
 666 +static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
 667 +{
 668 +       struct lantiq_ssc_spi *spi = data;
 669 +
 670 +       if (spi->tx) {
 671 +               if (spi->rx && spi->rx_todo)
 672 +                       rx_fifo_read_full_duplex(spi);
 673 +
 674 +               if (spi->tx_todo)
 675 +                       tx_fifo_write(spi);
 676 +               else if (!tx_fifo_level(spi))
 677 +                       goto completed;
 678 +       } else if (spi->rx) {
 679 +               if (spi->rx_todo) {
 680 +                       rx_fifo_read_half_duplex(spi);
 681 +
 682 +                       if (spi->rx_todo)
 683 +                               rx_request(spi);
 684 +                       else
 685 +                               goto completed;
 686 +               } else {
 687 +                       goto completed;
 688 +               }
 689 +       }
 690 +
 691 +       return IRQ_HANDLED;
 692 +
 693 +completed:
 694 +       spi->status = 0;
 695 +       spi_finalize_current_transfer(spi->master);
 696 +
 697 +       return IRQ_HANDLED;
 698 +}
 699 +
 700 +static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
 701 +{
 702 +       struct lantiq_ssc_spi *spi = data;
 703 +       u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
 704 +
 705 +       if (!(stat & SPI_STAT_ERRORS))
 706 +               return IRQ_NONE;
 707 +
 708 +       if (stat & SPI_STAT_RUE)
 709 +               dev_err(spi->dev, "receive underflow error\n");
 710 +       if (stat & SPI_STAT_TUE)
 711 +               dev_err(spi->dev, "transmit underflow error\n");
 712 +       if (stat & SPI_STAT_AE)
 713 +               dev_err(spi->dev, "abort error\n");
 714 +       if (stat & SPI_STAT_RE)
 715 +               dev_err(spi->dev, "receive overflow error\n");
 716 +       if (stat & SPI_STAT_TE)
 717 +               dev_err(spi->dev, "transmit overflow error\n");
 718 +       if (stat & SPI_STAT_ME)
 719 +               dev_err(spi->dev, "mode error\n");
 720 +
 721 +       /* Clear error flags */
 722 +       lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
 723 +
 724 +       /* set bad status so it can be retried */
 725 +       spi->status = -EIO;
 726 +       spi_finalize_current_transfer(spi->master);
 727 +
 728 +       return IRQ_HANDLED;
 729 +}
 730 +
 731 +static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
 732 +                         struct spi_transfer *t)
 733 +{
 734 +       unsigned long flags;
 735 +
 736 +       spin_lock_irqsave(&spi->lock, flags);
 737 +
 738 +       spi->tx = t->tx_buf;
 739 +       spi->rx = t->rx_buf;
 740 +       spi->status = -EINPROGRESS;
 741 +
 742 +       if (t->tx_buf) {
 743 +               spi->tx_todo = t->len;
 744 +
 745 +               /* initially fill TX FIFO */
 746 +               tx_fifo_write(spi);
 747 +       }
 748 +
 749 +       if (spi->rx) {
 750 +               spi->rx_todo = t->len;
 751 +
 752 +               /* start shift clock in RX-only mode */
 753 +               if (!spi->tx)
 754 +                       rx_request(spi);
 755 +       }
 756 +
 757 +       spin_unlock_irqrestore(&spi->lock, flags);
 758 +
 759 +       return t->len;
 760 +}
 761 +
 762 +static int lantiq_ssc_transfer_status(struct spi_master *master,
 763 +                                     unsigned long timeout)
 764 +{
 765 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 766 +       unsigned long end;
 767 +
 768 +       /*
 769 +        * The driver only gets an interrupt when the FIFO is empty, but there
 770 +        * is an additional shift register from which the data is written to
 771 +        * the wire. We get the last interrupt when the controller starts to
 772 +        * write the last word to the wire, not when it is finished. Do busy
 773 +        * waiting till it finishes.
 774 +        */
 775 +       end = jiffies + timeout;
 776 +       do {
 777 +               u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
 778 +
 779 +               if (!(stat & SPI_STAT_BSY))
 780 +                       return spi->status;
 781 +
 782 +               cond_resched();
 783 +       } while (!time_after_eq(jiffies, end));
 784 +
 785 +       return -ETIMEDOUT;
 786 +}
 787 +
 788 +static void lantiq_ssc_handle_err(struct spi_master *master,
 789 +                                 struct spi_message *message)
 790 +{
 791 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 792 +
 793 +       /* flush FIFOs on timeout */
 794 +       rx_fifo_flush(spi);
 795 +       tx_fifo_flush(spi);
 796 +}
 797 +
 798 +static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
 799 +{
 800 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
 801 +       unsigned int cs = spidev->chip_select;
 802 +       u32 fgpo;
 803 +
 804 +       if (!!(spidev->mode & SPI_CS_HIGH) == enable)
 805 +               fgpo = (1 << (cs - spi->base_cs));
 806 +       else
 807 +               fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S));
 808 +
 809 +       lantiq_ssc_writel(spi, fgpo, SPI_FPGO);
 810 +}
 811 +
 812 +static int lantiq_ssc_transfer_one(struct spi_master *master,
 813 +                                  struct spi_device *spidev,
 814 +                                  struct spi_transfer *t)
 815 +{
 816 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 817 +
 818 +       hw_setup_transfer(spi, spidev, t);
 819 +
 820 +       return transfer_start(spi, spidev, t);
 821 +}
 822 +
 823 +static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
 824 +       .irnen_r = SPI_IRNEN_R_XWAY,
 825 +       .irnen_t = SPI_IRNEN_T_XWAY,
 826 +};
 827 +
 828 +static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
 829 +       .irnen_r = SPI_IRNEN_R_XRX,
 830 +       .irnen_t = SPI_IRNEN_T_XRX,
 831 +};
 832 +
 833 +static const struct of_device_id lantiq_ssc_match[] = {
 834 +       { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
 835 +       { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
 836 +       { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
 837 +       {},
 838 +};
 839 +MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
 840 +
 841 +static int lantiq_ssc_probe(struct platform_device *pdev)
 842 +{
 843 +       struct spi_master *master;
 844 +       struct resource *res;
 845 +       struct lantiq_ssc_spi *spi;
 846 +       const struct lantiq_ssc_hwcfg *hwcfg;
 847 +       const struct of_device_id *match;
 848 +       int err, rx_irq, tx_irq, err_irq;
 849 +       u32 id, supports_dma, revision;
 850 +       unsigned int num_cs;
 851 +
 852 +       match = of_match_device(lantiq_ssc_match, &pdev->dev);
 853 +       if (!match) {
 854 +               dev_err(&pdev->dev, "no device match\n");
 855 +               return -EINVAL;
 856 +       }
 857 +       hwcfg = match->data;
 858 +
 859 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 860 +       if (!res) {
 861 +               dev_err(&pdev->dev, "failed to get resources\n");
 862 +               return -ENXIO;
 863 +       }
 864 +
 865 +       rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME);
 866 +       if (rx_irq < 0) {
 867 +               dev_err(&pdev->dev, "failed to get %s\n", SPI_RX_IRQ_NAME);
 868 +               return -ENXIO;
 869 +       }
 870 +
 871 +       tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME);
 872 +       if (tx_irq < 0) {
 873 +               dev_err(&pdev->dev, "failed to get %s\n", SPI_TX_IRQ_NAME);
 874 +               return -ENXIO;
 875 +       }
 876 +
 877 +       err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME);
 878 +       if (err_irq < 0) {
 879 +               dev_err(&pdev->dev, "failed to get %s\n", SPI_ERR_IRQ_NAME);
 880 +               return -ENXIO;
 881 +       }
 882 +
 883 +       master = spi_alloc_master(&pdev->dev, sizeof(struct lantiq_ssc_spi));
 884 +       if (!master)
 885 +               return -ENOMEM;
 886 +
 887 +       spi = spi_master_get_devdata(master);
 888 +       spi->master = master;
 889 +       spi->dev = &pdev->dev;
 890 +       spi->hwcfg = hwcfg;
 891 +       platform_set_drvdata(pdev, spi);
 892 +
 893 +       spi->regbase = devm_ioremap_resource(&pdev->dev, res);
 894 +       if (IS_ERR(spi->regbase)) {
 895 +               err = PTR_ERR(spi->regbase);
 896 +               goto err_master_put;
 897 +       }
 898 +
 899 +       err = devm_request_irq(&pdev->dev, rx_irq, lantiq_ssc_xmit_interrupt,
 900 +                              0, SPI_RX_IRQ_NAME, spi);
 901 +       if (err)
 902 +               goto err_master_put;
 903 +
 904 +       err = devm_request_irq(&pdev->dev, tx_irq, lantiq_ssc_xmit_interrupt,
 905 +                              0, SPI_TX_IRQ_NAME, spi);
 906 +       if (err)
 907 +               goto err_master_put;
 908 +
 909 +       err = devm_request_irq(&pdev->dev, err_irq, lantiq_ssc_err_interrupt,
 910 +                              0, SPI_ERR_IRQ_NAME, spi);
 911 +       if (err)
 912 +               goto err_master_put;
 913 +
 914 +       spi->spi_clk = devm_clk_get(&pdev->dev, NULL);
 915 +       if (IS_ERR(spi->spi_clk)) {
 916 +               err = PTR_ERR(spi->spi_clk);
 917 +               goto err_master_put;
 918 +       }
 919 +       err = clk_prepare_enable(spi->spi_clk);
 920 +       if (err)
 921 +               goto err_master_put;
 922 +
 923 +       spi->fpi_clk = clk_get_fpi();
 924 +       if (IS_ERR(spi->fpi_clk)) {
 925 +               err = PTR_ERR(spi->fpi_clk);
 926 +               goto err_clk_disable;
 927 +       }
 928 +
 929 +       num_cs = 8;
 930 +       of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
 931 +
 932 +       spi->base_cs = 1;
 933 +       of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
 934 +
 935 +       spin_lock_init(&spi->lock);
 936 +       spi->bits_per_word = 8;
 937 +       spi->speed_hz = 0;
 938 +
 939 +       master->dev.of_node = pdev->dev.of_node;
 940 +       master->num_chipselect = num_cs;
 941 +       master->setup = lantiq_ssc_setup;
 942 +       master->set_cs = lantiq_ssc_set_cs;
 943 +       master->handle_err = lantiq_ssc_handle_err;
 944 +       master->prepare_message = lantiq_ssc_prepare_message;
 945 +       master->unprepare_message = lantiq_ssc_unprepare_message;
 946 +       master->transfer_one = lantiq_ssc_transfer_one;
 947 +       master->transfer_status = lantiq_ssc_transfer_status;
 948 +       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
 949 +                               SPI_LOOP;
 950 +       master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
 951 +                                    SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
 952 +
 953 +       id = lantiq_ssc_readl(spi, SPI_ID);
 954 +       spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S;
 955 +       spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S;
 956 +       supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S;
 957 +       revision = id & SPI_ID_REV_M;
 958 +
 959 +       lantiq_ssc_hw_init(spi);
 960 +
 961 +       dev_info(&pdev->dev,
 962 +               "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
 963 +               revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
 964 +
 965 +       err = devm_spi_register_master(&pdev->dev, master);
 966 +       if (err) {
 967 +               dev_err(&pdev->dev, "failed to register spi_master\n");
 968 +               goto err_clk_put;
 969 +       }
 970 +
 971 +       return 0;
 972 +
 973 +err_clk_put:
 974 +       clk_put(spi->fpi_clk);
 975 +err_clk_disable:
 976 +       clk_disable_unprepare(spi->spi_clk);
 977 +err_master_put:
 978 +       spi_master_put(master);
 979 +
 980 +       return err;
 981 +}
 982 +
 983 +static int lantiq_ssc_remove(struct platform_device *pdev)
 984 +{
 985 +       struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
 986 +
 987 +       lantiq_ssc_writel(spi, 0, SPI_IRNEN);
 988 +       lantiq_ssc_writel(spi, 0, SPI_CLC);
 989 +       rx_fifo_flush(spi);
 990 +       tx_fifo_flush(spi);
 991 +       hw_enter_config_mode(spi);
 992 +
 993 +       clk_disable_unprepare(spi->spi_clk);
 994 +       clk_put(spi->fpi_clk);
 995 +
 996 +       return 0;
 997 +}
 998 +
 999 +static struct platform_driver lantiq_ssc_driver = {
1000 +       .probe = lantiq_ssc_probe,
1001 +       .remove = lantiq_ssc_remove,
1002 +       .driver = {
1003 +               .name = "spi-lantiq-ssc",
1004 +               .owner = THIS_MODULE,
1005 +               .of_match_table = lantiq_ssc_match,
1006 +       },
1007 +};
1008 +module_platform_driver(lantiq_ssc_driver);
1009 +
1010 +MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
1011 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
1012 +MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
1013 +MODULE_LICENSE("GPL");
1014 +MODULE_ALIAS("platform:spi-lantiq-ssc");