target/linux/lantiq/patches-5.4/0112-MIPS-lantiq-dma-fix-burst-length-for-DEU.patch

   1 From 7d9ea9052d6680d2910b8b005c397d95b3a8b012 Mon Sep 17 00:00:00 2001
   2 From: Aleksander Jan Bajkowski <olek2@wp.pl>
   3 Date: Wed, 7 Apr 2021 21:04:39 +0200
   4 Subject: [PATCH 3/5] MIPS: lantiq: dma: fix burst length for DEU
   5
   6 The current definition of 2W burst length is invalid.
   7 This patch fixes it. Current downstream DEU driver doesn't
   8 use DMA. An incorrect burst length value doesn't cause any
   9 errors. This patch also adds other burst length values.
  10
  11 Fixes: dfec1a827d2b ("MIPS: Lantiq: Add DMA support")
  12 Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
  13 ---
  14  arch/mips/lantiq/xway/dma.c | 9 +++++++--
  15  1 file changed, 7 insertions(+), 2 deletions(-)
  16
  17 --- a/arch/mips/lantiq/xway/dma.c
  18 +++ b/arch/mips/lantiq/xway/dma.c
  19 @@ -40,7 +40,11 @@
  20  #define DMA_IRQ_ACK            0x7e            /* IRQ status register */
  21  #define DMA_POLL               BIT(31)         /* turn on channel polling */
  22  #define DMA_CLK_DIV4           BIT(6)          /* polling clock divider */
  23 -#define DMA_2W_BURST           BIT(1)          /* 2 word burst length */
  24 +#define DMA_PCTRL_2W_BURST     0x1             /* 2 word burst length */
  25 +#define DMA_PCTRL_4W_BURST     0x2             /* 4 word burst length */
  26 +#define DMA_PCTRL_8W_BURST     0x3             /* 8 word burst length */
  27 +#define DMA_TX_BURST_SHIFT     4               /* tx burst shift */
  28 +#define DMA_RX_BURST_SHIFT     2               /* rx burst shift */
  29  #define DMA_ETOP_ENDIANNESS    (0xf << 8) /* endianness swap etop channels */
  30  #define DMA_WEIGHT     (BIT(17) | BIT(16))     /* default channel wheight */
  31
  32 @@ -191,7 +195,8 @@ ltq_dma_init_port(int p)
  33                 break;
  34
  35         case DMA_PORT_DEU:
  36 -               ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
  37 +               ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
  38 +                       (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
  39                         LTQ_DMA_PCTRL);
  40                 break;
  41