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kernel: bump 4.14 to 4.14.156
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.14 / 807-usb-support-layerscape.patch
1 From ca86ebf3fddbdfa8aecc4b887ef059948ee79621 Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Wed, 17 Apr 2019 18:59:08 +0800
4 Subject: [PATCH] usb: support layerscape
5
6 This is an integrated patch of usb for layerscape
7
8 Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
9 Signed-off-by: Biwen Li <biwen.li@nxp.com>
10 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
11 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
12 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
13 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Signed-off-by: Li Yang <leoli@freescale.com>
15 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
16 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
17 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
18 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
19 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
20 Signed-off-by: Roger Quadros <rogerq@ti.com>
21 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
22 Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
23 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
24 Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
25 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
26 ---
27 arch/arm64/include/asm/io.h | 28 +++
28 drivers/usb/common/common.c | 50 +++++
29 drivers/usb/core/usb.c | 1 +
30 drivers/usb/dwc3/core.c | 167 ++++++++++++++++
31 drivers/usb/dwc3/core.h | 58 ++++++
32 drivers/usb/dwc3/ep0.c | 4 +-
33 drivers/usb/dwc3/gadget.c | 7 +
34 drivers/usb/dwc3/host.c | 9 +
35 drivers/usb/gadget/udc/fsl_udc_core.c | 46 +++--
36 drivers/usb/gadget/udc/fsl_usb2_udc.h | 16 +-
37 drivers/usb/host/Kconfig | 2 +-
38 drivers/usb/host/ehci-fsl.c | 276 +++++++++++++++++++++++---
39 drivers/usb/host/ehci-fsl.h | 3 +
40 drivers/usb/host/ehci-hub.c | 2 +
41 drivers/usb/host/ehci.h | 3 +
42 drivers/usb/host/fsl-mph-dr-of.c | 11 +
43 drivers/usb/host/xhci-hub.c | 22 ++
44 drivers/usb/host/xhci-plat.c | 16 +-
45 drivers/usb/host/xhci-ring.c | 28 ++-
46 drivers/usb/host/xhci.c | 37 +++-
47 drivers/usb/host/xhci.h | 10 +-
48 drivers/usb/phy/phy-fsl-usb.c | 59 ++++--
49 drivers/usb/phy/phy-fsl-usb.h | 8 +
50 include/linux/usb.h | 1 +
51 include/linux/usb/of.h | 2 +
52 25 files changed, 780 insertions(+), 86 deletions(-)
53
54 --- a/arch/arm64/include/asm/io.h
55 +++ b/arch/arm64/include/asm/io.h
56 @@ -210,6 +210,34 @@ extern void __iomem *ioremap_cache(phys_
57 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
58 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
59
60 +/* access ports */
61 +#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
62 +#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
63 +
64 +#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
65 +#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
66 +
67 +#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
68 +#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
69 +
70 +/* Clear and set bits in one shot. These macros can be used to clear and
71 + * set multiple bits in a register using a single read-modify-write. These
72 + * macros can also be used to set a multiple-bit bit pattern using a mask,
73 + * by specifying the mask in the 'clear' parameter and the new bit pattern
74 + * in the 'set' parameter.
75 + */
76 +
77 +#define clrsetbits_be32(addr, clear, set) \
78 + iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
79 +#define clrsetbits_le32(addr, clear, set) \
80 + iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
81 +#define clrsetbits_be16(addr, clear, set) \
82 + iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
83 +#define clrsetbits_le16(addr, clear, set) \
84 + iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
85 +#define clrsetbits_8(addr, clear, set) \
86 + iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
87 +
88 #include <asm-generic/io.h>
89
90 /*
91 --- a/drivers/usb/common/common.c
92 +++ b/drivers/usb/common/common.c
93 @@ -105,6 +105,56 @@ static const char *const usb_dr_modes[]
94 [USB_DR_MODE_OTG] = "otg",
95 };
96
97 +/**
98 + * of_usb_get_dr_mode - Get dual role mode for given device_node
99 + * @np: Pointer to the given device_node
100 + *
101 + * The function gets phy interface string from property 'dr_mode',
102 + * and returns the correspondig enum usb_dr_mode
103 + */
104 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
105 +{
106 + const char *dr_mode;
107 + int err, i;
108 +
109 + err = of_property_read_string(np, "dr_mode", &dr_mode);
110 + if (err < 0)
111 + return USB_DR_MODE_UNKNOWN;
112 +
113 + for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
114 + if (!strcmp(dr_mode, usb_dr_modes[i]))
115 + return i;
116 +
117 + return USB_DR_MODE_UNKNOWN;
118 +}
119 +EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
120 +
121 +/**
122 + * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
123 + * controller.
124 + * @np: Pointer to the given device_node
125 + *
126 + * The function gets the maximum speed string from property "maximum-speed",
127 + * and returns the corresponding enum usb_device_speed.
128 + */
129 +enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
130 +{
131 + const char *maximum_speed;
132 + int err;
133 + int i;
134 +
135 + err = of_property_read_string(np, "maximum-speed", &maximum_speed);
136 + if (err < 0)
137 + return USB_SPEED_UNKNOWN;
138 +
139 + for (i = 0; i < ARRAY_SIZE(speed_names); i++)
140 + if (strcmp(maximum_speed, speed_names[i]) == 0)
141 + return i;
142 +
143 + return USB_SPEED_UNKNOWN;
144 +}
145 +EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
146 +
147 static enum usb_dr_mode usb_get_dr_mode_from_string(const char *str)
148 {
149 int ret;
150 --- a/drivers/usb/core/usb.c
151 +++ b/drivers/usb/core/usb.c
152 @@ -593,6 +593,7 @@ struct usb_device *usb_alloc_dev(struct
153 dev->dev.dma_mask = bus->sysdev->dma_mask;
154 dev->dev.dma_pfn_offset = bus->sysdev->dma_pfn_offset;
155 set_dev_node(&dev->dev, dev_to_node(bus->sysdev));
156 + dev->dev.of_node = bus->controller->of_node;
157 dev->state = USB_STATE_ATTACHED;
158 dev->lpm_disable_count = 1;
159 atomic_set(&dev->urbnum, 0);
160 --- a/drivers/usb/dwc3/core.c
161 +++ b/drivers/usb/dwc3/core.c
162 @@ -103,6 +103,41 @@ static int dwc3_get_dr_mode(struct dwc3
163 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
164 static int dwc3_event_buffers_setup(struct dwc3 *dwc);
165
166 +/*
167 + * dwc3_power_of_all_roothub_ports - Power off all Root hub ports
168 + * @dwc3: Pointer to our controller context structure
169 + */
170 +static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc)
171 +{
172 + int i, port_num;
173 + u32 reg, op_regs_base, offset;
174 + void __iomem *xhci_regs;
175 +
176 + /* xhci regs is not mapped yet, do it temperary here */
177 + if (dwc->xhci_resources[0].start) {
178 + xhci_regs = ioremap(dwc->xhci_resources[0].start,
179 + DWC3_XHCI_REGS_END);
180 + if (IS_ERR(xhci_regs)) {
181 + dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
182 + return;
183 + }
184 +
185 + op_regs_base = HC_LENGTH(readl(xhci_regs));
186 + reg = readl(xhci_regs + XHCI_HCSPARAMS1);
187 + port_num = HCS_MAX_PORTS(reg);
188 +
189 + for (i = 1; i <= port_num; i++) {
190 + offset = op_regs_base + XHCI_PORTSC_BASE + 0x10*(i-1);
191 + reg = readl(xhci_regs + offset);
192 + reg &= ~PORT_POWER;
193 + writel(reg, xhci_regs + offset);
194 + }
195 +
196 + iounmap(xhci_regs);
197 + } else
198 + dev_err(dwc->dev, "xhci base reg invalid\n");
199 +}
200 +
201 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
202 {
203 u32 reg;
204 @@ -111,6 +146,15 @@ static void dwc3_set_prtcap(struct dwc3
205 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
206 reg |= DWC3_GCTL_PRTCAPDIR(mode);
207 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
208 +
209 + /*
210 + * We have to power off all Root hub ports immediately after DWC3 set
211 + * to host mode to avoid VBUS glitch happen when xhci get reset later.
212 + */
213 + if (dwc->host_vbus_glitches) {
214 + if (mode == DWC3_GCTL_PRTCAP_HOST)
215 + dwc3_power_off_all_roothub_ports(dwc);
216 + }
217 }
218
219 static void __dwc3_set_mode(struct work_struct *work)
220 @@ -765,6 +809,96 @@ static void dwc3_core_setup_global_contr
221 static int dwc3_core_get_phy(struct dwc3 *dwc);
222 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
223
224 +/* set global soc bus configuration registers */
225 +static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
226 +{
227 + struct device *dev = dwc->dev;
228 + u32 *vals;
229 + u32 cfg;
230 + int ntype;
231 + int ret;
232 + int i;
233 +
234 + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
235 +
236 + /*
237 + * Handle property "snps,incr-burst-type-adjustment".
238 + * Get the number of value from this property:
239 + * result <= 0, means this property is not supported.
240 + * result = 1, means INCRx burst mode supported.
241 + * result > 1, means undefined length burst mode supported.
242 + */
243 + ntype = device_property_read_u32_array(dev,
244 + "snps,incr-burst-type-adjustment", NULL, 0);
245 + if (ntype > 0) {
246 + vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
247 + if (!vals) {
248 + dev_err(dev, "Error to get memory\n");
249 + return;
250 + }
251 + /* Get INCR burst type, and parse it */
252 + ret = device_property_read_u32_array(dev,
253 + "snps,incr-burst-type-adjustment", vals, ntype);
254 + if (ret) {
255 + dev_err(dev, "Error to get property\n");
256 + return;
257 + }
258 + *(dwc->incrx_type + 1) = vals[0];
259 + if (ntype > 1) {
260 + *dwc->incrx_type = 1;
261 + for (i = 1; i < ntype; i++) {
262 + if (vals[i] > *(dwc->incrx_type + 1))
263 + *(dwc->incrx_type + 1) = vals[i];
264 + }
265 + } else
266 + *dwc->incrx_type = 0;
267 +
268 + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
269 + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
270 + if (*dwc->incrx_type)
271 + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
272 + switch (*(dwc->incrx_type + 1)) {
273 + case 256:
274 + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
275 + break;
276 + case 128:
277 + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
278 + break;
279 + case 64:
280 + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
281 + break;
282 + case 32:
283 + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
284 + break;
285 + case 16:
286 + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
287 + break;
288 + case 8:
289 + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
290 + break;
291 + case 4:
292 + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
293 + break;
294 + case 1:
295 + break;
296 + default:
297 + dev_err(dev, "Invalid property\n");
298 + break;
299 + }
300 + }
301 +
302 + /* Handle usb snooping */
303 + if (dwc->dma_coherent) {
304 + cfg &= ~DWC3_GSBUSCFG0_SNP_MASK;
305 + cfg |= (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATARD_SHIFT) |
306 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCRD_SHIFT) |
307 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATAWR_SHIFT) |
308 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCWR_SHIFT);
309 + }
310 +
311 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
312 +}
313 +
314 /**
315 * dwc3_core_init - Low-level initialization of DWC3 Core
316 * @dwc: Pointer to our controller context structure
317 @@ -827,6 +961,8 @@ static int dwc3_core_init(struct dwc3 *d
318 /* Adjust Frame Length */
319 dwc3_frame_length_adjustment(dwc);
320
321 + dwc3_set_soc_bus_cfg(dwc);
322 +
323 usb_phy_set_suspend(dwc->usb2_phy, 0);
324 usb_phy_set_suspend(dwc->usb3_phy, 0);
325 ret = phy_power_on(dwc->usb2_generic_phy);
326 @@ -870,6 +1006,22 @@ static int dwc3_core_init(struct dwc3 *d
327 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
328 }
329
330 + if (dwc->dr_mode == USB_DR_MODE_HOST ||
331 + dwc->dr_mode == USB_DR_MODE_OTG) {
332 + reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
333 +
334 + /*
335 + * Enable Auto retry Feature to make the controller operating in
336 + * Host mode on seeing transaction errors(CRC errors or internal
337 + * overrun scenerios) on IN transfers to reply to the device
338 + * with a non-terminating retry ACK (i.e, an ACK transcation
339 + * packet with Retry=1 & Nump != 0)
340 + */
341 + reg |= DWC3_GUCTL_HSTINAUTORETRY;
342 +
343 + dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
344 + }
345 +
346 return 0;
347
348 err4:
349 @@ -1073,6 +1225,8 @@ static void dwc3_get_properties(struct d
350 &hird_threshold);
351 dwc->usb3_lpm_capable = device_property_read_bool(dev,
352 "snps,usb3_lpm_capable");
353 + dwc->dma_coherent = device_property_read_bool(dev,
354 + "dma-coherent");
355
356 dwc->disable_scramble_quirk = device_property_read_bool(dev,
357 "snps,disable_scramble_quirk");
358 @@ -1105,8 +1259,16 @@ static void dwc3_get_properties(struct d
359 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
360 "snps,dis-tx-ipgap-linecheck-quirk");
361
362 + dwc->quirk_reverse_in_out = device_property_read_bool(dev,
363 + "snps,quirk_reverse_in_out");
364 + dwc->quirk_stop_transfer_in_block = device_property_read_bool(dev,
365 + "snps,quirk_stop_transfer_in_block");
366 + dwc->quirk_stop_ep_in_u1 = device_property_read_bool(dev,
367 + "snps,quirk_stop_ep_in_u1");
368 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
369 "snps,tx_de_emphasis_quirk");
370 + dwc->disable_devinit_u1u2_quirk = device_property_read_bool(dev,
371 + "snps,disable_devinit_u1u2");
372 device_property_read_u8(dev, "snps,tx_de_emphasis",
373 &tx_de_emphasis);
374 device_property_read_string(dev, "snps,hsphy_interface",
375 @@ -1117,6 +1279,9 @@ static void dwc3_get_properties(struct d
376 dwc->dis_metastability_quirk = device_property_read_bool(dev,
377 "snps,dis_metastability_quirk");
378
379 + dwc->host_vbus_glitches = device_property_read_bool(dev,
380 + "snps,host-vbus-glitches");
381 +
382 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
383 dwc->tx_de_emphasis = tx_de_emphasis;
384
385 @@ -1367,12 +1532,14 @@ static int dwc3_resume_common(struct dwc
386
387 switch (dwc->dr_mode) {
388 case USB_DR_MODE_PERIPHERAL:
389 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
390 case USB_DR_MODE_OTG:
391 spin_lock_irqsave(&dwc->lock, flags);
392 dwc3_gadget_resume(dwc);
393 spin_unlock_irqrestore(&dwc->lock, flags);
394 /* FALLTHROUGH */
395 case USB_DR_MODE_HOST:
396 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
397 default:
398 /* do nothing */
399 break;
400 --- a/drivers/usb/dwc3/core.h
401 +++ b/drivers/usb/dwc3/core.h
402 @@ -161,6 +161,32 @@
403
404 /* Bit fields */
405
406 +/* Global SoC Bus Configuration Register 0 */
407 +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */
408 +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */
409 +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */
410 +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */
411 +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
412 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
413 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
414 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
415 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000
416 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11)
417 +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10)
418 +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
419 +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
420 +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
421 +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
422 +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
423 +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
424 +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
425 +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
426 +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
427 +
428 +/* Global SoC Bus Configuration Register 1 */
429 +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */
430 +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00
431 +
432 /* Global Debug Queue/FIFO Space Available Register */
433 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
434 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
435 @@ -205,6 +231,9 @@
436 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
437 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
438
439 +/* Global User Control Register */
440 +#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
441 +
442 /* Global User Control 1 Register */
443 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
444 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
445 @@ -477,6 +506,14 @@
446 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
447 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
448
449 +/* Partial XHCI Register and Bit fields for quirk */
450 +#define XHCI_HCSPARAMS1 0x4
451 +#define XHCI_PORTSC_BASE 0x400
452 +#define PORT_POWER (1 << 9)
453 +#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
454 +#define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
455 +#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
456 +
457 /* Structures */
458
459 struct dwc3_trb;
460 @@ -788,6 +825,7 @@ struct dwc3_scratchpad_array {
461 * @regs: base address for our registers
462 * @regs_size: address space size
463 * @fladj: frame length adjustment
464 + * @incrx_type: INCR burst type adjustment
465 * @irq_gadget: peripheral controller's IRQ number
466 * @nr_scratch: number of scratch buffers
467 * @u1u2: only used on revisions <1.83a for workaround
468 @@ -843,6 +881,7 @@ struct dwc3_scratchpad_array {
469 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
470 * @three_stage_setup: set if we perform a three phase setup
471 * @usb3_lpm_capable: set if hadrware supports Link Power Management
472 + * @dma_coherent: set if hadrware supports DMA snoop
473 * @disable_scramble_quirk: set if we enable the disable scramble quirk
474 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
475 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
476 @@ -922,6 +961,12 @@ struct dwc3 {
477 enum usb_phy_interface hsphy_mode;
478
479 u32 fladj;
480 + /*
481 + * For INCR burst type.
482 + * First field: for undefined length INCR burst type enable.
483 + * Second field: for INCRx burst type enable
484 + */
485 + u32 incrx_type[2];
486 u32 irq_gadget;
487 u32 nr_scratch;
488 u32 u1u2;
489 @@ -1006,6 +1051,7 @@ struct dwc3 {
490 unsigned setup_packet_pending:1;
491 unsigned three_stage_setup:1;
492 unsigned usb3_lpm_capable:1;
493 + unsigned dma_coherent:1;
494
495 unsigned disable_scramble_quirk:1;
496 unsigned u2exit_lfps_quirk:1;
497 @@ -1025,6 +1071,11 @@ struct dwc3 {
498
499 unsigned tx_de_emphasis_quirk:1;
500 unsigned tx_de_emphasis:2;
501 + unsigned disable_devinit_u1u2_quirk:1;
502 + unsigned quirk_reverse_in_out:1;
503 + unsigned quirk_stop_transfer_in_block:1;
504 + unsigned quirk_stop_ep_in_u1:1;
505 + unsigned host_vbus_glitches:1;
506
507 unsigned dis_metastability_quirk:1;
508
509 --- a/drivers/usb/dwc3/ep0.c
510 +++ b/drivers/usb/dwc3/ep0.c
511 @@ -391,7 +391,7 @@ static int dwc3_ep0_handle_u1(struct dwc
512 return -EINVAL;
513
514 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
515 - if (set)
516 + if (set && !dwc->disable_devinit_u1u2_quirk)
517 reg |= DWC3_DCTL_INITU1ENA;
518 else
519 reg &= ~DWC3_DCTL_INITU1ENA;
520 @@ -413,7 +413,7 @@ static int dwc3_ep0_handle_u2(struct dwc
521 return -EINVAL;
522
523 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
524 - if (set)
525 + if (set && !dwc->disable_devinit_u1u2_quirk)
526 reg |= DWC3_DCTL_INITU2ENA;
527 else
528 reg &= ~DWC3_DCTL_INITU2ENA;
529 --- a/drivers/usb/dwc3/gadget.c
530 +++ b/drivers/usb/dwc3/gadget.c
531 @@ -3220,6 +3220,7 @@ int dwc3_gadget_init(struct dwc3 *dwc)
532 {
533 int ret;
534 int irq;
535 + u32 reg;
536
537 irq = dwc3_gadget_get_irq(dwc);
538 if (irq < 0) {
539 @@ -3299,6 +3300,12 @@ int dwc3_gadget_init(struct dwc3 *dwc)
540
541 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
542
543 + if (dwc->disable_devinit_u1u2_quirk) {
544 + reg = dwc3_readl(dwc->regs, DWC3_DCTL);
545 + reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
546 + dwc3_writel(dwc->regs, DWC3_DCTL, reg);
547 + }
548 +
549 return 0;
550
551 err4:
552 --- a/drivers/usb/dwc3/host.c
553 +++ b/drivers/usb/dwc3/host.c
554 @@ -98,6 +98,15 @@ int dwc3_host_init(struct dwc3 *dwc)
555
556 memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
557
558 + if (dwc->quirk_reverse_in_out)
559 + props[prop_idx++].name = "quirk-reverse-in-out";
560 +
561 + if (dwc->quirk_stop_transfer_in_block)
562 + props[prop_idx++].name = "quirk-stop-transfer-in-block";
563 +
564 + if (dwc->quirk_stop_ep_in_u1)
565 + props[prop_idx++].name = "quirk-stop-ep-in-u1";
566 +
567 if (dwc->usb3_lpm_capable)
568 props[prop_idx++].name = "usb3-lpm-capable";
569
570 --- a/drivers/usb/gadget/udc/fsl_udc_core.c
571 +++ b/drivers/usb/gadget/udc/fsl_udc_core.c
572 @@ -198,7 +198,11 @@ __acquires(ep->udc->lock)
573
574 spin_unlock(&ep->udc->lock);
575
576 - usb_gadget_giveback_request(&ep->ep, &req->req);
577 + /* this complete() should a func implemented by gadget layer,
578 + * eg fsg->bulk_in_complete()
579 + */
580 + if (req->req.complete)
581 + usb_gadget_giveback_request(&ep->ep, &req->req);
582
583 spin_lock(&ep->udc->lock);
584 ep->stopped = stopped;
585 @@ -245,10 +249,10 @@ static int dr_controller_setup(struct fs
586 if (udc->pdata->have_sysif_regs) {
587 if (udc->pdata->controller_ver) {
588 /* controller version 1.6 or above */
589 - ctrl = __raw_readl(&usb_sys_regs->control);
590 + ctrl = ioread32be(&usb_sys_regs->control);
591 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
592 ctrl |= USB_CTRL_USB_EN;
593 - __raw_writel(ctrl, &usb_sys_regs->control);
594 + iowrite32be(ctrl, &usb_sys_regs->control);
595 }
596 }
597 portctrl |= PORTSCX_PTS_ULPI;
598 @@ -257,13 +261,14 @@ static int dr_controller_setup(struct fs
599 portctrl |= PORTSCX_PTW_16BIT;
600 /* fall through */
601 case FSL_USB2_PHY_UTMI:
602 + case FSL_USB2_PHY_UTMI_DUAL:
603 if (udc->pdata->have_sysif_regs) {
604 if (udc->pdata->controller_ver) {
605 /* controller version 1.6 or above */
606 - ctrl = __raw_readl(&usb_sys_regs->control);
607 + ctrl = ioread32be(&usb_sys_regs->control);
608 ctrl |= (USB_CTRL_UTMI_PHY_EN |
609 USB_CTRL_USB_EN);
610 - __raw_writel(ctrl, &usb_sys_regs->control);
611 + iowrite32be(ctrl, &usb_sys_regs->control);
612 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
613 PHY CLK to become stable - 10ms*/
614 }
615 @@ -329,22 +334,22 @@ static int dr_controller_setup(struct fs
616 /* Config control enable i/o output, cpu endian register */
617 #ifndef CONFIG_ARCH_MXC
618 if (udc->pdata->have_sysif_regs) {
619 - ctrl = __raw_readl(&usb_sys_regs->control);
620 + ctrl = ioread32be(&usb_sys_regs->control);
621 ctrl |= USB_CTRL_IOENB;
622 - __raw_writel(ctrl, &usb_sys_regs->control);
623 + iowrite32be(ctrl, &usb_sys_regs->control);
624 }
625 #endif
626
627 -#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
628 +#if !defined(CONFIG_NOT_COHERENT_CACHE)
629 /* Turn on cache snooping hardware, since some PowerPC platforms
630 * wholly rely on hardware to deal with cache coherent. */
631
632 if (udc->pdata->have_sysif_regs) {
633 /* Setup Snooping for all the 4GB space */
634 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
635 - __raw_writel(tmp, &usb_sys_regs->snoop1);
636 + iowrite32be(tmp, &usb_sys_regs->snoop1);
637 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
638 - __raw_writel(tmp, &usb_sys_regs->snoop2);
639 + iowrite32be(tmp, &usb_sys_regs->snoop2);
640 }
641 #endif
642
643 @@ -1056,7 +1061,7 @@ static int fsl_ep_fifo_status(struct usb
644 struct ep_queue_head *qh;
645
646 ep = container_of(_ep, struct fsl_ep, ep);
647 - if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
648 + if (!_ep || !ep->ep.desc || (ep_index(ep) == 0))
649 return -ENODEV;
650
651 udc = (struct fsl_udc *)ep->udc;
652 @@ -1598,14 +1603,13 @@ static int process_ep_req(struct fsl_udc
653 struct fsl_req *curr_req)
654 {
655 struct ep_td_struct *curr_td;
656 - int td_complete, actual, remaining_length, j, tmp;
657 + int actual, remaining_length, j, tmp;
658 int status = 0;
659 int errors = 0;
660 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
661 int direction = pipe % 2;
662
663 curr_td = curr_req->head;
664 - td_complete = 0;
665 actual = curr_req->req.length;
666
667 for (j = 0; j < curr_req->dtd_count; j++) {
668 @@ -1650,11 +1654,9 @@ static int process_ep_req(struct fsl_udc
669 status = -EPROTO;
670 break;
671 } else {
672 - td_complete++;
673 break;
674 }
675 } else {
676 - td_complete++;
677 VDBG("dTD transmitted successful");
678 }
679
680 @@ -1697,7 +1699,7 @@ static void dtd_complete_irq(struct fsl_
681 curr_ep = get_ep_by_pipe(udc, i);
682
683 /* If the ep is configured */
684 - if (!curr_ep->ep.name) {
685 + if (strncmp(curr_ep->name, "ep", 2)) {
686 WARNING("Invalid EP?");
687 continue;
688 }
689 @@ -2419,10 +2421,12 @@ static int fsl_udc_probe(struct platform
690 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
691 #endif
692
693 +#ifdef CONFIG_ARCH_MXC
694 /* Initialize USB clocks */
695 ret = fsl_udc_clk_init(pdev);
696 if (ret < 0)
697 goto err_iounmap_noclk;
698 +#endif
699
700 /* Read Device Controller Capability Parameters register */
701 dccparams = fsl_readl(&dr_regs->dccparams);
702 @@ -2462,9 +2466,11 @@ static int fsl_udc_probe(struct platform
703 dr_controller_setup(udc_controller);
704 }
705
706 +#ifdef CONFIG_ARCH_MXC
707 ret = fsl_udc_clk_finalize(pdev);
708 if (ret)
709 goto err_free_irq;
710 +#endif
711
712 /* Setup gadget structure */
713 udc_controller->gadget.ops = &fsl_gadget_ops;
714 @@ -2477,6 +2483,7 @@ static int fsl_udc_probe(struct platform
715 /* Setup gadget.dev and register with kernel */
716 dev_set_name(&udc_controller->gadget.dev, "gadget");
717 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
718 + set_dma_ops(&udc_controller->gadget.dev, pdev->dev.dma_ops);
719
720 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
721 udc_controller->gadget.is_otg = 1;
722 @@ -2528,7 +2535,9 @@ err_free_irq:
723 err_iounmap:
724 if (pdata->exit)
725 pdata->exit(pdev);
726 +#ifdef CONFIG_ARCH_MXC
727 fsl_udc_clk_release();
728 +#endif
729 err_iounmap_noclk:
730 iounmap(dr_regs);
731 err_release_mem_region:
732 @@ -2556,8 +2565,9 @@ static int fsl_udc_remove(struct platfor
733 udc_controller->done = &done;
734 usb_del_gadget_udc(&udc_controller->gadget);
735
736 +#ifdef CONFIG_ARCH_MXC
737 fsl_udc_clk_release();
738 -
739 +#endif
740 /* DR has been stopped in usb_gadget_unregister_driver() */
741 remove_proc_file();
742
743 --- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
744 +++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
745 @@ -20,6 +20,10 @@
746 #define USB_MAX_CTRL_PAYLOAD 64
747 #define USB_DR_SYS_OFFSET 0x400
748
749 +#ifdef CONFIG_SOC_LS1021A
750 +#undef CONFIG_ARCH_MXC
751 +#endif
752 +
753 /* USB DR device mode registers (Little Endian) */
754 struct usb_dr_device {
755 /* Capability register */
756 @@ -597,18 +601,6 @@ struct platform_device;
757 int fsl_udc_clk_init(struct platform_device *pdev);
758 int fsl_udc_clk_finalize(struct platform_device *pdev);
759 void fsl_udc_clk_release(void);
760 -#else
761 -static inline int fsl_udc_clk_init(struct platform_device *pdev)
762 -{
763 - return 0;
764 -}
765 -static inline int fsl_udc_clk_finalize(struct platform_device *pdev)
766 -{
767 - return 0;
768 -}
769 -static inline void fsl_udc_clk_release(void)
770 -{
771 -}
772 #endif
773
774 #endif
775 --- a/drivers/usb/host/Kconfig
776 +++ b/drivers/usb/host/Kconfig
777 @@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
778
779 config USB_EHCI_FSL
780 tristate "Support for Freescale PPC on-chip EHCI USB controller"
781 - depends on FSL_SOC
782 + depends on USB_EHCI_HCD
783 select USB_EHCI_ROOT_HUB_TT
784 ---help---
785 Variation of ARC USB block used in some Freescale chips.
786 --- a/drivers/usb/host/ehci-fsl.c
787 +++ b/drivers/usb/host/ehci-fsl.c
788 @@ -36,15 +36,126 @@
789 #include <linux/platform_device.h>
790 #include <linux/fsl_devices.h>
791 #include <linux/of_platform.h>
792 +#include <linux/io.h>
793 +
794 +#ifdef CONFIG_PM
795 +#include <linux/suspend.h>
796 +#endif
797
798 #include "ehci.h"
799 #include "ehci-fsl.h"
800
801 +#define FSL_USB_PHY_ADDR 0xffe214000
802 +
803 +struct ccsr_usb_port_ctrl {
804 + u32 ctrl;
805 + u32 drvvbuscfg;
806 + u32 pwrfltcfg;
807 + u32 sts;
808 + u8 res_14[0xc];
809 + u32 bistcfg;
810 + u32 biststs;
811 + u32 abistcfg;
812 + u32 abiststs;
813 + u8 res_30[0x10];
814 + u32 xcvrprg;
815 + u32 anaprg;
816 + u32 anadrv;
817 + u32 anasts;
818 +};
819 +
820 +struct ccsr_usb_phy {
821 + u32 id;
822 + struct ccsr_usb_port_ctrl port1;
823 + u8 res_50[0xc];
824 + u32 tvr;
825 + u32 pllprg[4];
826 + u8 res_70[0x4];
827 + u32 anaccfg;
828 + u32 dbg;
829 + u8 res_7c[0x4];
830 + struct ccsr_usb_port_ctrl port2;
831 + u8 res_dc[0x334];
832 +};
833 +
834 #define DRIVER_DESC "Freescale EHCI Host controller driver"
835 #define DRV_NAME "ehci-fsl"
836
837 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
838
839 +struct ehci_fsl {
840 + struct ehci_hcd ehci;
841 +
842 +#ifdef CONFIG_PM
843 +struct ehci_regs saved_regs;
844 +struct ccsr_usb_phy saved_phy_regs;
845 +/* Saved USB PHY settings, need to restore after deep sleep. */
846 +u32 usb_ctrl;
847 +#endif
848 + /*
849 + * store current hcd state for otg;
850 + * have_hcd is true when host drv al already part of otg framework,
851 + * otherwise false;
852 + * hcd_add is true when otg framework wants to add host
853 + * drv as part of otg;flase when it wants to remove it
854 + */
855 +unsigned have_hcd:1;
856 +unsigned hcd_add:1;
857 +};
858 +
859 +static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
860 +{
861 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
862 +
863 +return container_of(ehci, struct ehci_fsl, ehci);
864 +}
865 +
866 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
867 +static void do_change_hcd(struct work_struct *work)
868 +{
869 + struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
870 + change_hcd_work);
871 + struct usb_hcd *hcd = ehci_to_hcd(ehci);
872 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
873 + void __iomem *non_ehci = hcd->regs;
874 + int retval;
875 +
876 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
877 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
878 + /* host, gadget and otg share same int line */
879 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
880 + if (retval == 0)
881 + ehci_fsl->have_hcd = 1;
882 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
883 + usb_remove_hcd(hcd);
884 + ehci_fsl->have_hcd = 0;
885 + }
886 +}
887 +#endif
888 +
889 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
890 +static void do_change_hcd(struct work_struct *work)
891 +{
892 + struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
893 + change_hcd_work);
894 + struct usb_hcd *hcd = ehci_to_hcd(ehci);
895 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
896 + void __iomem *non_ehci = hcd->regs;
897 + int retval;
898 +
899 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
900 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
901 + /* host, gadget and otg share same int line */
902 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
903 + if (retval == 0)
904 + ehci_fsl->have_hcd = 1;
905 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
906 + usb_remove_hcd(hcd);
907 + ehci_fsl->have_hcd = 0;
908 + }
909 +}
910 +#endif
911 +
912 /* configure so an HC device and id are always provided */
913 /* always called with process context; sleeping is OK */
914
915 @@ -131,6 +242,12 @@ static int fsl_ehci_drv_probe(struct pla
916 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
917 CONTROL_REGISTER_W1C_MASK, 0x4);
918
919 + /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
920 + if (pdata->controller_ver == FSL_USB_VER_2_5 &&
921 + pdata->phy_mode == FSL_USB2_PHY_ULPI)
922 + iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
923 +
924 +
925 /*
926 * Enable UTMI phy and program PTS field in UTMI mode before asserting
927 * controller reset for USB Controller version 2.5
928 @@ -143,16 +260,20 @@ static int fsl_ehci_drv_probe(struct pla
929
930 /* Don't need to set host mode here. It will be done by tdi_reset() */
931
932 - retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
933 + retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_NO_SUSPEND);
934 if (retval != 0)
935 goto err2;
936 device_wakeup_enable(hcd->self.controller);
937
938 -#ifdef CONFIG_USB_OTG
939 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
940 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
941 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
942 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
943
944 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
945 +
946 + INIT_WORK(&ehci->change_hcd_work, do_change_hcd);
947 +
948 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
949 hcd, ehci, hcd->usb_phy);
950
951 @@ -168,6 +289,11 @@ static int fsl_ehci_drv_probe(struct pla
952 retval = -ENODEV;
953 goto err2;
954 }
955 +
956 + ehci_fsl->have_hcd = 1;
957 + } else {
958 + dev_err(&pdev->dev, "wrong operating mode\n");
959 + return -ENODEV;
960 }
961 #endif
962 return retval;
963 @@ -181,6 +307,17 @@ static int fsl_ehci_drv_probe(struct pla
964 return retval;
965 }
966
967 +static bool usb_phy_clk_valid(struct usb_hcd *hcd)
968 +{
969 + void __iomem *non_ehci = hcd->regs;
970 + bool ret = true;
971 +
972 + if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
973 + ret = false;
974 +
975 + return ret;
976 +}
977 +
978 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
979 enum fsl_usb2_phy_modes phy_mode,
980 unsigned int port_offset)
981 @@ -219,6 +356,21 @@ static int ehci_fsl_setup_phy(struct usb
982 /* fall through */
983 case FSL_USB2_PHY_UTMI:
984 case FSL_USB2_PHY_UTMI_DUAL:
985 + if (pdata->has_fsl_erratum_a006918) {
986 + pr_warn("fsl-ehci: USB PHY clock invalid\n");
987 + return -EINVAL;
988 + }
989 +
990 + /* PHY_CLK_VALID bit is de-featured from all controller
991 + * versions below 2.4 and is to be checked only for
992 + * internal UTMI phy
993 + */
994 + if (pdata->controller_ver > FSL_USB_VER_2_4 &&
995 + pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
996 + pr_err("fsl-ehci: USB PHY clock invalid\n");
997 + return -EINVAL;
998 + }
999 +
1000 if (pdata->have_sysif_regs && pdata->controller_ver) {
1001 /* controller version 1.6 or above */
1002 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
1003 @@ -295,14 +447,9 @@ static int ehci_fsl_usb_setup(struct ehc
1004 return -EINVAL;
1005
1006 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
1007 - unsigned int chip, rev, svr;
1008 -
1009 - svr = mfspr(SPRN_SVR);
1010 - chip = svr >> 16;
1011 - rev = (svr >> 4) & 0xf;
1012
1013 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
1014 - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
1015 + if (pdata->has_fsl_erratum_14 == 1)
1016 ehci->has_fsl_port_bug = 1;
1017
1018 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
1019 @@ -382,16 +529,56 @@ static int ehci_fsl_setup(struct usb_hcd
1020 return retval;
1021 }
1022
1023 -struct ehci_fsl {
1024 - struct ehci_hcd ehci;
1025 -
1026 #ifdef CONFIG_PM
1027 - /* Saved USB PHY settings, need to restore after deep sleep. */
1028 - u32 usb_ctrl;
1029 -#endif
1030 -};
1031 +void __iomem *phy_reg;
1032
1033 -#ifdef CONFIG_PM
1034 +#ifdef CONFIG_PPC
1035 +/* save usb registers */
1036 +static int ehci_fsl_save_context(struct usb_hcd *hcd)
1037 +{
1038 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1039 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1040 + void __iomem *non_ehci = hcd->regs;
1041 + struct device *dev = hcd->self.controller;
1042 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1043 +
1044 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1045 + phy_reg = ioremap(FSL_USB_PHY_ADDR,
1046 + sizeof(struct ccsr_usb_phy));
1047 + _memcpy_fromio((void *)&ehci_fsl->saved_phy_regs, phy_reg,
1048 + sizeof(struct ccsr_usb_phy));
1049 + }
1050 +
1051 + _memcpy_fromio((void *)&ehci_fsl->saved_regs, ehci->regs,
1052 + sizeof(struct ehci_regs));
1053 + ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
1054 +
1055 + return 0;
1056 +}
1057 +
1058 +/*Restore usb registers */
1059 +static int ehci_fsl_restore_context(struct usb_hcd *hcd)
1060 +{
1061 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1062 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1063 + void __iomem *non_ehci = hcd->regs;
1064 + struct device *dev = hcd->self.controller;
1065 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1066 +
1067 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1068 + if (phy_reg)
1069 + _memcpy_toio(phy_reg,
1070 + (void *)&ehci_fsl->saved_phy_regs,
1071 + sizeof(struct ccsr_usb_phy));
1072 + }
1073 +
1074 + _memcpy_toio(ehci->regs, (void *)&ehci_fsl->saved_regs,
1075 + sizeof(struct ehci_regs));
1076 + iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
1077 +
1078 + return 0;
1079 +}
1080 +#endif
1081
1082 #ifdef CONFIG_PPC_MPC512x
1083 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
1084 @@ -538,26 +725,45 @@ static inline int ehci_fsl_mpc512x_drv_r
1085 }
1086 #endif /* CONFIG_PPC_MPC512x */
1087
1088 -static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
1089 -{
1090 - struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1091 -
1092 - return container_of(ehci, struct ehci_fsl, ehci);
1093 -}
1094 -
1095 static int ehci_fsl_drv_suspend(struct device *dev)
1096 {
1097 struct usb_hcd *hcd = dev_get_drvdata(dev);
1098 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1099 void __iomem *non_ehci = hcd->regs;
1100 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1101 + struct usb_bus host = hcd->self;
1102 +#endif
1103 +
1104 +#ifdef CONFIG_PPC
1105 + suspend_state_t pm_state;
1106 + /* FIXME:Need to port fsl_pm.h before enable below code. */
1107 + /*pm_state = pm_suspend_state();*/
1108 + pm_state = PM_SUSPEND_MEM;
1109 +
1110 +if (pm_state == PM_SUSPEND_MEM)
1111 + ehci_fsl_save_context(hcd);
1112 +#endif
1113
1114 if (of_device_is_compatible(dev->parent->of_node,
1115 "fsl,mpc5121-usb2-dr")) {
1116 return ehci_fsl_mpc512x_drv_suspend(dev);
1117 }
1118
1119 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1120 + if (host.is_otg) {
1121 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1122 +
1123 + /* remove hcd */
1124 + ehci_fsl->hcd_add = 0;
1125 + schedule_work(&ehci->change_hcd_work);
1126 + host.is_otg = 0;
1127 + return 0;
1128 + }
1129 +#endif
1130 +
1131 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
1132 device_may_wakeup(dev));
1133 +
1134 if (!fsl_deep_sleep())
1135 return 0;
1136
1137 @@ -571,12 +777,36 @@ static int ehci_fsl_drv_resume(struct de
1138 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1139 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1140 void __iomem *non_ehci = hcd->regs;
1141 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1142 + struct usb_bus host = hcd->self;
1143 +#endif
1144 +
1145 +#ifdef CONFIG_PPC
1146 + suspend_state_t pm_state;
1147 + /* FIXME:Need to port fsl_pm.h before enable below code.*/
1148 + /* pm_state = pm_suspend_state(); */
1149 + pm_state = PM_SUSPEND_MEM;
1150 +
1151 + if (pm_state == PM_SUSPEND_MEM)
1152 + ehci_fsl_restore_context(hcd);
1153 +#endif
1154
1155 if (of_device_is_compatible(dev->parent->of_node,
1156 "fsl,mpc5121-usb2-dr")) {
1157 return ehci_fsl_mpc512x_drv_resume(dev);
1158 }
1159
1160 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1161 + if (host.is_otg) {
1162 + /* add hcd */
1163 + ehci_fsl->hcd_add = 1;
1164 + schedule_work(&ehci->change_hcd_work);
1165 + usb_hcd_resume_root_hub(hcd);
1166 + host.is_otg = 0;
1167 + return 0;
1168 + }
1169 +#endif
1170 +
1171 ehci_prepare_ports_for_controller_resume(ehci);
1172 if (!fsl_deep_sleep())
1173 return 0;
1174 --- a/drivers/usb/host/ehci-fsl.h
1175 +++ b/drivers/usb/host/ehci-fsl.h
1176 @@ -63,4 +63,7 @@
1177 #define UTMI_PHY_EN (1<<9)
1178 #define ULPI_PHY_CLK_SEL (1<<10)
1179 #define PHY_CLK_VALID (1<<17)
1180 +
1181 +/* Retry count for checking UTMI PHY CLK validity */
1182 +#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
1183 #endif /* _EHCI_FSL_H */
1184 --- a/drivers/usb/host/ehci-hub.c
1185 +++ b/drivers/usb/host/ehci-hub.c
1186 @@ -305,6 +305,8 @@ static int ehci_bus_suspend (struct usb_
1187 USB_PORT_STAT_HIGH_SPEED)
1188 fs_idle_delay = true;
1189 ehci_writel(ehci, t2, reg);
1190 + if (ehci_has_fsl_susp_errata(ehci))
1191 + usleep_range(10000, 20000);
1192 changed = 1;
1193 }
1194 }
1195 --- a/drivers/usb/host/ehci.h
1196 +++ b/drivers/usb/host/ehci.h
1197 @@ -180,6 +180,9 @@ struct ehci_hcd { /* one per controlle
1198 unsigned periodic_count; /* periodic activity count */
1199 unsigned uframe_periodic_max; /* max periodic time per uframe */
1200
1201 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1202 + struct work_struct change_hcd_work;
1203 +#endif
1204
1205 /* list of itds & sitds completed while now_frame was still active */
1206 struct list_head cached_itd_list;
1207 --- a/drivers/usb/host/fsl-mph-dr-of.c
1208 +++ b/drivers/usb/host/fsl-mph-dr-of.c
1209 @@ -229,6 +229,17 @@ static int fsl_usb2_mph_dr_of_probe(stru
1210 pdata->has_fsl_erratum_a005697 =
1211 of_property_read_bool(np, "fsl,usb_erratum-a005697");
1212
1213 + if (of_get_property(np, "fsl,erratum_a006918", NULL))
1214 + pdata->has_fsl_erratum_a006918 = 1;
1215 + else
1216 + pdata->has_fsl_erratum_a006918 = 0;
1217 +
1218 + if (of_get_property(np, "fsl,usb_erratum_14", NULL))
1219 + pdata->has_fsl_erratum_14 = 1;
1220 + else
1221 + pdata->has_fsl_erratum_14 = 0;
1222 +
1223 +
1224 /*
1225 * Determine whether phy_clk_valid needs to be checked
1226 * by reading property in device tree
1227 --- a/drivers/usb/host/xhci-hub.c
1228 +++ b/drivers/usb/host/xhci-hub.c
1229 @@ -689,12 +689,34 @@ void xhci_set_link_state(struct xhci_hcd
1230 int port_id, u32 link_state)
1231 {
1232 u32 temp;
1233 + u32 portpmsc_u2_backup = 0;
1234 +
1235 + /* Backup U2 timeout info before initiating U3 entry erratum A-010131 */
1236 + if (xhci->shared_hcd->speed >= HCD_USB3 &&
1237 + link_state == USB_SS_PORT_LS_U3 &&
1238 + (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
1239 + portpmsc_u2_backup = readl(port_array[port_id] + PORTPMSC);
1240 + portpmsc_u2_backup &= PORT_U2_TIMEOUT_MASK;
1241 + temp = readl(port_array[port_id] + PORTPMSC);
1242 + temp |= PORT_U2_TIMEOUT_MASK;
1243 + writel(temp, port_array[port_id] + PORTPMSC);
1244 + }
1245
1246 temp = readl(port_array[port_id]);
1247 temp = xhci_port_state_to_neutral(temp);
1248 temp &= ~PORT_PLS_MASK;
1249 temp |= PORT_LINK_STROBE | link_state;
1250 writel(temp, port_array[port_id]);
1251 +
1252 + /* Restore U2 timeout info after U3 entry complete */
1253 + if (xhci->shared_hcd->speed >= HCD_USB3 &&
1254 + link_state == USB_SS_PORT_LS_U3 &&
1255 + (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
1256 + temp = readl(port_array[port_id] + PORTPMSC);
1257 + temp &= ~PORT_U2_TIMEOUT_MASK;
1258 + temp |= portpmsc_u2_backup;
1259 + writel(temp, port_array[port_id] + PORTPMSC);
1260 + }
1261 }
1262
1263 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
1264 --- a/drivers/usb/host/xhci-plat.c
1265 +++ b/drivers/usb/host/xhci-plat.c
1266 @@ -263,8 +263,22 @@ static int xhci_plat_probe(struct platfo
1267 goto disable_clk;
1268 }
1269
1270 - if (device_property_read_bool(sysdev, "usb3-lpm-capable"))
1271 + if (device_property_read_bool(sysdev, "usb3-lpm-capable")) {
1272 xhci->quirks |= XHCI_LPM_SUPPORT;
1273 + if (device_property_read_bool(sysdev,
1274 + "snps,dis-u1u2-when-u3-quirk"))
1275 + xhci->quirks |= XHCI_DIS_U1U2_WHEN_U3;
1276 + }
1277 +
1278 + if (device_property_read_bool(&pdev->dev, "quirk-reverse-in-out"))
1279 + xhci->quirks |= XHCI_REVERSE_IN_OUT;
1280 +
1281 + if (device_property_read_bool(&pdev->dev,
1282 + "quirk-stop-transfer-in-block"))
1283 + xhci->quirks |= XHCI_STOP_TRANSFER_IN_BLOCK;
1284 +
1285 + if (device_property_read_bool(&pdev->dev, "quirk-stop-ep-in-u1"))
1286 + xhci->quirks |= XHCI_STOP_EP_IN_U1;
1287
1288 if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
1289 xhci->quirks |= XHCI_BROKEN_PORT_PED;
1290 --- a/drivers/usb/host/xhci-ring.c
1291 +++ b/drivers/usb/host/xhci-ring.c
1292 @@ -1976,10 +1976,12 @@ static int finish_td(struct xhci_hcd *xh
1293 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1294 struct xhci_virt_ep *ep, int *status)
1295 {
1296 + struct xhci_dequeue_state deq_state;
1297 struct xhci_virt_device *xdev;
1298 struct xhci_ep_ctx *ep_ctx;
1299 struct xhci_ring *ep_ring;
1300 unsigned int slot_id;
1301 + u32 remaining;
1302 u32 trb_comp_code;
1303 int ep_index;
1304
1305 @@ -2002,14 +2004,30 @@ static int finish_td(struct xhci_hcd *xh
1306 if (trb_comp_code == COMP_STALL_ERROR ||
1307 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1308 trb_comp_code)) {
1309 - /* Issue a reset endpoint command to clear the host side
1310 - * halt, followed by a set dequeue command to move the
1311 - * dequeue pointer past the TD.
1312 - * The class driver clears the device side halt later.
1313 + /*erratum A-007463:
1314 + *After transaction error, controller switches control transfer
1315 + *data stage from IN to OUT direction.
1316 */
1317 - xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1318 + remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1319 + if (remaining && xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1320 + trb_comp_code) &&
1321 + (xhci->quirks & XHCI_REVERSE_IN_OUT)) {
1322 + memset(&deq_state, 0, sizeof(deq_state));
1323 + xhci_find_new_dequeue_state(xhci, slot_id,
1324 + ep_index, td->urb->stream_id, td, &deq_state);
1325 + xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
1326 + &deq_state);
1327 + xhci_ring_cmd_db(xhci);
1328 + } else {
1329 + /* Issue a reset endpoint command to clear the host side
1330 + * halt, followed by a set dequeue command to move the
1331 + * dequeue pointer past the TD.
1332 + * The class driver clears the device side halt later.
1333 + */
1334 + xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1335 ep_ring->stream_id, td, ep_trb,
1336 EP_HARD_RESET);
1337 + }
1338 } else {
1339 /* Update ring dequeue pointer */
1340 while (ep_ring->dequeue != td->last_trb)
1341 --- a/drivers/usb/host/xhci.c
1342 +++ b/drivers/usb/host/xhci.c
1343 @@ -1607,13 +1607,38 @@ static int xhci_urb_dequeue(struct usb_h
1344 ret = -ENOMEM;
1345 goto done;
1346 }
1347 - ep->ep_state |= EP_STOP_CMD_PENDING;
1348 - ep->stop_cmd_timer.expires = jiffies +
1349 + /*
1350 + *erratum A-009611: Issuing an End Transfer command on an IN
1351 + *endpoint. when a transfer is in progress on USB blocks the
1352 + *transmission.
1353 + *Workaround: Software must wait for all existing TRBs to
1354 + *complete before issuing End transfer command.
1355 + */
1356 + if ((ep_ring->enqueue == ep_ring->dequeue &&
1357 + (xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) ||
1358 + !(xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) {
1359 + ep->ep_state |= EP_STOP_CMD_PENDING;
1360 + ep->stop_cmd_timer.expires = jiffies +
1361 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1362 - add_timer(&ep->stop_cmd_timer);
1363 - xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1364 - ep_index, 0);
1365 - xhci_ring_cmd_db(xhci);
1366 + add_timer(&ep->stop_cmd_timer);
1367 + xhci_queue_stop_endpoint(xhci, command,
1368 + urb->dev->slot_id,
1369 + ep_index, 0);
1370 + xhci_ring_cmd_db(xhci);
1371 + }
1372 +
1373 + /*
1374 + *erratum A-009668: Stop Endpoint Command does not complete.
1375 + *Workaround: Instead of issuing a Stop Endpoint Command,
1376 + *issue a Disable Slot Command with the corresponding slot ID.
1377 + *Alternately, you can issue an Address Device Command with
1378 + *BSR=1
1379 + */
1380 + if ((urb->dev->speed <= USB_SPEED_HIGH) &&
1381 + (xhci->quirks & XHCI_STOP_EP_IN_U1)) {
1382 + xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
1383 + urb->dev->slot_id);
1384 + }
1385 }
1386 done:
1387 spin_unlock_irqrestore(&xhci->lock, flags);
1388 --- a/drivers/usb/host/xhci.h
1389 +++ b/drivers/usb/host/xhci.h
1390 @@ -1794,7 +1794,7 @@ struct xhci_hcd {
1391 #define XHCI_STATE_DYING (1 << 0)
1392 #define XHCI_STATE_HALTED (1 << 1)
1393 #define XHCI_STATE_REMOVING (1 << 2)
1394 - unsigned long long quirks;
1395 + unsigned long long quirks;
1396 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1397 #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1398 #define XHCI_NEC_HOST BIT_ULL(2)
1399 @@ -1830,6 +1830,9 @@ struct xhci_hcd {
1400 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1401 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1402 #define XHCI_MISSING_CAS BIT_ULL(24)
1403 +#define XHCI_REVERSE_IN_OUT BIT(32)
1404 +#define XHCI_STOP_TRANSFER_IN_BLOCK BIT(33)
1405 +#define XHCI_STOP_EP_IN_U1 BIT(34)
1406 /* For controller with a broken Port Disable implementation */
1407 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1408 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1409 @@ -1838,8 +1841,9 @@ struct xhci_hcd {
1410 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1411 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1412 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1413 -#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1414 -#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1415 +#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(35)
1416 +#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(36)
1417 +#define XHCI_DIS_U1U2_WHEN_U3 BIT(37)
1418
1419 unsigned int num_active_eps;
1420 unsigned int limit_active_eps;
1421 --- a/drivers/usb/phy/phy-fsl-usb.c
1422 +++ b/drivers/usb/phy/phy-fsl-usb.c
1423 @@ -1,5 +1,5 @@
1424 /*
1425 - * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
1426 + * Copyright 2007,2008 Freescale Semiconductor, Inc.
1427 *
1428 * Author: Li Yang <LeoLi@freescale.com>
1429 * Jerry Huang <Chang-Ming.Huang@freescale.com>
1430 @@ -470,6 +470,7 @@ void otg_reset_controller(void)
1431 int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1432 {
1433 struct usb_otg *otg = fsm->otg;
1434 + struct usb_bus *host = otg->host;
1435 struct device *dev;
1436 struct fsl_otg *otg_dev =
1437 container_of(otg->usb_phy, struct fsl_otg, phy);
1438 @@ -493,6 +494,7 @@ int fsl_otg_start_host(struct otg_fsm *f
1439 otg_reset_controller();
1440 VDBG("host on......\n");
1441 if (dev->driver->pm && dev->driver->pm->resume) {
1442 + host->is_otg = 1;
1443 retval = dev->driver->pm->resume(dev);
1444 if (fsm->id) {
1445 /* default-b */
1446 @@ -517,8 +519,11 @@ int fsl_otg_start_host(struct otg_fsm *f
1447 else {
1448 VDBG("host off......\n");
1449 if (dev && dev->driver) {
1450 - if (dev->driver->pm && dev->driver->pm->suspend)
1451 + if (dev->driver->pm &&
1452 + dev->driver->pm->suspend) {
1453 + host->is_otg = 1;
1454 retval = dev->driver->pm->suspend(dev);
1455 + }
1456 if (fsm->id)
1457 /* default-b */
1458 fsl_otg_drv_vbus(fsm, 0);
1459 @@ -546,8 +551,17 @@ int fsl_otg_start_gadget(struct otg_fsm
1460 dev = otg->gadget->dev.parent;
1461
1462 if (on) {
1463 - if (dev->driver->resume)
1464 + /* Delay gadget resume to synchronize between host and gadget
1465 + * drivers. Upon role-reversal host drv is shutdown by kernel
1466 + * worker thread. By the time host drv shuts down, controller
1467 + * gets programmed for gadget role. Shutting host drv after
1468 + * this results in controller getting reset, and it stops
1469 + * responding to otg events
1470 + */
1471 + if (dev->driver->resume) {
1472 + msleep(1000);
1473 dev->driver->resume(dev);
1474 + }
1475 } else {
1476 if (dev->driver->suspend)
1477 dev->driver->suspend(dev, otg_suspend_state);
1478 @@ -668,6 +682,10 @@ static void fsl_otg_event(struct work_st
1479 fsl_otg_start_host(fsm, 0);
1480 otg_drv_vbus(fsm, 0);
1481 fsl_otg_start_gadget(fsm, 1);
1482 + } else {
1483 + fsl_otg_start_gadget(fsm, 0);
1484 + otg_drv_vbus(fsm, 1);
1485 + fsl_otg_start_host(fsm, 1);
1486 }
1487 }
1488
1489 @@ -720,6 +738,7 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1490 {
1491 struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
1492 struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
1493 + struct fsl_otg *otg_dev = dev_id;
1494 u32 otg_int_src, otg_sc;
1495
1496 otg_sc = fsl_readl(&usb_dr_regs->otgsc);
1497 @@ -749,18 +768,8 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1498 otg->gadget->is_a_peripheral = !fsm->id;
1499 VDBG("ID int (ID is %d)\n", fsm->id);
1500
1501 - if (fsm->id) { /* switch to gadget */
1502 - schedule_delayed_work(
1503 - &((struct fsl_otg *)dev_id)->otg_event,
1504 - 100);
1505 - } else { /* switch to host */
1506 - cancel_delayed_work(&
1507 - ((struct fsl_otg *)dev_id)->
1508 - otg_event);
1509 - fsl_otg_start_gadget(fsm, 0);
1510 - otg_drv_vbus(fsm, 1);
1511 - fsl_otg_start_host(fsm, 1);
1512 - }
1513 + schedule_delayed_work(&otg_dev->otg_event, 100);
1514 +
1515 return IRQ_HANDLED;
1516 }
1517 }
1518 @@ -920,12 +929,32 @@ int usb_otg_start(struct platform_device
1519 temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
1520 switch (pdata->phy_mode) {
1521 case FSL_USB2_PHY_ULPI:
1522 + if (pdata->controller_ver) {
1523 + /* controller version 1.6 or above */
1524 + setbits32(&p_otg->dr_mem_map->control,
1525 + USB_CTRL_ULPI_PHY_CLK_SEL);
1526 + /*
1527 + * Due to controller issue of PHY_CLK_VALID in ULPI
1528 + * mode, we set USB_CTRL_USB_EN before checking
1529 + * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
1530 + */
1531 + clrsetbits_be32(&p_otg->dr_mem_map->control,
1532 + USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
1533 + }
1534 temp |= PORTSC_PTS_ULPI;
1535 break;
1536 case FSL_USB2_PHY_UTMI_WIDE:
1537 temp |= PORTSC_PTW_16BIT;
1538 /* fall through */
1539 case FSL_USB2_PHY_UTMI:
1540 + if (pdata->controller_ver) {
1541 + /* controller version 1.6 or above */
1542 + setbits32(&p_otg->dr_mem_map->control,
1543 + USB_CTRL_UTMI_PHY_EN);
1544 + /* Delay for UTMI PHY CLK to become stable - 10ms */
1545 + mdelay(FSL_UTMI_PHY_DLY);
1546 + }
1547 + setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
1548 temp |= PORTSC_PTS_UTMI;
1549 /* fall through */
1550 default:
1551 --- a/drivers/usb/phy/phy-fsl-usb.h
1552 +++ b/drivers/usb/phy/phy-fsl-usb.h
1553 @@ -199,6 +199,14 @@
1554 /* control Register Bit Masks */
1555 #define USB_CTRL_IOENB (0x1<<2)
1556 #define USB_CTRL_ULPI_INT0EN (0x1<<0)
1557 +#define USB_CTRL_WU_INT_EN (0x1<<1)
1558 +#define USB_CTRL_LINE_STATE_FILTER__EN (0x1<<3)
1559 +#define USB_CTRL_KEEP_OTG_ON (0x1<<4)
1560 +#define USB_CTRL_OTG_PORT (0x1<<5)
1561 +#define USB_CTRL_PLL_RESET (0x1<<8)
1562 +#define USB_CTRL_UTMI_PHY_EN (0x1<<9)
1563 +#define USB_CTRL_ULPI_PHY_CLK_SEL (0x1<<10)
1564 +#define USB_CTRL_PHY_CLK_VALID (0x1<<17)
1565
1566 /* BCSR5 */
1567 #define BCSR5_INT_USB (0x02)
1568 --- a/include/linux/usb.h
1569 +++ b/include/linux/usb.h
1570 @@ -432,6 +432,7 @@ struct usb_bus {
1571 * for control transfers?
1572 */
1573 u8 otg_port; /* 0, or number of OTG/HNP port */
1574 + unsigned is_otg:1; /* true when host is also otg */
1575 unsigned is_b_host:1; /* true during some HNP roleswitches */
1576 unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */
1577 unsigned no_stop_on_short:1; /*
1578 --- a/include/linux/usb/of.h
1579 +++ b/include/linux/usb/of.h
1580 @@ -11,6 +11,8 @@
1581 #include <linux/usb/otg.h>
1582 #include <linux/usb/phy.h>
1583
1584 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
1585 +
1586 #if IS_ENABLED(CONFIG_OF)
1587 enum usb_dr_mode of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0);
1588 bool of_usb_host_tpl_support(struct device_node *np);
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