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[openwrt/openwrt.git] / target / linux / layerscape / patches-4.14 / 807-usb-support-layerscape.patch
1 From 01b1b2989e907305d8b885468c2743f5e35e1b9a Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Thu, 13 Dec 2018 11:15:15 +0800
4 Subject: [PATCH] usb: support layerscape
5
6 This is an integrated patch of usb for layerscape
7
8 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
9 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
10 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
11 Signed-off-by: Li Yang <leoli@freescale.com>
12 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
14 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
15 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
16 Signed-off-by: Roger Quadros <rogerq@ti.com>
17 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
18 Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
19 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
20 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
21 Signed-off-by: Biwen Li <biwen.li@nxp.com>
22 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
23 ---
24 .../devicetree/bindings/usb/dwc3.txt | 2 +
25 arch/arm64/include/asm/io.h | 28 ++
26 drivers/usb/common/common.c | 50 ++++
27 drivers/usb/core/usb.c | 1 +
28 drivers/usb/dwc3/core.c | 104 +++++++
29 drivers/usb/dwc3/core.h | 44 +++
30 drivers/usb/dwc3/ep0.c | 4 +-
31 drivers/usb/dwc3/gadget.c | 7 +
32 drivers/usb/dwc3/host.c | 9 +
33 drivers/usb/gadget/udc/fsl_udc_core.c | 46 +--
34 drivers/usb/gadget/udc/fsl_usb2_udc.h | 16 +-
35 drivers/usb/host/Kconfig | 2 +-
36 drivers/usb/host/ehci-fsl.c | 276 ++++++++++++++++--
37 drivers/usb/host/ehci-fsl.h | 3 +
38 drivers/usb/host/ehci-hub.c | 2 +
39 drivers/usb/host/ehci.h | 3 +
40 drivers/usb/host/fsl-mph-dr-of.c | 11 +
41 drivers/usb/host/xhci-hub.c | 22 ++
42 drivers/usb/host/xhci-plat.c | 16 +-
43 drivers/usb/host/xhci-ring.c | 28 +-
44 drivers/usb/host/xhci.c | 39 ++-
45 drivers/usb/host/xhci.h | 6 +-
46 drivers/usb/phy/phy-fsl-usb.c | 59 +++-
47 drivers/usb/phy/phy-fsl-usb.h | 8 +
48 include/linux/usb.h | 1 +
49 include/linux/usb/of.h | 2 +
50 26 files changed, 704 insertions(+), 85 deletions(-)
51
52 --- a/Documentation/devicetree/bindings/usb/dwc3.txt
53 +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
54 @@ -47,6 +47,8 @@ Optional properties:
55 from P0 to P1/P2/P3 without delay.
56 - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
57 during HS transmit.
58 + - snps,disable_devinit_u1u2: when set, disable device-initiated U1/U2
59 + LPM request in USB device mode.
60 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
61 utmi_l1_suspend_n, false when asserts utmi_sleep_n
62 - snps,hird-threshold: HIRD threshold
63 --- a/arch/arm64/include/asm/io.h
64 +++ b/arch/arm64/include/asm/io.h
65 @@ -210,6 +210,34 @@ extern void __iomem *ioremap_cache(phys_
66 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
67 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
68
69 +/* access ports */
70 +#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
71 +#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
72 +
73 +#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
74 +#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
75 +
76 +#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
77 +#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
78 +
79 +/* Clear and set bits in one shot. These macros can be used to clear and
80 + * set multiple bits in a register using a single read-modify-write. These
81 + * macros can also be used to set a multiple-bit bit pattern using a mask,
82 + * by specifying the mask in the 'clear' parameter and the new bit pattern
83 + * in the 'set' parameter.
84 + */
85 +
86 +#define clrsetbits_be32(addr, clear, set) \
87 + iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
88 +#define clrsetbits_le32(addr, clear, set) \
89 + iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
90 +#define clrsetbits_be16(addr, clear, set) \
91 + iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
92 +#define clrsetbits_le16(addr, clear, set) \
93 + iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
94 +#define clrsetbits_8(addr, clear, set) \
95 + iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
96 +
97 #include <asm-generic/io.h>
98
99 /*
100 --- a/drivers/usb/common/common.c
101 +++ b/drivers/usb/common/common.c
102 @@ -105,6 +105,56 @@ static const char *const usb_dr_modes[]
103 [USB_DR_MODE_OTG] = "otg",
104 };
105
106 +/**
107 + * of_usb_get_dr_mode - Get dual role mode for given device_node
108 + * @np: Pointer to the given device_node
109 + *
110 + * The function gets phy interface string from property 'dr_mode',
111 + * and returns the correspondig enum usb_dr_mode
112 + */
113 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
114 +{
115 + const char *dr_mode;
116 + int err, i;
117 +
118 + err = of_property_read_string(np, "dr_mode", &dr_mode);
119 + if (err < 0)
120 + return USB_DR_MODE_UNKNOWN;
121 +
122 + for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
123 + if (!strcmp(dr_mode, usb_dr_modes[i]))
124 + return i;
125 +
126 + return USB_DR_MODE_UNKNOWN;
127 +}
128 +EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
129 +
130 +/**
131 + * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
132 + * controller.
133 + * @np: Pointer to the given device_node
134 + *
135 + * The function gets the maximum speed string from property "maximum-speed",
136 + * and returns the corresponding enum usb_device_speed.
137 + */
138 +enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
139 +{
140 + const char *maximum_speed;
141 + int err;
142 + int i;
143 +
144 + err = of_property_read_string(np, "maximum-speed", &maximum_speed);
145 + if (err < 0)
146 + return USB_SPEED_UNKNOWN;
147 +
148 + for (i = 0; i < ARRAY_SIZE(speed_names); i++)
149 + if (strcmp(maximum_speed, speed_names[i]) == 0)
150 + return i;
151 +
152 + return USB_SPEED_UNKNOWN;
153 +}
154 +EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
155 +
156 static enum usb_dr_mode usb_get_dr_mode_from_string(const char *str)
157 {
158 int ret;
159 --- a/drivers/usb/core/usb.c
160 +++ b/drivers/usb/core/usb.c
161 @@ -593,6 +593,7 @@ struct usb_device *usb_alloc_dev(struct
162 dev->dev.dma_mask = bus->sysdev->dma_mask;
163 dev->dev.dma_pfn_offset = bus->sysdev->dma_pfn_offset;
164 set_dev_node(&dev->dev, dev_to_node(bus->sysdev));
165 + dev->dev.of_node = bus->controller->of_node;
166 dev->state = USB_STATE_ATTACHED;
167 dev->lpm_disable_count = 1;
168 atomic_set(&dev->urbnum, 0);
169 --- a/drivers/usb/dwc3/core.c
170 +++ b/drivers/usb/dwc3/core.c
171 @@ -766,6 +766,96 @@ static void dwc3_core_setup_global_contr
172 static int dwc3_core_get_phy(struct dwc3 *dwc);
173 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
174
175 +/* set global soc bus configuration registers */
176 +static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
177 +{
178 + struct device *dev = dwc->dev;
179 + u32 *vals;
180 + u32 cfg;
181 + int ntype;
182 + int ret;
183 + int i;
184 +
185 + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
186 +
187 + /*
188 + * Handle property "snps,incr-burst-type-adjustment".
189 + * Get the number of value from this property:
190 + * result <= 0, means this property is not supported.
191 + * result = 1, means INCRx burst mode supported.
192 + * result > 1, means undefined length burst mode supported.
193 + */
194 + ntype = device_property_read_u32_array(dev,
195 + "snps,incr-burst-type-adjustment", NULL, 0);
196 + if (ntype > 0) {
197 + vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
198 + if (!vals) {
199 + dev_err(dev, "Error to get memory\n");
200 + return;
201 + }
202 + /* Get INCR burst type, and parse it */
203 + ret = device_property_read_u32_array(dev,
204 + "snps,incr-burst-type-adjustment", vals, ntype);
205 + if (ret) {
206 + dev_err(dev, "Error to get property\n");
207 + return;
208 + }
209 + *(dwc->incrx_type + 1) = vals[0];
210 + if (ntype > 1) {
211 + *dwc->incrx_type = 1;
212 + for (i = 1; i < ntype; i++) {
213 + if (vals[i] > *(dwc->incrx_type + 1))
214 + *(dwc->incrx_type + 1) = vals[i];
215 + }
216 + } else
217 + *dwc->incrx_type = 0;
218 +
219 + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
220 + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
221 + if (*dwc->incrx_type)
222 + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
223 + switch (*(dwc->incrx_type + 1)) {
224 + case 256:
225 + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
226 + break;
227 + case 128:
228 + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
229 + break;
230 + case 64:
231 + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
232 + break;
233 + case 32:
234 + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
235 + break;
236 + case 16:
237 + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
238 + break;
239 + case 8:
240 + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
241 + break;
242 + case 4:
243 + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
244 + break;
245 + case 1:
246 + break;
247 + default:
248 + dev_err(dev, "Invalid property\n");
249 + break;
250 + }
251 + }
252 +
253 + /* Handle usb snooping */
254 + if (dwc->dma_coherent) {
255 + cfg &= ~DWC3_GSBUSCFG0_SNP_MASK;
256 + cfg |= (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATARD_SHIFT) |
257 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCRD_SHIFT) |
258 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATAWR_SHIFT) |
259 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCWR_SHIFT);
260 + }
261 +
262 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
263 +}
264 +
265 /**
266 * dwc3_core_init - Low-level initialization of DWC3 Core
267 * @dwc: Pointer to our controller context structure
268 @@ -828,6 +918,8 @@ static int dwc3_core_init(struct dwc3 *d
269 /* Adjust Frame Length */
270 dwc3_frame_length_adjustment(dwc);
271
272 + dwc3_set_soc_bus_cfg(dwc);
273 +
274 usb_phy_set_suspend(dwc->usb2_phy, 0);
275 usb_phy_set_suspend(dwc->usb3_phy, 0);
276 ret = phy_power_on(dwc->usb2_generic_phy);
277 @@ -1074,6 +1166,8 @@ static void dwc3_get_properties(struct d
278 &hird_threshold);
279 dwc->usb3_lpm_capable = device_property_read_bool(dev,
280 "snps,usb3_lpm_capable");
281 + dwc->dma_coherent = device_property_read_bool(dev,
282 + "dma-coherent");
283
284 dwc->disable_scramble_quirk = device_property_read_bool(dev,
285 "snps,disable_scramble_quirk");
286 @@ -1106,8 +1200,16 @@ static void dwc3_get_properties(struct d
287 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
288 "snps,dis-tx-ipgap-linecheck-quirk");
289
290 + dwc->quirk_reverse_in_out = device_property_read_bool(dev,
291 + "snps,quirk_reverse_in_out");
292 + dwc->quirk_stop_transfer_in_block = device_property_read_bool(dev,
293 + "snps,quirk_stop_transfer_in_block");
294 + dwc->quirk_stop_ep_in_u1 = device_property_read_bool(dev,
295 + "snps,quirk_stop_ep_in_u1");
296 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
297 "snps,tx_de_emphasis_quirk");
298 + dwc->disable_devinit_u1u2_quirk = device_property_read_bool(dev,
299 + "snps,disable_devinit_u1u2");
300 device_property_read_u8(dev, "snps,tx_de_emphasis",
301 &tx_de_emphasis);
302 device_property_read_string(dev, "snps,hsphy_interface",
303 @@ -1365,12 +1467,14 @@ static int dwc3_resume_common(struct dwc
304
305 switch (dwc->dr_mode) {
306 case USB_DR_MODE_PERIPHERAL:
307 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
308 case USB_DR_MODE_OTG:
309 spin_lock_irqsave(&dwc->lock, flags);
310 dwc3_gadget_resume(dwc);
311 spin_unlock_irqrestore(&dwc->lock, flags);
312 /* FALLTHROUGH */
313 case USB_DR_MODE_HOST:
314 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
315 default:
316 /* do nothing */
317 break;
318 --- a/drivers/usb/dwc3/core.h
319 +++ b/drivers/usb/dwc3/core.h
320 @@ -161,6 +161,32 @@
321
322 /* Bit fields */
323
324 +/* Global SoC Bus Configuration Register 0 */
325 +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */
326 +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */
327 +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */
328 +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */
329 +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
330 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
331 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
332 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
333 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000
334 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11)
335 +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10)
336 +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
337 +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
338 +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
339 +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
340 +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
341 +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
342 +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
343 +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
344 +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
345 +
346 +/* Global SoC Bus Configuration Register 1 */
347 +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */
348 +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00
349 +
350 /* Global Debug Queue/FIFO Space Available Register */
351 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
352 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
353 @@ -788,6 +814,7 @@ struct dwc3_scratchpad_array {
354 * @regs: base address for our registers
355 * @regs_size: address space size
356 * @fladj: frame length adjustment
357 + * @incrx_type: INCR burst type adjustment
358 * @irq_gadget: peripheral controller's IRQ number
359 * @nr_scratch: number of scratch buffers
360 * @u1u2: only used on revisions <1.83a for workaround
361 @@ -843,6 +870,7 @@ struct dwc3_scratchpad_array {
362 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
363 * @three_stage_setup: set if we perform a three phase setup
364 * @usb3_lpm_capable: set if hadrware supports Link Power Management
365 + * @dma_coherent: set if hadrware supports DMA snoop
366 * @disable_scramble_quirk: set if we enable the disable scramble quirk
367 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
368 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
369 @@ -869,6 +897,11 @@ struct dwc3_scratchpad_array {
370 * 1 - -3.5dB de-emphasis
371 * 2 - No de-emphasis
372 * 3 - Reserved
373 + * @disable_devinit_u1u2_quirk: disable device-initiated U1/U2 request.
374 + * @quirk_reverse_in_out: prevent tx fifo reverse the data direction
375 + * @quirk_stop_transfer_in_block: prevent block transmission from being
376 + * interrupted
377 + * @quirk_stop_ep_in_u1: replace stop commad with disable slot command
378 * @imod_interval: set the interrupt moderation interval in 250ns
379 * increments or 0 to disable.
380 */
381 @@ -921,6 +954,12 @@ struct dwc3 {
382 enum usb_phy_interface hsphy_mode;
383
384 u32 fladj;
385 + /*
386 + * For INCR burst type.
387 + * First field: for undefined length INCR burst type enable.
388 + * Second field: for INCRx burst type enable
389 + */
390 + u32 incrx_type[2];
391 u32 irq_gadget;
392 u32 nr_scratch;
393 u32 u1u2;
394 @@ -1005,6 +1044,7 @@ struct dwc3 {
395 unsigned setup_packet_pending:1;
396 unsigned three_stage_setup:1;
397 unsigned usb3_lpm_capable:1;
398 + unsigned dma_coherent:1;
399
400 unsigned disable_scramble_quirk:1;
401 unsigned u2exit_lfps_quirk:1;
402 @@ -1024,6 +1064,10 @@ struct dwc3 {
403
404 unsigned tx_de_emphasis_quirk:1;
405 unsigned tx_de_emphasis:2;
406 + unsigned disable_devinit_u1u2_quirk:1;
407 + unsigned quirk_reverse_in_out:1;
408 + unsigned quirk_stop_transfer_in_block:1;
409 + unsigned quirk_stop_ep_in_u1:1;
410
411 u16 imod_interval;
412 };
413 --- a/drivers/usb/dwc3/ep0.c
414 +++ b/drivers/usb/dwc3/ep0.c
415 @@ -391,7 +391,7 @@ static int dwc3_ep0_handle_u1(struct dwc
416 return -EINVAL;
417
418 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
419 - if (set)
420 + if (set && !dwc->disable_devinit_u1u2_quirk)
421 reg |= DWC3_DCTL_INITU1ENA;
422 else
423 reg &= ~DWC3_DCTL_INITU1ENA;
424 @@ -413,7 +413,7 @@ static int dwc3_ep0_handle_u2(struct dwc
425 return -EINVAL;
426
427 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
428 - if (set)
429 + if (set && !dwc->disable_devinit_u1u2_quirk)
430 reg |= DWC3_DCTL_INITU2ENA;
431 else
432 reg &= ~DWC3_DCTL_INITU2ENA;
433 --- a/drivers/usb/dwc3/gadget.c
434 +++ b/drivers/usb/dwc3/gadget.c
435 @@ -3210,6 +3210,7 @@ int dwc3_gadget_init(struct dwc3 *dwc)
436 {
437 int ret;
438 int irq;
439 + u32 reg;
440
441 irq = dwc3_gadget_get_irq(dwc);
442 if (irq < 0) {
443 @@ -3286,6 +3287,12 @@ int dwc3_gadget_init(struct dwc3 *dwc)
444 goto err4;
445 }
446
447 + if (dwc->disable_devinit_u1u2_quirk) {
448 + reg = dwc3_readl(dwc->regs, DWC3_DCTL);
449 + reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
450 + dwc3_writel(dwc->regs, DWC3_DCTL, reg);
451 + }
452 +
453 return 0;
454
455 err4:
456 --- a/drivers/usb/dwc3/host.c
457 +++ b/drivers/usb/dwc3/host.c
458 @@ -98,6 +98,15 @@ int dwc3_host_init(struct dwc3 *dwc)
459
460 memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
461
462 + if (dwc->quirk_reverse_in_out)
463 + props[prop_idx++].name = "quirk-reverse-in-out";
464 +
465 + if (dwc->quirk_stop_transfer_in_block)
466 + props[prop_idx++].name = "quirk-stop-transfer-in-block";
467 +
468 + if (dwc->quirk_stop_ep_in_u1)
469 + props[prop_idx++].name = "quirk-stop-ep-in-u1";
470 +
471 if (dwc->usb3_lpm_capable)
472 props[prop_idx++].name = "usb3-lpm-capable";
473
474 --- a/drivers/usb/gadget/udc/fsl_udc_core.c
475 +++ b/drivers/usb/gadget/udc/fsl_udc_core.c
476 @@ -198,7 +198,11 @@ __acquires(ep->udc->lock)
477
478 spin_unlock(&ep->udc->lock);
479
480 - usb_gadget_giveback_request(&ep->ep, &req->req);
481 + /* this complete() should a func implemented by gadget layer,
482 + * eg fsg->bulk_in_complete()
483 + */
484 + if (req->req.complete)
485 + usb_gadget_giveback_request(&ep->ep, &req->req);
486
487 spin_lock(&ep->udc->lock);
488 ep->stopped = stopped;
489 @@ -245,10 +249,10 @@ static int dr_controller_setup(struct fs
490 if (udc->pdata->have_sysif_regs) {
491 if (udc->pdata->controller_ver) {
492 /* controller version 1.6 or above */
493 - ctrl = __raw_readl(&usb_sys_regs->control);
494 + ctrl = ioread32be(&usb_sys_regs->control);
495 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
496 ctrl |= USB_CTRL_USB_EN;
497 - __raw_writel(ctrl, &usb_sys_regs->control);
498 + iowrite32be(ctrl, &usb_sys_regs->control);
499 }
500 }
501 portctrl |= PORTSCX_PTS_ULPI;
502 @@ -257,13 +261,14 @@ static int dr_controller_setup(struct fs
503 portctrl |= PORTSCX_PTW_16BIT;
504 /* fall through */
505 case FSL_USB2_PHY_UTMI:
506 + case FSL_USB2_PHY_UTMI_DUAL:
507 if (udc->pdata->have_sysif_regs) {
508 if (udc->pdata->controller_ver) {
509 /* controller version 1.6 or above */
510 - ctrl = __raw_readl(&usb_sys_regs->control);
511 + ctrl = ioread32be(&usb_sys_regs->control);
512 ctrl |= (USB_CTRL_UTMI_PHY_EN |
513 USB_CTRL_USB_EN);
514 - __raw_writel(ctrl, &usb_sys_regs->control);
515 + iowrite32be(ctrl, &usb_sys_regs->control);
516 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
517 PHY CLK to become stable - 10ms*/
518 }
519 @@ -329,22 +334,22 @@ static int dr_controller_setup(struct fs
520 /* Config control enable i/o output, cpu endian register */
521 #ifndef CONFIG_ARCH_MXC
522 if (udc->pdata->have_sysif_regs) {
523 - ctrl = __raw_readl(&usb_sys_regs->control);
524 + ctrl = ioread32be(&usb_sys_regs->control);
525 ctrl |= USB_CTRL_IOENB;
526 - __raw_writel(ctrl, &usb_sys_regs->control);
527 + iowrite32be(ctrl, &usb_sys_regs->control);
528 }
529 #endif
530
531 -#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
532 +#if !defined(CONFIG_NOT_COHERENT_CACHE)
533 /* Turn on cache snooping hardware, since some PowerPC platforms
534 * wholly rely on hardware to deal with cache coherent. */
535
536 if (udc->pdata->have_sysif_regs) {
537 /* Setup Snooping for all the 4GB space */
538 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
539 - __raw_writel(tmp, &usb_sys_regs->snoop1);
540 + iowrite32be(tmp, &usb_sys_regs->snoop1);
541 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
542 - __raw_writel(tmp, &usb_sys_regs->snoop2);
543 + iowrite32be(tmp, &usb_sys_regs->snoop2);
544 }
545 #endif
546
547 @@ -1056,7 +1061,7 @@ static int fsl_ep_fifo_status(struct usb
548 struct ep_queue_head *qh;
549
550 ep = container_of(_ep, struct fsl_ep, ep);
551 - if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
552 + if (!_ep || !ep->ep.desc || (ep_index(ep) == 0))
553 return -ENODEV;
554
555 udc = (struct fsl_udc *)ep->udc;
556 @@ -1598,14 +1603,13 @@ static int process_ep_req(struct fsl_udc
557 struct fsl_req *curr_req)
558 {
559 struct ep_td_struct *curr_td;
560 - int td_complete, actual, remaining_length, j, tmp;
561 + int actual, remaining_length, j, tmp;
562 int status = 0;
563 int errors = 0;
564 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
565 int direction = pipe % 2;
566
567 curr_td = curr_req->head;
568 - td_complete = 0;
569 actual = curr_req->req.length;
570
571 for (j = 0; j < curr_req->dtd_count; j++) {
572 @@ -1650,11 +1654,9 @@ static int process_ep_req(struct fsl_udc
573 status = -EPROTO;
574 break;
575 } else {
576 - td_complete++;
577 break;
578 }
579 } else {
580 - td_complete++;
581 VDBG("dTD transmitted successful");
582 }
583
584 @@ -1697,7 +1699,7 @@ static void dtd_complete_irq(struct fsl_
585 curr_ep = get_ep_by_pipe(udc, i);
586
587 /* If the ep is configured */
588 - if (!curr_ep->ep.name) {
589 + if (strncmp(curr_ep->name, "ep", 2)) {
590 WARNING("Invalid EP?");
591 continue;
592 }
593 @@ -2419,10 +2421,12 @@ static int fsl_udc_probe(struct platform
594 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
595 #endif
596
597 +#ifdef CONFIG_ARCH_MXC
598 /* Initialize USB clocks */
599 ret = fsl_udc_clk_init(pdev);
600 if (ret < 0)
601 goto err_iounmap_noclk;
602 +#endif
603
604 /* Read Device Controller Capability Parameters register */
605 dccparams = fsl_readl(&dr_regs->dccparams);
606 @@ -2462,9 +2466,11 @@ static int fsl_udc_probe(struct platform
607 dr_controller_setup(udc_controller);
608 }
609
610 +#ifdef CONFIG_ARCH_MXC
611 ret = fsl_udc_clk_finalize(pdev);
612 if (ret)
613 goto err_free_irq;
614 +#endif
615
616 /* Setup gadget structure */
617 udc_controller->gadget.ops = &fsl_gadget_ops;
618 @@ -2477,6 +2483,7 @@ static int fsl_udc_probe(struct platform
619 /* Setup gadget.dev and register with kernel */
620 dev_set_name(&udc_controller->gadget.dev, "gadget");
621 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
622 + set_dma_ops(&udc_controller->gadget.dev, pdev->dev.dma_ops);
623
624 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
625 udc_controller->gadget.is_otg = 1;
626 @@ -2528,7 +2535,9 @@ err_free_irq:
627 err_iounmap:
628 if (pdata->exit)
629 pdata->exit(pdev);
630 +#ifdef CONFIG_ARCH_MXC
631 fsl_udc_clk_release();
632 +#endif
633 err_iounmap_noclk:
634 iounmap(dr_regs);
635 err_release_mem_region:
636 @@ -2556,8 +2565,9 @@ static int fsl_udc_remove(struct platfor
637 udc_controller->done = &done;
638 usb_del_gadget_udc(&udc_controller->gadget);
639
640 +#ifdef CONFIG_ARCH_MXC
641 fsl_udc_clk_release();
642 -
643 +#endif
644 /* DR has been stopped in usb_gadget_unregister_driver() */
645 remove_proc_file();
646
647 @@ -2569,7 +2579,7 @@ static int fsl_udc_remove(struct platfor
648 dma_pool_destroy(udc_controller->td_pool);
649 free_irq(udc_controller->irq, udc_controller);
650 iounmap(dr_regs);
651 - if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
652 + if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
653 release_mem_region(res->start, resource_size(res));
654
655 /* free udc --wait for the release() finished */
656 --- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
657 +++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
658 @@ -20,6 +20,10 @@
659 #define USB_MAX_CTRL_PAYLOAD 64
660 #define USB_DR_SYS_OFFSET 0x400
661
662 +#ifdef CONFIG_SOC_LS1021A
663 +#undef CONFIG_ARCH_MXC
664 +#endif
665 +
666 /* USB DR device mode registers (Little Endian) */
667 struct usb_dr_device {
668 /* Capability register */
669 @@ -597,18 +601,6 @@ struct platform_device;
670 int fsl_udc_clk_init(struct platform_device *pdev);
671 int fsl_udc_clk_finalize(struct platform_device *pdev);
672 void fsl_udc_clk_release(void);
673 -#else
674 -static inline int fsl_udc_clk_init(struct platform_device *pdev)
675 -{
676 - return 0;
677 -}
678 -static inline int fsl_udc_clk_finalize(struct platform_device *pdev)
679 -{
680 - return 0;
681 -}
682 -static inline void fsl_udc_clk_release(void)
683 -{
684 -}
685 #endif
686
687 #endif
688 --- a/drivers/usb/host/Kconfig
689 +++ b/drivers/usb/host/Kconfig
690 @@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
691
692 config USB_EHCI_FSL
693 tristate "Support for Freescale PPC on-chip EHCI USB controller"
694 - depends on FSL_SOC
695 + depends on USB_EHCI_HCD
696 select USB_EHCI_ROOT_HUB_TT
697 ---help---
698 Variation of ARC USB block used in some Freescale chips.
699 --- a/drivers/usb/host/ehci-fsl.c
700 +++ b/drivers/usb/host/ehci-fsl.c
701 @@ -36,15 +36,126 @@
702 #include <linux/platform_device.h>
703 #include <linux/fsl_devices.h>
704 #include <linux/of_platform.h>
705 +#include <linux/io.h>
706 +
707 +#ifdef CONFIG_PM
708 +#include <linux/suspend.h>
709 +#endif
710
711 #include "ehci.h"
712 #include "ehci-fsl.h"
713
714 +#define FSL_USB_PHY_ADDR 0xffe214000
715 +
716 +struct ccsr_usb_port_ctrl {
717 + u32 ctrl;
718 + u32 drvvbuscfg;
719 + u32 pwrfltcfg;
720 + u32 sts;
721 + u8 res_14[0xc];
722 + u32 bistcfg;
723 + u32 biststs;
724 + u32 abistcfg;
725 + u32 abiststs;
726 + u8 res_30[0x10];
727 + u32 xcvrprg;
728 + u32 anaprg;
729 + u32 anadrv;
730 + u32 anasts;
731 +};
732 +
733 +struct ccsr_usb_phy {
734 + u32 id;
735 + struct ccsr_usb_port_ctrl port1;
736 + u8 res_50[0xc];
737 + u32 tvr;
738 + u32 pllprg[4];
739 + u8 res_70[0x4];
740 + u32 anaccfg;
741 + u32 dbg;
742 + u8 res_7c[0x4];
743 + struct ccsr_usb_port_ctrl port2;
744 + u8 res_dc[0x334];
745 +};
746 +
747 #define DRIVER_DESC "Freescale EHCI Host controller driver"
748 #define DRV_NAME "ehci-fsl"
749
750 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
751
752 +struct ehci_fsl {
753 + struct ehci_hcd ehci;
754 +
755 +#ifdef CONFIG_PM
756 +struct ehci_regs saved_regs;
757 +struct ccsr_usb_phy saved_phy_regs;
758 +/* Saved USB PHY settings, need to restore after deep sleep. */
759 +u32 usb_ctrl;
760 +#endif
761 + /*
762 + * store current hcd state for otg;
763 + * have_hcd is true when host drv al already part of otg framework,
764 + * otherwise false;
765 + * hcd_add is true when otg framework wants to add host
766 + * drv as part of otg;flase when it wants to remove it
767 + */
768 +unsigned have_hcd:1;
769 +unsigned hcd_add:1;
770 +};
771 +
772 +static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
773 +{
774 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
775 +
776 +return container_of(ehci, struct ehci_fsl, ehci);
777 +}
778 +
779 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
780 +static void do_change_hcd(struct work_struct *work)
781 +{
782 + struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
783 + change_hcd_work);
784 + struct usb_hcd *hcd = ehci_to_hcd(ehci);
785 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
786 + void __iomem *non_ehci = hcd->regs;
787 + int retval;
788 +
789 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
790 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
791 + /* host, gadget and otg share same int line */
792 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
793 + if (retval == 0)
794 + ehci_fsl->have_hcd = 1;
795 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
796 + usb_remove_hcd(hcd);
797 + ehci_fsl->have_hcd = 0;
798 + }
799 +}
800 +#endif
801 +
802 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
803 +static void do_change_hcd(struct work_struct *work)
804 +{
805 + struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
806 + change_hcd_work);
807 + struct usb_hcd *hcd = ehci_to_hcd(ehci);
808 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
809 + void __iomem *non_ehci = hcd->regs;
810 + int retval;
811 +
812 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
813 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
814 + /* host, gadget and otg share same int line */
815 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
816 + if (retval == 0)
817 + ehci_fsl->have_hcd = 1;
818 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
819 + usb_remove_hcd(hcd);
820 + ehci_fsl->have_hcd = 0;
821 + }
822 +}
823 +#endif
824 +
825 /* configure so an HC device and id are always provided */
826 /* always called with process context; sleeping is OK */
827
828 @@ -131,6 +242,12 @@ static int fsl_ehci_drv_probe(struct pla
829 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
830 CONTROL_REGISTER_W1C_MASK, 0x4);
831
832 + /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
833 + if (pdata->controller_ver == FSL_USB_VER_2_5 &&
834 + pdata->phy_mode == FSL_USB2_PHY_ULPI)
835 + iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
836 +
837 +
838 /*
839 * Enable UTMI phy and program PTS field in UTMI mode before asserting
840 * controller reset for USB Controller version 2.5
841 @@ -143,16 +260,20 @@ static int fsl_ehci_drv_probe(struct pla
842
843 /* Don't need to set host mode here. It will be done by tdi_reset() */
844
845 - retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
846 + retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_NO_SUSPEND);
847 if (retval != 0)
848 goto err2;
849 device_wakeup_enable(hcd->self.controller);
850
851 -#ifdef CONFIG_USB_OTG
852 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
853 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
854 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
855 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
856
857 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
858 +
859 + INIT_WORK(&ehci->change_hcd_work, do_change_hcd);
860 +
861 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
862 hcd, ehci, hcd->usb_phy);
863
864 @@ -168,6 +289,11 @@ static int fsl_ehci_drv_probe(struct pla
865 retval = -ENODEV;
866 goto err2;
867 }
868 +
869 + ehci_fsl->have_hcd = 1;
870 + } else {
871 + dev_err(&pdev->dev, "wrong operating mode\n");
872 + return -ENODEV;
873 }
874 #endif
875 return retval;
876 @@ -181,6 +307,17 @@ static int fsl_ehci_drv_probe(struct pla
877 return retval;
878 }
879
880 +static bool usb_phy_clk_valid(struct usb_hcd *hcd)
881 +{
882 + void __iomem *non_ehci = hcd->regs;
883 + bool ret = true;
884 +
885 + if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
886 + ret = false;
887 +
888 + return ret;
889 +}
890 +
891 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
892 enum fsl_usb2_phy_modes phy_mode,
893 unsigned int port_offset)
894 @@ -219,6 +356,21 @@ static int ehci_fsl_setup_phy(struct usb
895 /* fall through */
896 case FSL_USB2_PHY_UTMI:
897 case FSL_USB2_PHY_UTMI_DUAL:
898 + if (pdata->has_fsl_erratum_a006918) {
899 + pr_warn("fsl-ehci: USB PHY clock invalid\n");
900 + return -EINVAL;
901 + }
902 +
903 + /* PHY_CLK_VALID bit is de-featured from all controller
904 + * versions below 2.4 and is to be checked only for
905 + * internal UTMI phy
906 + */
907 + if (pdata->controller_ver > FSL_USB_VER_2_4 &&
908 + pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
909 + pr_err("fsl-ehci: USB PHY clock invalid\n");
910 + return -EINVAL;
911 + }
912 +
913 if (pdata->have_sysif_regs && pdata->controller_ver) {
914 /* controller version 1.6 or above */
915 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
916 @@ -295,14 +447,9 @@ static int ehci_fsl_usb_setup(struct ehc
917 return -EINVAL;
918
919 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
920 - unsigned int chip, rev, svr;
921 -
922 - svr = mfspr(SPRN_SVR);
923 - chip = svr >> 16;
924 - rev = (svr >> 4) & 0xf;
925
926 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
927 - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
928 + if (pdata->has_fsl_erratum_14 == 1)
929 ehci->has_fsl_port_bug = 1;
930
931 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
932 @@ -382,16 +529,56 @@ static int ehci_fsl_setup(struct usb_hcd
933 return retval;
934 }
935
936 -struct ehci_fsl {
937 - struct ehci_hcd ehci;
938 -
939 #ifdef CONFIG_PM
940 - /* Saved USB PHY settings, need to restore after deep sleep. */
941 - u32 usb_ctrl;
942 -#endif
943 -};
944 +void __iomem *phy_reg;
945
946 -#ifdef CONFIG_PM
947 +#ifdef CONFIG_PPC
948 +/* save usb registers */
949 +static int ehci_fsl_save_context(struct usb_hcd *hcd)
950 +{
951 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
952 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
953 + void __iomem *non_ehci = hcd->regs;
954 + struct device *dev = hcd->self.controller;
955 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
956 +
957 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
958 + phy_reg = ioremap(FSL_USB_PHY_ADDR,
959 + sizeof(struct ccsr_usb_phy));
960 + _memcpy_fromio((void *)&ehci_fsl->saved_phy_regs, phy_reg,
961 + sizeof(struct ccsr_usb_phy));
962 + }
963 +
964 + _memcpy_fromio((void *)&ehci_fsl->saved_regs, ehci->regs,
965 + sizeof(struct ehci_regs));
966 + ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
967 +
968 + return 0;
969 +}
970 +
971 +/*Restore usb registers */
972 +static int ehci_fsl_restore_context(struct usb_hcd *hcd)
973 +{
974 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
975 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
976 + void __iomem *non_ehci = hcd->regs;
977 + struct device *dev = hcd->self.controller;
978 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
979 +
980 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
981 + if (phy_reg)
982 + _memcpy_toio(phy_reg,
983 + (void *)&ehci_fsl->saved_phy_regs,
984 + sizeof(struct ccsr_usb_phy));
985 + }
986 +
987 + _memcpy_toio(ehci->regs, (void *)&ehci_fsl->saved_regs,
988 + sizeof(struct ehci_regs));
989 + iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
990 +
991 + return 0;
992 +}
993 +#endif
994
995 #ifdef CONFIG_PPC_MPC512x
996 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
997 @@ -538,26 +725,45 @@ static inline int ehci_fsl_mpc512x_drv_r
998 }
999 #endif /* CONFIG_PPC_MPC512x */
1000
1001 -static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
1002 -{
1003 - struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1004 -
1005 - return container_of(ehci, struct ehci_fsl, ehci);
1006 -}
1007 -
1008 static int ehci_fsl_drv_suspend(struct device *dev)
1009 {
1010 struct usb_hcd *hcd = dev_get_drvdata(dev);
1011 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1012 void __iomem *non_ehci = hcd->regs;
1013 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1014 + struct usb_bus host = hcd->self;
1015 +#endif
1016 +
1017 +#ifdef CONFIG_PPC
1018 + suspend_state_t pm_state;
1019 + /* FIXME:Need to port fsl_pm.h before enable below code. */
1020 + /*pm_state = pm_suspend_state();*/
1021 + pm_state = PM_SUSPEND_MEM;
1022 +
1023 +if (pm_state == PM_SUSPEND_MEM)
1024 + ehci_fsl_save_context(hcd);
1025 +#endif
1026
1027 if (of_device_is_compatible(dev->parent->of_node,
1028 "fsl,mpc5121-usb2-dr")) {
1029 return ehci_fsl_mpc512x_drv_suspend(dev);
1030 }
1031
1032 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1033 + if (host.is_otg) {
1034 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1035 +
1036 + /* remove hcd */
1037 + ehci_fsl->hcd_add = 0;
1038 + schedule_work(&ehci->change_hcd_work);
1039 + host.is_otg = 0;
1040 + return 0;
1041 + }
1042 +#endif
1043 +
1044 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
1045 device_may_wakeup(dev));
1046 +
1047 if (!fsl_deep_sleep())
1048 return 0;
1049
1050 @@ -571,12 +777,36 @@ static int ehci_fsl_drv_resume(struct de
1051 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1052 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1053 void __iomem *non_ehci = hcd->regs;
1054 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1055 + struct usb_bus host = hcd->self;
1056 +#endif
1057 +
1058 +#ifdef CONFIG_PPC
1059 + suspend_state_t pm_state;
1060 + /* FIXME:Need to port fsl_pm.h before enable below code.*/
1061 + /* pm_state = pm_suspend_state(); */
1062 + pm_state = PM_SUSPEND_MEM;
1063 +
1064 + if (pm_state == PM_SUSPEND_MEM)
1065 + ehci_fsl_restore_context(hcd);
1066 +#endif
1067
1068 if (of_device_is_compatible(dev->parent->of_node,
1069 "fsl,mpc5121-usb2-dr")) {
1070 return ehci_fsl_mpc512x_drv_resume(dev);
1071 }
1072
1073 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1074 + if (host.is_otg) {
1075 + /* add hcd */
1076 + ehci_fsl->hcd_add = 1;
1077 + schedule_work(&ehci->change_hcd_work);
1078 + usb_hcd_resume_root_hub(hcd);
1079 + host.is_otg = 0;
1080 + return 0;
1081 + }
1082 +#endif
1083 +
1084 ehci_prepare_ports_for_controller_resume(ehci);
1085 if (!fsl_deep_sleep())
1086 return 0;
1087 --- a/drivers/usb/host/ehci-fsl.h
1088 +++ b/drivers/usb/host/ehci-fsl.h
1089 @@ -63,4 +63,7 @@
1090 #define UTMI_PHY_EN (1<<9)
1091 #define ULPI_PHY_CLK_SEL (1<<10)
1092 #define PHY_CLK_VALID (1<<17)
1093 +
1094 +/* Retry count for checking UTMI PHY CLK validity */
1095 +#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
1096 #endif /* _EHCI_FSL_H */
1097 --- a/drivers/usb/host/ehci-hub.c
1098 +++ b/drivers/usb/host/ehci-hub.c
1099 @@ -305,6 +305,8 @@ static int ehci_bus_suspend (struct usb_
1100 USB_PORT_STAT_HIGH_SPEED)
1101 fs_idle_delay = true;
1102 ehci_writel(ehci, t2, reg);
1103 + if (ehci_has_fsl_susp_errata(ehci))
1104 + usleep_range(10000, 20000);
1105 changed = 1;
1106 }
1107 }
1108 --- a/drivers/usb/host/ehci.h
1109 +++ b/drivers/usb/host/ehci.h
1110 @@ -180,6 +180,9 @@ struct ehci_hcd { /* one per controlle
1111 unsigned periodic_count; /* periodic activity count */
1112 unsigned uframe_periodic_max; /* max periodic time per uframe */
1113
1114 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1115 + struct work_struct change_hcd_work;
1116 +#endif
1117
1118 /* list of itds & sitds completed while now_frame was still active */
1119 struct list_head cached_itd_list;
1120 --- a/drivers/usb/host/fsl-mph-dr-of.c
1121 +++ b/drivers/usb/host/fsl-mph-dr-of.c
1122 @@ -229,6 +229,17 @@ static int fsl_usb2_mph_dr_of_probe(stru
1123 pdata->has_fsl_erratum_a005697 =
1124 of_property_read_bool(np, "fsl,usb_erratum-a005697");
1125
1126 + if (of_get_property(np, "fsl,erratum_a006918", NULL))
1127 + pdata->has_fsl_erratum_a006918 = 1;
1128 + else
1129 + pdata->has_fsl_erratum_a006918 = 0;
1130 +
1131 + if (of_get_property(np, "fsl,usb_erratum_14", NULL))
1132 + pdata->has_fsl_erratum_14 = 1;
1133 + else
1134 + pdata->has_fsl_erratum_14 = 0;
1135 +
1136 +
1137 /*
1138 * Determine whether phy_clk_valid needs to be checked
1139 * by reading property in device tree
1140 --- a/drivers/usb/host/xhci-hub.c
1141 +++ b/drivers/usb/host/xhci-hub.c
1142 @@ -689,12 +689,34 @@ void xhci_set_link_state(struct xhci_hcd
1143 int port_id, u32 link_state)
1144 {
1145 u32 temp;
1146 + u32 portpmsc_u2_backup = 0;
1147 +
1148 + /* Backup U2 timeout info before initiating U3 entry erratum A-010131 */
1149 + if (xhci->shared_hcd->speed >= HCD_USB3 &&
1150 + link_state == USB_SS_PORT_LS_U3 &&
1151 + (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
1152 + portpmsc_u2_backup = readl(port_array[port_id] + PORTPMSC);
1153 + portpmsc_u2_backup &= PORT_U2_TIMEOUT_MASK;
1154 + temp = readl(port_array[port_id] + PORTPMSC);
1155 + temp |= PORT_U2_TIMEOUT_MASK;
1156 + writel(temp, port_array[port_id] + PORTPMSC);
1157 + }
1158
1159 temp = readl(port_array[port_id]);
1160 temp = xhci_port_state_to_neutral(temp);
1161 temp &= ~PORT_PLS_MASK;
1162 temp |= PORT_LINK_STROBE | link_state;
1163 writel(temp, port_array[port_id]);
1164 +
1165 + /* Restore U2 timeout info after U3 entry complete */
1166 + if (xhci->shared_hcd->speed >= HCD_USB3 &&
1167 + link_state == USB_SS_PORT_LS_U3 &&
1168 + (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
1169 + temp = readl(port_array[port_id] + PORTPMSC);
1170 + temp &= ~PORT_U2_TIMEOUT_MASK;
1171 + temp |= portpmsc_u2_backup;
1172 + writel(temp, port_array[port_id] + PORTPMSC);
1173 + }
1174 }
1175
1176 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
1177 --- a/drivers/usb/host/xhci-plat.c
1178 +++ b/drivers/usb/host/xhci-plat.c
1179 @@ -263,8 +263,22 @@ static int xhci_plat_probe(struct platfo
1180 goto disable_clk;
1181 }
1182
1183 - if (device_property_read_bool(sysdev, "usb3-lpm-capable"))
1184 + if (device_property_read_bool(sysdev, "usb3-lpm-capable")) {
1185 xhci->quirks |= XHCI_LPM_SUPPORT;
1186 + if (device_property_read_bool(sysdev,
1187 + "snps,dis-u1u2-when-u3-quirk"))
1188 + xhci->quirks |= XHCI_DIS_U1U2_WHEN_U3;
1189 + }
1190 +
1191 + if (device_property_read_bool(&pdev->dev, "quirk-reverse-in-out"))
1192 + xhci->quirks |= XHCI_REVERSE_IN_OUT;
1193 +
1194 + if (device_property_read_bool(&pdev->dev,
1195 + "quirk-stop-transfer-in-block"))
1196 + xhci->quirks |= XHCI_STOP_TRANSFER_IN_BLOCK;
1197 +
1198 + if (device_property_read_bool(&pdev->dev, "quirk-stop-ep-in-u1"))
1199 + xhci->quirks |= XHCI_STOP_EP_IN_U1;
1200
1201 if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
1202 xhci->quirks |= XHCI_BROKEN_PORT_PED;
1203 --- a/drivers/usb/host/xhci-ring.c
1204 +++ b/drivers/usb/host/xhci-ring.c
1205 @@ -1972,10 +1972,12 @@ static int finish_td(struct xhci_hcd *xh
1206 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1207 struct xhci_virt_ep *ep, int *status)
1208 {
1209 + struct xhci_dequeue_state deq_state;
1210 struct xhci_virt_device *xdev;
1211 struct xhci_ep_ctx *ep_ctx;
1212 struct xhci_ring *ep_ring;
1213 unsigned int slot_id;
1214 + u32 remaining;
1215 u32 trb_comp_code;
1216 int ep_index;
1217
1218 @@ -1998,14 +2000,30 @@ static int finish_td(struct xhci_hcd *xh
1219 if (trb_comp_code == COMP_STALL_ERROR ||
1220 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1221 trb_comp_code)) {
1222 - /* Issue a reset endpoint command to clear the host side
1223 - * halt, followed by a set dequeue command to move the
1224 - * dequeue pointer past the TD.
1225 - * The class driver clears the device side halt later.
1226 + /*erratum A-007463:
1227 + *After transaction error, controller switches control transfer
1228 + *data stage from IN to OUT direction.
1229 */
1230 - xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1231 + remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1232 + if (remaining && xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1233 + trb_comp_code) &&
1234 + (xhci->quirks & XHCI_REVERSE_IN_OUT)) {
1235 + memset(&deq_state, 0, sizeof(deq_state));
1236 + xhci_find_new_dequeue_state(xhci, slot_id,
1237 + ep_index, td->urb->stream_id, td, &deq_state);
1238 + xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
1239 + &deq_state);
1240 + xhci_ring_cmd_db(xhci);
1241 + } else {
1242 + /* Issue a reset endpoint command to clear the host side
1243 + * halt, followed by a set dequeue command to move the
1244 + * dequeue pointer past the TD.
1245 + * The class driver clears the device side halt later.
1246 + */
1247 + xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1248 ep_ring->stream_id, td, ep_trb,
1249 EP_HARD_RESET);
1250 + }
1251 } else {
1252 /* Update ring dequeue pointer */
1253 while (ep_ring->dequeue != td->last_trb)
1254 --- a/drivers/usb/host/xhci.c
1255 +++ b/drivers/usb/host/xhci.c
1256 @@ -1597,13 +1597,38 @@ static int xhci_urb_dequeue(struct usb_h
1257 ret = -ENOMEM;
1258 goto done;
1259 }
1260 - ep->ep_state |= EP_STOP_CMD_PENDING;
1261 - ep->stop_cmd_timer.expires = jiffies +
1262 + /*
1263 + *erratum A-009611: Issuing an End Transfer command on an IN
1264 + *endpoint. when a transfer is in progress on USB blocks the
1265 + *transmission.
1266 + *Workaround: Software must wait for all existing TRBs to
1267 + *complete before issuing End transfer command.
1268 + */
1269 + if ((ep_ring->enqueue == ep_ring->dequeue &&
1270 + (xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) ||
1271 + !(xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) {
1272 + ep->ep_state |= EP_STOP_CMD_PENDING;
1273 + ep->stop_cmd_timer.expires = jiffies +
1274 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1275 - add_timer(&ep->stop_cmd_timer);
1276 - xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1277 - ep_index, 0);
1278 - xhci_ring_cmd_db(xhci);
1279 + add_timer(&ep->stop_cmd_timer);
1280 + xhci_queue_stop_endpoint(xhci, command,
1281 + urb->dev->slot_id,
1282 + ep_index, 0);
1283 + xhci_ring_cmd_db(xhci);
1284 + }
1285 +
1286 + /*
1287 + *erratum A-009668: Stop Endpoint Command does not complete.
1288 + *Workaround: Instead of issuing a Stop Endpoint Command,
1289 + *issue a Disable Slot Command with the corresponding slot ID.
1290 + *Alternately, you can issue an Address Device Command with
1291 + *BSR=1
1292 + */
1293 + if ((urb->dev->speed <= USB_SPEED_HIGH) &&
1294 + (xhci->quirks & XHCI_STOP_EP_IN_U1)) {
1295 + xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
1296 + urb->dev->slot_id);
1297 + }
1298 }
1299 done:
1300 spin_unlock_irqrestore(&xhci->lock, flags);
1301 @@ -4988,7 +5013,7 @@ int xhci_gen_setup(struct usb_hcd *hcd,
1302 return retval;
1303 xhci_dbg(xhci, "Called HCD init\n");
1304
1305 - xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
1306 + xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%llx\n",
1307 xhci->hcc_params, xhci->hci_version, xhci->quirks);
1308
1309 return 0;
1310 --- a/drivers/usb/host/xhci.h
1311 +++ b/drivers/usb/host/xhci.h
1312 @@ -1794,7 +1794,7 @@ struct xhci_hcd {
1313 #define XHCI_STATE_DYING (1 << 0)
1314 #define XHCI_STATE_HALTED (1 << 1)
1315 #define XHCI_STATE_REMOVING (1 << 2)
1316 - unsigned long long quirks;
1317 + u64 quirks;
1318 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1319 #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1320 #define XHCI_NEC_HOST BIT_ULL(2)
1321 @@ -1830,6 +1830,9 @@ struct xhci_hcd {
1322 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1323 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1324 #define XHCI_MISSING_CAS BIT_ULL(24)
1325 +#define XHCI_REVERSE_IN_OUT BIT(32)
1326 +#define XHCI_STOP_TRANSFER_IN_BLOCK BIT(33)
1327 +#define XHCI_STOP_EP_IN_U1 BIT(34)
1328 /* For controller with a broken Port Disable implementation */
1329 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1330 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1331 @@ -1840,6 +1843,7 @@ struct xhci_hcd {
1332 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1333 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1334 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1335 +#define XHCI_DIS_U1U2_WHEN_U3 BIT(36)
1336
1337 unsigned int num_active_eps;
1338 unsigned int limit_active_eps;
1339 --- a/drivers/usb/phy/phy-fsl-usb.c
1340 +++ b/drivers/usb/phy/phy-fsl-usb.c
1341 @@ -1,5 +1,5 @@
1342 /*
1343 - * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
1344 + * Copyright 2007,2008 Freescale Semiconductor, Inc.
1345 *
1346 * Author: Li Yang <LeoLi@freescale.com>
1347 * Jerry Huang <Chang-Ming.Huang@freescale.com>
1348 @@ -470,6 +470,7 @@ void otg_reset_controller(void)
1349 int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1350 {
1351 struct usb_otg *otg = fsm->otg;
1352 + struct usb_bus *host = otg->host;
1353 struct device *dev;
1354 struct fsl_otg *otg_dev =
1355 container_of(otg->usb_phy, struct fsl_otg, phy);
1356 @@ -493,6 +494,7 @@ int fsl_otg_start_host(struct otg_fsm *f
1357 otg_reset_controller();
1358 VDBG("host on......\n");
1359 if (dev->driver->pm && dev->driver->pm->resume) {
1360 + host->is_otg = 1;
1361 retval = dev->driver->pm->resume(dev);
1362 if (fsm->id) {
1363 /* default-b */
1364 @@ -517,8 +519,11 @@ int fsl_otg_start_host(struct otg_fsm *f
1365 else {
1366 VDBG("host off......\n");
1367 if (dev && dev->driver) {
1368 - if (dev->driver->pm && dev->driver->pm->suspend)
1369 + if (dev->driver->pm &&
1370 + dev->driver->pm->suspend) {
1371 + host->is_otg = 1;
1372 retval = dev->driver->pm->suspend(dev);
1373 + }
1374 if (fsm->id)
1375 /* default-b */
1376 fsl_otg_drv_vbus(fsm, 0);
1377 @@ -546,8 +551,17 @@ int fsl_otg_start_gadget(struct otg_fsm
1378 dev = otg->gadget->dev.parent;
1379
1380 if (on) {
1381 - if (dev->driver->resume)
1382 + /* Delay gadget resume to synchronize between host and gadget
1383 + * drivers. Upon role-reversal host drv is shutdown by kernel
1384 + * worker thread. By the time host drv shuts down, controller
1385 + * gets programmed for gadget role. Shutting host drv after
1386 + * this results in controller getting reset, and it stops
1387 + * responding to otg events
1388 + */
1389 + if (dev->driver->resume) {
1390 + msleep(1000);
1391 dev->driver->resume(dev);
1392 + }
1393 } else {
1394 if (dev->driver->suspend)
1395 dev->driver->suspend(dev, otg_suspend_state);
1396 @@ -668,6 +682,10 @@ static void fsl_otg_event(struct work_st
1397 fsl_otg_start_host(fsm, 0);
1398 otg_drv_vbus(fsm, 0);
1399 fsl_otg_start_gadget(fsm, 1);
1400 + } else {
1401 + fsl_otg_start_gadget(fsm, 0);
1402 + otg_drv_vbus(fsm, 1);
1403 + fsl_otg_start_host(fsm, 1);
1404 }
1405 }
1406
1407 @@ -720,6 +738,7 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1408 {
1409 struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
1410 struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
1411 + struct fsl_otg *otg_dev = dev_id;
1412 u32 otg_int_src, otg_sc;
1413
1414 otg_sc = fsl_readl(&usb_dr_regs->otgsc);
1415 @@ -749,18 +768,8 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1416 otg->gadget->is_a_peripheral = !fsm->id;
1417 VDBG("ID int (ID is %d)\n", fsm->id);
1418
1419 - if (fsm->id) { /* switch to gadget */
1420 - schedule_delayed_work(
1421 - &((struct fsl_otg *)dev_id)->otg_event,
1422 - 100);
1423 - } else { /* switch to host */
1424 - cancel_delayed_work(&
1425 - ((struct fsl_otg *)dev_id)->
1426 - otg_event);
1427 - fsl_otg_start_gadget(fsm, 0);
1428 - otg_drv_vbus(fsm, 1);
1429 - fsl_otg_start_host(fsm, 1);
1430 - }
1431 + schedule_delayed_work(&otg_dev->otg_event, 100);
1432 +
1433 return IRQ_HANDLED;
1434 }
1435 }
1436 @@ -920,12 +929,32 @@ int usb_otg_start(struct platform_device
1437 temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
1438 switch (pdata->phy_mode) {
1439 case FSL_USB2_PHY_ULPI:
1440 + if (pdata->controller_ver) {
1441 + /* controller version 1.6 or above */
1442 + setbits32(&p_otg->dr_mem_map->control,
1443 + USB_CTRL_ULPI_PHY_CLK_SEL);
1444 + /*
1445 + * Due to controller issue of PHY_CLK_VALID in ULPI
1446 + * mode, we set USB_CTRL_USB_EN before checking
1447 + * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
1448 + */
1449 + clrsetbits_be32(&p_otg->dr_mem_map->control,
1450 + USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
1451 + }
1452 temp |= PORTSC_PTS_ULPI;
1453 break;
1454 case FSL_USB2_PHY_UTMI_WIDE:
1455 temp |= PORTSC_PTW_16BIT;
1456 /* fall through */
1457 case FSL_USB2_PHY_UTMI:
1458 + if (pdata->controller_ver) {
1459 + /* controller version 1.6 or above */
1460 + setbits32(&p_otg->dr_mem_map->control,
1461 + USB_CTRL_UTMI_PHY_EN);
1462 + /* Delay for UTMI PHY CLK to become stable - 10ms */
1463 + mdelay(FSL_UTMI_PHY_DLY);
1464 + }
1465 + setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
1466 temp |= PORTSC_PTS_UTMI;
1467 /* fall through */
1468 default:
1469 --- a/drivers/usb/phy/phy-fsl-usb.h
1470 +++ b/drivers/usb/phy/phy-fsl-usb.h
1471 @@ -199,6 +199,14 @@
1472 /* control Register Bit Masks */
1473 #define USB_CTRL_IOENB (0x1<<2)
1474 #define USB_CTRL_ULPI_INT0EN (0x1<<0)
1475 +#define USB_CTRL_WU_INT_EN (0x1<<1)
1476 +#define USB_CTRL_LINE_STATE_FILTER__EN (0x1<<3)
1477 +#define USB_CTRL_KEEP_OTG_ON (0x1<<4)
1478 +#define USB_CTRL_OTG_PORT (0x1<<5)
1479 +#define USB_CTRL_PLL_RESET (0x1<<8)
1480 +#define USB_CTRL_UTMI_PHY_EN (0x1<<9)
1481 +#define USB_CTRL_ULPI_PHY_CLK_SEL (0x1<<10)
1482 +#define USB_CTRL_PHY_CLK_VALID (0x1<<17)
1483
1484 /* BCSR5 */
1485 #define BCSR5_INT_USB (0x02)
1486 --- a/include/linux/usb.h
1487 +++ b/include/linux/usb.h
1488 @@ -434,6 +434,7 @@ struct usb_bus {
1489 * for control transfers?
1490 */
1491 u8 otg_port; /* 0, or number of OTG/HNP port */
1492 + unsigned is_otg:1; /* true when host is also otg */
1493 unsigned is_b_host:1; /* true during some HNP roleswitches */
1494 unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */
1495 unsigned no_stop_on_short:1; /*
1496 --- a/include/linux/usb/of.h
1497 +++ b/include/linux/usb/of.h
1498 @@ -11,6 +11,8 @@
1499 #include <linux/usb/otg.h>
1500 #include <linux/usb/phy.h>
1501
1502 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
1503 +
1504 #if IS_ENABLED(CONFIG_OF)
1505 enum usb_dr_mode of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0);
1506 bool of_usb_host_tpl_support(struct device_node *np);
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