target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch

   1 From a00c035c7b82f51716a1a30637b1bd276dee3c5a Mon Sep 17 00:00:00 2001
   2 From: Biwen Li <biwen.li@nxp.com>
   3 Date: Wed, 17 Apr 2019 18:58:17 +0800
   4 Subject: [PATCH] clock: support layerscape
   5
   6 This is an integrated patch of clock for layerscape
   7
   8 Signed-off-by: Biwen Li <biwen.li@nxp.com>
   9 Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
  10 Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
  11 Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  12 ---
  13  drivers/clk/clk-qoriq.c         | 25 ++++++++++++++++++++++---
  14  drivers/cpufreq/qoriq-cpufreq.c |  1 +
  15  2 files changed, 23 insertions(+), 3 deletions(-)
  16
  17 --- a/drivers/clk/clk-qoriq.c
  18 +++ b/drivers/clk/clk-qoriq.c
  19 @@ -41,7 +41,7 @@ struct clockgen_pll_div {
  20  };
  21
  22  struct clockgen_pll {
  23 -       struct clockgen_pll_div div[4];
  24 +       struct clockgen_pll_div div[8];
  25  };
  26
  27  #define CLKSEL_VALID   1
  28 @@ -79,7 +79,7 @@ struct clockgen_chipinfo {
  29         const struct clockgen_muxinfo *cmux_groups[2];
  30         const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
  31         void (*init_periph)(struct clockgen *cg);
  32 -       int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
  33 +       int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */
  34         u32 pll_mask;   /* 1 << n bit set if PLL n is valid */
  35         u32 flags;      /* CG_xxx */
  36  };
  37 @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo ch
  38                 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
  39         },
  40         {
  41 +               .compat = "fsl,lx2160a-clockgen",
  42 +               .cmux_groups = {
  43 +                       &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
  44 +               },
  45 +               .cmux_to_group = {
  46 +                       0, 0, 0, 0, 1, 1, 1, 1, -1
  47 +               },
  48 +               .pll_mask = 0x37,
  49 +               .flags = CG_VER3 | CG_LITTLE_ENDIAN,
  50 +       },
  51 +       {
  52                 .compat = "fsl,p2041-clockgen",
  53                 .guts_compat = "fsl,qoriq-device-config-1.0",
  54                 .init_periph = p2041_init_periph,
  55 @@ -601,7 +612,7 @@ static const struct clockgen_chipinfo ch
  56                         &p4080_cmux_grp1, &p4080_cmux_grp2
  57                 },
  58                 .cmux_to_group = {
  59 -                       0, 0, 0, 0, 1, 1, 1, 1
  60 +                       0, 0, 0, 0, 1, 1, 1, 1, -1
  61                 },
  62                 .pll_mask = 0x1f,
  63         },
  64 @@ -1127,6 +1138,13 @@ static void __init create_one_pll(struct
  65                 struct clk *clk;
  66                 int ret;
  67
  68 +               /*
  69 +                * For platform PLL, there are 8 divider clocks.
  70 +                * For core PLL, there are 4 divider clocks at most.
  71 +                */
  72 +               if (idx != 0 && i >= 4)
  73 +                       break;
  74 +
  75                 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
  76                          "cg-pll%d-div%d", idx, i + 1);
  77
  78 @@ -1418,6 +1436,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "
  79  CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
  80  CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
  81  CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
  82 +CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
  83
  84  /* Legacy nodes */
  85  CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
  86 --- a/drivers/cpufreq/qoriq-cpufreq.c
  87 +++ b/drivers/cpufreq/qoriq-cpufreq.c
  88 @@ -320,6 +320,7 @@ static const struct of_device_id node_ma
  89         { .compatible = "fsl,ls1046a-clockgen", },
  90         { .compatible = "fsl,ls1088a-clockgen", },
  91         { .compatible = "fsl,ls2080a-clockgen", },
  92 +       { .compatible = "fsl,lx2160a-clockgen", },
  93         { .compatible = "fsl,p4080-clockgen", },
  94         { .compatible = "fsl,qoriq-clockgen-1.0", },
  95         { .compatible = "fsl,qoriq-clockgen-2.0", },