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kernel: bump 4.14 to 4.14.176
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.14 / 816-pcie-support-layerscape.patch
1 From c54a010fe105281259b996d318ed85efc4103fee Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 6 May 2019 15:18:05 +0800
4 Subject: [PATCH] pcie: support layerscape
5
6 This is an integrated patch of pcie for layerscape
7
8 Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
9 Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
10 Signed-off-by: Biwen Li <biwen.li@nxp.com>
11 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
12 Signed-off-by: Christoph Hellwig <hch@lst.de>
13 Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
14 Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
15 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
16 Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
17 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
18 Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
19 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
20 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
22 Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
23 Signed-off-by: Po Liu <po.liu@nxp.com>
24 Signed-off-by: Rob Herring <robh@kernel.org>
25 Signed-off-by: Rolf Evers-Fischer <rolf.evers.fischer@aptiv.com>
26 Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
27 Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
28 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
29 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
30 ---
31 arch/arm/kernel/bios32.c | 43 ++
32 arch/arm64/kernel/pci.c | 43 ++
33 drivers/misc/pci_endpoint_test.c | 332 ++++++++++---
34 drivers/pci/Kconfig | 1 +
35 drivers/pci/dwc/Kconfig | 39 +-
36 drivers/pci/dwc/Makefile | 2 +-
37 drivers/pci/dwc/pci-dra7xx.c | 9 -
38 drivers/pci/dwc/pci-layerscape-ep.c | 146 ++++++
39 drivers/pci/dwc/pci-layerscape.c | 12 +
40 drivers/pci/dwc/pcie-designware-ep.c | 338 ++++++++++++--
41 drivers/pci/dwc/pcie-designware-host.c | 5 +-
42 drivers/pci/dwc/pcie-designware-plat.c | 159 ++++++-
43 drivers/pci/dwc/pcie-designware.c | 5 +-
44 drivers/pci/dwc/pcie-designware.h | 57 ++-
45 drivers/pci/endpoint/Kconfig | 1 +
46 drivers/pci/endpoint/Makefile | 1 +
47 drivers/pci/endpoint/functions/Kconfig | 1 +
48 drivers/pci/endpoint/functions/Makefile | 1 +
49 drivers/pci/endpoint/functions/pci-epf-test.c | 191 +++++---
50 drivers/pci/endpoint/pci-ep-cfs.c | 95 +++-
51 drivers/pci/endpoint/pci-epc-core.c | 159 +++++--
52 drivers/pci/endpoint/pci-epc-mem.c | 13 +-
53 drivers/pci/endpoint/pci-epf-core.c | 116 +++--
54 drivers/pci/host/pci-host-common.c | 8 -
55 drivers/pci/host/pcie-xilinx-nwl.c | 9 -
56 drivers/pci/host/pcie-xilinx.c | 7 -
57 drivers/pci/mobiveil/Kconfig | 50 ++
58 drivers/pci/mobiveil/Makefile | 7 +
59 drivers/pci/mobiveil/pci-layerscape-gen4-ep.c | 178 +++++++
60 drivers/pci/mobiveil/pci-layerscape-gen4.c | 292 ++++++++++++
61 drivers/pci/mobiveil/pcie-mobiveil-ep.c | 512 +++++++++++++++++++++
62 drivers/pci/mobiveil/pcie-mobiveil-host.c | 640 ++++++++++++++++++++++++++
63 drivers/pci/mobiveil/pcie-mobiveil-plat.c | 54 +++
64 drivers/pci/mobiveil/pcie-mobiveil.c | 334 ++++++++++++++
65 drivers/pci/mobiveil/pcie-mobiveil.h | 296 ++++++++++++
66 drivers/pci/pcie/portdrv_core.c | 29 ++
67 drivers/pci/quirks.c | 15 +
68 include/linux/pci-ep-cfs.h | 5 +-
69 include/linux/pci-epc.h | 73 +--
70 include/linux/pci-epf.h | 12 +-
71 include/linux/pci.h | 1 +
72 include/uapi/linux/pcitest.h | 3 +
73 tools/pci/pcitest.c | 51 +-
74 tools/pci/pcitest.sh | 15 +
75 44 files changed, 3917 insertions(+), 443 deletions(-)
76 create mode 100644 drivers/pci/dwc/pci-layerscape-ep.c
77 create mode 100644 drivers/pci/mobiveil/Kconfig
78 create mode 100644 drivers/pci/mobiveil/Makefile
79 create mode 100644 drivers/pci/mobiveil/pci-layerscape-gen4-ep.c
80 create mode 100644 drivers/pci/mobiveil/pci-layerscape-gen4.c
81 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil-ep.c
82 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil-host.c
83 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil-plat.c
84 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil.c
85 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil.h
86
87 --- a/arch/arm/kernel/bios32.c
88 +++ b/arch/arm/kernel/bios32.c
89 @@ -12,6 +12,8 @@
90 #include <linux/slab.h>
91 #include <linux/init.h>
92 #include <linux/io.h>
93 +#include <linux/of_irq.h>
94 +#include <linux/pcieport_if.h>
95
96 #include <asm/mach-types.h>
97 #include <asm/mach/map.h>
98 @@ -65,6 +67,47 @@ void pcibios_report_status(u_int status_
99 }
100
101 /*
102 + * Check device tree if the service interrupts are there
103 + */
104 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
105 +{
106 + int ret, count = 0;
107 + struct device_node *np = NULL;
108 +
109 + if (dev->bus->dev.of_node)
110 + np = dev->bus->dev.of_node;
111 +
112 + if (np == NULL)
113 + return 0;
114 +
115 + if (!IS_ENABLED(CONFIG_OF_IRQ))
116 + return 0;
117 +
118 + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
119 + * request irq for aer
120 + */
121 + if (mask & PCIE_PORT_SERVICE_AER) {
122 + ret = of_irq_get_byname(np, "aer");
123 + if (ret > 0) {
124 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
125 + count++;
126 + }
127 + }
128 +
129 + if (mask & PCIE_PORT_SERVICE_PME) {
130 + ret = of_irq_get_byname(np, "pme");
131 + if (ret > 0) {
132 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
133 + count++;
134 + }
135 + }
136 +
137 + /* TODO: add more service interrupts if there it is in the device tree*/
138 +
139 + return count;
140 +}
141 +
142 +/*
143 * We don't use this to fix the device, but initialisation of it.
144 * It's not the correct use for this, but it works.
145 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
146 --- a/arch/arm64/kernel/pci.c
147 +++ b/arch/arm64/kernel/pci.c
148 @@ -17,6 +17,8 @@
149 #include <linux/mm.h>
150 #include <linux/of_pci.h>
151 #include <linux/of_platform.h>
152 +#include <linux/of_irq.h>
153 +#include <linux/pcieport_if.h>
154 #include <linux/pci.h>
155 #include <linux/pci-acpi.h>
156 #include <linux/pci-ecam.h>
157 @@ -36,6 +38,47 @@ int pcibios_alloc_irq(struct pci_dev *de
158 #endif
159
160 /*
161 + * Check device tree if the service interrupts are there
162 + */
163 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
164 +{
165 + int ret, count = 0;
166 + struct device_node *np = NULL;
167 +
168 + if (dev->bus->dev.of_node)
169 + np = dev->bus->dev.of_node;
170 +
171 + if (np == NULL)
172 + return 0;
173 +
174 + if (!IS_ENABLED(CONFIG_OF_IRQ))
175 + return 0;
176 +
177 + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
178 + * request irq for aer
179 + */
180 + if (mask & PCIE_PORT_SERVICE_AER) {
181 + ret = of_irq_get_byname(np, "aer");
182 + if (ret > 0) {
183 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
184 + count++;
185 + }
186 + }
187 +
188 + if (mask & PCIE_PORT_SERVICE_PME) {
189 + ret = of_irq_get_byname(np, "pme");
190 + if (ret > 0) {
191 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
192 + count++;
193 + }
194 + }
195 +
196 + /* TODO: add more service interrupts if there it is in the device tree*/
197 +
198 + return count;
199 +}
200 +
201 +/*
202 * raw_pci_read/write - Platform-specific PCI config space access.
203 */
204 int raw_pci_read(unsigned int domain, unsigned int bus,
205 --- a/drivers/misc/pci_endpoint_test.c
206 +++ b/drivers/misc/pci_endpoint_test.c
207 @@ -35,38 +35,45 @@
208
209 #include <uapi/linux/pcitest.h>
210
211 -#define DRV_MODULE_NAME "pci-endpoint-test"
212 +#define DRV_MODULE_NAME "pci-endpoint-test"
213
214 -#define PCI_ENDPOINT_TEST_MAGIC 0x0
215 +#define IRQ_TYPE_UNDEFINED -1
216 +#define IRQ_TYPE_LEGACY 0
217 +#define IRQ_TYPE_MSI 1
218 +#define IRQ_TYPE_MSIX 2
219 +
220 +#define PCI_ENDPOINT_TEST_MAGIC 0x0
221 +
222 +#define PCI_ENDPOINT_TEST_COMMAND 0x4
223 +#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
224 +#define COMMAND_RAISE_MSI_IRQ BIT(1)
225 +#define COMMAND_RAISE_MSIX_IRQ BIT(2)
226 +#define COMMAND_READ BIT(3)
227 +#define COMMAND_WRITE BIT(4)
228 +#define COMMAND_COPY BIT(5)
229 +
230 +#define PCI_ENDPOINT_TEST_STATUS 0x8
231 +#define STATUS_READ_SUCCESS BIT(0)
232 +#define STATUS_READ_FAIL BIT(1)
233 +#define STATUS_WRITE_SUCCESS BIT(2)
234 +#define STATUS_WRITE_FAIL BIT(3)
235 +#define STATUS_COPY_SUCCESS BIT(4)
236 +#define STATUS_COPY_FAIL BIT(5)
237 +#define STATUS_IRQ_RAISED BIT(6)
238 +#define STATUS_SRC_ADDR_INVALID BIT(7)
239 +#define STATUS_DST_ADDR_INVALID BIT(8)
240
241 -#define PCI_ENDPOINT_TEST_COMMAND 0x4
242 -#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
243 -#define COMMAND_RAISE_MSI_IRQ BIT(1)
244 -#define MSI_NUMBER_SHIFT 2
245 -/* 6 bits for MSI number */
246 -#define COMMAND_READ BIT(8)
247 -#define COMMAND_WRITE BIT(9)
248 -#define COMMAND_COPY BIT(10)
249 -
250 -#define PCI_ENDPOINT_TEST_STATUS 0x8
251 -#define STATUS_READ_SUCCESS BIT(0)
252 -#define STATUS_READ_FAIL BIT(1)
253 -#define STATUS_WRITE_SUCCESS BIT(2)
254 -#define STATUS_WRITE_FAIL BIT(3)
255 -#define STATUS_COPY_SUCCESS BIT(4)
256 -#define STATUS_COPY_FAIL BIT(5)
257 -#define STATUS_IRQ_RAISED BIT(6)
258 -#define STATUS_SRC_ADDR_INVALID BIT(7)
259 -#define STATUS_DST_ADDR_INVALID BIT(8)
260 -
261 -#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
262 +#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
263 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
264
265 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
266 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
267
268 -#define PCI_ENDPOINT_TEST_SIZE 0x1c
269 -#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
270 +#define PCI_ENDPOINT_TEST_SIZE 0x1c
271 +#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
272 +
273 +#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
274 +#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
275
276 static DEFINE_IDA(pci_endpoint_test_ida);
277
278 @@ -77,6 +84,10 @@ static bool no_msi;
279 module_param(no_msi, bool, 0444);
280 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
281
282 +static int irq_type = IRQ_TYPE_MSI;
283 +module_param(irq_type, int, 0444);
284 +MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
285 +
286 enum pci_barno {
287 BAR_0,
288 BAR_1,
289 @@ -103,7 +114,7 @@ struct pci_endpoint_test {
290 struct pci_endpoint_test_data {
291 enum pci_barno test_reg_bar;
292 size_t alignment;
293 - bool no_msi;
294 + int irq_type;
295 };
296
297 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
298 @@ -147,6 +158,100 @@ static irqreturn_t pci_endpoint_test_irq
299 return IRQ_HANDLED;
300 }
301
302 +static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
303 +{
304 + struct pci_dev *pdev = test->pdev;
305 +
306 + pci_free_irq_vectors(pdev);
307 +}
308 +
309 +static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
310 + int type)
311 +{
312 + int irq = -1;
313 + struct pci_dev *pdev = test->pdev;
314 + struct device *dev = &pdev->dev;
315 + bool res = true;
316 +
317 + switch (type) {
318 + case IRQ_TYPE_LEGACY:
319 + irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
320 + if (irq < 0)
321 + dev_err(dev, "Failed to get Legacy interrupt\n");
322 + break;
323 + case IRQ_TYPE_MSI:
324 + irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
325 + if (irq < 0)
326 + dev_err(dev, "Failed to get MSI interrupts\n");
327 + break;
328 + case IRQ_TYPE_MSIX:
329 + irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
330 + if (irq < 0)
331 + dev_err(dev, "Failed to get MSI-X interrupts\n");
332 + break;
333 + default:
334 + dev_err(dev, "Invalid IRQ type selected\n");
335 + }
336 +
337 + if (irq < 0) {
338 + irq = 0;
339 + res = false;
340 + }
341 + test->num_irqs = irq;
342 +
343 + return res;
344 +}
345 +
346 +static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
347 +{
348 + int i;
349 + struct pci_dev *pdev = test->pdev;
350 + struct device *dev = &pdev->dev;
351 +
352 + for (i = 0; i < test->num_irqs; i++)
353 + devm_free_irq(dev, pci_irq_vector(pdev, i), test);
354 +
355 + test->num_irqs = 0;
356 +}
357 +
358 +static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
359 +{
360 + int i;
361 + int err;
362 + struct pci_dev *pdev = test->pdev;
363 + struct device *dev = &pdev->dev;
364 +
365 + for (i = 0; i < test->num_irqs; i++) {
366 + err = devm_request_irq(dev, pci_irq_vector(pdev, i),
367 + pci_endpoint_test_irqhandler,
368 + IRQF_SHARED, DRV_MODULE_NAME, test);
369 + if (err)
370 + goto fail;
371 + }
372 +
373 + return true;
374 +
375 +fail:
376 + switch (irq_type) {
377 + case IRQ_TYPE_LEGACY:
378 + dev_err(dev, "Failed to request IRQ %d for Legacy\n",
379 + pci_irq_vector(pdev, i));
380 + break;
381 + case IRQ_TYPE_MSI:
382 + dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
383 + pci_irq_vector(pdev, i),
384 + i + 1);
385 + break;
386 + case IRQ_TYPE_MSIX:
387 + dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
388 + pci_irq_vector(pdev, i),
389 + i + 1);
390 + break;
391 + }
392 +
393 + return false;
394 +}
395 +
396 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
397 enum pci_barno barno)
398 {
399 @@ -179,6 +284,9 @@ static bool pci_endpoint_test_legacy_irq
400 {
401 u32 val;
402
403 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
404 + IRQ_TYPE_LEGACY);
405 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
406 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
407 COMMAND_RAISE_LEGACY_IRQ);
408 val = wait_for_completion_timeout(&test->irq_raised,
409 @@ -190,20 +298,24 @@ static bool pci_endpoint_test_legacy_irq
410 }
411
412 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
413 - u8 msi_num)
414 + u16 msi_num, bool msix)
415 {
416 u32 val;
417 struct pci_dev *pdev = test->pdev;
418
419 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
420 + msix == false ? IRQ_TYPE_MSI :
421 + IRQ_TYPE_MSIX);
422 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
423 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
424 - msi_num << MSI_NUMBER_SHIFT |
425 - COMMAND_RAISE_MSI_IRQ);
426 + msix == false ? COMMAND_RAISE_MSI_IRQ :
427 + COMMAND_RAISE_MSIX_IRQ);
428 val = wait_for_completion_timeout(&test->irq_raised,
429 msecs_to_jiffies(1000));
430 if (!val)
431 return false;
432
433 - if (test->last_irq - pdev->irq == msi_num - 1)
434 + if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
435 return true;
436
437 return false;
438 @@ -230,10 +342,18 @@ static bool pci_endpoint_test_copy(struc
439 if (size > SIZE_MAX - alignment)
440 goto err;
441
442 + if (size > SIZE_MAX - alignment)
443 + goto err;
444 +
445 + if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
446 + dev_err(dev, "Invalid IRQ type option\n");
447 + goto err;
448 + }
449 +
450 orig_src_addr = dma_alloc_coherent(dev, size + alignment,
451 &orig_src_phys_addr, GFP_KERNEL);
452 if (!orig_src_addr) {
453 - dev_err(dev, "failed to allocate source buffer\n");
454 + dev_err(dev, "Failed to allocate source buffer\n");
455 ret = false;
456 goto err;
457 }
458 @@ -259,7 +379,7 @@ static bool pci_endpoint_test_copy(struc
459 orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
460 &orig_dst_phys_addr, GFP_KERNEL);
461 if (!orig_dst_addr) {
462 - dev_err(dev, "failed to allocate destination address\n");
463 + dev_err(dev, "Failed to allocate destination address\n");
464 ret = false;
465 goto err_orig_src_addr;
466 }
467 @@ -281,8 +401,10 @@ static bool pci_endpoint_test_copy(struc
468 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
469 size);
470
471 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
472 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
473 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
474 - 1 << MSI_NUMBER_SHIFT | COMMAND_COPY);
475 + COMMAND_COPY);
476
477 wait_for_completion(&test->irq_raised);
478
479 @@ -318,10 +440,18 @@ static bool pci_endpoint_test_write(stru
480 if (size > SIZE_MAX - alignment)
481 goto err;
482
483 + if (size > SIZE_MAX - alignment)
484 + goto err;
485 +
486 + if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
487 + dev_err(dev, "Invalid IRQ type option\n");
488 + goto err;
489 + }
490 +
491 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
492 GFP_KERNEL);
493 if (!orig_addr) {
494 - dev_err(dev, "failed to allocate address\n");
495 + dev_err(dev, "Failed to allocate address\n");
496 ret = false;
497 goto err;
498 }
499 @@ -348,8 +478,10 @@ static bool pci_endpoint_test_write(stru
500
501 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
502
503 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
504 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
505 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
506 - 1 << MSI_NUMBER_SHIFT | COMMAND_READ);
507 + COMMAND_READ);
508
509 wait_for_completion(&test->irq_raised);
510
511 @@ -379,10 +511,18 @@ static bool pci_endpoint_test_read(struc
512 if (size > SIZE_MAX - alignment)
513 goto err;
514
515 + if (size > SIZE_MAX - alignment)
516 + goto err;
517 +
518 + if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
519 + dev_err(dev, "Invalid IRQ type option\n");
520 + goto err;
521 + }
522 +
523 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
524 GFP_KERNEL);
525 if (!orig_addr) {
526 - dev_err(dev, "failed to allocate destination address\n");
527 + dev_err(dev, "Failed to allocate destination address\n");
528 ret = false;
529 goto err;
530 }
531 @@ -403,8 +543,10 @@ static bool pci_endpoint_test_read(struc
532
533 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
534
535 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
536 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
537 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
538 - 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE);
539 + COMMAND_WRITE);
540
541 wait_for_completion(&test->irq_raised);
542
543 @@ -417,6 +559,38 @@ err:
544 return ret;
545 }
546
547 +static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
548 + int req_irq_type)
549 +{
550 + struct pci_dev *pdev = test->pdev;
551 + struct device *dev = &pdev->dev;
552 +
553 + if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
554 + dev_err(dev, "Invalid IRQ type option\n");
555 + return false;
556 + }
557 +
558 + if (irq_type == req_irq_type)
559 + return true;
560 +
561 + pci_endpoint_test_release_irq(test);
562 + pci_endpoint_test_free_irq_vectors(test);
563 +
564 + if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
565 + goto err;
566 +
567 + if (!pci_endpoint_test_request_irq(test))
568 + goto err;
569 +
570 + irq_type = req_irq_type;
571 + return true;
572 +
573 +err:
574 + pci_endpoint_test_free_irq_vectors(test);
575 + irq_type = IRQ_TYPE_UNDEFINED;
576 + return false;
577 +}
578 +
579 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
580 unsigned long arg)
581 {
582 @@ -436,7 +610,8 @@ static long pci_endpoint_test_ioctl(stru
583 ret = pci_endpoint_test_legacy_irq(test);
584 break;
585 case PCITEST_MSI:
586 - ret = pci_endpoint_test_msi_irq(test, arg);
587 + case PCITEST_MSIX:
588 + ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
589 break;
590 case PCITEST_WRITE:
591 ret = pci_endpoint_test_write(test, arg);
592 @@ -447,6 +622,12 @@ static long pci_endpoint_test_ioctl(stru
593 case PCITEST_COPY:
594 ret = pci_endpoint_test_copy(test, arg);
595 break;
596 + case PCITEST_SET_IRQTYPE:
597 + ret = pci_endpoint_test_set_irq(test, arg);
598 + break;
599 + case PCITEST_GET_IRQTYPE:
600 + ret = irq_type;
601 + break;
602 }
603
604 ret:
605 @@ -462,9 +643,7 @@ static const struct file_operations pci_
606 static int pci_endpoint_test_probe(struct pci_dev *pdev,
607 const struct pci_device_id *ent)
608 {
609 - int i;
610 int err;
611 - int irq = 0;
612 int id;
613 char name[24];
614 enum pci_barno bar;
615 @@ -486,12 +665,15 @@ static int pci_endpoint_test_probe(struc
616 test->alignment = 0;
617 test->pdev = pdev;
618
619 + if (no_msi)
620 + irq_type = IRQ_TYPE_LEGACY;
621 +
622 data = (struct pci_endpoint_test_data *)ent->driver_data;
623 if (data) {
624 test_reg_bar = data->test_reg_bar;
625 test->test_reg_bar = test_reg_bar;
626 test->alignment = data->alignment;
627 - no_msi = data->no_msi;
628 + irq_type = data->irq_type;
629 }
630
631 init_completion(&test->irq_raised);
632 @@ -511,36 +693,21 @@ static int pci_endpoint_test_probe(struc
633
634 pci_set_master(pdev);
635
636 - if (!no_msi) {
637 - irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
638 - if (irq < 0)
639 - dev_err(dev, "failed to get MSI interrupts\n");
640 - test->num_irqs = irq;
641 - }
642 + if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type))
643 + goto err_disable_irq;
644
645 - err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
646 - IRQF_SHARED, DRV_MODULE_NAME, test);
647 - if (err) {
648 - dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
649 - goto err_disable_msi;
650 - }
651 -
652 - for (i = 1; i < irq; i++) {
653 - err = devm_request_irq(dev, pdev->irq + i,
654 - pci_endpoint_test_irqhandler,
655 - IRQF_SHARED, DRV_MODULE_NAME, test);
656 - if (err)
657 - dev_err(dev, "failed to request IRQ %d for MSI %d\n",
658 - pdev->irq + i, i + 1);
659 - }
660 + if (!pci_endpoint_test_request_irq(test))
661 + goto err_disable_irq;
662
663 for (bar = BAR_0; bar <= BAR_5; bar++) {
664 - base = pci_ioremap_bar(pdev, bar);
665 - if (!base) {
666 - dev_err(dev, "failed to read BAR%d\n", bar);
667 - WARN_ON(bar == test_reg_bar);
668 + if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
669 + base = pci_ioremap_bar(pdev, bar);
670 + if (!base) {
671 + dev_err(dev, "Failed to read BAR%d\n", bar);
672 + WARN_ON(bar == test_reg_bar);
673 + }
674 + test->bar[bar] = base;
675 }
676 - test->bar[bar] = base;
677 }
678
679 test->base = test->bar[test_reg_bar];
680 @@ -556,24 +723,31 @@ static int pci_endpoint_test_probe(struc
681 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
682 if (id < 0) {
683 err = id;
684 - dev_err(dev, "unable to get id\n");
685 + dev_err(dev, "Unable to get id\n");
686 goto err_iounmap;
687 }
688
689 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
690 misc_device = &test->miscdev;
691 misc_device->minor = MISC_DYNAMIC_MINOR;
692 - misc_device->name = name;
693 + misc_device->name = kstrdup(name, GFP_KERNEL);
694 + if (!misc_device->name) {
695 + err = -ENOMEM;
696 + goto err_ida_remove;
697 + }
698 misc_device->fops = &pci_endpoint_test_fops,
699
700 err = misc_register(misc_device);
701 if (err) {
702 - dev_err(dev, "failed to register device\n");
703 - goto err_ida_remove;
704 + dev_err(dev, "Failed to register device\n");
705 + goto err_kfree_name;
706 }
707
708 return 0;
709
710 +err_kfree_name:
711 + kfree(misc_device->name);
712 +
713 err_ida_remove:
714 ida_simple_remove(&pci_endpoint_test_ida, id);
715
716 @@ -583,11 +757,13 @@ err_iounmap:
717 pci_iounmap(pdev, test->bar[bar]);
718 }
719
720 - for (i = 0; i < irq; i++)
721 - devm_free_irq(dev, pdev->irq + i, test);
722 + pci_endpoint_test_release_irq(test);
723
724 err_disable_msi:
725 pci_disable_msi(pdev);
726 +
727 +err_disable_irq:
728 + pci_endpoint_test_free_irq_vectors(test);
729 pci_release_regions(pdev);
730
731 err_disable_pdev:
732 @@ -610,14 +786,15 @@ static void pci_endpoint_test_remove(str
733 return;
734
735 misc_deregister(&test->miscdev);
736 + kfree(misc_device->name);
737 ida_simple_remove(&pci_endpoint_test_ida, id);
738 for (bar = BAR_0; bar <= BAR_5; bar++) {
739 if (test->bar[bar])
740 pci_iounmap(pdev, test->bar[bar]);
741 }
742 - for (i = 0; i < test->num_irqs; i++)
743 - devm_free_irq(&pdev->dev, pdev->irq + i, test);
744 - pci_disable_msi(pdev);
745 +
746 + pci_endpoint_test_release_irq(test);
747 + pci_endpoint_test_free_irq_vectors(test);
748 pci_release_regions(pdev);
749 pci_disable_device(pdev);
750 }
751 @@ -625,6 +802,7 @@ static void pci_endpoint_test_remove(str
752 static const struct pci_device_id pci_endpoint_test_tbl[] = {
753 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
754 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
755 + { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID) },
756 { }
757 };
758 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
759 --- a/drivers/pci/Kconfig
760 +++ b/drivers/pci/Kconfig
761 @@ -142,6 +142,7 @@ config PCI_HYPERV
762
763 source "drivers/pci/hotplug/Kconfig"
764 source "drivers/pci/dwc/Kconfig"
765 +source "drivers/pci/mobiveil/Kconfig"
766 source "drivers/pci/host/Kconfig"
767 source "drivers/pci/endpoint/Kconfig"
768 source "drivers/pci/switch/Kconfig"
769 --- a/drivers/pci/dwc/Kconfig
770 +++ b/drivers/pci/dwc/Kconfig
771 @@ -50,17 +50,36 @@ config PCI_DRA7XX_EP
772 endif
773
774 config PCIE_DW_PLAT
775 - bool "Platform bus based DesignWare PCIe Controller"
776 - depends on PCI
777 - depends on PCI_MSI_IRQ_DOMAIN
778 - select PCIE_DW_HOST
779 - ---help---
780 - This selects the DesignWare PCIe controller support. Select this if
781 - you have a PCIe controller on Platform bus.
782 + bool
783
784 - If you have a controller with this interface, say Y or M here.
785 +config PCIE_DW_PLAT_HOST
786 + bool "Platform bus based DesignWare PCIe Controller - Host mode"
787 + depends on PCI && PCI_MSI_IRQ_DOMAIN
788 + select PCIE_DW_HOST
789 + select PCIE_DW_PLAT
790 + help
791 + Enables support for the PCIe controller in the Designware IP to
792 + work in host mode. There are two instances of PCIe controller in
793 + Designware IP.
794 + This controller can work either as EP or RC. In order to enable
795 + host-specific features PCIE_DW_PLAT_HOST must be selected and in
796 + order to enable device-specific features PCI_DW_PLAT_EP must be
797 + selected.
798
799 - If unsure, say N.
800 +config PCIE_DW_PLAT_EP
801 + bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
802 + depends on PCI && PCI_MSI_IRQ_DOMAIN
803 + depends on PCI_ENDPOINT
804 + select PCIE_DW_EP
805 + select PCIE_DW_PLAT
806 + help
807 + Enables support for the PCIe controller in the Designware IP to
808 + work in endpoint mode. There are two instances of PCIe controller
809 + in Designware IP.
810 + This controller can work either as EP or RC. In order to enable
811 + host-specific features PCIE_DW_PLAT_HOST must be selected and in
812 + order to enable device-specific features PCI_DW_PLAT_EP must be
813 + selected.
814
815 config PCI_EXYNOS
816 bool "Samsung Exynos PCIe controller"
817 --- a/drivers/pci/dwc/Makefile
818 +++ b/drivers/pci/dwc/Makefile
819 @@ -10,7 +10,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
820 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
821 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
822 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
823 -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
824 +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
825 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
826 obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
827 obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
828 --- a/drivers/pci/dwc/pci-dra7xx.c
829 +++ b/drivers/pci/dwc/pci-dra7xx.c
830 @@ -339,15 +339,6 @@ static irqreturn_t dra7xx_pcie_irq_handl
831 return IRQ_HANDLED;
832 }
833
834 -static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
835 -{
836 - u32 reg;
837 -
838 - reg = PCI_BASE_ADDRESS_0 + (4 * bar);
839 - dw_pcie_writel_dbi2(pci, reg, 0x0);
840 - dw_pcie_writel_dbi(pci, reg, 0x0);
841 -}
842 -
843 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
844 {
845 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
846 --- /dev/null
847 +++ b/drivers/pci/dwc/pci-layerscape-ep.c
848 @@ -0,0 +1,146 @@
849 +// SPDX-License-Identifier: GPL-2.0
850 +/*
851 + * PCIe controller EP driver for Freescale Layerscape SoCs
852 + *
853 + * Copyright (C) 2018 NXP Semiconductor.
854 + *
855 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
856 + */
857 +
858 +#include <linux/kernel.h>
859 +#include <linux/init.h>
860 +#include <linux/of_pci.h>
861 +#include <linux/of_platform.h>
862 +#include <linux/of_address.h>
863 +#include <linux/pci.h>
864 +#include <linux/platform_device.h>
865 +#include <linux/resource.h>
866 +
867 +#include "pcie-designware.h"
868 +
869 +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
870 +
871 +struct ls_pcie_ep {
872 + struct dw_pcie *pci;
873 +};
874 +
875 +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
876 +
877 +static int ls_pcie_establish_link(struct dw_pcie *pci)
878 +{
879 + return 0;
880 +}
881 +
882 +static const struct dw_pcie_ops ls_pcie_ep_ops = {
883 + .start_link = ls_pcie_establish_link,
884 +};
885 +
886 +static const struct of_device_id ls_pcie_ep_of_match[] = {
887 + { .compatible = "fsl,ls-pcie-ep",},
888 + { },
889 +};
890 +
891 +static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
892 +{
893 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
894 + struct pci_epc *epc = ep->epc;
895 + enum pci_barno bar;
896 +
897 + for (bar = BAR_0; bar <= BAR_5; bar++)
898 + dw_pcie_ep_reset_bar(pci, bar);
899 +
900 + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
901 +}
902 +
903 +static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
904 + enum pci_epc_irq_type type, u16 interrupt_num)
905 +{
906 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
907 +
908 + switch (type) {
909 + case PCI_EPC_IRQ_LEGACY:
910 + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
911 + case PCI_EPC_IRQ_MSI:
912 + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
913 + case PCI_EPC_IRQ_MSIX:
914 + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
915 + default:
916 + dev_err(pci->dev, "UNKNOWN IRQ type\n");
917 + return -EINVAL;
918 + }
919 +}
920 +
921 +static struct dw_pcie_ep_ops pcie_ep_ops = {
922 + .ep_init = ls_pcie_ep_init,
923 + .raise_irq = ls_pcie_ep_raise_irq,
924 +};
925 +
926 +static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
927 + struct platform_device *pdev)
928 +{
929 + struct dw_pcie *pci = pcie->pci;
930 + struct device *dev = pci->dev;
931 + struct dw_pcie_ep *ep;
932 + struct resource *res;
933 + int ret;
934 +
935 + ep = &pci->ep;
936 + ep->ops = &pcie_ep_ops;
937 +
938 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
939 + if (!res)
940 + return -EINVAL;
941 +
942 + ep->phys_base = res->start;
943 + ep->addr_size = resource_size(res);
944 +
945 + ret = dw_pcie_ep_init(ep);
946 + if (ret) {
947 + dev_err(dev, "failed to initialize endpoint\n");
948 + return ret;
949 + }
950 +
951 + return 0;
952 +}
953 +
954 +static int __init ls_pcie_ep_probe(struct platform_device *pdev)
955 +{
956 + struct device *dev = &pdev->dev;
957 + struct dw_pcie *pci;
958 + struct ls_pcie_ep *pcie;
959 + struct resource *dbi_base;
960 + int ret;
961 +
962 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
963 + if (!pcie)
964 + return -ENOMEM;
965 +
966 + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
967 + if (!pci)
968 + return -ENOMEM;
969 +
970 + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
971 + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
972 + if (IS_ERR(pci->dbi_base))
973 + return PTR_ERR(pci->dbi_base);
974 +
975 + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
976 + pci->dev = dev;
977 + pci->ops = &ls_pcie_ep_ops;
978 + pcie->pci = pci;
979 +
980 + platform_set_drvdata(pdev, pcie);
981 +
982 + ret = ls_add_pcie_ep(pcie, pdev);
983 +
984 + return ret;
985 +}
986 +
987 +static struct platform_driver ls_pcie_ep_driver = {
988 + .driver = {
989 + .name = "layerscape-pcie-ep",
990 + .of_match_table = ls_pcie_ep_of_match,
991 + .suppress_bind_attrs = true,
992 + },
993 +};
994 +builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
995 --- a/drivers/pci/dwc/pci-layerscape.c
996 +++ b/drivers/pci/dwc/pci-layerscape.c
997 @@ -33,6 +33,8 @@
998
999 /* PEX Internal Configuration Registers */
1000 #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
1001 +#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
1002 +#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
1003
1004 #define PCIE_IATU_NUM 6
1005
1006 @@ -124,6 +126,14 @@ static int ls_pcie_link_up(struct dw_pci
1007 return 1;
1008 }
1009
1010 +/* Forward error response of outbound non-posted requests */
1011 +static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
1012 +{
1013 + struct dw_pcie *pci = pcie->pci;
1014 +
1015 + iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
1016 +}
1017 +
1018 static int ls_pcie_host_init(struct pcie_port *pp)
1019 {
1020 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1021 @@ -135,6 +145,7 @@ static int ls_pcie_host_init(struct pcie
1022 * dw_pcie_setup_rc() will reconfigure the outbound windows.
1023 */
1024 ls_pcie_disable_outbound_atus(pcie);
1025 + ls_pcie_fix_error_response(pcie);
1026
1027 dw_pcie_dbi_ro_wr_en(pci);
1028 ls_pcie_clear_multifunction(pcie);
1029 @@ -253,6 +264,7 @@ static struct ls_pcie_drvdata ls2088_drv
1030 };
1031
1032 static const struct of_device_id ls_pcie_of_match[] = {
1033 + { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
1034 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
1035 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1036 { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1037 --- a/drivers/pci/dwc/pcie-designware-ep.c
1038 +++ b/drivers/pci/dwc/pcie-designware-ep.c
1039 @@ -1,20 +1,9 @@
1040 +// SPDX-License-Identifier: GPL-2.0
1041 /**
1042 * Synopsys DesignWare PCIe Endpoint controller driver
1043 *
1044 * Copyright (C) 2017 Texas Instruments
1045 * Author: Kishon Vijay Abraham I <kishon@ti.com>
1046 - *
1047 - * This program is free software: you can redistribute it and/or modify
1048 - * it under the terms of the GNU General Public License version 2 of
1049 - * the License as published by the Free Software Foundation.
1050 - *
1051 - * This program is distributed in the hope that it will be useful,
1052 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1053 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1054 - * GNU General Public License for more details.
1055 - *
1056 - * You should have received a copy of the GNU General Public License
1057 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1058 */
1059
1060 #include <linux/of.h>
1061 @@ -30,7 +19,8 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep
1062 pci_epc_linkup(epc);
1063 }
1064
1065 -static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
1066 +static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
1067 + int flags)
1068 {
1069 u32 reg;
1070
1071 @@ -38,10 +28,52 @@ static void dw_pcie_ep_reset_bar(struct
1072 dw_pcie_dbi_ro_wr_en(pci);
1073 dw_pcie_writel_dbi2(pci, reg, 0x0);
1074 dw_pcie_writel_dbi(pci, reg, 0x0);
1075 + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1076 + dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
1077 + dw_pcie_writel_dbi(pci, reg + 4, 0x0);
1078 + }
1079 dw_pcie_dbi_ro_wr_dis(pci);
1080 }
1081
1082 -static int dw_pcie_ep_write_header(struct pci_epc *epc,
1083 +void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
1084 +{
1085 + __dw_pcie_ep_reset_bar(pci, bar, 0);
1086 +}
1087 +
1088 +static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
1089 + u8 cap)
1090 +{
1091 + u8 cap_id, next_cap_ptr;
1092 + u16 reg;
1093 +
1094 + reg = dw_pcie_readw_dbi(pci, cap_ptr);
1095 + next_cap_ptr = (reg & 0xff00) >> 8;
1096 + cap_id = (reg & 0x00ff);
1097 +
1098 + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
1099 + return 0;
1100 +
1101 + if (cap_id == cap)
1102 + return cap_ptr;
1103 +
1104 + return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
1105 +}
1106 +
1107 +static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)
1108 +{
1109 + u8 next_cap_ptr;
1110 + u16 reg;
1111 +
1112 + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
1113 + next_cap_ptr = (reg & 0x00ff);
1114 +
1115 + if (!next_cap_ptr)
1116 + return 0;
1117 +
1118 + return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
1119 +}
1120 +
1121 +static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
1122 struct pci_epf_header *hdr)
1123 {
1124 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1125 @@ -114,24 +146,29 @@ static int dw_pcie_ep_outbound_atu(struc
1126 return 0;
1127 }
1128
1129 -static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
1130 +static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
1131 + struct pci_epf_bar *epf_bar)
1132 {
1133 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1134 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1135 + enum pci_barno bar = epf_bar->barno;
1136 u32 atu_index = ep->bar_to_atu[bar];
1137
1138 - dw_pcie_ep_reset_bar(pci, bar);
1139 + __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
1140
1141 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
1142 clear_bit(atu_index, ep->ib_window_map);
1143 }
1144
1145 -static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
1146 - dma_addr_t bar_phys, size_t size, int flags)
1147 +static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
1148 + struct pci_epf_bar *epf_bar)
1149 {
1150 int ret;
1151 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1152 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1153 + enum pci_barno bar = epf_bar->barno;
1154 + size_t size = epf_bar->size;
1155 + int flags = epf_bar->flags;
1156 enum dw_pcie_as_type as_type;
1157 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
1158
1159 @@ -140,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci
1160 else
1161 as_type = DW_PCIE_AS_IO;
1162
1163 - ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
1164 + ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type);
1165 if (ret)
1166 return ret;
1167
1168 dw_pcie_dbi_ro_wr_en(pci);
1169 - dw_pcie_writel_dbi2(pci, reg, size - 1);
1170 +
1171 + dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
1172 dw_pcie_writel_dbi(pci, reg, flags);
1173 +
1174 + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1175 + dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
1176 + dw_pcie_writel_dbi(pci, reg + 4, 0);
1177 + }
1178 +
1179 dw_pcie_dbi_ro_wr_dis(pci);
1180
1181 return 0;
1182 @@ -167,7 +211,8 @@ static int dw_pcie_find_index(struct dw_
1183 return -EINVAL;
1184 }
1185
1186 -static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
1187 +static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
1188 + phys_addr_t addr)
1189 {
1190 int ret;
1191 u32 atu_index;
1192 @@ -182,8 +227,9 @@ static void dw_pcie_ep_unmap_addr(struct
1193 clear_bit(atu_index, ep->ob_window_map);
1194 }
1195
1196 -static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
1197 - u64 pci_addr, size_t size)
1198 +static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
1199 + phys_addr_t addr,
1200 + u64 pci_addr, size_t size)
1201 {
1202 int ret;
1203 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1204 @@ -198,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc
1205 return 0;
1206 }
1207
1208 -static int dw_pcie_ep_get_msi(struct pci_epc *epc)
1209 +static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
1210 +{
1211 + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1212 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1213 + u32 val, reg;
1214 +
1215 + if (!ep->msi_cap)
1216 + return -EINVAL;
1217 +
1218 + reg = ep->msi_cap + PCI_MSI_FLAGS;
1219 + val = dw_pcie_readw_dbi(pci, reg);
1220 + if (!(val & PCI_MSI_FLAGS_ENABLE))
1221 + return -EINVAL;
1222 +
1223 + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
1224 +
1225 + return val;
1226 +}
1227 +
1228 +static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
1229 +{
1230 + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1231 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1232 + u32 val, reg;
1233 +
1234 + if (!ep->msi_cap)
1235 + return -EINVAL;
1236 +
1237 + reg = ep->msi_cap + PCI_MSI_FLAGS;
1238 + val = dw_pcie_readw_dbi(pci, reg);
1239 + val &= ~PCI_MSI_FLAGS_QMASK;
1240 + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
1241 + dw_pcie_dbi_ro_wr_en(pci);
1242 + dw_pcie_writew_dbi(pci, reg, val);
1243 + dw_pcie_dbi_ro_wr_dis(pci);
1244 +
1245 + return 0;
1246 +}
1247 +
1248 +static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
1249 {
1250 - int val;
1251 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1252 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1253 + u32 val, reg;
1254 +
1255 + if (!ep->msix_cap)
1256 + return -EINVAL;
1257
1258 - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
1259 - if (!(val & MSI_CAP_MSI_EN_MASK))
1260 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
1261 + val = dw_pcie_readw_dbi(pci, reg);
1262 + if (!(val & PCI_MSIX_FLAGS_ENABLE))
1263 return -EINVAL;
1264
1265 - val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
1266 + val &= PCI_MSIX_FLAGS_QSIZE;
1267 +
1268 return val;
1269 }
1270
1271 -static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
1272 +static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
1273 {
1274 - int val;
1275 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1276 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1277 + u32 val, reg;
1278
1279 - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
1280 - val &= ~MSI_CAP_MMC_MASK;
1281 - val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
1282 + if (!ep->msix_cap)
1283 + return -EINVAL;
1284 +
1285 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
1286 + val = dw_pcie_readw_dbi(pci, reg);
1287 + val &= ~PCI_MSIX_FLAGS_QSIZE;
1288 + val |= interrupts;
1289 dw_pcie_dbi_ro_wr_en(pci);
1290 - dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
1291 + dw_pcie_writew_dbi(pci, reg, val);
1292 dw_pcie_dbi_ro_wr_dis(pci);
1293
1294 return 0;
1295 }
1296
1297 -static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
1298 - enum pci_epc_irq_type type, u8 interrupt_num)
1299 +static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
1300 + enum pci_epc_irq_type type, u16 interrupt_num)
1301 {
1302 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1303
1304 if (!ep->ops->raise_irq)
1305 return -EINVAL;
1306
1307 - return ep->ops->raise_irq(ep, type, interrupt_num);
1308 + return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
1309 }
1310
1311 static void dw_pcie_ep_stop(struct pci_epc *epc)
1312 @@ -269,15 +363,130 @@ static const struct pci_epc_ops epc_ops
1313 .unmap_addr = dw_pcie_ep_unmap_addr,
1314 .set_msi = dw_pcie_ep_set_msi,
1315 .get_msi = dw_pcie_ep_get_msi,
1316 + .set_msix = dw_pcie_ep_set_msix,
1317 + .get_msix = dw_pcie_ep_get_msix,
1318 .raise_irq = dw_pcie_ep_raise_irq,
1319 .start = dw_pcie_ep_start,
1320 .stop = dw_pcie_ep_stop,
1321 };
1322
1323 +int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
1324 +{
1325 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1326 + struct device *dev = pci->dev;
1327 +
1328 + dev_err(dev, "EP cannot trigger legacy IRQs\n");
1329 +
1330 + return -EINVAL;
1331 +}
1332 +
1333 +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
1334 + u8 interrupt_num)
1335 +{
1336 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1337 + struct pci_epc *epc = ep->epc;
1338 + u16 msg_ctrl, msg_data;
1339 + u32 msg_addr_lower, msg_addr_upper, reg;
1340 + u64 msg_addr;
1341 + bool has_upper;
1342 + int ret;
1343 +
1344 + if (!ep->msi_cap)
1345 + return -EINVAL;
1346 +
1347 + /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
1348 + reg = ep->msi_cap + PCI_MSI_FLAGS;
1349 + msg_ctrl = dw_pcie_readw_dbi(pci, reg);
1350 + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
1351 + reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
1352 + msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
1353 + if (has_upper) {
1354 + reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
1355 + msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
1356 + reg = ep->msi_cap + PCI_MSI_DATA_64;
1357 + msg_data = dw_pcie_readw_dbi(pci, reg);
1358 + } else {
1359 + msg_addr_upper = 0;
1360 + reg = ep->msi_cap + PCI_MSI_DATA_32;
1361 + msg_data = dw_pcie_readw_dbi(pci, reg);
1362 + }
1363 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
1364 + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
1365 + epc->mem->page_size);
1366 + if (ret)
1367 + return ret;
1368 +
1369 + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
1370 +
1371 + dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
1372 +
1373 + return 0;
1374 +}
1375 +
1376 +int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
1377 + u16 interrupt_num)
1378 +{
1379 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1380 + struct pci_epc *epc = ep->epc;
1381 + u16 tbl_offset, bir;
1382 + u32 bar_addr_upper, bar_addr_lower;
1383 + u32 msg_addr_upper, msg_addr_lower;
1384 + u32 reg, msg_data, vec_ctrl;
1385 + u64 tbl_addr, msg_addr, reg_u64;
1386 + void __iomem *msix_tbl;
1387 + int ret;
1388 +
1389 + reg = ep->msix_cap + PCI_MSIX_TABLE;
1390 + tbl_offset = dw_pcie_readl_dbi(pci, reg);
1391 + bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
1392 + tbl_offset &= PCI_MSIX_TABLE_OFFSET;
1393 +
1394 + reg = PCI_BASE_ADDRESS_0 + (4 * bir);
1395 + bar_addr_upper = 0;
1396 + bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
1397 + reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
1398 + if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1399 + bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
1400 +
1401 + tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
1402 + tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
1403 + tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
1404 +
1405 + msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr,
1406 + PCI_MSIX_ENTRY_SIZE);
1407 + if (!msix_tbl)
1408 + return -EINVAL;
1409 +
1410 + msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
1411 + msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
1412 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
1413 + msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
1414 + vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
1415 +
1416 + iounmap(msix_tbl);
1417 +
1418 + if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)
1419 + return -EPERM;
1420 +
1421 + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
1422 + epc->mem->page_size);
1423 + if (ret)
1424 + return ret;
1425 +
1426 + writel(msg_data, ep->msi_mem);
1427 +
1428 + dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
1429 +
1430 + return 0;
1431 +}
1432 +
1433 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
1434 {
1435 struct pci_epc *epc = ep->epc;
1436
1437 + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
1438 + epc->mem->page_size);
1439 +
1440 pci_epc_mem_exit(epc);
1441 }
1442
1443 @@ -291,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1444 struct device_node *np = dev->of_node;
1445
1446 if (!pci->dbi_base || !pci->dbi_base2) {
1447 - dev_err(dev, "dbi_base/deb_base2 is not populated\n");
1448 + dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
1449 return -EINVAL;
1450 }
1451
1452 @@ -333,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1453 return -ENOMEM;
1454 ep->outbound_addr = addr;
1455
1456 - if (ep->ops->ep_init)
1457 - ep->ops->ep_init(ep);
1458 -
1459 epc = devm_pci_epc_create(dev, &epc_ops);
1460 if (IS_ERR(epc)) {
1461 dev_err(dev, "failed to create epc device\n");
1462 return PTR_ERR(epc);
1463 }
1464
1465 + ep->epc = epc;
1466 + epc_set_drvdata(epc, ep);
1467 +
1468 + if (ep->ops->ep_init)
1469 + ep->ops->ep_init(ep);
1470 +
1471 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
1472 if (ret < 0)
1473 epc->max_functions = 1;
1474 @@ -353,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1475 return ret;
1476 }
1477
1478 - ep->epc = epc;
1479 - epc_set_drvdata(epc, ep);
1480 + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
1481 + epc->mem->page_size);
1482 + if (!ep->msi_mem) {
1483 + dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
1484 + return -ENOMEM;
1485 + }
1486 + ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
1487 +
1488 + ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
1489 +
1490 dw_pcie_setup(pci);
1491
1492 return 0;
1493 --- a/drivers/pci/dwc/pcie-designware-host.c
1494 +++ b/drivers/pci/dwc/pcie-designware-host.c
1495 @@ -1,3 +1,4 @@
1496 +// SPDX-License-Identifier: GPL-2.0
1497 /*
1498 * Synopsys DesignWare PCIe host controller driver
1499 *
1500 @@ -5,10 +6,6 @@
1501 * http://www.samsung.com
1502 *
1503 * Author: Jingoo Han <jg1.han@samsung.com>
1504 - *
1505 - * This program is free software; you can redistribute it and/or modify
1506 - * it under the terms of the GNU General Public License version 2 as
1507 - * published by the Free Software Foundation.
1508 */
1509
1510 #include <linux/irqdomain.h>
1511 --- a/drivers/pci/dwc/pcie-designware-plat.c
1512 +++ b/drivers/pci/dwc/pcie-designware-plat.c
1513 @@ -1,13 +1,10 @@
1514 +// SPDX-License-Identifier: GPL-2.0
1515 /*
1516 * PCIe RC driver for Synopsys DesignWare Core
1517 *
1518 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
1519 *
1520 * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
1521 - *
1522 - * This program is free software; you can redistribute it and/or modify
1523 - * it under the terms of the GNU General Public License version 2 as
1524 - * published by the Free Software Foundation.
1525 */
1526 #include <linux/clk.h>
1527 #include <linux/delay.h>
1528 @@ -15,19 +12,29 @@
1529 #include <linux/interrupt.h>
1530 #include <linux/kernel.h>
1531 #include <linux/init.h>
1532 +#include <linux/of_device.h>
1533 #include <linux/of_gpio.h>
1534 #include <linux/pci.h>
1535 #include <linux/platform_device.h>
1536 #include <linux/resource.h>
1537 #include <linux/signal.h>
1538 #include <linux/types.h>
1539 +#include <linux/regmap.h>
1540
1541 #include "pcie-designware.h"
1542
1543 struct dw_plat_pcie {
1544 - struct dw_pcie *pci;
1545 + struct dw_pcie *pci;
1546 + struct regmap *regmap;
1547 + enum dw_pcie_device_mode mode;
1548 +};
1549 +
1550 +struct dw_plat_pcie_of_data {
1551 + enum dw_pcie_device_mode mode;
1552 };
1553
1554 +static const struct of_device_id dw_plat_pcie_of_match[];
1555 +
1556 static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
1557 {
1558 struct pcie_port *pp = arg;
1559 @@ -52,9 +59,58 @@ static const struct dw_pcie_host_ops dw_
1560 .host_init = dw_plat_pcie_host_init,
1561 };
1562
1563 -static int dw_plat_add_pcie_port(struct pcie_port *pp,
1564 +static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
1565 +{
1566 + return 0;
1567 +}
1568 +
1569 +static const struct dw_pcie_ops dw_pcie_ops = {
1570 + .start_link = dw_plat_pcie_establish_link,
1571 +};
1572 +
1573 +static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
1574 +{
1575 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1576 + struct pci_epc *epc = ep->epc;
1577 + enum pci_barno bar;
1578 +
1579 + for (bar = BAR_0; bar <= BAR_5; bar++)
1580 + dw_pcie_ep_reset_bar(pci, bar);
1581 +
1582 + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
1583 + epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
1584 +}
1585 +
1586 +static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
1587 + enum pci_epc_irq_type type,
1588 + u16 interrupt_num)
1589 +{
1590 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1591 +
1592 + switch (type) {
1593 + case PCI_EPC_IRQ_LEGACY:
1594 + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
1595 + case PCI_EPC_IRQ_MSI:
1596 + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
1597 + case PCI_EPC_IRQ_MSIX:
1598 + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
1599 + default:
1600 + dev_err(pci->dev, "UNKNOWN IRQ type\n");
1601 + }
1602 +
1603 + return 0;
1604 +}
1605 +
1606 +static struct dw_pcie_ep_ops pcie_ep_ops = {
1607 + .ep_init = dw_plat_pcie_ep_init,
1608 + .raise_irq = dw_plat_pcie_ep_raise_irq,
1609 +};
1610 +
1611 +static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
1612 struct platform_device *pdev)
1613 {
1614 + struct dw_pcie *pci = dw_plat_pcie->pci;
1615 + struct pcie_port *pp = &pci->pp;
1616 struct device *dev = &pdev->dev;
1617 int ret;
1618
1619 @@ -82,15 +138,44 @@ static int dw_plat_add_pcie_port(struct
1620
1621 ret = dw_pcie_host_init(pp);
1622 if (ret) {
1623 - dev_err(dev, "failed to initialize host\n");
1624 + dev_err(dev, "Failed to initialize host\n");
1625 return ret;
1626 }
1627
1628 return 0;
1629 }
1630
1631 -static const struct dw_pcie_ops dw_pcie_ops = {
1632 -};
1633 +static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie,
1634 + struct platform_device *pdev)
1635 +{
1636 + int ret;
1637 + struct dw_pcie_ep *ep;
1638 + struct resource *res;
1639 + struct device *dev = &pdev->dev;
1640 + struct dw_pcie *pci = dw_plat_pcie->pci;
1641 +
1642 + ep = &pci->ep;
1643 + ep->ops = &pcie_ep_ops;
1644 +
1645 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
1646 + pci->dbi_base2 = devm_ioremap_resource(dev, res);
1647 + if (IS_ERR(pci->dbi_base2))
1648 + return PTR_ERR(pci->dbi_base2);
1649 +
1650 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
1651 + if (!res)
1652 + return -EINVAL;
1653 +
1654 + ep->phys_base = res->start;
1655 + ep->addr_size = resource_size(res);
1656 +
1657 + ret = dw_pcie_ep_init(ep);
1658 + if (ret) {
1659 + dev_err(dev, "Failed to initialize endpoint\n");
1660 + return ret;
1661 + }
1662 + return 0;
1663 +}
1664
1665 static int dw_plat_pcie_probe(struct platform_device *pdev)
1666 {
1667 @@ -99,6 +184,16 @@ static int dw_plat_pcie_probe(struct pla
1668 struct dw_pcie *pci;
1669 struct resource *res; /* Resource from DT */
1670 int ret;
1671 + const struct of_device_id *match;
1672 + const struct dw_plat_pcie_of_data *data;
1673 + enum dw_pcie_device_mode mode;
1674 +
1675 + match = of_match_device(dw_plat_pcie_of_match, dev);
1676 + if (!match)
1677 + return -EINVAL;
1678 +
1679 + data = (struct dw_plat_pcie_of_data *)match->data;
1680 + mode = (enum dw_pcie_device_mode)data->mode;
1681
1682 dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
1683 if (!dw_plat_pcie)
1684 @@ -112,23 +207,59 @@ static int dw_plat_pcie_probe(struct pla
1685 pci->ops = &dw_pcie_ops;
1686
1687 dw_plat_pcie->pci = pci;
1688 + dw_plat_pcie->mode = mode;
1689 +
1690 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1691 + if (!res)
1692 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1693
1694 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1695 pci->dbi_base = devm_ioremap_resource(dev, res);
1696 if (IS_ERR(pci->dbi_base))
1697 return PTR_ERR(pci->dbi_base);
1698
1699 platform_set_drvdata(pdev, dw_plat_pcie);
1700
1701 - ret = dw_plat_add_pcie_port(&pci->pp, pdev);
1702 - if (ret < 0)
1703 - return ret;
1704 + switch (dw_plat_pcie->mode) {
1705 + case DW_PCIE_RC_TYPE:
1706 + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST))
1707 + return -ENODEV;
1708 +
1709 + ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev);
1710 + if (ret < 0)
1711 + return ret;
1712 + break;
1713 + case DW_PCIE_EP_TYPE:
1714 + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
1715 + return -ENODEV;
1716 +
1717 + ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev);
1718 + if (ret < 0)
1719 + return ret;
1720 + break;
1721 + default:
1722 + dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
1723 + }
1724
1725 return 0;
1726 }
1727
1728 +static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = {
1729 + .mode = DW_PCIE_RC_TYPE,
1730 +};
1731 +
1732 +static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = {
1733 + .mode = DW_PCIE_EP_TYPE,
1734 +};
1735 +
1736 static const struct of_device_id dw_plat_pcie_of_match[] = {
1737 - { .compatible = "snps,dw-pcie", },
1738 + {
1739 + .compatible = "snps,dw-pcie",
1740 + .data = &dw_plat_pcie_rc_of_data,
1741 + },
1742 + {
1743 + .compatible = "snps,dw-pcie-ep",
1744 + .data = &dw_plat_pcie_ep_of_data,
1745 + },
1746 {},
1747 };
1748
1749 --- a/drivers/pci/dwc/pcie-designware.c
1750 +++ b/drivers/pci/dwc/pcie-designware.c
1751 @@ -1,3 +1,4 @@
1752 +// SPDX-License-Identifier: GPL-2.0
1753 /*
1754 * Synopsys DesignWare PCIe host controller driver
1755 *
1756 @@ -5,10 +6,6 @@
1757 * http://www.samsung.com
1758 *
1759 * Author: Jingoo Han <jg1.han@samsung.com>
1760 - *
1761 - * This program is free software; you can redistribute it and/or modify
1762 - * it under the terms of the GNU General Public License version 2 as
1763 - * published by the Free Software Foundation.
1764 */
1765
1766 #include <linux/delay.h>
1767 --- a/drivers/pci/dwc/pcie-designware.h
1768 +++ b/drivers/pci/dwc/pcie-designware.h
1769 @@ -1,3 +1,4 @@
1770 +// SPDX-License-Identifier: GPL-2.0
1771 /*
1772 * Synopsys DesignWare PCIe host controller driver
1773 *
1774 @@ -5,10 +6,6 @@
1775 * http://www.samsung.com
1776 *
1777 * Author: Jingoo Han <jg1.han@samsung.com>
1778 - *
1779 - * This program is free software; you can redistribute it and/or modify
1780 - * it under the terms of the GNU General Public License version 2 as
1781 - * published by the Free Software Foundation.
1782 */
1783
1784 #ifndef _PCIE_DESIGNWARE_H
1785 @@ -97,15 +94,6 @@
1786 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
1787 ((0x3 << 20) | ((region) << 9) | (0x1 << 8))
1788
1789 -#define MSI_MESSAGE_CONTROL 0x52
1790 -#define MSI_CAP_MMC_SHIFT 1
1791 -#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT)
1792 -#define MSI_CAP_MME_SHIFT 4
1793 -#define MSI_CAP_MSI_EN_MASK 0x1
1794 -#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
1795 -#define MSI_MESSAGE_ADDR_L32 0x54
1796 -#define MSI_MESSAGE_ADDR_U32 0x58
1797 -
1798 /*
1799 * Maximum number of MSI IRQs can be 256 per controller. But keep
1800 * it 32 as of now. Probably we will never need more than 32. If needed,
1801 @@ -118,6 +106,10 @@
1802 #define MAX_IATU_IN 256
1803 #define MAX_IATU_OUT 256
1804
1805 +/* Maximum number of inbound/outbound iATUs */
1806 +#define MAX_IATU_IN 256
1807 +#define MAX_IATU_OUT 256
1808 +
1809 struct pcie_port;
1810 struct dw_pcie;
1811 struct dw_pcie_ep;
1812 @@ -185,8 +177,8 @@ enum dw_pcie_as_type {
1813
1814 struct dw_pcie_ep_ops {
1815 void (*ep_init)(struct dw_pcie_ep *ep);
1816 - int (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
1817 - u8 interrupt_num);
1818 + int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
1819 + enum pci_epc_irq_type type, u16 interrupt_num);
1820 };
1821
1822 struct dw_pcie_ep {
1823 @@ -201,6 +193,10 @@ struct dw_pcie_ep {
1824 unsigned long *ob_window_map;
1825 u32 num_ib_windows;
1826 u32 num_ob_windows;
1827 + void __iomem *msi_mem;
1828 + phys_addr_t msi_mem_phys;
1829 + u8 msi_cap; /* MSI capability offset */
1830 + u8 msix_cap; /* MSI-X capability offset */
1831 };
1832
1833 struct dw_pcie_ops {
1834 @@ -339,6 +335,12 @@ static inline int dw_pcie_host_init(stru
1835 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
1836 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
1837 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
1838 +int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
1839 +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
1840 + u8 interrupt_num);
1841 +int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
1842 + u16 interrupt_num);
1843 +void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
1844 #else
1845 static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
1846 {
1847 @@ -352,5 +354,26 @@ static inline int dw_pcie_ep_init(struct
1848 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
1849 {
1850 }
1851 +
1852 +static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
1853 +{
1854 + return 0;
1855 +}
1856 +
1857 +static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
1858 + u8 interrupt_num)
1859 +{
1860 + return 0;
1861 +}
1862 +
1863 +static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
1864 + u16 interrupt_num)
1865 +{
1866 + return 0;
1867 +}
1868 +
1869 +static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
1870 +{
1871 +}
1872 #endif
1873 #endif /* _PCIE_DESIGNWARE_H */
1874 --- a/drivers/pci/endpoint/Kconfig
1875 +++ b/drivers/pci/endpoint/Kconfig
1876 @@ -1,3 +1,4 @@
1877 +# SPDX-License-Identifier: GPL-2.0
1878 #
1879 # PCI Endpoint Support
1880 #
1881 --- a/drivers/pci/endpoint/Makefile
1882 +++ b/drivers/pci/endpoint/Makefile
1883 @@ -1,3 +1,4 @@
1884 +# SPDX-License-Identifier: GPL-2.0
1885 #
1886 # Makefile for PCI Endpoint Support
1887 #
1888 --- a/drivers/pci/endpoint/functions/Kconfig
1889 +++ b/drivers/pci/endpoint/functions/Kconfig
1890 @@ -1,3 +1,4 @@
1891 +# SPDX-License-Identifier: GPL-2.0
1892 #
1893 # PCI Endpoint Functions
1894 #
1895 --- a/drivers/pci/endpoint/functions/Makefile
1896 +++ b/drivers/pci/endpoint/functions/Makefile
1897 @@ -1,3 +1,4 @@
1898 +# SPDX-License-Identifier: GPL-2.0
1899 #
1900 # Makefile for PCI Endpoint Functions
1901 #
1902 --- a/drivers/pci/endpoint/functions/pci-epf-test.c
1903 +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
1904 @@ -1,20 +1,9 @@
1905 +// SPDX-License-Identifier: GPL-2.0
1906 /**
1907 * Test driver to test endpoint functionality
1908 *
1909 * Copyright (C) 2017 Texas Instruments
1910 * Author: Kishon Vijay Abraham I <kishon@ti.com>
1911 - *
1912 - * This program is free software: you can redistribute it and/or modify
1913 - * it under the terms of the GNU General Public License version 2 of
1914 - * the License as published by the Free Software Foundation.
1915 - *
1916 - * This program is distributed in the hope that it will be useful,
1917 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1918 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1919 - * GNU General Public License for more details.
1920 - *
1921 - * You should have received a copy of the GNU General Public License
1922 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1923 */
1924
1925 #include <linux/crc32.h>
1926 @@ -29,13 +18,16 @@
1927 #include <linux/pci-epf.h>
1928 #include <linux/pci_regs.h>
1929
1930 +#define IRQ_TYPE_LEGACY 0
1931 +#define IRQ_TYPE_MSI 1
1932 +#define IRQ_TYPE_MSIX 2
1933 +
1934 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
1935 #define COMMAND_RAISE_MSI_IRQ BIT(1)
1936 -#define MSI_NUMBER_SHIFT 2
1937 -#define MSI_NUMBER_MASK (0x3f << MSI_NUMBER_SHIFT)
1938 -#define COMMAND_READ BIT(8)
1939 -#define COMMAND_WRITE BIT(9)
1940 -#define COMMAND_COPY BIT(10)
1941 +#define COMMAND_RAISE_MSIX_IRQ BIT(2)
1942 +#define COMMAND_READ BIT(3)
1943 +#define COMMAND_WRITE BIT(4)
1944 +#define COMMAND_COPY BIT(5)
1945
1946 #define STATUS_READ_SUCCESS BIT(0)
1947 #define STATUS_READ_FAIL BIT(1)
1948 @@ -56,6 +48,7 @@ struct pci_epf_test {
1949 struct pci_epf *epf;
1950 enum pci_barno test_reg_bar;
1951 bool linkup_notifier;
1952 + bool msix_available;
1953 struct delayed_work cmd_handler;
1954 };
1955
1956 @@ -67,6 +60,8 @@ struct pci_epf_test_reg {
1957 u64 dst_addr;
1958 u32 size;
1959 u32 checksum;
1960 + u32 irq_type;
1961 + u32 irq_number;
1962 } __packed;
1963
1964 static struct pci_epf_header test_header = {
1965 @@ -81,7 +76,7 @@ struct pci_epf_test_data {
1966 bool linkup_notifier;
1967 };
1968
1969 -static int bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
1970 +static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
1971
1972 static int pci_epf_test_copy(struct pci_epf_test *epf_test)
1973 {
1974 @@ -98,43 +93,45 @@ static int pci_epf_test_copy(struct pci_
1975
1976 src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size);
1977 if (!src_addr) {
1978 - dev_err(dev, "failed to allocate source address\n");
1979 + dev_err(dev, "Failed to allocate source address\n");
1980 reg->status = STATUS_SRC_ADDR_INVALID;
1981 ret = -ENOMEM;
1982 goto err;
1983 }
1984
1985 - ret = pci_epc_map_addr(epc, src_phys_addr, reg->src_addr, reg->size);
1986 + ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr,
1987 + reg->size);
1988 if (ret) {
1989 - dev_err(dev, "failed to map source address\n");
1990 + dev_err(dev, "Failed to map source address\n");
1991 reg->status = STATUS_SRC_ADDR_INVALID;
1992 goto err_src_addr;
1993 }
1994
1995 dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size);
1996 if (!dst_addr) {
1997 - dev_err(dev, "failed to allocate destination address\n");
1998 + dev_err(dev, "Failed to allocate destination address\n");
1999 reg->status = STATUS_DST_ADDR_INVALID;
2000 ret = -ENOMEM;
2001 goto err_src_map_addr;
2002 }
2003
2004 - ret = pci_epc_map_addr(epc, dst_phys_addr, reg->dst_addr, reg->size);
2005 + ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr,
2006 + reg->size);
2007 if (ret) {
2008 - dev_err(dev, "failed to map destination address\n");
2009 + dev_err(dev, "Failed to map destination address\n");
2010 reg->status = STATUS_DST_ADDR_INVALID;
2011 goto err_dst_addr;
2012 }
2013
2014 memcpy(dst_addr, src_addr, reg->size);
2015
2016 - pci_epc_unmap_addr(epc, dst_phys_addr);
2017 + pci_epc_unmap_addr(epc, epf->func_no, dst_phys_addr);
2018
2019 err_dst_addr:
2020 pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
2021
2022 err_src_map_addr:
2023 - pci_epc_unmap_addr(epc, src_phys_addr);
2024 + pci_epc_unmap_addr(epc, epf->func_no, src_phys_addr);
2025
2026 err_src_addr:
2027 pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
2028 @@ -158,15 +155,16 @@ static int pci_epf_test_read(struct pci_
2029
2030 src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
2031 if (!src_addr) {
2032 - dev_err(dev, "failed to allocate address\n");
2033 + dev_err(dev, "Failed to allocate address\n");
2034 reg->status = STATUS_SRC_ADDR_INVALID;
2035 ret = -ENOMEM;
2036 goto err;
2037 }
2038
2039 - ret = pci_epc_map_addr(epc, phys_addr, reg->src_addr, reg->size);
2040 + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr,
2041 + reg->size);
2042 if (ret) {
2043 - dev_err(dev, "failed to map address\n");
2044 + dev_err(dev, "Failed to map address\n");
2045 reg->status = STATUS_SRC_ADDR_INVALID;
2046 goto err_addr;
2047 }
2048 @@ -186,7 +184,7 @@ static int pci_epf_test_read(struct pci_
2049 kfree(buf);
2050
2051 err_map_addr:
2052 - pci_epc_unmap_addr(epc, phys_addr);
2053 + pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
2054
2055 err_addr:
2056 pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
2057 @@ -209,15 +207,16 @@ static int pci_epf_test_write(struct pci
2058
2059 dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
2060 if (!dst_addr) {
2061 - dev_err(dev, "failed to allocate address\n");
2062 + dev_err(dev, "Failed to allocate address\n");
2063 reg->status = STATUS_DST_ADDR_INVALID;
2064 ret = -ENOMEM;
2065 goto err;
2066 }
2067
2068 - ret = pci_epc_map_addr(epc, phys_addr, reg->dst_addr, reg->size);
2069 + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr,
2070 + reg->size);
2071 if (ret) {
2072 - dev_err(dev, "failed to map address\n");
2073 + dev_err(dev, "Failed to map address\n");
2074 reg->status = STATUS_DST_ADDR_INVALID;
2075 goto err_addr;
2076 }
2077 @@ -237,12 +236,12 @@ static int pci_epf_test_write(struct pci
2078 * wait 1ms inorder for the write to complete. Without this delay L3
2079 * error in observed in the host system.
2080 */
2081 - mdelay(1);
2082 + usleep_range(1000, 2000);
2083
2084 kfree(buf);
2085
2086 err_map_addr:
2087 - pci_epc_unmap_addr(epc, phys_addr);
2088 + pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
2089
2090 err_addr:
2091 pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
2092 @@ -251,31 +250,42 @@ err:
2093 return ret;
2094 }
2095
2096 -static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq)
2097 +static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq_type,
2098 + u16 irq)
2099 {
2100 - u8 msi_count;
2101 struct pci_epf *epf = epf_test->epf;
2102 + struct device *dev = &epf->dev;
2103 struct pci_epc *epc = epf->epc;
2104 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
2105 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
2106
2107 reg->status |= STATUS_IRQ_RAISED;
2108 - msi_count = pci_epc_get_msi(epc);
2109 - if (irq > msi_count || msi_count <= 0)
2110 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
2111 - else
2112 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
2113 +
2114 + switch (irq_type) {
2115 + case IRQ_TYPE_LEGACY:
2116 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
2117 + break;
2118 + case IRQ_TYPE_MSI:
2119 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
2120 + break;
2121 + case IRQ_TYPE_MSIX:
2122 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX, irq);
2123 + break;
2124 + default:
2125 + dev_err(dev, "Failed to raise IRQ, unknown type\n");
2126 + break;
2127 + }
2128 }
2129
2130 static void pci_epf_test_cmd_handler(struct work_struct *work)
2131 {
2132 int ret;
2133 - u8 irq;
2134 - u8 msi_count;
2135 + int count;
2136 u32 command;
2137 struct pci_epf_test *epf_test = container_of(work, struct pci_epf_test,
2138 cmd_handler.work);
2139 struct pci_epf *epf = epf_test->epf;
2140 + struct device *dev = &epf->dev;
2141 struct pci_epc *epc = epf->epc;
2142 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
2143 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
2144 @@ -287,11 +297,14 @@ static void pci_epf_test_cmd_handler(str
2145 reg->command = 0;
2146 reg->status = 0;
2147
2148 - irq = (command & MSI_NUMBER_MASK) >> MSI_NUMBER_SHIFT;
2149 + if (reg->irq_type > IRQ_TYPE_MSIX) {
2150 + dev_err(dev, "Failed to detect IRQ type\n");
2151 + goto reset_handler;
2152 + }
2153
2154 if (command & COMMAND_RAISE_LEGACY_IRQ) {
2155 reg->status = STATUS_IRQ_RAISED;
2156 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
2157 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
2158 goto reset_handler;
2159 }
2160
2161 @@ -301,7 +314,8 @@ static void pci_epf_test_cmd_handler(str
2162 reg->status |= STATUS_WRITE_FAIL;
2163 else
2164 reg->status |= STATUS_WRITE_SUCCESS;
2165 - pci_epf_test_raise_irq(epf_test, irq);
2166 + pci_epf_test_raise_irq(epf_test, reg->irq_type,
2167 + reg->irq_number);
2168 goto reset_handler;
2169 }
2170
2171 @@ -311,7 +325,8 @@ static void pci_epf_test_cmd_handler(str
2172 reg->status |= STATUS_READ_SUCCESS;
2173 else
2174 reg->status |= STATUS_READ_FAIL;
2175 - pci_epf_test_raise_irq(epf_test, irq);
2176 + pci_epf_test_raise_irq(epf_test, reg->irq_type,
2177 + reg->irq_number);
2178 goto reset_handler;
2179 }
2180
2181 @@ -321,16 +336,28 @@ static void pci_epf_test_cmd_handler(str
2182 reg->status |= STATUS_COPY_SUCCESS;
2183 else
2184 reg->status |= STATUS_COPY_FAIL;
2185 - pci_epf_test_raise_irq(epf_test, irq);
2186 + pci_epf_test_raise_irq(epf_test, reg->irq_type,
2187 + reg->irq_number);
2188 goto reset_handler;
2189 }
2190
2191 if (command & COMMAND_RAISE_MSI_IRQ) {
2192 - msi_count = pci_epc_get_msi(epc);
2193 - if (irq > msi_count || msi_count <= 0)
2194 + count = pci_epc_get_msi(epc, epf->func_no);
2195 + if (reg->irq_number > count || count <= 0)
2196 + goto reset_handler;
2197 + reg->status = STATUS_IRQ_RAISED;
2198 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI,
2199 + reg->irq_number);
2200 + goto reset_handler;
2201 + }
2202 +
2203 + if (command & COMMAND_RAISE_MSIX_IRQ) {
2204 + count = pci_epc_get_msix(epc, epf->func_no);
2205 + if (reg->irq_number > count || count <= 0)
2206 goto reset_handler;
2207 reg->status = STATUS_IRQ_RAISED;
2208 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
2209 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX,
2210 + reg->irq_number);
2211 goto reset_handler;
2212 }
2213
2214 @@ -351,21 +378,23 @@ static void pci_epf_test_unbind(struct p
2215 {
2216 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
2217 struct pci_epc *epc = epf->epc;
2218 + struct pci_epf_bar *epf_bar;
2219 int bar;
2220
2221 cancel_delayed_work(&epf_test->cmd_handler);
2222 pci_epc_stop(epc);
2223 for (bar = BAR_0; bar <= BAR_5; bar++) {
2224 + epf_bar = &epf->bar[bar];
2225 +
2226 if (epf_test->reg[bar]) {
2227 pci_epf_free_space(epf, epf_test->reg[bar], bar);
2228 - pci_epc_clear_bar(epc, bar);
2229 + pci_epc_clear_bar(epc, epf->func_no, epf_bar);
2230 }
2231 }
2232 }
2233
2234 static int pci_epf_test_set_bar(struct pci_epf *epf)
2235 {
2236 - int flags;
2237 int bar;
2238 int ret;
2239 struct pci_epf_bar *epf_bar;
2240 @@ -374,20 +403,27 @@ static int pci_epf_test_set_bar(struct p
2241 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
2242 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
2243
2244 - flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;
2245 - if (sizeof(dma_addr_t) == 0x8)
2246 - flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
2247 -
2248 for (bar = BAR_0; bar <= BAR_5; bar++) {
2249 epf_bar = &epf->bar[bar];
2250 - ret = pci_epc_set_bar(epc, bar, epf_bar->phys_addr,
2251 - epf_bar->size, flags);
2252 +
2253 + epf_bar->flags |= upper_32_bits(epf_bar->size) ?
2254 + PCI_BASE_ADDRESS_MEM_TYPE_64 :
2255 + PCI_BASE_ADDRESS_MEM_TYPE_32;
2256 +
2257 + ret = pci_epc_set_bar(epc, epf->func_no, epf_bar);
2258 if (ret) {
2259 pci_epf_free_space(epf, epf_test->reg[bar], bar);
2260 - dev_err(dev, "failed to set BAR%d\n", bar);
2261 + dev_err(dev, "Failed to set BAR%d\n", bar);
2262 if (bar == test_reg_bar)
2263 return ret;
2264 }
2265 + /*
2266 + * pci_epc_set_bar() sets PCI_BASE_ADDRESS_MEM_TYPE_64
2267 + * if the specific implementation required a 64-bit BAR,
2268 + * even if we only requested a 32-bit BAR.
2269 + */
2270 + if (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
2271 + bar++;
2272 }
2273
2274 return 0;
2275 @@ -404,7 +440,7 @@ static int pci_epf_test_alloc_space(stru
2276 base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
2277 test_reg_bar);
2278 if (!base) {
2279 - dev_err(dev, "failed to allocated register space\n");
2280 + dev_err(dev, "Failed to allocated register space\n");
2281 return -ENOMEM;
2282 }
2283 epf_test->reg[test_reg_bar] = base;
2284 @@ -414,7 +450,7 @@ static int pci_epf_test_alloc_space(stru
2285 continue;
2286 base = pci_epf_alloc_space(epf, bar_size[bar], bar);
2287 if (!base)
2288 - dev_err(dev, "failed to allocate space for BAR%d\n",
2289 + dev_err(dev, "Failed to allocate space for BAR%d\n",
2290 bar);
2291 epf_test->reg[bar] = base;
2292 }
2293 @@ -433,9 +469,18 @@ static int pci_epf_test_bind(struct pci_
2294 if (WARN_ON_ONCE(!epc))
2295 return -EINVAL;
2296
2297 - ret = pci_epc_write_header(epc, header);
2298 + if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER)
2299 + epf_test->linkup_notifier = false;
2300 + else
2301 + epf_test->linkup_notifier = true;
2302 +
2303 + epf_test->msix_available = epc->features & EPC_FEATURE_MSIX_AVAILABLE;
2304 +
2305 + epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features);
2306 +
2307 + ret = pci_epc_write_header(epc, epf->func_no, header);
2308 if (ret) {
2309 - dev_err(dev, "configuration header write failed\n");
2310 + dev_err(dev, "Configuration header write failed\n");
2311 return ret;
2312 }
2313
2314 @@ -447,9 +492,19 @@ static int pci_epf_test_bind(struct pci_
2315 if (ret)
2316 return ret;
2317
2318 - ret = pci_epc_set_msi(epc, epf->msi_interrupts);
2319 - if (ret)
2320 + ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
2321 + if (ret) {
2322 + dev_err(dev, "MSI configuration failed\n");
2323 return ret;
2324 + }
2325 +
2326 + if (epf_test->msix_available) {
2327 + ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
2328 + if (ret) {
2329 + dev_err(dev, "MSI-X configuration failed\n");
2330 + return ret;
2331 + }
2332 + }
2333
2334 if (!epf_test->linkup_notifier)
2335 queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
2336 @@ -517,7 +572,7 @@ static int __init pci_epf_test_init(void
2337 WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
2338 ret = pci_epf_register_driver(&test_driver);
2339 if (ret) {
2340 - pr_err("failed to register pci epf test driver --> %d\n", ret);
2341 + pr_err("Failed to register pci epf test driver --> %d\n", ret);
2342 return ret;
2343 }
2344
2345 --- a/drivers/pci/endpoint/pci-ep-cfs.c
2346 +++ b/drivers/pci/endpoint/pci-ep-cfs.c
2347 @@ -1,35 +1,28 @@
2348 +// SPDX-License-Identifier: GPL-2.0
2349 /**
2350 * configfs to configure the PCI endpoint
2351 *
2352 * Copyright (C) 2017 Texas Instruments
2353 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2354 - *
2355 - * This program is free software: you can redistribute it and/or modify
2356 - * it under the terms of the GNU General Public License version 2 of
2357 - * the License as published by the Free Software Foundation.
2358 - *
2359 - * This program is distributed in the hope that it will be useful,
2360 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2361 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2362 - * GNU General Public License for more details.
2363 - *
2364 - * You should have received a copy of the GNU General Public License
2365 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2366 */
2367
2368 #include <linux/module.h>
2369 +#include <linux/idr.h>
2370 #include <linux/slab.h>
2371
2372 #include <linux/pci-epc.h>
2373 #include <linux/pci-epf.h>
2374 #include <linux/pci-ep-cfs.h>
2375
2376 +static DEFINE_IDR(functions_idr);
2377 +static DEFINE_MUTEX(functions_mutex);
2378 static struct config_group *functions_group;
2379 static struct config_group *controllers_group;
2380
2381 struct pci_epf_group {
2382 struct config_group group;
2383 struct pci_epf *epf;
2384 + int index;
2385 };
2386
2387 struct pci_epc_group {
2388 @@ -151,7 +144,7 @@ static struct configfs_item_operations p
2389 .drop_link = pci_epc_epf_unlink,
2390 };
2391
2392 -static struct config_item_type pci_epc_type = {
2393 +static const struct config_item_type pci_epc_type = {
2394 .ct_item_ops = &pci_epc_item_ops,
2395 .ct_attrs = pci_epc_attrs,
2396 .ct_owner = THIS_MODULE,
2397 @@ -293,6 +286,28 @@ static ssize_t pci_epf_msi_interrupts_sh
2398 to_pci_epf_group(item)->epf->msi_interrupts);
2399 }
2400
2401 +static ssize_t pci_epf_msix_interrupts_store(struct config_item *item,
2402 + const char *page, size_t len)
2403 +{
2404 + u16 val;
2405 + int ret;
2406 +
2407 + ret = kstrtou16(page, 0, &val);
2408 + if (ret)
2409 + return ret;
2410 +
2411 + to_pci_epf_group(item)->epf->msix_interrupts = val;
2412 +
2413 + return len;
2414 +}
2415 +
2416 +static ssize_t pci_epf_msix_interrupts_show(struct config_item *item,
2417 + char *page)
2418 +{
2419 + return sprintf(page, "%d\n",
2420 + to_pci_epf_group(item)->epf->msix_interrupts);
2421 +}
2422 +
2423 PCI_EPF_HEADER_R(vendorid)
2424 PCI_EPF_HEADER_W_u16(vendorid)
2425
2426 @@ -334,6 +349,7 @@ CONFIGFS_ATTR(pci_epf_, subsys_vendor_id
2427 CONFIGFS_ATTR(pci_epf_, subsys_id);
2428 CONFIGFS_ATTR(pci_epf_, interrupt_pin);
2429 CONFIGFS_ATTR(pci_epf_, msi_interrupts);
2430 +CONFIGFS_ATTR(pci_epf_, msix_interrupts);
2431
2432 static struct configfs_attribute *pci_epf_attrs[] = {
2433 &pci_epf_attr_vendorid,
2434 @@ -347,6 +363,7 @@ static struct configfs_attribute *pci_ep
2435 &pci_epf_attr_subsys_id,
2436 &pci_epf_attr_interrupt_pin,
2437 &pci_epf_attr_msi_interrupts,
2438 + &pci_epf_attr_msix_interrupts,
2439 NULL,
2440 };
2441
2442 @@ -354,6 +371,9 @@ static void pci_epf_release(struct confi
2443 {
2444 struct pci_epf_group *epf_group = to_pci_epf_group(item);
2445
2446 + mutex_lock(&functions_mutex);
2447 + idr_remove(&functions_idr, epf_group->index);
2448 + mutex_unlock(&functions_mutex);
2449 pci_epf_destroy(epf_group->epf);
2450 kfree(epf_group);
2451 }
2452 @@ -362,7 +382,7 @@ static struct configfs_item_operations p
2453 .release = pci_epf_release,
2454 };
2455
2456 -static struct config_item_type pci_epf_type = {
2457 +static const struct config_item_type pci_epf_type = {
2458 .ct_item_ops = &pci_epf_ops,
2459 .ct_attrs = pci_epf_attrs,
2460 .ct_owner = THIS_MODULE,
2461 @@ -373,22 +393,57 @@ static struct config_group *pci_epf_make
2462 {
2463 struct pci_epf_group *epf_group;
2464 struct pci_epf *epf;
2465 + char *epf_name;
2466 + int index, err;
2467
2468 epf_group = kzalloc(sizeof(*epf_group), GFP_KERNEL);
2469 if (!epf_group)
2470 return ERR_PTR(-ENOMEM);
2471
2472 + mutex_lock(&functions_mutex);
2473 + index = idr_alloc(&functions_idr, epf_group, 0, 0, GFP_KERNEL);
2474 + mutex_unlock(&functions_mutex);
2475 + if (index < 0) {
2476 + err = index;
2477 + goto free_group;
2478 + }
2479 +
2480 + epf_group->index = index;
2481 +
2482 config_group_init_type_name(&epf_group->group, name, &pci_epf_type);
2483
2484 - epf = pci_epf_create(group->cg_item.ci_name);
2485 + epf_name = kasprintf(GFP_KERNEL, "%s.%d",
2486 + group->cg_item.ci_name, epf_group->index);
2487 + if (!epf_name) {
2488 + err = -ENOMEM;
2489 + goto remove_idr;
2490 + }
2491 +
2492 + epf = pci_epf_create(epf_name);
2493 if (IS_ERR(epf)) {
2494 pr_err("failed to create endpoint function device\n");
2495 - return ERR_PTR(-EINVAL);
2496 + err = -EINVAL;
2497 + goto free_name;
2498 }
2499
2500 epf_group->epf = epf;
2501
2502 + kfree(epf_name);
2503 +
2504 return &epf_group->group;
2505 +
2506 +free_name:
2507 + kfree(epf_name);
2508 +
2509 +remove_idr:
2510 + mutex_lock(&functions_mutex);
2511 + idr_remove(&functions_idr, epf_group->index);
2512 + mutex_unlock(&functions_mutex);
2513 +
2514 +free_group:
2515 + kfree(epf_group);
2516 +
2517 + return ERR_PTR(err);
2518 }
2519
2520 static void pci_epf_drop(struct config_group *group, struct config_item *item)
2521 @@ -401,7 +456,7 @@ static struct configfs_group_operations
2522 .drop_item = &pci_epf_drop,
2523 };
2524
2525 -static struct config_item_type pci_epf_group_type = {
2526 +static const struct config_item_type pci_epf_group_type = {
2527 .ct_group_ops = &pci_epf_group_ops,
2528 .ct_owner = THIS_MODULE,
2529 };
2530 @@ -429,15 +484,15 @@ void pci_ep_cfs_remove_epf_group(struct
2531 }
2532 EXPORT_SYMBOL(pci_ep_cfs_remove_epf_group);
2533
2534 -static struct config_item_type pci_functions_type = {
2535 +static const struct config_item_type pci_functions_type = {
2536 .ct_owner = THIS_MODULE,
2537 };
2538
2539 -static struct config_item_type pci_controllers_type = {
2540 +static const struct config_item_type pci_controllers_type = {
2541 .ct_owner = THIS_MODULE,
2542 };
2543
2544 -static struct config_item_type pci_ep_type = {
2545 +static const struct config_item_type pci_ep_type = {
2546 .ct_owner = THIS_MODULE,
2547 };
2548
2549 --- a/drivers/pci/endpoint/pci-epc-core.c
2550 +++ b/drivers/pci/endpoint/pci-epc-core.c
2551 @@ -1,20 +1,9 @@
2552 +// SPDX-License-Identifier: GPL-2.0
2553 /**
2554 * PCI Endpoint *Controller* (EPC) library
2555 *
2556 * Copyright (C) 2017 Texas Instruments
2557 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2558 - *
2559 - * This program is free software: you can redistribute it and/or modify
2560 - * it under the terms of the GNU General Public License version 2 of
2561 - * the License as published by the Free Software Foundation.
2562 - *
2563 - * This program is distributed in the hope that it will be useful,
2564 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2565 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2566 - * GNU General Public License for more details.
2567 - *
2568 - * You should have received a copy of the GNU General Public License
2569 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2570 */
2571
2572 #include <linux/device.h>
2573 @@ -141,25 +130,26 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
2574 /**
2575 * pci_epc_raise_irq() - interrupt the host system
2576 * @epc: the EPC device which has to interrupt the host
2577 - * @type: specify the type of interrupt; legacy or MSI
2578 - * @interrupt_num: the MSI interrupt number
2579 + * @func_no: the endpoint function number in the EPC device
2580 + * @type: specify the type of interrupt; legacy, MSI or MSI-X
2581 + * @interrupt_num: the MSI or MSI-X interrupt number
2582 *
2583 - * Invoke to raise an MSI or legacy interrupt
2584 + * Invoke to raise an legacy, MSI or MSI-X interrupt
2585 */
2586 -int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
2587 - u8 interrupt_num)
2588 +int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
2589 + enum pci_epc_irq_type type, u16 interrupt_num)
2590 {
2591 int ret;
2592 unsigned long flags;
2593
2594 - if (IS_ERR(epc))
2595 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2596 return -EINVAL;
2597
2598 if (!epc->ops->raise_irq)
2599 return 0;
2600
2601 spin_lock_irqsave(&epc->lock, flags);
2602 - ret = epc->ops->raise_irq(epc, type, interrupt_num);
2603 + ret = epc->ops->raise_irq(epc, func_no, type, interrupt_num);
2604 spin_unlock_irqrestore(&epc->lock, flags);
2605
2606 return ret;
2607 @@ -169,22 +159,23 @@ EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
2608 /**
2609 * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated
2610 * @epc: the EPC device to which MSI interrupts was requested
2611 + * @func_no: the endpoint function number in the EPC device
2612 *
2613 * Invoke to get the number of MSI interrupts allocated by the RC
2614 */
2615 -int pci_epc_get_msi(struct pci_epc *epc)
2616 +int pci_epc_get_msi(struct pci_epc *epc, u8 func_no)
2617 {
2618 int interrupt;
2619 unsigned long flags;
2620
2621 - if (IS_ERR(epc))
2622 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2623 return 0;
2624
2625 if (!epc->ops->get_msi)
2626 return 0;
2627
2628 spin_lock_irqsave(&epc->lock, flags);
2629 - interrupt = epc->ops->get_msi(epc);
2630 + interrupt = epc->ops->get_msi(epc, func_no);
2631 spin_unlock_irqrestore(&epc->lock, flags);
2632
2633 if (interrupt < 0)
2634 @@ -199,17 +190,19 @@ EXPORT_SYMBOL_GPL(pci_epc_get_msi);
2635 /**
2636 * pci_epc_set_msi() - set the number of MSI interrupt numbers required
2637 * @epc: the EPC device on which MSI has to be configured
2638 + * @func_no: the endpoint function number in the EPC device
2639 * @interrupts: number of MSI interrupts required by the EPF
2640 *
2641 * Invoke to set the required number of MSI interrupts.
2642 */
2643 -int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts)
2644 +int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
2645 {
2646 int ret;
2647 u8 encode_int;
2648 unsigned long flags;
2649
2650 - if (IS_ERR(epc))
2651 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2652 + interrupts > 32)
2653 return -EINVAL;
2654
2655 if (!epc->ops->set_msi)
2656 @@ -218,7 +211,7 @@ int pci_epc_set_msi(struct pci_epc *epc,
2657 encode_int = order_base_2(interrupts);
2658
2659 spin_lock_irqsave(&epc->lock, flags);
2660 - ret = epc->ops->set_msi(epc, encode_int);
2661 + ret = epc->ops->set_msi(epc, func_no, encode_int);
2662 spin_unlock_irqrestore(&epc->lock, flags);
2663
2664 return ret;
2665 @@ -226,24 +219,83 @@ int pci_epc_set_msi(struct pci_epc *epc,
2666 EXPORT_SYMBOL_GPL(pci_epc_set_msi);
2667
2668 /**
2669 + * pci_epc_get_msix() - get the number of MSI-X interrupt numbers allocated
2670 + * @epc: the EPC device to which MSI-X interrupts was requested
2671 + * @func_no: the endpoint function number in the EPC device
2672 + *
2673 + * Invoke to get the number of MSI-X interrupts allocated by the RC
2674 + */
2675 +int pci_epc_get_msix(struct pci_epc *epc, u8 func_no)
2676 +{
2677 + int interrupt;
2678 + unsigned long flags;
2679 +
2680 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2681 + return 0;
2682 +
2683 + if (!epc->ops->get_msix)
2684 + return 0;
2685 +
2686 + spin_lock_irqsave(&epc->lock, flags);
2687 + interrupt = epc->ops->get_msix(epc, func_no);
2688 + spin_unlock_irqrestore(&epc->lock, flags);
2689 +
2690 + if (interrupt < 0)
2691 + return 0;
2692 +
2693 + return interrupt + 1;
2694 +}
2695 +EXPORT_SYMBOL_GPL(pci_epc_get_msix);
2696 +
2697 +/**
2698 + * pci_epc_set_msix() - set the number of MSI-X interrupt numbers required
2699 + * @epc: the EPC device on which MSI-X has to be configured
2700 + * @func_no: the endpoint function number in the EPC device
2701 + * @interrupts: number of MSI-X interrupts required by the EPF
2702 + *
2703 + * Invoke to set the required number of MSI-X interrupts.
2704 + */
2705 +int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
2706 +{
2707 + int ret;
2708 + unsigned long flags;
2709 +
2710 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2711 + interrupts < 1 || interrupts > 2048)
2712 + return -EINVAL;
2713 +
2714 + if (!epc->ops->set_msix)
2715 + return 0;
2716 +
2717 + spin_lock_irqsave(&epc->lock, flags);
2718 + ret = epc->ops->set_msix(epc, func_no, interrupts - 1);
2719 + spin_unlock_irqrestore(&epc->lock, flags);
2720 +
2721 + return ret;
2722 +}
2723 +EXPORT_SYMBOL_GPL(pci_epc_set_msix);
2724 +
2725 +/**
2726 * pci_epc_unmap_addr() - unmap CPU address from PCI address
2727 * @epc: the EPC device on which address is allocated
2728 + * @func_no: the endpoint function number in the EPC device
2729 * @phys_addr: physical address of the local system
2730 *
2731 * Invoke to unmap the CPU address from PCI address.
2732 */
2733 -void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr)
2734 +void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
2735 + phys_addr_t phys_addr)
2736 {
2737 unsigned long flags;
2738
2739 - if (IS_ERR(epc))
2740 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2741 return;
2742
2743 if (!epc->ops->unmap_addr)
2744 return;
2745
2746 spin_lock_irqsave(&epc->lock, flags);
2747 - epc->ops->unmap_addr(epc, phys_addr);
2748 + epc->ops->unmap_addr(epc, func_no, phys_addr);
2749 spin_unlock_irqrestore(&epc->lock, flags);
2750 }
2751 EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
2752 @@ -251,26 +303,27 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
2753 /**
2754 * pci_epc_map_addr() - map CPU address to PCI address
2755 * @epc: the EPC device on which address is allocated
2756 + * @func_no: the endpoint function number in the EPC device
2757 * @phys_addr: physical address of the local system
2758 * @pci_addr: PCI address to which the physical address should be mapped
2759 * @size: the size of the allocation
2760 *
2761 * Invoke to map CPU address with PCI address.
2762 */
2763 -int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
2764 - u64 pci_addr, size_t size)
2765 +int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
2766 + phys_addr_t phys_addr, u64 pci_addr, size_t size)
2767 {
2768 int ret;
2769 unsigned long flags;
2770
2771 - if (IS_ERR(epc))
2772 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2773 return -EINVAL;
2774
2775 if (!epc->ops->map_addr)
2776 return 0;
2777
2778 spin_lock_irqsave(&epc->lock, flags);
2779 - ret = epc->ops->map_addr(epc, phys_addr, pci_addr, size);
2780 + ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size);
2781 spin_unlock_irqrestore(&epc->lock, flags);
2782
2783 return ret;
2784 @@ -280,22 +333,26 @@ EXPORT_SYMBOL_GPL(pci_epc_map_addr);
2785 /**
2786 * pci_epc_clear_bar() - reset the BAR
2787 * @epc: the EPC device for which the BAR has to be cleared
2788 - * @bar: the BAR number that has to be reset
2789 + * @func_no: the endpoint function number in the EPC device
2790 + * @epf_bar: the struct epf_bar that contains the BAR information
2791 *
2792 * Invoke to reset the BAR of the endpoint device.
2793 */
2794 -void pci_epc_clear_bar(struct pci_epc *epc, int bar)
2795 +void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
2796 + struct pci_epf_bar *epf_bar)
2797 {
2798 unsigned long flags;
2799
2800 - if (IS_ERR(epc))
2801 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2802 + (epf_bar->barno == BAR_5 &&
2803 + epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
2804 return;
2805
2806 if (!epc->ops->clear_bar)
2807 return;
2808
2809 spin_lock_irqsave(&epc->lock, flags);
2810 - epc->ops->clear_bar(epc, bar);
2811 + epc->ops->clear_bar(epc, func_no, epf_bar);
2812 spin_unlock_irqrestore(&epc->lock, flags);
2813 }
2814 EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
2815 @@ -303,26 +360,32 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
2816 /**
2817 * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space
2818 * @epc: the EPC device on which BAR has to be configured
2819 - * @bar: the BAR number that has to be configured
2820 - * @size: the size of the addr space
2821 - * @flags: specify memory allocation/io allocation/32bit address/64 bit address
2822 + * @func_no: the endpoint function number in the EPC device
2823 + * @epf_bar: the struct epf_bar that contains the BAR information
2824 *
2825 * Invoke to configure the BAR of the endpoint device.
2826 */
2827 -int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
2828 - dma_addr_t bar_phys, size_t size, int flags)
2829 +int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
2830 + struct pci_epf_bar *epf_bar)
2831 {
2832 int ret;
2833 unsigned long irq_flags;
2834 + int flags = epf_bar->flags;
2835
2836 - if (IS_ERR(epc))
2837 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2838 + (epf_bar->barno == BAR_5 &&
2839 + flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ||
2840 + (flags & PCI_BASE_ADDRESS_SPACE_IO &&
2841 + flags & PCI_BASE_ADDRESS_IO_MASK) ||
2842 + (upper_32_bits(epf_bar->size) &&
2843 + !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
2844 return -EINVAL;
2845
2846 if (!epc->ops->set_bar)
2847 return 0;
2848
2849 spin_lock_irqsave(&epc->lock, irq_flags);
2850 - ret = epc->ops->set_bar(epc, bar, bar_phys, size, flags);
2851 + ret = epc->ops->set_bar(epc, func_no, epf_bar);
2852 spin_unlock_irqrestore(&epc->lock, irq_flags);
2853
2854 return ret;
2855 @@ -332,6 +395,7 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
2856 /**
2857 * pci_epc_write_header() - write standard configuration header
2858 * @epc: the EPC device to which the configuration header should be written
2859 + * @func_no: the endpoint function number in the EPC device
2860 * @header: standard configuration header fields
2861 *
2862 * Invoke to write the configuration header to the endpoint controller. Every
2863 @@ -339,19 +403,20 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
2864 * configuration header would be written. The callback function should write
2865 * the header fields to this dedicated location.
2866 */
2867 -int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *header)
2868 +int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
2869 + struct pci_epf_header *header)
2870 {
2871 int ret;
2872 unsigned long flags;
2873
2874 - if (IS_ERR(epc))
2875 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2876 return -EINVAL;
2877
2878 if (!epc->ops->write_header)
2879 return 0;
2880
2881 spin_lock_irqsave(&epc->lock, flags);
2882 - ret = epc->ops->write_header(epc, header);
2883 + ret = epc->ops->write_header(epc, func_no, header);
2884 spin_unlock_irqrestore(&epc->lock, flags);
2885
2886 return ret;
2887 --- a/drivers/pci/endpoint/pci-epc-mem.c
2888 +++ b/drivers/pci/endpoint/pci-epc-mem.c
2889 @@ -1,20 +1,9 @@
2890 +// SPDX-License-Identifier: GPL-2.0
2891 /**
2892 * PCI Endpoint *Controller* Address Space Management
2893 *
2894 * Copyright (C) 2017 Texas Instruments
2895 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2896 - *
2897 - * This program is free software: you can redistribute it and/or modify
2898 - * it under the terms of the GNU General Public License version 2 of
2899 - * the License as published by the Free Software Foundation.
2900 - *
2901 - * This program is distributed in the hope that it will be useful,
2902 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2903 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2904 - * GNU General Public License for more details.
2905 - *
2906 - * You should have received a copy of the GNU General Public License
2907 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2908 */
2909
2910 #include <linux/io.h>
2911 --- a/drivers/pci/endpoint/pci-epf-core.c
2912 +++ b/drivers/pci/endpoint/pci-epf-core.c
2913 @@ -1,20 +1,9 @@
2914 +// SPDX-License-Identifier: GPL-2.0
2915 /**
2916 * PCI Endpoint *Function* (EPF) library
2917 *
2918 * Copyright (C) 2017 Texas Instruments
2919 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2920 - *
2921 - * This program is free software: you can redistribute it and/or modify
2922 - * it under the terms of the GNU General Public License version 2 of
2923 - * the License as published by the Free Software Foundation.
2924 - *
2925 - * This program is distributed in the hope that it will be useful,
2926 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2927 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2928 - * GNU General Public License for more details.
2929 - *
2930 - * You should have received a copy of the GNU General Public License
2931 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2932 */
2933
2934 #include <linux/device.h>
2935 @@ -26,6 +15,8 @@
2936 #include <linux/pci-epf.h>
2937 #include <linux/pci-ep-cfs.h>
2938
2939 +static DEFINE_MUTEX(pci_epf_mutex);
2940 +
2941 static struct bus_type pci_epf_bus_type;
2942 static const struct device_type pci_epf_type;
2943
2944 @@ -109,6 +100,8 @@ void pci_epf_free_space(struct pci_epf *
2945
2946 epf->bar[bar].phys_addr = 0;
2947 epf->bar[bar].size = 0;
2948 + epf->bar[bar].barno = 0;
2949 + epf->bar[bar].flags = 0;
2950 }
2951 EXPORT_SYMBOL_GPL(pci_epf_free_space);
2952
2953 @@ -137,11 +130,27 @@ void *pci_epf_alloc_space(struct pci_epf
2954
2955 epf->bar[bar].phys_addr = phys_addr;
2956 epf->bar[bar].size = size;
2957 + epf->bar[bar].barno = bar;
2958 + epf->bar[bar].flags = PCI_BASE_ADDRESS_SPACE_MEMORY;
2959
2960 return space;
2961 }
2962 EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
2963
2964 +static void pci_epf_remove_cfs(struct pci_epf_driver *driver)
2965 +{
2966 + struct config_group *group, *tmp;
2967 +
2968 + if (!IS_ENABLED(CONFIG_PCI_ENDPOINT_CONFIGFS))
2969 + return;
2970 +
2971 + mutex_lock(&pci_epf_mutex);
2972 + list_for_each_entry_safe(group, tmp, &driver->epf_group, group_entry)
2973 + pci_ep_cfs_remove_epf_group(group);
2974 + list_del(&driver->epf_group);
2975 + mutex_unlock(&pci_epf_mutex);
2976 +}
2977 +
2978 /**
2979 * pci_epf_unregister_driver() - unregister the PCI EPF driver
2980 * @driver: the PCI EPF driver that has to be unregistered
2981 @@ -150,11 +159,38 @@ EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
2982 */
2983 void pci_epf_unregister_driver(struct pci_epf_driver *driver)
2984 {
2985 - pci_ep_cfs_remove_epf_group(driver->group);
2986 + pci_epf_remove_cfs(driver);
2987 driver_unregister(&driver->driver);
2988 }
2989 EXPORT_SYMBOL_GPL(pci_epf_unregister_driver);
2990
2991 +static int pci_epf_add_cfs(struct pci_epf_driver *driver)
2992 +{
2993 + struct config_group *group;
2994 + const struct pci_epf_device_id *id;
2995 +
2996 + if (!IS_ENABLED(CONFIG_PCI_ENDPOINT_CONFIGFS))
2997 + return 0;
2998 +
2999 + INIT_LIST_HEAD(&driver->epf_group);
3000 +
3001 + id = driver->id_table;
3002 + while (id->name[0]) {
3003 + group = pci_ep_cfs_add_epf_group(id->name);
3004 + if (IS_ERR(group)) {
3005 + pci_epf_remove_cfs(driver);
3006 + return PTR_ERR(group);
3007 + }
3008 +
3009 + mutex_lock(&pci_epf_mutex);
3010 + list_add_tail(&group->group_entry, &driver->epf_group);
3011 + mutex_unlock(&pci_epf_mutex);
3012 + id++;
3013 + }
3014 +
3015 + return 0;
3016 +}
3017 +
3018 /**
3019 * __pci_epf_register_driver() - register a new PCI EPF driver
3020 * @driver: structure representing PCI EPF driver
3021 @@ -180,7 +216,7 @@ int __pci_epf_register_driver(struct pci
3022 if (ret)
3023 return ret;
3024
3025 - driver->group = pci_ep_cfs_add_epf_group(driver->driver.name);
3026 + pci_epf_add_cfs(driver);
3027
3028 return 0;
3029 }
3030 @@ -211,29 +247,17 @@ struct pci_epf *pci_epf_create(const cha
3031 int ret;
3032 struct pci_epf *epf;
3033 struct device *dev;
3034 - char *func_name;
3035 - char *buf;
3036 + int len;
3037
3038 epf = kzalloc(sizeof(*epf), GFP_KERNEL);
3039 - if (!epf) {
3040 - ret = -ENOMEM;
3041 - goto err_ret;
3042 - }
3043 + if (!epf)
3044 + return ERR_PTR(-ENOMEM);
3045
3046 - buf = kstrdup(name, GFP_KERNEL);
3047 - if (!buf) {
3048 - ret = -ENOMEM;
3049 - goto free_epf;
3050 - }
3051 -
3052 - func_name = buf;
3053 - buf = strchrnul(buf, '.');
3054 - *buf = '\0';
3055 -
3056 - epf->name = kstrdup(func_name, GFP_KERNEL);
3057 + len = strchrnul(name, '.') - name;
3058 + epf->name = kstrndup(name, len, GFP_KERNEL);
3059 if (!epf->name) {
3060 - ret = -ENOMEM;
3061 - goto free_func_name;
3062 + kfree(epf);
3063 + return ERR_PTR(-ENOMEM);
3064 }
3065
3066 dev = &epf->dev;
3067 @@ -242,28 +266,18 @@ struct pci_epf *pci_epf_create(const cha
3068 dev->type = &pci_epf_type;
3069
3070 ret = dev_set_name(dev, "%s", name);
3071 - if (ret)
3072 - goto put_dev;
3073 + if (ret) {
3074 + put_device(dev);
3075 + return ERR_PTR(ret);
3076 + }
3077
3078 ret = device_add(dev);
3079 - if (ret)
3080 - goto put_dev;
3081 + if (ret) {
3082 + put_device(dev);
3083 + return ERR_PTR(ret);
3084 + }
3085
3086 - kfree(func_name);
3087 return epf;
3088 -
3089 -put_dev:
3090 - put_device(dev);
3091 - kfree(epf->name);
3092 -
3093 -free_func_name:
3094 - kfree(func_name);
3095 -
3096 -free_epf:
3097 - kfree(epf);
3098 -
3099 -err_ret:
3100 - return ERR_PTR(ret);
3101 }
3102 EXPORT_SYMBOL_GPL(pci_epf_create);
3103
3104 --- a/drivers/pci/host/pci-host-common.c
3105 +++ b/drivers/pci/host/pci-host-common.c
3106 @@ -113,9 +113,7 @@ err_out:
3107 int pci_host_common_probe(struct platform_device *pdev,
3108 struct pci_ecam_ops *ops)
3109 {
3110 - const char *type;
3111 struct device *dev = &pdev->dev;
3112 - struct device_node *np = dev->of_node;
3113 struct pci_bus *bus, *child;
3114 struct pci_host_bridge *bridge;
3115 struct pci_config_window *cfg;
3116 @@ -126,12 +124,6 @@ int pci_host_common_probe(struct platfor
3117 if (!bridge)
3118 return -ENOMEM;
3119
3120 - type = of_get_property(np, "device_type", NULL);
3121 - if (!type || strcmp(type, "pci")) {
3122 - dev_err(dev, "invalid \"device_type\" %s\n", type);
3123 - return -EINVAL;
3124 - }
3125 -
3126 of_pci_check_probe_only();
3127
3128 /* Parse and map our Configuration Space windows */
3129 --- a/drivers/pci/host/pcie-xilinx-nwl.c
3130 +++ b/drivers/pci/host/pcie-xilinx-nwl.c
3131 @@ -778,16 +778,7 @@ static int nwl_pcie_parse_dt(struct nwl_
3132 struct platform_device *pdev)
3133 {
3134 struct device *dev = pcie->dev;
3135 - struct device_node *node = dev->of_node;
3136 struct resource *res;
3137 - const char *type;
3138 -
3139 - /* Check for device type */
3140 - type = of_get_property(node, "device_type", NULL);
3141 - if (!type || strcmp(type, "pci")) {
3142 - dev_err(dev, "invalid \"device_type\" %s\n", type);
3143 - return -EINVAL;
3144 - }
3145
3146 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
3147 pcie->breg_base = devm_ioremap_resource(dev, res);
3148 --- a/drivers/pci/host/pcie-xilinx.c
3149 +++ b/drivers/pci/host/pcie-xilinx.c
3150 @@ -584,15 +584,8 @@ static int xilinx_pcie_parse_dt(struct x
3151 struct device *dev = port->dev;
3152 struct device_node *node = dev->of_node;
3153 struct resource regs;
3154 - const char *type;
3155 int err;
3156
3157 - type = of_get_property(node, "device_type", NULL);
3158 - if (!type || strcmp(type, "pci")) {
3159 - dev_err(dev, "invalid \"device_type\" %s\n", type);
3160 - return -EINVAL;
3161 - }
3162 -
3163 err = of_address_to_resource(node, 0, &regs);
3164 if (err) {
3165 dev_err(dev, "missing \"reg\" property\n");
3166 --- /dev/null
3167 +++ b/drivers/pci/mobiveil/Kconfig
3168 @@ -0,0 +1,50 @@
3169 +# SPDX-License-Identifier: GPL-2.0
3170 +
3171 +menu "Mobiveil PCIe Core Support"
3172 + depends on PCI
3173 +
3174 +config PCIE_MOBIVEIL
3175 + bool
3176 +
3177 +config PCIE_MOBIVEIL_HOST
3178 + bool
3179 + depends on PCI_MSI_IRQ_DOMAIN
3180 + select PCIE_MOBIVEIL
3181 +
3182 +config PCIE_MOBIVEIL_EP
3183 + bool
3184 + depends on PCI_ENDPOINT
3185 + select PCIE_MOBIVEIL
3186 +
3187 +config PCIE_MOBIVEIL_PLAT
3188 + bool "Mobiveil AXI PCIe controller"
3189 + depends on ARCH_ZYNQMP || COMPILE_TEST
3190 + depends on OF
3191 + select PCIE_MOBIVEIL_HOST
3192 + help
3193 + Say Y here if you want to enable support for the Mobiveil AXI PCIe
3194 + Soft IP. It has up to 8 outbound and inbound windows
3195 + for address translation and it is a PCIe Gen4 IP.
3196 +
3197 +config PCI_LAYERSCAPE_GEN4
3198 + bool "Freescale Layerscpe PCIe Gen4 controller in RC mode"
3199 + depends on PCI
3200 + depends on OF && (ARM64 || ARCH_LAYERSCAPE)
3201 + depends on PCI_MSI_IRQ_DOMAIN
3202 + select PCIE_MOBIVEIL_HOST
3203 + help
3204 + Say Y here if you want PCIe Gen4 controller support on
3205 + Layerscape SoCs. And the PCIe controller work in RC mode
3206 + by setting the RCW[HOST_AGT_PEX] to 0.
3207 +
3208 +config PCI_LAYERSCAPE_GEN4_EP
3209 + bool "Freescale Layerscpe PCIe Gen4 controller in EP mode"
3210 + depends on PCI
3211 + depends on OF && (ARM64 || ARCH_LAYERSCAPE)
3212 + depends on PCI_ENDPOINT
3213 + select PCIE_MOBIVEIL_EP
3214 + help
3215 + Say Y here if you want PCIe Gen4 controller support on
3216 + Layerscape SoCs. And the PCIe controller work in EP mode
3217 + by setting the RCW[HOST_AGT_PEX] to 1.
3218 +endmenu
3219 --- /dev/null
3220 +++ b/drivers/pci/mobiveil/Makefile
3221 @@ -0,0 +1,7 @@
3222 +# SPDX-License-Identifier: GPL-2.0
3223 +obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
3224 +obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
3225 +obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
3226 +obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
3227 +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
3228 +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4_EP) += pci-layerscape-gen4-ep.o
3229 --- /dev/null
3230 +++ b/drivers/pci/mobiveil/pci-layerscape-gen4-ep.c
3231 @@ -0,0 +1,178 @@
3232 +// SPDX-License-Identifier: GPL-2.0
3233 +/*
3234 + * PCIe controller EP driver for Freescale Layerscape SoCs
3235 + *
3236 + * Copyright (C) 2018 NXP Semiconductor.
3237 + *
3238 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
3239 + */
3240 +
3241 +#include <linux/kernel.h>
3242 +#include <linux/init.h>
3243 +#include <linux/of_pci.h>
3244 +#include <linux/of_platform.h>
3245 +#include <linux/of_address.h>
3246 +#include <linux/pci.h>
3247 +#include <linux/platform_device.h>
3248 +#include <linux/resource.h>
3249 +
3250 +#include "pcie-mobiveil.h"
3251 +
3252 +struct ls_pcie_g4_ep {
3253 + struct mobiveil_pcie *mv_pci;
3254 +};
3255 +
3256 +#define to_ls_pcie_g4_ep(x) dev_get_drvdata((x)->dev)
3257 +
3258 +static const struct of_device_id ls_pcie_g4_ep_of_match[] = {
3259 + { .compatible = "fsl,lx2160a-pcie-ep",},
3260 + { },
3261 +};
3262 +
3263 +static void ls_pcie_g4_get_bar_num(struct mobiveil_pcie_ep *ep)
3264 +{
3265 + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
3266 + u32 type, reg;
3267 + u8 bar;
3268 +
3269 + ep->bar_num = BAR_5 + 1;
3270 +
3271 + for (bar = BAR_0; bar <= BAR_5; bar++) {
3272 + reg = PCI_BASE_ADDRESS_0 + (4 * bar);
3273 + type = csr_readl(mv_pci, reg) &
3274 + PCI_BASE_ADDRESS_MEM_TYPE_MASK;
3275 + if (type & PCI_BASE_ADDRESS_MEM_TYPE_64)
3276 + ep->bar_num--;
3277 + }
3278 +}
3279 +
3280 +static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
3281 +{
3282 + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
3283 + struct pci_epc *epc = ep->epc;
3284 + enum pci_barno bar;
3285 + int win_idx, val;
3286 +
3287 + /*
3288 + * Errata: unsupported request error on inbound posted write
3289 + * transaction, PCIe controller reports advisory error instead
3290 + * of uncorrectable error message to RC.
3291 + * workaround: set the bit20(unsupported_request_Error_severity) with
3292 + * value 1 in uncorrectable_Error_Severity_Register, make the
3293 + * unsupported request error generate the fatal error.
3294 + */
3295 + val = csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
3296 + val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT;
3297 + csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
3298 +
3299 + ls_pcie_g4_get_bar_num(ep);
3300 +
3301 + for (bar = BAR_0; bar < (ep->bar_num * ep->pf_num); bar++)
3302 + mobiveil_pcie_ep_reset_bar(mv_pci, bar);
3303 +
3304 + for (win_idx = 0; win_idx < MAX_IATU_OUT; win_idx++)
3305 + mobiveil_pcie_disable_ob_win(mv_pci, win_idx);
3306 +
3307 + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
3308 + epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
3309 +}
3310 +
3311 +static int ls_pcie_g4_ep_raise_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
3312 + enum pci_epc_irq_type type,
3313 + u16 interrupt_num)
3314 +{
3315 + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
3316 +
3317 + switch (type) {
3318 + case PCI_EPC_IRQ_LEGACY:
3319 + return mobiveil_pcie_ep_raise_legacy_irq(ep, func_no);
3320 + case PCI_EPC_IRQ_MSI:
3321 + return mobiveil_pcie_ep_raise_msi_irq(ep, func_no,
3322 + interrupt_num);
3323 + case PCI_EPC_IRQ_MSIX:
3324 + return mobiveil_pcie_ep_raise_msix_irq(ep, func_no,
3325 + interrupt_num);
3326 + default:
3327 + dev_err(&mv_pci->pdev->dev, "UNKNOWN IRQ type\n");
3328 + }
3329 +
3330 + return 0;
3331 +}
3332 +
3333 +static struct mobiveil_pcie_ep_ops pcie_ep_ops = {
3334 + .ep_init = ls_pcie_g4_ep_init,
3335 + .raise_irq = ls_pcie_g4_ep_raise_irq,
3336 +};
3337 +
3338 +static int __init ls_pcie_gen4_add_pcie_ep(struct ls_pcie_g4_ep *ls_pcie_g4_ep,
3339 + struct platform_device *pdev)
3340 +{
3341 + struct mobiveil_pcie *mv_pci = ls_pcie_g4_ep->mv_pci;
3342 + struct device *dev = &pdev->dev;
3343 + struct mobiveil_pcie_ep *ep;
3344 + struct resource *res;
3345 + int ret;
3346 + struct device_node *np = dev->of_node;
3347 +
3348 + ep = &mv_pci->ep;
3349 + ep->ops = &pcie_ep_ops;
3350 +
3351 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
3352 + if (!res)
3353 + return -EINVAL;
3354 +
3355 + ep->phys_base = res->start;
3356 + ep->addr_size = resource_size(res);
3357 +
3358 + ret = of_property_read_u32(np, "max-functions", &ep->pf_num);
3359 + if (ret < 0)
3360 + ep->pf_num = 1;
3361 +
3362 + ret = mobiveil_pcie_ep_init(ep);
3363 + if (ret) {
3364 + dev_err(dev, "failed to initialize endpoint\n");
3365 + return ret;
3366 + }
3367 +
3368 + return 0;
3369 +}
3370 +
3371 +static int __init ls_pcie_g4_ep_probe(struct platform_device *pdev)
3372 +{
3373 + struct device *dev = &pdev->dev;
3374 + struct mobiveil_pcie *mv_pci;
3375 + struct ls_pcie_g4_ep *ls_pcie_g4_ep;
3376 + struct resource *res;
3377 + int ret;
3378 +
3379 + ls_pcie_g4_ep = devm_kzalloc(dev, sizeof(*ls_pcie_g4_ep), GFP_KERNEL);
3380 + if (!ls_pcie_g4_ep)
3381 + return -ENOMEM;
3382 +
3383 + mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
3384 + if (!mv_pci)
3385 + return -ENOMEM;
3386 +
3387 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3388 + mv_pci->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
3389 + if (IS_ERR(mv_pci->csr_axi_slave_base))
3390 + return PTR_ERR(mv_pci->csr_axi_slave_base);
3391 +
3392 + mv_pci->pdev = pdev;
3393 + ls_pcie_g4_ep->mv_pci = mv_pci;
3394 +
3395 + platform_set_drvdata(pdev, ls_pcie_g4_ep);
3396 +
3397 + ret = ls_pcie_gen4_add_pcie_ep(ls_pcie_g4_ep, pdev);
3398 +
3399 + return ret;
3400 +}
3401 +
3402 +static struct platform_driver ls_pcie_g4_ep_driver = {
3403 + .driver = {
3404 + .name = "layerscape-pcie-gen4-ep",
3405 + .of_match_table = ls_pcie_g4_ep_of_match,
3406 + .suppress_bind_attrs = true,
3407 + },
3408 +};
3409 +builtin_platform_driver_probe(ls_pcie_g4_ep_driver, ls_pcie_g4_ep_probe);
3410 --- /dev/null
3411 +++ b/drivers/pci/mobiveil/pci-layerscape-gen4.c
3412 @@ -0,0 +1,292 @@
3413 +// SPDX-License-Identifier: GPL-2.0
3414 +/*
3415 + * PCIe host controller driver for NXP Layerscape SoCs
3416 + *
3417 + * Copyright 2018 NXP
3418 + *
3419 + * Author: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
3420 + */
3421 +
3422 +#include <linux/kernel.h>
3423 +#include <linux/interrupt.h>
3424 +#include <linux/init.h>
3425 +#include <linux/of_pci.h>
3426 +#include <linux/of_platform.h>
3427 +#include <linux/of_irq.h>
3428 +#include <linux/of_address.h>
3429 +#include <linux/pci.h>
3430 +#include <linux/platform_device.h>
3431 +#include <linux/resource.h>
3432 +#include <linux/mfd/syscon.h>
3433 +#include <linux/regmap.h>
3434 +
3435 +#include "pcie-mobiveil.h"
3436 +
3437 +/* LUT and PF control registers */
3438 +#define PCIE_LUT_OFF (0x80000)
3439 +#define PCIE_LUT_GCR (0x28)
3440 +#define PCIE_LUT_GCR_RRE (0)
3441 +
3442 +#define PCIE_PF_OFF (0xc0000)
3443 +#define PCIE_PF_INT_STAT (0x18)
3444 +#define PF_INT_STAT_PABRST (31)
3445 +
3446 +#define PCIE_PF_DBG (0x7fc)
3447 +#define PF_DBG_LTSSM_MASK (0x3f)
3448 +#define PF_DBG_WE (31)
3449 +#define PF_DBG_PABR (27)
3450 +
3451 +#define LS_PCIE_G4_LTSSM_L0 0x2d /* L0 state */
3452 +
3453 +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev)
3454 +
3455 +struct ls_pcie_g4 {
3456 + struct mobiveil_pcie *pci;
3457 + struct delayed_work dwork;
3458 + int irq;
3459 +};
3460 +
3461 +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
3462 +{
3463 + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
3464 +}
3465 +
3466 +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie,
3467 + u32 off, u32 val)
3468 +{
3469 + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
3470 +}
3471 +
3472 +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off)
3473 +{
3474 + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
3475 +}
3476 +
3477 +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie,
3478 + u32 off, u32 val)
3479 +{
3480 + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
3481 +}
3482 +
3483 +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
3484 +{
3485 + struct mobiveil_pcie *mv_pci = pcie->pci;
3486 + u32 header_type;
3487 +
3488 + header_type = csr_readb(mv_pci, PCI_HEADER_TYPE);
3489 + header_type &= 0x7f;
3490 +
3491 + return header_type == PCI_HEADER_TYPE_BRIDGE;
3492 +}
3493 +
3494 +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci)
3495 +{
3496 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
3497 + u32 state;
3498 +
3499 + state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3500 + state = state & PF_DBG_LTSSM_MASK;
3501 +
3502 + if (state == LS_PCIE_G4_LTSSM_L0)
3503 + return 1;
3504 +
3505 + return 0;
3506 +}
3507 +
3508 +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie)
3509 +{
3510 + struct mobiveil_pcie *mv_pci = pcie->pci;
3511 + u32 val, act_stat;
3512 + int to = 100;
3513 +
3514 + /* Poll for pab_csb_reset to set and PAB activity to clear */
3515 + do {
3516 + usleep_range(10, 15);
3517 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT);
3518 + act_stat = csr_readl(mv_pci, PAB_ACTIVITY_STAT);
3519 + } while (((val & 1 << PF_INT_STAT_PABRST) == 0 || act_stat) && to--);
3520 + if (to < 0) {
3521 + dev_err(&mv_pci->pdev->dev, "poll PABRST&PABACT timeout\n");
3522 + return;
3523 + }
3524 +
3525 + /* clear PEX_RESET bit in PEX_PF0_DBG register */
3526 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3527 + val |= 1 << PF_DBG_WE;
3528 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
3529 +
3530 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3531 + val |= 1 << PF_DBG_PABR;
3532 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
3533 +
3534 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3535 + val &= ~(1 << PF_DBG_WE);
3536 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
3537 +
3538 + mobiveil_host_init(mv_pci, true);
3539 +
3540 + to = 100;
3541 + while (!ls_pcie_g4_link_up(mv_pci) && to--)
3542 + usleep_range(200, 250);
3543 + if (to < 0)
3544 + dev_err(&mv_pci->pdev->dev, "PCIe link trainning timeout\n");
3545 +}
3546 +
3547 +static irqreturn_t ls_pcie_g4_handler(int irq, void *dev_id)
3548 +{
3549 + struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id;
3550 + struct mobiveil_pcie *mv_pci = pcie->pci;
3551 + u32 val;
3552 +
3553 + val = csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT);
3554 + if (!val)
3555 + return IRQ_NONE;
3556 +
3557 + if (val & PAB_INTP_RESET)
3558 + schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1));
3559 +
3560 + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT);
3561 +
3562 + return IRQ_HANDLED;
3563 +}
3564 +
3565 +static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci)
3566 +{
3567 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci);
3568 + u32 val;
3569 + int ret;
3570 +
3571 + pcie->irq = platform_get_irq_byname(mv_pci->pdev, "intr");
3572 + if (pcie->irq < 0) {
3573 + dev_err(&mv_pci->pdev->dev, "Can't get 'intr' irq.\n");
3574 + return pcie->irq;
3575 + }
3576 + ret = devm_request_irq(&mv_pci->pdev->dev, pcie->irq,
3577 + ls_pcie_g4_handler, IRQF_SHARED,
3578 + mv_pci->pdev->name, pcie);
3579 + if (ret) {
3580 + dev_err(&mv_pci->pdev->dev, "Can't register PCIe IRQ.\n");
3581 + return ret;
3582 + }
3583 +
3584 + /* Enable interrupts */
3585 + val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET |
3586 + PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC;
3587 + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB);
3588 +
3589 + return 0;
3590 +}
3591 +
3592 +static void ls_pcie_g4_reset(struct work_struct *work)
3593 +{
3594 + struct delayed_work *dwork = container_of(work, struct delayed_work,
3595 + work);
3596 + struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork);
3597 + struct mobiveil_pcie *mv_pci = pcie->pci;
3598 + u16 ctrl;
3599 +
3600 + ctrl = csr_readw(mv_pci, PCI_BRIDGE_CONTROL);
3601 + ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3602 + csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL);
3603 + ls_pcie_g4_reinit_hw(pcie);
3604 +}
3605 +
3606 +static int ls_pcie_g4_read_other_conf(struct pci_bus *bus, unsigned int devfn,
3607 + int where, int size, u32 *val)
3608 +{
3609 + struct mobiveil_pcie *pci = bus->sysdata;
3610 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
3611 + int ret;
3612 +
3613 + if (where == PCI_VENDOR_ID)
3614 + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
3615 + 0 << PCIE_LUT_GCR_RRE);
3616 +
3617 + ret = pci_generic_config_read(bus, devfn, where, size, val);
3618 +
3619 + if (where == PCI_VENDOR_ID)
3620 + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
3621 + 1 << PCIE_LUT_GCR_RRE);
3622 +
3623 + return ret;
3624 +}
3625 +
3626 +static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = {
3627 + .interrupt_init = ls_pcie_g4_interrupt_init,
3628 + .read_other_conf = ls_pcie_g4_read_other_conf,
3629 +};
3630 +
3631 +static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = {
3632 + .link_up = ls_pcie_g4_link_up,
3633 +};
3634 +
3635 +static void workaround_tkt381274(struct ls_pcie_g4 *pcie)
3636 +{
3637 + struct mobiveil_pcie *mv_pci = pcie->pci;
3638 + u32 val;
3639 +
3640 + /* Set ACK latency timeout */
3641 + val = csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
3642 + val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
3643 + val |= (4 << ACK_LAT_TO_VAL_SHIFT);
3644 + csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
3645 +}
3646 +
3647 +static int __init ls_pcie_g4_probe(struct platform_device *pdev)
3648 +{
3649 + struct device *dev = &pdev->dev;
3650 + struct mobiveil_pcie *mv_pci;
3651 + struct ls_pcie_g4 *pcie;
3652 + struct device_node *np = dev->of_node;
3653 + int ret;
3654 +
3655 + if (!of_parse_phandle(np, "msi-parent", 0)) {
3656 + dev_err(dev, "failed to find msi-parent\n");
3657 + return -EINVAL;
3658 + }
3659 +
3660 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
3661 + if (!pcie)
3662 + return -ENOMEM;
3663 +
3664 + mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
3665 + if (!mv_pci)
3666 + return -ENOMEM;
3667 +
3668 + mv_pci->pdev = pdev;
3669 + mv_pci->ops = &ls_pcie_g4_pab_ops;
3670 + mv_pci->rp.ops = &ls_pcie_g4_rp_ops;
3671 + pcie->pci = mv_pci;
3672 +
3673 + platform_set_drvdata(pdev, pcie);
3674 +
3675 + INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset);
3676 +
3677 + ret = mobiveil_pcie_host_probe(mv_pci);
3678 + if (ret) {
3679 + dev_err(dev, "fail to probe!\n");
3680 + return ret;
3681 + }
3682 +
3683 + if (!ls_pcie_g4_is_bridge(pcie))
3684 + return -ENODEV;
3685 +
3686 + workaround_tkt381274(pcie);
3687 +
3688 + return 0;
3689 +}
3690 +
3691 +static const struct of_device_id ls_pcie_g4_of_match[] = {
3692 + { .compatible = "fsl,lx2160a-pcie", },
3693 + { },
3694 +};
3695 +
3696 +static struct platform_driver ls_pcie_g4_driver = {
3697 + .driver = {
3698 + .name = "layerscape-pcie-gen4",
3699 + .of_match_table = ls_pcie_g4_of_match,
3700 + .suppress_bind_attrs = true,
3701 + },
3702 +};
3703 +
3704 +builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe);
3705 --- /dev/null
3706 +++ b/drivers/pci/mobiveil/pcie-mobiveil-ep.c
3707 @@ -0,0 +1,512 @@
3708 +// SPDX-License-Identifier: GPL-2.0
3709 +/**
3710 + * Mobiveil PCIe Endpoint controller driver
3711 + *
3712 + * Copyright (C) 2018 NXP Semiconductor.
3713 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
3714 + */
3715 +
3716 +#include <linux/of.h>
3717 +#include <linux/pci-epc.h>
3718 +#include <linux/pci-epf.h>
3719 +#include <linux/platform_device.h>
3720 +#include "pcie-mobiveil.h"
3721 +
3722 +void mobiveil_pcie_ep_linkup(struct mobiveil_pcie_ep *ep)
3723 +{
3724 + struct pci_epc *epc = ep->epc;
3725 +
3726 + pci_epc_linkup(epc);
3727 +}
3728 +
3729 +static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
3730 + enum pci_barno bar)
3731 +{
3732 + csr_writel(pcie, bar, GPEX_BAR_SELECT);
3733 + csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
3734 + csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
3735 +}
3736 +
3737 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
3738 + enum pci_barno bar)
3739 +{
3740 + __mobiveil_pcie_ep_reset_bar(pcie, bar);
3741 +}
3742 +
3743 +static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
3744 + u8 cap_ptr, u8 cap)
3745 +{
3746 + u8 cap_id, next_cap_ptr;
3747 + u16 reg;
3748 +
3749 + reg = csr_readw(pcie, cap_ptr);
3750 + next_cap_ptr = (reg & 0xff00) >> 8;
3751 + cap_id = (reg & 0x00ff);
3752 +
3753 + if (cap_id == cap)
3754 + return cap_ptr;
3755 +
3756 + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
3757 + return 0;
3758 +
3759 + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
3760 +}
3761 +
3762 +static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie *pcie,
3763 + u8 cap)
3764 +{
3765 + u8 next_cap_ptr;
3766 + u16 reg;
3767 +
3768 + reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
3769 + next_cap_ptr = (reg & 0x00ff);
3770 +
3771 + if (!next_cap_ptr)
3772 + return 0;
3773 +
3774 + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
3775 +}
3776 +
3777 +static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
3778 + struct pci_epf_header *hdr)
3779 +{
3780 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3781 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3782 +
3783 + csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
3784 + csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
3785 + csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
3786 + csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
3787 + csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
3788 + PCI_CLASS_DEVICE);
3789 + csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
3790 + csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
3791 + csr_writew(pcie, hdr->subsys_id, PCI_SUBSYSTEM_ID);
3792 + csr_writeb(pcie, hdr->interrupt_pin, PCI_INTERRUPT_PIN);
3793 +
3794 + return 0;
3795 +}
3796 +
3797 +static int mobiveil_pcie_ep_inbound_atu(struct mobiveil_pcie_ep *ep,
3798 + u8 func_no, enum pci_barno bar,
3799 + dma_addr_t cpu_addr)
3800 +{
3801 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3802 +
3803 + program_ib_windows_ep(pcie, func_no, bar, cpu_addr);
3804 +
3805 + return 0;
3806 +}
3807 +
3808 +static int mobiveil_pcie_ep_outbound_atu(struct mobiveil_pcie_ep *ep,
3809 + phys_addr_t phys_addr,
3810 + u64 pci_addr, u8 func_no,
3811 + size_t size)
3812 +{
3813 + int ret;
3814 + u32 free_win;
3815 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3816 +
3817 + free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
3818 + if (free_win >= ep->num_ob_windows) {
3819 + dev_err(&pcie->pdev->dev, "No free outbound window\n");
3820 + return -EINVAL;
3821 + }
3822 +
3823 + ret = program_ob_windows_ep(pcie, free_win, MEM_WINDOW_TYPE,
3824 + phys_addr, pci_addr, func_no, size);
3825 + if (ret < 0) {
3826 + dev_err(&pcie->pdev->dev, "Failed to program IB window\n");
3827 + return ret;
3828 + }
3829 +
3830 + set_bit(free_win, ep->ob_window_map);
3831 + ep->outbound_addr[free_win] = phys_addr;
3832 +
3833 + return 0;
3834 +}
3835 +
3836 +static void mobiveil_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
3837 + struct pci_epf_bar *epf_bar)
3838 +{
3839 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3840 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3841 + enum pci_barno bar = epf_bar->barno;
3842 +
3843 + if (bar < ep->bar_num) {
3844 + __mobiveil_pcie_ep_reset_bar(pcie,
3845 + func_no * ep->bar_num + bar);
3846 +
3847 + mobiveil_pcie_disable_ib_win_ep(pcie, func_no, bar);
3848 + }
3849 +}
3850 +
3851 +static int mobiveil_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
3852 + struct pci_epf_bar *epf_bar)
3853 +{
3854 + int ret;
3855 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3856 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3857 + enum pci_barno bar = epf_bar->barno;
3858 + size_t size = epf_bar->size;
3859 +
3860 + if (bar < ep->bar_num) {
3861 + ret = mobiveil_pcie_ep_inbound_atu(ep, func_no, bar,
3862 + epf_bar->phys_addr);
3863 + if (ret)
3864 + return ret;
3865 +
3866 + csr_writel(pcie, func_no * ep->bar_num + bar,
3867 + GPEX_BAR_SELECT);
3868 + csr_writel(pcie, lower_32_bits(~(size - 1)),
3869 + GPEX_BAR_SIZE_LDW);
3870 + csr_writel(pcie, upper_32_bits(~(size - 1)),
3871 + GPEX_BAR_SIZE_UDW);
3872 + }
3873 +
3874 + return 0;
3875 +}
3876 +
3877 +static int mobiveil_pcie_find_index(struct mobiveil_pcie_ep *ep,
3878 + phys_addr_t addr,
3879 + u32 *atu_index)
3880 +{
3881 + u32 index;
3882 +
3883 + for (index = 0; index < ep->num_ob_windows; index++) {
3884 + if (ep->outbound_addr[index] != addr)
3885 + continue;
3886 + *atu_index = index;
3887 + return 0;
3888 + }
3889 +
3890 + return -EINVAL;
3891 +}
3892 +
3893 +static void mobiveil_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
3894 + phys_addr_t addr)
3895 +{
3896 + int ret;
3897 + u32 atu_index;
3898 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3899 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3900 +
3901 + ret = mobiveil_pcie_find_index(ep, addr, &atu_index);
3902 + if (ret < 0)
3903 + return;
3904 +
3905 + mobiveil_pcie_disable_ob_win(pcie, atu_index);
3906 + clear_bit(atu_index, ep->ob_window_map);
3907 +}
3908 +
3909 +static int mobiveil_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
3910 + phys_addr_t addr,
3911 + u64 pci_addr, size_t size)
3912 +{
3913 + int ret;
3914 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3915 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3916 +
3917 + ret = mobiveil_pcie_ep_outbound_atu(ep, addr, pci_addr, func_no, size);
3918 + if (ret) {
3919 + dev_err(&pcie->pdev->dev, "Failed to enable address\n");
3920 + return ret;
3921 + }
3922 +
3923 + return 0;
3924 +}
3925 +
3926 +static int mobiveil_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
3927 +{
3928 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3929 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3930 + u32 val, reg;
3931 +
3932 + if (!ep->msi_cap)
3933 + return -EINVAL;
3934 +
3935 + reg = ep->msi_cap + PCI_MSI_FLAGS;
3936 + val = csr_readw(pcie, reg);
3937 + if (!(val & PCI_MSI_FLAGS_ENABLE))
3938 + return -EINVAL;
3939 +
3940 + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
3941 +
3942 + return val;
3943 +}
3944 +
3945 +static int mobiveil_pcie_ep_set_msi(struct pci_epc *epc,
3946 + u8 func_no, u8 interrupts)
3947 +{
3948 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3949 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3950 + u32 val, reg;
3951 +
3952 + if (!ep->msi_cap)
3953 + return -EINVAL;
3954 +
3955 + reg = ep->msi_cap + PCI_MSI_FLAGS;
3956 + val = csr_readw(pcie, reg);
3957 + val &= ~PCI_MSI_FLAGS_QMASK;
3958 + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
3959 + csr_writew(pcie, val, reg);
3960 +
3961 + return 0;
3962 +}
3963 +
3964 +static int mobiveil_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
3965 +{
3966 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3967 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3968 + u32 val, reg;
3969 +
3970 + if (!ep->msix_cap)
3971 + return -EINVAL;
3972 +
3973 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
3974 + val = csr_readw(pcie, reg);
3975 + if (!(val & PCI_MSIX_FLAGS_ENABLE))
3976 + return -EINVAL;
3977 +
3978 + val &= PCI_MSIX_FLAGS_QSIZE;
3979 +
3980 + return val;
3981 +}
3982 +
3983 +static int mobiveil_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no,
3984 + u16 interrupts)
3985 +{
3986 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3987 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3988 + u32 val, reg;
3989 +
3990 + if (!ep->msix_cap)
3991 + return -EINVAL;
3992 +
3993 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
3994 + val = csr_readw(pcie, reg);
3995 + val &= ~PCI_MSIX_FLAGS_QSIZE;
3996 + val |= interrupts;
3997 + csr_writew(pcie, val, reg);
3998 +
3999 + return 0;
4000 +}
4001 +
4002 +static int mobiveil_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
4003 + enum pci_epc_irq_type type,
4004 + u16 interrupt_num)
4005 +{
4006 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
4007 +
4008 + if (!ep->ops->raise_irq)
4009 + return -EINVAL;
4010 +
4011 + return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
4012 +}
4013 +
4014 +static const struct pci_epc_ops epc_ops = {
4015 + .write_header = mobiveil_pcie_ep_write_header,
4016 + .set_bar = mobiveil_pcie_ep_set_bar,
4017 + .clear_bar = mobiveil_pcie_ep_clear_bar,
4018 + .map_addr = mobiveil_pcie_ep_map_addr,
4019 + .unmap_addr = mobiveil_pcie_ep_unmap_addr,
4020 + .set_msi = mobiveil_pcie_ep_set_msi,
4021 + .get_msi = mobiveil_pcie_ep_get_msi,
4022 + .set_msix = mobiveil_pcie_ep_set_msix,
4023 + .get_msix = mobiveil_pcie_ep_get_msix,
4024 + .raise_irq = mobiveil_pcie_ep_raise_irq,
4025 +};
4026 +
4027 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no)
4028 +{
4029 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4030 +
4031 + dev_err(&pcie->pdev->dev, "EP cannot trigger legacy IRQs\n");
4032 +
4033 + return -EINVAL;
4034 +}
4035 +
4036 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
4037 + u8 interrupt_num)
4038 +{
4039 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4040 + struct pci_epc *epc = ep->epc;
4041 + u16 msg_ctrl, msg_data;
4042 + u32 msg_addr_lower, msg_addr_upper, reg;
4043 + u64 msg_addr;
4044 + u32 func_num;
4045 + bool has_upper;
4046 + int ret;
4047 +
4048 + if (!ep->msi_cap)
4049 + return -EINVAL;
4050 +
4051 + func_num = csr_readl(pcie, PAB_CTRL);
4052 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4053 + func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
4054 + csr_writel(pcie, func_num, PAB_CTRL);
4055 +
4056 + /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
4057 + reg = ep->msi_cap + PCI_MSI_FLAGS;
4058 + msg_ctrl = csr_readw(pcie, reg);
4059 + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
4060 + reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
4061 + msg_addr_lower = csr_readl(pcie, reg);
4062 + if (has_upper) {
4063 + reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
4064 + msg_addr_upper = csr_readl(pcie, reg);
4065 + reg = ep->msi_cap + PCI_MSI_DATA_64;
4066 + msg_data = csr_readw(pcie, reg);
4067 + } else {
4068 + msg_addr_upper = 0;
4069 + reg = ep->msi_cap + PCI_MSI_DATA_32;
4070 + msg_data = csr_readw(pcie, reg);
4071 + }
4072 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
4073 +
4074 + func_num = csr_readl(pcie, PAB_CTRL);
4075 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4076 + csr_writel(pcie, func_num, PAB_CTRL);
4077 +
4078 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
4079 + msg_addr, epc->mem->page_size);
4080 + if (ret)
4081 + return ret;
4082 +
4083 + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
4084 +
4085 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
4086 +
4087 + return 0;
4088 +}
4089 +
4090 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
4091 + u16 interrupt_num)
4092 +{
4093 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4094 + struct pci_epc *epc = ep->epc;
4095 + u32 msg_addr_upper, msg_addr_lower;
4096 + u32 msg_data;
4097 + u64 msg_addr;
4098 + u32 func_num;
4099 + int ret;
4100 +
4101 + func_num = csr_readl(pcie, PAB_CTRL);
4102 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4103 + func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
4104 + csr_writel(pcie, func_num, PAB_CTRL);
4105 +
4106 + msg_addr_lower = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
4107 + PCI_MSIX_ENTRY_LOWER_ADDR +
4108 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
4109 + msg_addr_upper = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
4110 + PCI_MSIX_ENTRY_UPPER_ADDR +
4111 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
4112 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
4113 + msg_data = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
4114 + PCI_MSIX_ENTRY_DATA +
4115 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
4116 +
4117 + func_num = csr_readl(pcie, PAB_CTRL);
4118 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4119 + csr_writel(pcie, func_num, PAB_CTRL);
4120 +
4121 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
4122 + msg_addr, epc->mem->page_size);
4123 + if (ret)
4124 + return ret;
4125 +
4126 + writel(msg_data, ep->msi_mem);
4127 +
4128 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
4129 +
4130 + return 0;
4131 +}
4132 +
4133 +void mobiveil_pcie_ep_exit(struct mobiveil_pcie_ep *ep)
4134 +{
4135 + struct pci_epc *epc = ep->epc;
4136 +
4137 + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
4138 + epc->mem->page_size);
4139 +
4140 + pci_epc_mem_exit(epc);
4141 +}
4142 +
4143 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep)
4144 +{
4145 + int ret;
4146 + void *addr;
4147 + struct pci_epc *epc;
4148 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4149 + struct device *dev = &pcie->pdev->dev;
4150 + struct device_node *np = dev->of_node;
4151 +
4152 + if (!pcie->csr_axi_slave_base) {
4153 + dev_err(dev, "csr_base is not populated\n");
4154 + return -EINVAL;
4155 + }
4156 +
4157 + ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
4158 + if (ret < 0) {
4159 + dev_err(dev, "Unable to read *num-ob-windows* property\n");
4160 + return ret;
4161 + }
4162 +
4163 + if (ep->num_ob_windows > MAX_IATU_OUT) {
4164 + dev_err(dev, "Invalid *num-ob-windows*\n");
4165 + return -EINVAL;
4166 + }
4167 + ep->ob_window_map = devm_kcalloc(dev,
4168 + BITS_TO_LONGS(ep->num_ob_windows),
4169 + sizeof(long),
4170 + GFP_KERNEL);
4171 + if (!ep->ob_window_map)
4172 + return -ENOMEM;
4173 +
4174 + addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t),
4175 + GFP_KERNEL);
4176 + if (!addr)
4177 + return -ENOMEM;
4178 + ep->outbound_addr = addr;
4179 +
4180 + mobiveil_pcie_enable_bridge_pio(pcie);
4181 + mobiveil_pcie_enable_engine_apio(pcie);
4182 + mobiveil_pcie_enable_engine_ppio(pcie);
4183 + mobiveil_pcie_enable_msi_ep(pcie);
4184 +
4185 + epc = devm_pci_epc_create(dev, &epc_ops);
4186 + if (IS_ERR(epc)) {
4187 + dev_err(dev, "Failed to create epc device\n");
4188 + return PTR_ERR(epc);
4189 + }
4190 +
4191 + ep->epc = epc;
4192 + epc_set_drvdata(epc, ep);
4193 +
4194 + ep->msi_cap = mobiveil_pcie_ep_find_capability(pcie, PCI_CAP_ID_MSI);
4195 +
4196 + ep->msix_cap = mobiveil_pcie_ep_find_capability(pcie,
4197 + PCI_CAP_ID_MSIX);
4198 +
4199 + if (ep->ops->ep_init)
4200 + ep->ops->ep_init(ep);
4201 +
4202 + epc->max_functions = ep->pf_num;
4203 +
4204 + ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
4205 + ep->page_size);
4206 + if (ret < 0) {
4207 + dev_err(dev, "Failed to initialize address space\n");
4208 + return ret;
4209 + }
4210 +
4211 + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
4212 + epc->mem->page_size);
4213 + if (!ep->msi_mem) {
4214 + dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
4215 + return -ENOMEM;
4216 + }
4217 +
4218 + return 0;
4219 +}
4220 --- /dev/null
4221 +++ b/drivers/pci/mobiveil/pcie-mobiveil-host.c
4222 @@ -0,0 +1,640 @@
4223 +// SPDX-License-Identifier: GPL-2.0
4224 +/*
4225 + * PCIe host controller driver for Mobiveil PCIe Host controller
4226 + *
4227 + * Copyright (c) 2018 Mobiveil Inc.
4228 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
4229 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
4230 + */
4231 +
4232 +#include <linux/init.h>
4233 +#include <linux/interrupt.h>
4234 +#include <linux/irq.h>
4235 +#include <linux/irqchip/chained_irq.h>
4236 +#include <linux/irqdomain.h>
4237 +#include <linux/kernel.h>
4238 +#include <linux/module.h>
4239 +#include <linux/msi.h>
4240 +#include <linux/of_address.h>
4241 +#include <linux/of_irq.h>
4242 +#include <linux/of_platform.h>
4243 +#include <linux/of_pci.h>
4244 +#include <linux/pci.h>
4245 +#include <linux/platform_device.h>
4246 +#include <linux/slab.h>
4247 +
4248 +#include "pcie-mobiveil.h"
4249 +
4250 +static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
4251 +{
4252 + struct mobiveil_pcie *pcie = bus->sysdata;
4253 +
4254 + /* If there is no link, then there is no device */
4255 + if (bus->number > pcie->rp.root_bus_nr && !mobiveil_pcie_link_up(pcie))
4256 + return false;
4257 +
4258 + /* Only one device down on each root port */
4259 + if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
4260 + return false;
4261 +
4262 + /*
4263 + * Do not read more than one device on the bus directly
4264 + * attached to RC
4265 + */
4266 + if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))
4267 + return false;
4268 +
4269 + return true;
4270 +}
4271 +
4272 +/*
4273 + * mobiveil_pcie_map_bus - routine to get the configuration base of either
4274 + * root port or endpoint
4275 + */
4276 +static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
4277 + unsigned int devfn, int where)
4278 +{
4279 + struct mobiveil_pcie *pcie = bus->sysdata;
4280 + u32 value;
4281 +
4282 + if (!mobiveil_pcie_valid_device(bus, devfn))
4283 + return NULL;
4284 +
4285 + /* RC config access */
4286 + if (bus->number == pcie->rp.root_bus_nr)
4287 + return pcie->csr_axi_slave_base + where;
4288 +
4289 + /*
4290 + * EP config access (in Config/APIO space)
4291 + * Program PEX Address base (31..16 bits) with appropriate value
4292 + * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
4293 + * Relies on pci_lock serialization
4294 + */
4295 + value = bus->number << PAB_BUS_SHIFT |
4296 + PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
4297 + PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
4298 +
4299 + csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
4300 +
4301 + return pcie->rp.config_axi_slave_base + where;
4302 +}
4303 +
4304 +static int mobiveil_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
4305 + int where, int size, u32 *val)
4306 +{
4307 + struct mobiveil_pcie *pcie = bus->sysdata;
4308 + struct root_port *rp = &pcie->rp;
4309 +
4310 + if (bus->number > rp->root_bus_nr && rp->ops->read_other_conf)
4311 + return rp->ops->read_other_conf(bus, devfn, where, size, val);
4312 +
4313 + return pci_generic_config_read(bus, devfn, where, size, val);
4314 +}
4315 +static struct pci_ops mobiveil_pcie_ops = {
4316 + .map_bus = mobiveil_pcie_map_bus,
4317 + .read = mobiveil_pcie_config_read,
4318 + .write = pci_generic_config_write,
4319 +};
4320 +
4321 +static void mobiveil_pcie_isr(struct irq_desc *desc)
4322 +{
4323 + struct irq_chip *chip = irq_desc_get_chip(desc);
4324 + struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
4325 + struct device *dev = &pcie->pdev->dev;
4326 + struct mobiveil_msi *msi = &pcie->rp.msi;
4327 + u32 msi_data, msi_addr_lo, msi_addr_hi;
4328 + u32 intr_status, msi_status;
4329 + unsigned long shifted_status;
4330 + u32 bit, virq, val, mask;
4331 +
4332 + /*
4333 + * The core provides a single interrupt for both INTx/MSI messages.
4334 + * So we'll read both INTx and MSI status
4335 + */
4336 +
4337 + chained_irq_enter(chip, desc);
4338 +
4339 + /* read INTx status */
4340 + val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
4341 + mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
4342 + intr_status = val & mask;
4343 +
4344 + /* Handle INTx */
4345 + if (intr_status & PAB_INTP_INTX_MASK) {
4346 + shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
4347 + shifted_status &= PAB_INTP_INTX_MASK;
4348 + shifted_status >>= PAB_INTX_START;
4349 + do {
4350 + for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
4351 + virq = irq_find_mapping(pcie->rp.intx_domain,
4352 + bit + 1);
4353 + if (virq)
4354 + generic_handle_irq(virq);
4355 + else
4356 + dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
4357 + bit);
4358 +
4359 + /* clear interrupt handled */
4360 + csr_writel(pcie, 1 << (PAB_INTX_START + bit),
4361 + PAB_INTP_AMBA_MISC_STAT);
4362 + }
4363 +
4364 + shifted_status = csr_readl(pcie,
4365 + PAB_INTP_AMBA_MISC_STAT);
4366 + shifted_status &= PAB_INTP_INTX_MASK;
4367 + shifted_status >>= PAB_INTX_START;
4368 + } while (shifted_status != 0);
4369 + }
4370 +
4371 + /* read extra MSI status register */
4372 + msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
4373 +
4374 + /* handle MSI interrupts */
4375 + while (msi_status & 1) {
4376 + msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
4377 +
4378 + /*
4379 + * MSI_STATUS_OFFSET register gets updated to zero
4380 + * once we pop not only the MSI data but also address
4381 + * from MSI hardware FIFO. So keeping these following
4382 + * two dummy reads.
4383 + */
4384 + msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
4385 + MSI_ADDR_L_OFFSET);
4386 + msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
4387 + MSI_ADDR_H_OFFSET);
4388 + dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
4389 + msi_data, msi_addr_hi, msi_addr_lo);
4390 +
4391 + virq = irq_find_mapping(msi->dev_domain, msi_data);
4392 + if (virq)
4393 + generic_handle_irq(virq);
4394 +
4395 + msi_status = readl_relaxed(pcie->apb_csr_base +
4396 + MSI_STATUS_OFFSET);
4397 + }
4398 +
4399 + /* Clear the interrupt status */
4400 + csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
4401 + chained_irq_exit(chip, desc);
4402 +}
4403 +
4404 +static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
4405 +{
4406 + struct device *dev = &pcie->pdev->dev;
4407 + struct platform_device *pdev = pcie->pdev;
4408 + struct device_node *node = dev->of_node;
4409 + struct resource *res;
4410 +
4411 + /* map config resource */
4412 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4413 + "config_axi_slave");
4414 + pcie->rp.config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
4415 + if (IS_ERR(pcie->rp.config_axi_slave_base))
4416 + return PTR_ERR(pcie->rp.config_axi_slave_base);
4417 + pcie->rp.ob_io_res = res;
4418 +
4419 + /* map csr resource */
4420 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4421 + "csr_axi_slave");
4422 + pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
4423 + if (IS_ERR(pcie->csr_axi_slave_base))
4424 + return PTR_ERR(pcie->csr_axi_slave_base);
4425 + pcie->pcie_reg_base = res->start;
4426 +
4427 + /* read the number of windows requested */
4428 + if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
4429 + pcie->apio_wins = MAX_PIO_WINDOWS;
4430 +
4431 + if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
4432 + pcie->ppio_wins = MAX_PIO_WINDOWS;
4433 +
4434 + return 0;
4435 +}
4436 +
4437 +static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
4438 +{
4439 + phys_addr_t msg_addr = pcie->pcie_reg_base;
4440 + struct mobiveil_msi *msi = &pcie->rp.msi;
4441 +
4442 + msi->num_of_vectors = PCI_NUM_MSI;
4443 + msi->msi_pages_phys = (phys_addr_t)msg_addr;
4444 +
4445 + writel_relaxed(lower_32_bits(msg_addr),
4446 + pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
4447 + writel_relaxed(upper_32_bits(msg_addr),
4448 + pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
4449 + writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
4450 + writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
4451 +}
4452 +
4453 +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
4454 +{
4455 + u32 value, pab_ctrl, type;
4456 + struct resource_entry *win;
4457 + int i;
4458 +
4459 + /* Disable all inbound/outbound windows */
4460 + for (i = 0; i < pcie->apio_wins; i++)
4461 + mobiveil_pcie_disable_ob_win(pcie, i);
4462 + for (i = 0; i < pcie->ppio_wins; i++)
4463 + mobiveil_pcie_disable_ib_win(pcie, i);
4464 +
4465 + pcie->ib_wins_configured = 0;
4466 + pcie->ob_wins_configured = 0;
4467 +
4468 + if (!reinit) {
4469 + /* setup bus numbers */
4470 + value = csr_readl(pcie, PCI_PRIMARY_BUS);
4471 + value &= 0xff000000;
4472 + value |= 0x00ff0100;
4473 + csr_writel(pcie, value, PCI_PRIMARY_BUS);
4474 + }
4475 +
4476 + /*
4477 + * program Bus Master Enable Bit in Command Register in PAB Config
4478 + * Space
4479 + */
4480 + value = csr_readl(pcie, PCI_COMMAND);
4481 + value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
4482 + csr_writel(pcie, value, PCI_COMMAND);
4483 +
4484 + /*
4485 + * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
4486 + * register
4487 + */
4488 + pab_ctrl = csr_readl(pcie, PAB_CTRL);
4489 + pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
4490 + csr_writel(pcie, pab_ctrl, PAB_CTRL);
4491 +
4492 + /*
4493 + * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
4494 + * PAB_AXI_PIO_CTRL Register
4495 + */
4496 + value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
4497 + value |= APIO_EN_MASK;
4498 + csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
4499 +
4500 + /* Enable PCIe PIO master */
4501 + value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
4502 + value |= 1 << PIO_ENABLE_SHIFT;
4503 + csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
4504 +
4505 + /*
4506 + * we'll program one outbound window for config reads and
4507 + * another default inbound window for all the upstream traffic
4508 + * rest of the outbound windows will be configured according to
4509 + * the "ranges" field defined in device tree
4510 + */
4511 +
4512 + /* config outbound translation window */
4513 + program_ob_windows(pcie, WIN_NUM_0, pcie->rp.ob_io_res->start, 0,
4514 + CFG_WINDOW_TYPE, resource_size(pcie->rp.ob_io_res));
4515 +
4516 + /* memory inbound translation window */
4517 + program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
4518 +
4519 + /* Get the I/O and memory ranges from DT */
4520 + resource_list_for_each_entry(win, pcie->resources) {
4521 + if (resource_type(win->res) == IORESOURCE_MEM) {
4522 + type = MEM_WINDOW_TYPE;
4523 + } else if (resource_type(win->res) == IORESOURCE_IO) {
4524 + type = IO_WINDOW_TYPE;
4525 + } else if (resource_type(win->res) == IORESOURCE_BUS) {
4526 + pcie->rp.root_bus_nr = win->res->start;
4527 + continue;
4528 + } else {
4529 + continue;
4530 + }
4531 +
4532 + /* configure outbound translation window */
4533 + program_ob_windows(pcie, pcie->ob_wins_configured,
4534 + win->res->start,
4535 + win->res->start - win->offset,
4536 + type, resource_size(win->res));
4537 + }
4538 +
4539 + /* fixup for PCIe class register */
4540 + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
4541 + value &= 0xff;
4542 + value |= (PCI_CLASS_BRIDGE_PCI << 16);
4543 + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
4544 +
4545 + return 0;
4546 +}
4547 +
4548 +static void mobiveil_mask_intx_irq(struct irq_data *data)
4549 +{
4550 + struct irq_desc *desc = irq_to_desc(data->irq);
4551 + struct mobiveil_pcie *pcie;
4552 + unsigned long flags;
4553 + u32 mask, shifted_val;
4554 +
4555 + pcie = irq_desc_get_chip_data(desc);
4556 + mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
4557 + raw_spin_lock_irqsave(&pcie->rp.intx_mask_lock, flags);
4558 + shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
4559 + shifted_val &= ~mask;
4560 + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
4561 + raw_spin_unlock_irqrestore(&pcie->rp.intx_mask_lock, flags);
4562 +}
4563 +
4564 +static void mobiveil_unmask_intx_irq(struct irq_data *data)
4565 +{
4566 + struct irq_desc *desc = irq_to_desc(data->irq);
4567 + struct mobiveil_pcie *pcie;
4568 + unsigned long flags;
4569 + u32 shifted_val, mask;
4570 +
4571 + pcie = irq_desc_get_chip_data(desc);
4572 + mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
4573 + raw_spin_lock_irqsave(&pcie->rp.intx_mask_lock, flags);
4574 + shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
4575 + shifted_val |= mask;
4576 + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
4577 + raw_spin_unlock_irqrestore(&pcie->rp.intx_mask_lock, flags);
4578 +}
4579 +
4580 +static struct irq_chip intx_irq_chip = {
4581 + .name = "mobiveil_pcie:intx",
4582 + .irq_enable = mobiveil_unmask_intx_irq,
4583 + .irq_disable = mobiveil_mask_intx_irq,
4584 + .irq_mask = mobiveil_mask_intx_irq,
4585 + .irq_unmask = mobiveil_unmask_intx_irq,
4586 +};
4587 +
4588 +/* routine to setup the INTx related data */
4589 +static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
4590 + irq_hw_number_t hwirq)
4591 +{
4592 + irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
4593 + irq_set_chip_data(irq, domain->host_data);
4594 +
4595 + return 0;
4596 +}
4597 +
4598 +/* INTx domain operations structure */
4599 +static const struct irq_domain_ops intx_domain_ops = {
4600 + .map = mobiveil_pcie_intx_map,
4601 +};
4602 +
4603 +static struct irq_chip mobiveil_msi_irq_chip = {
4604 + .name = "Mobiveil PCIe MSI",
4605 + .irq_mask = pci_msi_mask_irq,
4606 + .irq_unmask = pci_msi_unmask_irq,
4607 +};
4608 +
4609 +static struct msi_domain_info mobiveil_msi_domain_info = {
4610 + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
4611 + MSI_FLAG_PCI_MSIX),
4612 + .chip = &mobiveil_msi_irq_chip,
4613 +};
4614 +
4615 +static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
4616 +{
4617 + struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
4618 + phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
4619 +
4620 + msg->address_lo = lower_32_bits(addr);
4621 + msg->address_hi = upper_32_bits(addr);
4622 + msg->data = data->hwirq;
4623 +
4624 + dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
4625 + (int)data->hwirq, msg->address_hi, msg->address_lo);
4626 +}
4627 +
4628 +static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
4629 + const struct cpumask *mask, bool force)
4630 +{
4631 + return -EINVAL;
4632 +}
4633 +
4634 +static struct irq_chip mobiveil_msi_bottom_irq_chip = {
4635 + .name = "Mobiveil MSI",
4636 + .irq_compose_msi_msg = mobiveil_compose_msi_msg,
4637 + .irq_set_affinity = mobiveil_msi_set_affinity,
4638 +};
4639 +
4640 +static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
4641 + unsigned int virq,
4642 + unsigned int nr_irqs, void *args)
4643 +{
4644 + struct mobiveil_pcie *pcie = domain->host_data;
4645 + struct mobiveil_msi *msi = &pcie->rp.msi;
4646 + unsigned long bit;
4647 +
4648 + WARN_ON(nr_irqs != 1);
4649 + mutex_lock(&msi->lock);
4650 +
4651 + bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
4652 + if (bit >= msi->num_of_vectors) {
4653 + mutex_unlock(&msi->lock);
4654 + return -ENOSPC;
4655 + }
4656 +
4657 + set_bit(bit, msi->msi_irq_in_use);
4658 +
4659 + mutex_unlock(&msi->lock);
4660 +
4661 + irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
4662 + domain->host_data, handle_level_irq, NULL, NULL);
4663 + return 0;
4664 +}
4665 +
4666 +static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
4667 + unsigned int virq,
4668 + unsigned int nr_irqs)
4669 +{
4670 + struct irq_data *d = irq_domain_get_irq_data(domain, virq);
4671 + struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
4672 + struct mobiveil_msi *msi = &pcie->rp.msi;
4673 +
4674 + mutex_lock(&msi->lock);
4675 +
4676 + if (!test_bit(d->hwirq, msi->msi_irq_in_use))
4677 + dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
4678 + d->hwirq);
4679 + else
4680 + __clear_bit(d->hwirq, msi->msi_irq_in_use);
4681 +
4682 + mutex_unlock(&msi->lock);
4683 +}
4684 +static const struct irq_domain_ops msi_domain_ops = {
4685 + .alloc = mobiveil_irq_msi_domain_alloc,
4686 + .free = mobiveil_irq_msi_domain_free,
4687 +};
4688 +
4689 +static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
4690 +{
4691 + struct device *dev = &pcie->pdev->dev;
4692 + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
4693 + struct mobiveil_msi *msi = &pcie->rp.msi;
4694 +
4695 + mutex_init(&msi->lock);
4696 + msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
4697 + &msi_domain_ops, pcie);
4698 + if (!msi->dev_domain) {
4699 + dev_err(dev, "failed to create IRQ domain\n");
4700 + return -ENOMEM;
4701 + }
4702 +
4703 + msi->msi_domain = pci_msi_create_irq_domain(fwnode,
4704 + &mobiveil_msi_domain_info,
4705 + msi->dev_domain);
4706 + if (!msi->msi_domain) {
4707 + dev_err(dev, "failed to create MSI domain\n");
4708 + irq_domain_remove(msi->dev_domain);
4709 + return -ENOMEM;
4710 + }
4711 +
4712 + return 0;
4713 +}
4714 +
4715 +static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
4716 +{
4717 + struct device *dev = &pcie->pdev->dev;
4718 + struct device_node *node = dev->of_node;
4719 + int ret;
4720 +
4721 + /* setup INTx */
4722 + pcie->rp.intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
4723 + &intx_domain_ops, pcie);
4724 +
4725 + if (!pcie->rp.intx_domain) {
4726 + dev_err(dev, "Failed to get a INTx IRQ domain\n");
4727 + return -ENOMEM;
4728 + }
4729 +
4730 + raw_spin_lock_init(&pcie->rp.intx_mask_lock);
4731 +
4732 + /* setup MSI */
4733 + ret = mobiveil_allocate_msi_domains(pcie);
4734 + if (ret)
4735 + return ret;
4736 +
4737 + return 0;
4738 +}
4739 +
4740 +static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie)
4741 +{
4742 + struct device *dev = &pcie->pdev->dev;
4743 + struct resource *res;
4744 + int ret;
4745 +
4746 + if (pcie->rp.ops->interrupt_init)
4747 + return pcie->rp.ops->interrupt_init(pcie);
4748 +
4749 + /* map MSI config resource */
4750 + res = platform_get_resource_byname(pcie->pdev, IORESOURCE_MEM,
4751 + "apb_csr");
4752 + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
4753 + if (IS_ERR(pcie->apb_csr_base))
4754 + return PTR_ERR(pcie->apb_csr_base);
4755 +
4756 + /* setup MSI hardware registers */
4757 + mobiveil_pcie_enable_msi(pcie);
4758 +
4759 + pcie->rp.irq = platform_get_irq(pcie->pdev, 0);
4760 + if (pcie->rp.irq <= 0) {
4761 + dev_err(dev, "failed to map IRQ: %d\n", pcie->rp.irq);
4762 + return -ENODEV;
4763 + }
4764 +
4765 + /* initialize the IRQ domains */
4766 + ret = mobiveil_pcie_init_irq_domain(pcie);
4767 + if (ret) {
4768 + dev_err(dev, "Failed creating IRQ Domain\n");
4769 + return ret;
4770 + }
4771 +
4772 + irq_set_chained_handler_and_data(pcie->rp.irq,
4773 + mobiveil_pcie_isr, pcie);
4774 +
4775 + /* Enable interrupts */
4776 + csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
4777 + PAB_INTP_AMBA_MISC_ENB);
4778 +
4779 + return 0;
4780 +}
4781 +
4782 +int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
4783 +{
4784 + struct pci_bus *bus;
4785 + struct pci_bus *child;
4786 + struct pci_host_bridge *bridge;
4787 + struct device *dev = &pcie->pdev->dev;
4788 + struct device_node *np = dev->of_node;
4789 + resource_size_t iobase;
4790 + int ret;
4791 +
4792 + ret = mobiveil_pcie_parse_dt(pcie);
4793 + if (ret) {
4794 + dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
4795 + return ret;
4796 + }
4797 +
4798 + /* allocate the PCIe port */
4799 + bridge = devm_pci_alloc_host_bridge(dev, 0);
4800 + if (!bridge)
4801 + return -ENOMEM;
4802 +
4803 + /* parse the host bridge base addresses from the device tree file */
4804 + ret = of_pci_get_host_bridge_resources(np, 0, 0xff,
4805 + &bridge->windows, &iobase);
4806 + if (ret) {
4807 + dev_err(dev, "Getting bridge resources failed\n");
4808 + return ret;
4809 + }
4810 +
4811 + pcie->resources = &bridge->windows;
4812 +
4813 + /*
4814 + * configure all inbound and outbound windows and prepare the RC for
4815 + * config access
4816 + */
4817 + ret = mobiveil_host_init(pcie, false);
4818 + if (ret) {
4819 + dev_err(dev, "Failed to initialize host\n");
4820 + goto error;
4821 + }
4822 +
4823 + ret = mobiveil_pcie_interrupt_init(pcie);
4824 + if (ret) {
4825 + dev_err(dev, "Interrupt init failed\n");
4826 + goto error;
4827 + }
4828 +
4829 + ret = devm_request_pci_bus_resources(dev, pcie->resources);
4830 + if (ret)
4831 + goto error;
4832 +
4833 + /* Initialize bridge */
4834 + bridge->dev.parent = dev;
4835 + bridge->sysdata = pcie;
4836 + bridge->busnr = pcie->rp.root_bus_nr;
4837 + bridge->ops = &mobiveil_pcie_ops;
4838 + bridge->map_irq = of_irq_parse_and_map_pci;
4839 + bridge->swizzle_irq = pci_common_swizzle;
4840 +
4841 + ret = mobiveil_bringup_link(pcie);
4842 + if (ret) {
4843 + dev_info(dev, "link bring-up failed\n");
4844 + }
4845 +
4846 + /* setup the kernel resources for the newly added PCIe root bus */
4847 + ret = pci_scan_root_bus_bridge(bridge);
4848 + if (ret)
4849 + goto error;
4850 +
4851 + bus = bridge->bus;
4852 +
4853 + pci_assign_unassigned_bus_resources(bus);
4854 + list_for_each_entry(child, &bus->children, node)
4855 + pcie_bus_configure_settings(child);
4856 + pci_bus_add_devices(bus);
4857 +
4858 + return 0;
4859 +error:
4860 + pci_free_resource_list(pcie->resources);
4861 + return ret;
4862 +}
4863 --- /dev/null
4864 +++ b/drivers/pci/mobiveil/pcie-mobiveil-plat.c
4865 @@ -0,0 +1,54 @@
4866 +// SPDX-License-Identifier: GPL-2.0
4867 +/*
4868 + * PCIe host controller driver for Mobiveil PCIe Host controller
4869 + *
4870 + * Copyright (c) 2018 Mobiveil Inc.
4871 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
4872 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
4873 + */
4874 +
4875 +#include <linux/init.h>
4876 +#include <linux/kernel.h>
4877 +#include <linux/module.h>
4878 +#include <linux/of_pci.h>
4879 +#include <linux/pci.h>
4880 +#include <linux/platform_device.h>
4881 +#include <linux/slab.h>
4882 +
4883 +#include "pcie-mobiveil.h"
4884 +
4885 +static int mobiveil_pcie_probe(struct platform_device *pdev)
4886 +{
4887 + struct mobiveil_pcie *pcie;
4888 + struct device *dev = &pdev->dev;
4889 +
4890 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
4891 + if (!pcie)
4892 + return -ENOMEM;
4893 +
4894 + pcie->pdev = pdev;
4895 +
4896 + return mobiveil_pcie_host_probe(pcie);
4897 +}
4898 +
4899 +static const struct of_device_id mobiveil_pcie_of_match[] = {
4900 + {.compatible = "mbvl,gpex40-pcie",},
4901 + {},
4902 +};
4903 +
4904 +MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
4905 +
4906 +static struct platform_driver mobiveil_pcie_driver = {
4907 + .probe = mobiveil_pcie_probe,
4908 + .driver = {
4909 + .name = "mobiveil-pcie",
4910 + .of_match_table = mobiveil_pcie_of_match,
4911 + .suppress_bind_attrs = true,
4912 + },
4913 +};
4914 +
4915 +builtin_platform_driver(mobiveil_pcie_driver);
4916 +
4917 +MODULE_LICENSE("GPL v2");
4918 +MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
4919 +MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");
4920 --- /dev/null
4921 +++ b/drivers/pci/mobiveil/pcie-mobiveil.c
4922 @@ -0,0 +1,334 @@
4923 +// SPDX-License-Identifier: GPL-2.0
4924 +/*
4925 + * PCIe host controller driver for Mobiveil PCIe Host controller
4926 + *
4927 + * Copyright (c) 2018 Mobiveil Inc.
4928 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
4929 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
4930 + */
4931 +
4932 +#include <linux/delay.h>
4933 +#include <linux/init.h>
4934 +#include <linux/kernel.h>
4935 +#include <linux/pci.h>
4936 +#include <linux/platform_device.h>
4937 +
4938 +#include "pcie-mobiveil.h"
4939 +
4940 +/*
4941 + * mobiveil_pcie_sel_page - routine to access paged register
4942 + *
4943 + * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
4944 + * for this scheme to work extracted higher 6 bits of the offset will be
4945 + * written to pg_sel field of PAB_CTRL register and rest of the lower 10
4946 + * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
4947 + */
4948 +static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
4949 +{
4950 + u32 val;
4951 +
4952 + val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
4953 + val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
4954 + val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
4955 +
4956 + writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
4957 +}
4958 +
4959 +static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
4960 +{
4961 + if (off < PAGED_ADDR_BNDRY) {
4962 + /* For directly accessed registers, clear the pg_sel field */
4963 + mobiveil_pcie_sel_page(pcie, 0);
4964 + return pcie->csr_axi_slave_base + off;
4965 + }
4966 +
4967 + mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
4968 + return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
4969 +}
4970 +
4971 +static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
4972 +{
4973 + if ((uintptr_t)addr & (size - 1)) {
4974 + *val = 0;
4975 + return PCIBIOS_BAD_REGISTER_NUMBER;
4976 + }
4977 +
4978 + switch (size) {
4979 + case 4:
4980 + *val = readl(addr);
4981 + break;
4982 + case 2:
4983 + *val = readw(addr);
4984 + break;
4985 + case 1:
4986 + *val = readb(addr);
4987 + break;
4988 + default:
4989 + *val = 0;
4990 + return PCIBIOS_BAD_REGISTER_NUMBER;
4991 + }
4992 +
4993 + return PCIBIOS_SUCCESSFUL;
4994 +}
4995 +
4996 +static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
4997 +{
4998 + if ((uintptr_t)addr & (size - 1))
4999 + return PCIBIOS_BAD_REGISTER_NUMBER;
5000 +
5001 + switch (size) {
5002 + case 4:
5003 + writel(val, addr);
5004 + break;
5005 + case 2:
5006 + writew(val, addr);
5007 + break;
5008 + case 1:
5009 + writeb(val, addr);
5010 + break;
5011 + default:
5012 + return PCIBIOS_BAD_REGISTER_NUMBER;
5013 + }
5014 +
5015 + return PCIBIOS_SUCCESSFUL;
5016 +}
5017 +
5018 +u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
5019 +{
5020 + void *addr;
5021 + u32 val;
5022 + int ret;
5023 +
5024 + addr = mobiveil_pcie_comp_addr(pcie, off);
5025 +
5026 + ret = mobiveil_pcie_read(addr, size, &val);
5027 + if (ret)
5028 + dev_err(&pcie->pdev->dev, "read CSR address failed\n");
5029 +
5030 + return val;
5031 +}
5032 +
5033 +void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
5034 +{
5035 + void *addr;
5036 + int ret;
5037 +
5038 + addr = mobiveil_pcie_comp_addr(pcie, off);
5039 +
5040 + ret = mobiveil_pcie_write(addr, size, val);
5041 + if (ret)
5042 + dev_err(&pcie->pdev->dev, "write CSR address failed\n");
5043 +}
5044 +
5045 +bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
5046 +{
5047 + if (pcie->ops->link_up)
5048 + return pcie->ops->link_up(pcie);
5049 +
5050 + return (csr_readl(pcie, LTSSM_STATUS) &
5051 + LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
5052 +}
5053 +
5054 +void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5055 + u64 pci_addr, u32 type, u64 size)
5056 +{
5057 + u32 value;
5058 + u64 size64 = ~(size - 1);
5059 +
5060 + if (win_num >= pcie->ppio_wins) {
5061 + dev_err(&pcie->pdev->dev,
5062 + "ERROR: max inbound windows reached !\n");
5063 + return;
5064 + }
5065 +
5066 + value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
5067 + value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT |
5068 + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5069 + value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) |
5070 + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5071 + csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
5072 +
5073 + csr_writel(pcie, upper_32_bits(size64),
5074 + PAB_EXT_PEX_AMAP_SIZEN(win_num));
5075 +
5076 + csr_writel(pcie, lower_32_bits(cpu_addr),
5077 + PAB_PEX_AMAP_AXI_WIN(win_num));
5078 + csr_writel(pcie, upper_32_bits(cpu_addr),
5079 + PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
5080 +
5081 + csr_writel(pcie, lower_32_bits(pci_addr),
5082 + PAB_PEX_AMAP_PEX_WIN_L(win_num));
5083 + csr_writel(pcie, upper_32_bits(pci_addr),
5084 + PAB_PEX_AMAP_PEX_WIN_H(win_num));
5085 +
5086 + pcie->ib_wins_configured++;
5087 +}
5088 +
5089 +/*
5090 + * routine to program the outbound windows
5091 + */
5092 +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5093 + u64 pci_addr, u32 type, u64 size)
5094 +{
5095 +
5096 + u32 value;
5097 + u64 size64 = ~(size - 1);
5098 +
5099 + if (win_num >= pcie->apio_wins) {
5100 + dev_err(&pcie->pdev->dev,
5101 + "ERROR: max outbound windows reached !\n");
5102 + return;
5103 + }
5104 +
5105 + /*
5106 + * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
5107 + * to 4 KB in PAB_AXI_AMAP_CTRL register
5108 + */
5109 + value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
5110 + value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
5111 + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5112 + value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
5113 + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5114 + csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
5115 +
5116 + csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
5117 +
5118 + /*
5119 + * program AXI window base with appropriate value in
5120 + * PAB_AXI_AMAP_AXI_WIN0 register
5121 + */
5122 + csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
5123 + PAB_AXI_AMAP_AXI_WIN(win_num));
5124 + csr_writel(pcie, upper_32_bits(cpu_addr),
5125 + PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
5126 +
5127 + csr_writel(pcie, lower_32_bits(pci_addr),
5128 + PAB_AXI_AMAP_PEX_WIN_L(win_num));
5129 + csr_writel(pcie, upper_32_bits(pci_addr),
5130 + PAB_AXI_AMAP_PEX_WIN_H(win_num));
5131 +
5132 + pcie->ob_wins_configured++;
5133 +}
5134 +
5135 +int program_ob_windows_ep(struct mobiveil_pcie *pcie, int win_num, int type,
5136 + u64 phys, u64 bus_addr, u8 func, u64 size)
5137 +{
5138 + u32 val;
5139 + u32 size_h, size_l;
5140 +
5141 + if (size & (size - 1))
5142 + size = 1 << (1 + ilog2(size));
5143 +
5144 + size_h = upper_32_bits(~(size - 1));
5145 + size_l = lower_32_bits(~(size - 1));
5146 +
5147 + val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
5148 + val &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
5149 + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5150 + val |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
5151 + (size_l & (WIN_SIZE_MASK << WIN_SIZE_SHIFT));
5152 + csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(win_num));
5153 +
5154 + csr_writel(pcie, func, PAB_AXI_AMAP_PCI_HDR_PARAM(win_num));
5155 + csr_writel(pcie, lower_32_bits(phys), PAB_AXI_AMAP_AXI_WIN(win_num));
5156 + csr_writel(pcie, upper_32_bits(phys),
5157 + PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
5158 + csr_writel(pcie, lower_32_bits(bus_addr),
5159 + PAB_AXI_AMAP_PEX_WIN_L(win_num));
5160 + csr_writel(pcie, upper_32_bits(bus_addr),
5161 + PAB_AXI_AMAP_PEX_WIN_H(win_num));
5162 + csr_writel(pcie, size_h, PAB_EXT_AXI_AMAP_SIZE(win_num));
5163 +
5164 + return 0;
5165 +}
5166 +
5167 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
5168 + int bar, u64 phys)
5169 +{
5170 + csr_writel(pcie, upper_32_bits(phys),
5171 + PAB_EXT_PEX_BAR_AMAP(func_no, bar));
5172 + csr_writel(pcie, lower_32_bits(phys) | PEX_BAR_AMAP_EN,
5173 + PAB_PEX_BAR_AMAP(func_no, bar));
5174 +}
5175 +
5176 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pcie,
5177 + u8 func_no, u8 bar)
5178 +{
5179 + u32 val;
5180 +
5181 + val = csr_readl(pcie, PAB_PEX_BAR_AMAP(func_no, bar));
5182 + val &= ~(1 << 0);
5183 + csr_writel(pcie, val, PAB_PEX_BAR_AMAP(func_no, bar));
5184 +}
5185 +
5186 +int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
5187 +{
5188 + int retries;
5189 +
5190 + /* check if the link is up or not */
5191 + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
5192 + if (mobiveil_pcie_link_up(pcie))
5193 + return 0;
5194 +
5195 + usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
5196 + }
5197 +
5198 + dev_info(&pcie->pdev->dev, "link never came up\n");
5199 +
5200 + return -ETIMEDOUT;
5201 +}
5202 +
5203 +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pcie, int win_num)
5204 +{
5205 + u32 val;
5206 +
5207 + val = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
5208 + val &= ~(1 << AMAP_CTRL_EN_SHIFT);
5209 + csr_writel(pcie, val, PAB_PEX_AMAP_CTRL(win_num));
5210 +}
5211 +
5212 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int win_num)
5213 +{
5214 + u32 val;
5215 +
5216 + val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
5217 + val &= ~(1 << WIN_ENABLE_SHIFT);
5218 + csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(win_num));
5219 +}
5220 +
5221 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pcie)
5222 +{
5223 + u32 val;
5224 +
5225 + val = csr_readl(pcie, PAB_CTRL);
5226 + val |= 1 << AMBA_PIO_ENABLE_SHIFT;
5227 + val |= 1 << PEX_PIO_ENABLE_SHIFT;
5228 + csr_writel(pcie, val, PAB_CTRL);
5229 +}
5230 +
5231 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pcie)
5232 +{
5233 + u32 val;
5234 +
5235 + val = csr_readl(pcie, PAB_AXI_PIO_CTRL);
5236 + val |= APIO_EN_MASK;
5237 + csr_writel(pcie, val, PAB_AXI_PIO_CTRL);
5238 +}
5239 +
5240 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pcie)
5241 +{
5242 + u32 val;
5243 +
5244 + val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
5245 + val |= 1 << PIO_ENABLE_SHIFT;
5246 + csr_writel(pcie, val, PAB_PEX_PIO_CTRL);
5247 +}
5248 +
5249 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pcie)
5250 +{
5251 + u32 val;
5252 +
5253 + val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
5254 + val |= 1 << 0;
5255 + csr_writel(pcie, val, PAB_INTP_AMBA_MISC_ENB);
5256 +}
5257 --- /dev/null
5258 +++ b/drivers/pci/mobiveil/pcie-mobiveil.h
5259 @@ -0,0 +1,296 @@
5260 +/* SPDX-License-Identifier: GPL-2.0 */
5261 +/*
5262 + * PCIe host controller driver for Mobiveil PCIe Host controller
5263 + *
5264 + * Copyright (c) 2018 Mobiveil Inc.
5265 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
5266 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
5267 + */
5268 +
5269 +#ifndef _PCIE_MOBIVEIL_H
5270 +#define _PCIE_MOBIVEIL_H
5271 +
5272 +#include <linux/pci.h>
5273 +#include <linux/irq.h>
5274 +#include <linux/msi.h>
5275 +#include "../pci.h"
5276 +
5277 +#include <linux/pci-epc.h>
5278 +#include <linux/pci-epf.h>
5279 +
5280 +#define MAX_IATU_OUT 256
5281 +/* register offsets and bit positions */
5282 +
5283 +/*
5284 + * translation tables are grouped into windows, each window registers are
5285 + * grouped into blocks of 4 or 16 registers each
5286 + */
5287 +#define PAB_REG_BLOCK_SIZE 16
5288 +#define PAB_EXT_REG_BLOCK_SIZE 4
5289 +
5290 +#define PAB_REG_ADDR(offset, win) \
5291 + (offset + (win * PAB_REG_BLOCK_SIZE))
5292 +#define PAB_EXT_REG_ADDR(offset, win) \
5293 + (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
5294 +
5295 +#define LTSSM_STATUS 0x0404
5296 +#define LTSSM_STATUS_L0_MASK 0x3f
5297 +#define LTSSM_STATUS_L0 0x2d
5298 +
5299 +#define PAB_CTRL 0x0808
5300 +#define AMBA_PIO_ENABLE_SHIFT 0
5301 +#define PEX_PIO_ENABLE_SHIFT 1
5302 +#define PAGE_SEL_SHIFT 13
5303 +#define PAGE_SEL_MASK 0x3f
5304 +#define PAGE_LO_MASK 0x3ff
5305 +#define PAGE_SEL_OFFSET_SHIFT 10
5306 +#define FUNC_SEL_SHIFT 19
5307 +#define FUNC_SEL_MASK 0x1ff
5308 +#define MSI_SW_CTRL_EN (1 << 29)
5309 +
5310 +#define PAB_ACTIVITY_STAT 0x81c
5311 +
5312 +#define PAB_AXI_PIO_CTRL 0x0840
5313 +#define APIO_EN_MASK 0xf
5314 +
5315 +#define PAB_PEX_PIO_CTRL 0x08c0
5316 +#define PIO_ENABLE_SHIFT 0
5317 +
5318 +#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
5319 +#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
5320 +#define PAB_INTP_RESET (0x1 << 1)
5321 +#define PAB_INTP_MSI (0x1 << 3)
5322 +#define PAB_INTP_INTA (0x1 << 5)
5323 +#define PAB_INTP_INTB (0x1 << 6)
5324 +#define PAB_INTP_INTC (0x1 << 7)
5325 +#define PAB_INTP_INTD (0x1 << 8)
5326 +#define PAB_INTP_PCIE_UE (0x1 << 9)
5327 +#define PAB_INTP_IE_PMREDI (0x1 << 29)
5328 +#define PAB_INTP_IE_EC (0x1 << 30)
5329 +#define PAB_INTP_MSI_MASK PAB_INTP_MSI
5330 +#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\
5331 + PAB_INTP_INTC | PAB_INTP_INTD)
5332 +
5333 +#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
5334 +#define WIN_ENABLE_SHIFT 0
5335 +#define WIN_TYPE_SHIFT 1
5336 +#define WIN_TYPE_MASK 0x3
5337 +#define WIN_SIZE_SHIFT 10
5338 +#define WIN_SIZE_MASK 0x3fffff
5339 +
5340 +#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
5341 +
5342 +#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
5343 +#define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
5344 +#define AXI_WINDOW_ALIGN_MASK 3
5345 +
5346 +#define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
5347 +#define PAB_BUS_SHIFT 24
5348 +#define PAB_DEVICE_SHIFT 19
5349 +#define PAB_FUNCTION_SHIFT 16
5350 +
5351 +#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
5352 +#define PAB_INTP_AXI_PIO_CLASS 0x474
5353 +
5354 +#define GPEX_ACK_REPLAY_TO 0x438
5355 +#define ACK_LAT_TO_VAL_MASK 0x1fff
5356 +#define ACK_LAT_TO_VAL_SHIFT 0
5357 +
5358 +#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
5359 +#define AMAP_CTRL_EN_SHIFT 0
5360 +#define AMAP_CTRL_TYPE_SHIFT 1
5361 +#define AMAP_CTRL_TYPE_MASK 3
5362 +
5363 +#define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
5364 +#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
5365 +#define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
5366 +#define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
5367 +#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
5368 +
5369 +/* PPIO WINs EP mode */
5370 +#define PAB_PEX_BAR_AMAP(func, bar) (0x1ba0 + 0x20 * func + 4 * bar)
5371 +#define PAB_EXT_PEX_BAR_AMAP(func, bar) (0x84a0 + 0x20 * func + 4 * bar)
5372 +#define PEX_BAR_AMAP_EN (1 << 0)
5373 +
5374 +#define PAB_AXI_AMAP_PCI_HDR_PARAM(idx) (0x5ba0 + 0x04 * idx)
5375 +#define PAB_MSIX_TABLE_PBA_ACCESS 0xD000
5376 +
5377 +#define GPEX_BAR_ENABLE 0x4D4
5378 +#define GPEX_BAR_SIZE_LDW 0x4D8
5379 +#define GPEX_BAR_SIZE_UDW 0x4DC
5380 +#define GPEX_BAR_SELECT 0x4E0
5381 +
5382 +#define CFG_UNCORRECTABLE_ERROR_SEVERITY 0x10c
5383 +#define UNSUPPORTED_REQUEST_ERROR_SHIFT 20
5384 +#define CFG_UNCORRECTABLE_ERROR_MASK 0x108
5385 +
5386 +/* starting offset of INTX bits in status register */
5387 +#define PAB_INTX_START 5
5388 +
5389 +/* supported number of MSI interrupts */
5390 +#define PCI_NUM_MSI 16
5391 +
5392 +/* MSI registers */
5393 +#define MSI_BASE_LO_OFFSET 0x04
5394 +#define MSI_BASE_HI_OFFSET 0x08
5395 +#define MSI_SIZE_OFFSET 0x0c
5396 +#define MSI_ENABLE_OFFSET 0x14
5397 +#define MSI_STATUS_OFFSET 0x18
5398 +#define MSI_DATA_OFFSET 0x20
5399 +#define MSI_ADDR_L_OFFSET 0x24
5400 +#define MSI_ADDR_H_OFFSET 0x28
5401 +
5402 +/* outbound and inbound window definitions */
5403 +#define WIN_NUM_0 0
5404 +#define WIN_NUM_1 1
5405 +#define CFG_WINDOW_TYPE 0
5406 +#define IO_WINDOW_TYPE 1
5407 +#define MEM_WINDOW_TYPE 2
5408 +#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
5409 +#define MAX_PIO_WINDOWS 8
5410 +
5411 +/* Parameters for the waiting for link up routine */
5412 +#define LINK_WAIT_MAX_RETRIES 10
5413 +#define LINK_WAIT_MIN 90000
5414 +#define LINK_WAIT_MAX 100000
5415 +
5416 +#define PAGED_ADDR_BNDRY 0xc00
5417 +#define OFFSET_TO_PAGE_ADDR(off) \
5418 + ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
5419 +#define OFFSET_TO_PAGE_IDX(off) \
5420 + ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
5421 +
5422 +struct mobiveil_pcie;
5423 +struct mobiveil_pcie_ep;
5424 +
5425 +struct mobiveil_msi { /* MSI information */
5426 + struct mutex lock; /* protect bitmap variable */
5427 + struct irq_domain *msi_domain;
5428 + struct irq_domain *dev_domain;
5429 + phys_addr_t msi_pages_phys;
5430 + int num_of_vectors;
5431 + DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
5432 +};
5433 +
5434 +struct mobiveil_rp_ops {
5435 + int (*interrupt_init)(struct mobiveil_pcie *pcie);
5436 + int (*read_other_conf)(struct pci_bus *bus, unsigned int devfn,
5437 + int where, int size, u32 *val);
5438 +};
5439 +
5440 +struct root_port {
5441 + u8 root_bus_nr;
5442 + void __iomem *config_axi_slave_base; /* endpoint config base */
5443 + struct resource *ob_io_res;
5444 + struct mobiveil_rp_ops *ops;
5445 + int irq;
5446 + raw_spinlock_t intx_mask_lock;
5447 + struct irq_domain *intx_domain;
5448 + struct mobiveil_msi msi;
5449 +};
5450 +
5451 +struct mobiveil_pab_ops {
5452 + int (*link_up)(struct mobiveil_pcie *pcie);
5453 +};
5454 +
5455 +struct mobiveil_pcie_ep_ops {
5456 + void (*ep_init)(struct mobiveil_pcie_ep *ep);
5457 + int (*raise_irq)(struct mobiveil_pcie_ep *ep, u8 func_no,
5458 + enum pci_epc_irq_type type, u16 interrupt_num);
5459 +};
5460 +
5461 +struct mobiveil_pcie_ep {
5462 + struct pci_epc *epc;
5463 + struct mobiveil_pcie_ep_ops *ops;
5464 + phys_addr_t phys_base;
5465 + size_t addr_size;
5466 + size_t page_size;
5467 + phys_addr_t *outbound_addr;
5468 + unsigned long *ob_window_map;
5469 + u32 num_ob_windows;
5470 + void __iomem *msi_mem;
5471 + phys_addr_t msi_mem_phys;
5472 + u8 msi_cap; /* MSI capability offset */
5473 + u8 msix_cap; /* MSI-X capability offset */
5474 + u8 bar_num;
5475 + u32 pf_num;
5476 +};
5477 +
5478 +struct mobiveil_pcie {
5479 + struct platform_device *pdev;
5480 + struct list_head *resources;
5481 + void __iomem *csr_axi_slave_base; /* PAB registers base */
5482 + phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
5483 + void __iomem *apb_csr_base; /* MSI register base */
5484 + u32 apio_wins;
5485 + u32 ppio_wins;
5486 + u32 ob_wins_configured; /* configured outbound windows */
5487 + u32 ib_wins_configured; /* configured inbound windows */
5488 + const struct mobiveil_pab_ops *ops;
5489 + struct root_port rp;
5490 + struct mobiveil_pcie_ep ep;
5491 +};
5492 +#define to_mobiveil_pcie_from_ep(endpoint) \
5493 + container_of((endpoint), struct mobiveil_pcie, ep)
5494 +
5495 +int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
5496 +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
5497 +bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
5498 +int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
5499 +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5500 + u64 pci_addr, u32 type, u64 size);
5501 +void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5502 + u64 pci_addr, u32 type, u64 size);
5503 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
5504 +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
5505 +u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
5506 +void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
5507 +
5508 +static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
5509 +{
5510 + return csr_read(pcie, off, 0x4);
5511 +}
5512 +
5513 +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)
5514 +{
5515 + return csr_read(pcie, off, 0x2);
5516 +}
5517 +
5518 +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)
5519 +{
5520 + return csr_read(pcie, off, 0x1);
5521 +}
5522 +
5523 +static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
5524 +{
5525 + csr_write(pcie, val, off, 0x4);
5526 +}
5527 +
5528 +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
5529 +{
5530 + csr_write(pcie, val, off, 0x2);
5531 +}
5532 +
5533 +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
5534 +{
5535 + csr_write(pcie, val, off, 0x1);
5536 +}
5537 +
5538 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
5539 + int bar, u64 phys);
5540 +int program_ob_windows_ep(struct mobiveil_pcie *pcie, int win_num, int type,
5541 + u64 phys, u64 bus_addr, u8 func, u64 size);
5542 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pci,
5543 + u8 func_no, u8 bar);
5544 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep);
5545 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no);
5546 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
5547 + u8 interrupt_num);
5548 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
5549 + u16 interrupt_num);
5550 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pci, enum pci_barno bar);
5551 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pci);
5552 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pci);
5553 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pci);
5554 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pci);
5555 +#endif /* _PCIE_MOBIVEIL_H */
5556 --- a/drivers/pci/pcie/portdrv_core.c
5557 +++ b/drivers/pci/pcie/portdrv_core.c
5558 @@ -45,6 +45,20 @@ static void release_pcie_device(struct d
5559 }
5560
5561 /**
5562 + * pcibios_check_service_irqs - check irqs in the device tree
5563 + * @dev: PCI Express port to handle
5564 + * @irqs: Array of irqs to populate
5565 + * @mask: Bitmask of port capabilities returned by get_port_device_capability()
5566 + *
5567 + * Return value: 0 means no service irqs in the device tree
5568 + *
5569 + */
5570 +int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
5571 +{
5572 + return 0;
5573 +}
5574 +
5575 +/**
5576 * pcie_port_enable_irq_vec - try to set up MSI-X or MSI as interrupt mode
5577 * for given port
5578 * @dev: PCI Express port to handle
5579 @@ -185,10 +199,25 @@ out_free_irqs:
5580 static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
5581 {
5582 int ret, i;
5583 + int irq = -1;
5584
5585 for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
5586 irqs[i] = -1;
5587
5588 + /* Check if some platforms owns independent irq pins for AER/PME etc.
5589 + * Some platforms may own independent AER/PME interrupts and set
5590 + * them in the device tree file.
5591 + */
5592 + ret = pcibios_check_service_irqs(dev, irqs, mask);
5593 + if (ret) {
5594 + if (dev->irq)
5595 + irq = dev->irq;
5596 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
5597 + if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
5598 + irqs[i] = irq;
5599 + return 0;
5600 + }
5601 +
5602 /*
5603 * If we support PME or hotplug, but we can't use MSI/MSI-X for
5604 * them, we have to fall back to INTx or other interrupts, e.g., a
5605 --- a/drivers/pci/quirks.c
5606 +++ b/drivers/pci/quirks.c
5607 @@ -3394,6 +3394,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A
5608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
5609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
5610
5611 +/*
5612 + * NXP (Freescale Vendor ID) LS1088 chips do not behave correctly after
5613 + * bus reset. Link state of device does not comes UP and so config space
5614 + * never accessible again.
5615 + */
5616 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x80c0, quirk_no_bus_reset);
5617 +
5618 static void quirk_no_pm_reset(struct pci_dev *dev)
5619 {
5620 /*
5621 @@ -4918,3 +4925,11 @@ static void quirk_no_ats(struct pci_dev
5622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
5623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
5624 #endif /* CONFIG_PCI_ATS */
5625 +
5626 +/* Freescale PCIe doesn't support MSI in RC mode */
5627 +static void quirk_fsl_no_msi(struct pci_dev *pdev)
5628 +{
5629 + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5630 + pdev->no_msi = 1;
5631 +}
5632 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5633 --- a/include/linux/pci-ep-cfs.h
5634 +++ b/include/linux/pci-ep-cfs.h
5635 @@ -1,12 +1,9 @@
5636 +/* SPDX-License-Identifier: GPL-2.0+ */
5637 /**
5638 * PCI Endpoint ConfigFS header file
5639 *
5640 * Copyright (C) 2017 Texas Instruments
5641 * Author: Kishon Vijay Abraham I <kishon@ti.com>
5642 - *
5643 - * This program is free software: you can redistribute it and/or modify
5644 - * it under the terms of the GNU General Public License version 2 of
5645 - * the License as published by the Free Software Foundation.
5646 */
5647
5648 #ifndef __LINUX_PCI_EP_CFS_H
5649 --- a/include/linux/pci-epc.h
5650 +++ b/include/linux/pci-epc.h
5651 @@ -1,12 +1,9 @@
5652 +/* SPDX-License-Identifier: GPL-2.0+ */
5653 /**
5654 * PCI Endpoint *Controller* (EPC) header file
5655 *
5656 * Copyright (C) 2017 Texas Instruments
5657 * Author: Kishon Vijay Abraham I <kishon@ti.com>
5658 - *
5659 - * This program is free software: you can redistribute it and/or modify
5660 - * it under the terms of the GNU General Public License version 2 of
5661 - * the License as published by the Free Software Foundation.
5662 */
5663
5664 #ifndef __LINUX_PCI_EPC_H
5665 @@ -20,6 +17,7 @@ enum pci_epc_irq_type {
5666 PCI_EPC_IRQ_UNKNOWN,
5667 PCI_EPC_IRQ_LEGACY,
5668 PCI_EPC_IRQ_MSI,
5669 + PCI_EPC_IRQ_MSIX,
5670 };
5671
5672 /**
5673 @@ -33,24 +31,32 @@ enum pci_epc_irq_type {
5674 * capability register
5675 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
5676 * the MSI capability register
5677 - * @raise_irq: ops to raise a legacy or MSI interrupt
5678 + * @set_msix: ops to set the requested number of MSI-X interrupts in the
5679 + * MSI-X capability register
5680 + * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
5681 + * from the MSI-X capability register
5682 + * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
5683 * @start: ops to start the PCI link
5684 * @stop: ops to stop the PCI link
5685 * @owner: the module owner containing the ops
5686 */
5687 struct pci_epc_ops {
5688 - int (*write_header)(struct pci_epc *pci_epc,
5689 + int (*write_header)(struct pci_epc *epc, u8 func_no,
5690 struct pci_epf_header *hdr);
5691 - int (*set_bar)(struct pci_epc *epc, enum pci_barno bar,
5692 - dma_addr_t bar_phys, size_t size, int flags);
5693 - void (*clear_bar)(struct pci_epc *epc, enum pci_barno bar);
5694 - int (*map_addr)(struct pci_epc *epc, phys_addr_t addr,
5695 - u64 pci_addr, size_t size);
5696 - void (*unmap_addr)(struct pci_epc *epc, phys_addr_t addr);
5697 - int (*set_msi)(struct pci_epc *epc, u8 interrupts);
5698 - int (*get_msi)(struct pci_epc *epc);
5699 - int (*raise_irq)(struct pci_epc *pci_epc,
5700 - enum pci_epc_irq_type type, u8 interrupt_num);
5701 + int (*set_bar)(struct pci_epc *epc, u8 func_no,
5702 + struct pci_epf_bar *epf_bar);
5703 + void (*clear_bar)(struct pci_epc *epc, u8 func_no,
5704 + struct pci_epf_bar *epf_bar);
5705 + int (*map_addr)(struct pci_epc *epc, u8 func_no,
5706 + phys_addr_t addr, u64 pci_addr, size_t size);
5707 + void (*unmap_addr)(struct pci_epc *epc, u8 func_no,
5708 + phys_addr_t addr);
5709 + int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
5710 + int (*get_msi)(struct pci_epc *epc, u8 func_no);
5711 + int (*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts);
5712 + int (*get_msix)(struct pci_epc *epc, u8 func_no);
5713 + int (*raise_irq)(struct pci_epc *epc, u8 func_no,
5714 + enum pci_epc_irq_type type, u16 interrupt_num);
5715 int (*start)(struct pci_epc *epc);
5716 void (*stop)(struct pci_epc *epc);
5717 struct module *owner;
5718 @@ -91,8 +97,17 @@ struct pci_epc {
5719 struct config_group *group;
5720 /* spinlock to protect against concurrent access of EP controller */
5721 spinlock_t lock;
5722 + unsigned int features;
5723 };
5724
5725 +#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0)
5726 +#define EPC_FEATURE_BAR_MASK (BIT(1) | BIT(2) | BIT(3))
5727 +#define EPC_FEATURE_MSIX_AVAILABLE BIT(4)
5728 +#define EPC_FEATURE_SET_BAR(features, bar) \
5729 + (features |= (EPC_FEATURE_BAR_MASK & (bar << 1)))
5730 +#define EPC_FEATURE_GET_BAR(features) \
5731 + ((features & EPC_FEATURE_BAR_MASK) >> 1)
5732 +
5733 #define to_pci_epc(device) container_of((device), struct pci_epc, dev)
5734
5735 #define pci_epc_create(dev, ops) \
5736 @@ -124,17 +139,23 @@ void pci_epc_destroy(struct pci_epc *epc
5737 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
5738 void pci_epc_linkup(struct pci_epc *epc);
5739 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
5740 -int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hdr);
5741 -int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
5742 - dma_addr_t bar_phys, size_t size, int flags);
5743 -void pci_epc_clear_bar(struct pci_epc *epc, int bar);
5744 -int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
5745 +int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
5746 + struct pci_epf_header *hdr);
5747 +int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
5748 + struct pci_epf_bar *epf_bar);
5749 +void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
5750 + struct pci_epf_bar *epf_bar);
5751 +int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
5752 + phys_addr_t phys_addr,
5753 u64 pci_addr, size_t size);
5754 -void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr);
5755 -int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts);
5756 -int pci_epc_get_msi(struct pci_epc *epc);
5757 -int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
5758 - u8 interrupt_num);
5759 +void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
5760 + phys_addr_t phys_addr);
5761 +int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
5762 +int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
5763 +int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts);
5764 +int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
5765 +int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
5766 + enum pci_epc_irq_type type, u16 interrupt_num);
5767 int pci_epc_start(struct pci_epc *epc);
5768 void pci_epc_stop(struct pci_epc *epc);
5769 struct pci_epc *pci_epc_get(const char *epc_name);
5770 --- a/include/linux/pci-epf.h
5771 +++ b/include/linux/pci-epf.h
5772 @@ -1,12 +1,9 @@
5773 +/* SPDX-License-Identifier: GPL-2.0+ */
5774 /**
5775 * PCI Endpoint *Function* (EPF) header file
5776 *
5777 * Copyright (C) 2017 Texas Instruments
5778 * Author: Kishon Vijay Abraham I <kishon@ti.com>
5779 - *
5780 - * This program is free software: you can redistribute it and/or modify
5781 - * it under the terms of the GNU General Public License version 2 of
5782 - * the License as published by the Free Software Foundation.
5783 */
5784
5785 #ifndef __LINUX_PCI_EPF_H
5786 @@ -75,7 +72,7 @@ struct pci_epf_ops {
5787 * @driver: PCI EPF driver
5788 * @ops: set of function pointers for performing EPF operations
5789 * @owner: the owner of the module that registers the PCI EPF driver
5790 - * @group: configfs group corresponding to the PCI EPF driver
5791 + * @epf_group: list of configfs group corresponding to the PCI EPF driver
5792 * @id_table: identifies EPF devices for probing
5793 */
5794 struct pci_epf_driver {
5795 @@ -85,7 +82,7 @@ struct pci_epf_driver {
5796 struct device_driver driver;
5797 struct pci_epf_ops *ops;
5798 struct module *owner;
5799 - struct config_group *group;
5800 + struct list_head epf_group;
5801 const struct pci_epf_device_id *id_table;
5802 };
5803
5804 @@ -100,6 +97,8 @@ struct pci_epf_driver {
5805 struct pci_epf_bar {
5806 dma_addr_t phys_addr;
5807 size_t size;
5808 + enum pci_barno barno;
5809 + int flags;
5810 };
5811
5812 /**
5813 @@ -120,6 +119,7 @@ struct pci_epf {
5814 struct pci_epf_header *header;
5815 struct pci_epf_bar bar[6];
5816 u8 msi_interrupts;
5817 + u16 msix_interrupts;
5818 u8 func_no;
5819
5820 struct pci_epc *epc;
5821 --- a/include/linux/pci.h
5822 +++ b/include/linux/pci.h
5823 @@ -1946,6 +1946,7 @@ void pcibios_release_device(struct pci_d
5824 void pcibios_penalize_isa_irq(int irq, int active);
5825 int pcibios_alloc_irq(struct pci_dev *dev);
5826 void pcibios_free_irq(struct pci_dev *dev);
5827 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
5828
5829 #ifdef CONFIG_HIBERNATE_CALLBACKS
5830 extern struct dev_pm_ops pcibios_pm_ops;
5831 --- a/include/uapi/linux/pcitest.h
5832 +++ b/include/uapi/linux/pcitest.h
5833 @@ -16,5 +16,8 @@
5834 #define PCITEST_WRITE _IOW('P', 0x4, unsigned long)
5835 #define PCITEST_READ _IOW('P', 0x5, unsigned long)
5836 #define PCITEST_COPY _IOW('P', 0x6, unsigned long)
5837 +#define PCITEST_MSIX _IOW('P', 0x7, int)
5838 +#define PCITEST_SET_IRQTYPE _IOW('P', 0x8, int)
5839 +#define PCITEST_GET_IRQTYPE _IO('P', 0x9)
5840
5841 #endif /* __UAPI_LINUX_PCITEST_H */
5842 --- a/tools/pci/pcitest.c
5843 +++ b/tools/pci/pcitest.c
5844 @@ -30,12 +30,17 @@
5845 #define BILLION 1E9
5846
5847 static char *result[] = { "NOT OKAY", "OKAY" };
5848 +static char *irq[] = { "LEGACY", "MSI", "MSI-X" };
5849
5850 struct pci_test {
5851 char *device;
5852 char barnum;
5853 bool legacyirq;
5854 unsigned int msinum;
5855 + unsigned int msixnum;
5856 + int irqtype;
5857 + bool set_irqtype;
5858 + bool get_irqtype;
5859 bool read;
5860 bool write;
5861 bool copy;
5862 @@ -62,6 +67,24 @@ static int run_test(struct pci_test *tes
5863 fprintf(stdout, "%s\n", result[ret]);
5864 }
5865
5866 + if (test->set_irqtype) {
5867 + ret = ioctl(fd, PCITEST_SET_IRQTYPE, test->irqtype);
5868 + fprintf(stdout, "SET IRQ TYPE TO %s:\t\t", irq[test->irqtype]);
5869 + if (ret < 0)
5870 + fprintf(stdout, "FAILED\n");
5871 + else
5872 + fprintf(stdout, "%s\n", result[ret]);
5873 + }
5874 +
5875 + if (test->get_irqtype) {
5876 + ret = ioctl(fd, PCITEST_GET_IRQTYPE);
5877 + fprintf(stdout, "GET IRQ TYPE:\t\t");
5878 + if (ret < 0)
5879 + fprintf(stdout, "FAILED\n");
5880 + else
5881 + fprintf(stdout, "%s\n", irq[ret]);
5882 + }
5883 +
5884 if (test->legacyirq) {
5885 ret = ioctl(fd, PCITEST_LEGACY_IRQ, 0);
5886 fprintf(stdout, "LEGACY IRQ:\t");
5887 @@ -80,6 +103,15 @@ static int run_test(struct pci_test *tes
5888 fprintf(stdout, "%s\n", result[ret]);
5889 }
5890
5891 + if (test->msixnum > 0 && test->msixnum <= 2048) {
5892 + ret = ioctl(fd, PCITEST_MSIX, test->msixnum);
5893 + fprintf(stdout, "MSI-X%d:\t\t", test->msixnum);
5894 + if (ret < 0)
5895 + fprintf(stdout, "TEST FAILED\n");
5896 + else
5897 + fprintf(stdout, "%s\n", result[ret]);
5898 + }
5899 +
5900 if (test->write) {
5901 ret = ioctl(fd, PCITEST_WRITE, test->size);
5902 fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
5903 @@ -130,7 +162,7 @@ int main(int argc, char **argv)
5904 /* set default endpoint device */
5905 test->device = "/dev/pci-endpoint-test.0";
5906
5907 - while ((c = getopt(argc, argv, "D:b:m:lrwcs:")) != EOF)
5908 + while ((c = getopt(argc, argv, "D:b:m:x:i:Ilrwcs:")) != EOF)
5909 switch (c) {
5910 case 'D':
5911 test->device = optarg;
5912 @@ -148,6 +180,20 @@ int main(int argc, char **argv)
5913 if (test->msinum < 1 || test->msinum > 32)
5914 goto usage;
5915 continue;
5916 + case 'x':
5917 + test->msixnum = atoi(optarg);
5918 + if (test->msixnum < 1 || test->msixnum > 2048)
5919 + goto usage;
5920 + continue;
5921 + case 'i':
5922 + test->irqtype = atoi(optarg);
5923 + if (test->irqtype < 0 || test->irqtype > 2)
5924 + goto usage;
5925 + test->set_irqtype = true;
5926 + continue;
5927 + case 'I':
5928 + test->get_irqtype = true;
5929 + continue;
5930 case 'r':
5931 test->read = true;
5932 continue;
5933 @@ -170,6 +216,9 @@ usage:
5934 "\t-D <dev> PCI endpoint test device {default: /dev/pci-endpoint-test.0}\n"
5935 "\t-b <bar num> BAR test (bar number between 0..5)\n"
5936 "\t-m <msi num> MSI test (msi number between 1..32)\n"
5937 + "\t-x <msix num> \tMSI-X test (msix number between 1..2048)\n"
5938 + "\t-i <irq type> \tSet IRQ type (0 - Legacy, 1 - MSI, 2 - MSI-X)\n"
5939 + "\t-I Get current IRQ type configured\n"
5940 "\t-l Legacy IRQ test\n"
5941 "\t-r Read buffer test\n"
5942 "\t-w Write buffer test\n"
5943 --- a/tools/pci/pcitest.sh
5944 +++ b/tools/pci/pcitest.sh
5945 @@ -16,7 +16,10 @@ echo
5946 echo "Interrupt tests"
5947 echo
5948
5949 +pcitest -i 0
5950 pcitest -l
5951 +
5952 +pcitest -i 1
5953 msi=1
5954
5955 while [ $msi -lt 33 ]
5956 @@ -26,9 +29,21 @@ do
5957 done
5958 echo
5959
5960 +pcitest -i 2
5961 +msix=1
5962 +
5963 +while [ $msix -lt 2049 ]
5964 +do
5965 + pcitest -x $msix
5966 + msix=`expr $msix + 1`
5967 +done
5968 +echo
5969 +
5970 echo "Read Tests"
5971 echo
5972
5973 +pcitest -i 1
5974 +
5975 pcitest -r -s 1
5976 pcitest -r -s 1024
5977 pcitest -r -s 1025
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