target/linux/layerscape/patches-4.4/1097-mtd-fsl-quadspi-use-the-property-fields-of-SPI-NOR.patch

   1 From 5c315652c1b43a6a3abe48c2842cde822ac0ff3c Mon Sep 17 00:00:00 2001
   2 From: Yunhui Cui <B56489@freescale.com>
   3 Date: Wed, 20 Jan 2016 18:40:31 +0800
   4 Subject: [PATCH 097/113] mtd:fsl-quadspi:use the property fields of SPI-NOR
   5
   6 We can get the read/write/erase opcode from the spi nor framework
   7 directly. This patch uses the information stored in the SPI-NOR to
   8 remove the hardcode in the fsl_qspi_init_lut().
   9
  10 Signed-off-by: Yunhui Cui <B56489@freescale.com>
  11 ---
  12  drivers/mtd/spi-nor/fsl-quadspi.c |   40 +++++++++++--------------------------
  13  1 file changed, 12 insertions(+), 28 deletions(-)
  14
  15 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
  16 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
  17 @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl
  18         void __iomem *base = q->iobase;
  19         int rxfifo = q->devtype_data->rxfifo;
  20         u32 lut_base;
  21 -       u8 cmd, addrlen, dummy;
  22         int i;
  23
  24 +       struct spi_nor *nor = &q->nor[0];
  25 +       u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
  26 +       u8 read_op = nor->read_opcode;
  27 +       u8 read_dm = nor->read_dummy;
  28 +
  29         fsl_qspi_unlock_lut(q);
  30
  31         /* Clear all the LUT table */
  32 @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl
  33         /* Quad Read */
  34         lut_base = SEQID_QUAD_READ * 4;
  35
  36 -       if (q->nor_size <= SZ_16M) {
  37 -               cmd = SPINOR_OP_READ_1_1_4;
  38 -               addrlen = ADDR24BIT;
  39 -               dummy = 8;
  40 -       } else {
  41 -               /* use the 4-byte address */
  42 -               cmd = SPINOR_OP_READ_1_1_4;
  43 -               addrlen = ADDR32BIT;
  44 -               dummy = 8;
  45 -       }
  46 -
  47 -       qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
  48 +       qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
  49                         base + QUADSPI_LUT(lut_base));
  50 -       qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
  51 +       qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
  52 +                   LUT1(FSL_READ, PAD4, rxfifo),
  53                         base + QUADSPI_LUT(lut_base + 1));
  54
  55         /* Write enable */
  56 @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl
  57         /* Page Program */
  58         lut_base = SEQID_PP * 4;
  59
  60 -       if (q->nor_size <= SZ_16M) {
  61 -               cmd = SPINOR_OP_PP;
  62 -               addrlen = ADDR24BIT;
  63 -       } else {
  64 -               /* use the 4-byte address */
  65 -               cmd = SPINOR_OP_PP;
  66 -               addrlen = ADDR32BIT;
  67 -       }
  68 -
  69 -       qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
  70 +       qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
  71 +                   LUT1(ADDR, PAD1, addrlen),
  72                         base + QUADSPI_LUT(lut_base));
  73         qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
  74                         base + QUADSPI_LUT(lut_base + 1));
  75 @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl
  76         /* Erase a sector */
  77         lut_base = SEQID_SE * 4;
  78
  79 -       cmd = q->nor[0].erase_opcode;
  80 -       addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
  81 -
  82 -       qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
  83 +       qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
  84 +                   LUT1(ADDR, PAD1, addrlen),
  85                         base + QUADSPI_LUT(lut_base));
  86
  87         /* Erase the whole chip */