target/linux/layerscape/patches-4.4/3001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch

   1 From 3ce895cbe3469bfcaa84674ec4f1b2d60e8b370b Mon Sep 17 00:00:00 2001
   2 From: Mingkai Hu <Mingkai.Hu@freescale.com>
   3 Date: Mon, 21 Jul 2014 14:48:42 +0800
   4 Subject: [PATCH 01/70] arm64/ls1043a: add DTS for Freescale LS1043A SoC
   5
   6 LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks
   7 similar to LS1021a which complies to Chassis 2.1 spec.
   8
   9 Following levels of DTSI/DTS files have been created for the
  10 LS1043A SoC family:
  11
  12 - fsl-ls1043a.dtsi:
  13   DTS-Include file for FSL LS1043A SoC.
  14
  15 Signed-off-by: Li Yang <leoli@freescale.com>
  16 Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
  17 Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
  18 Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
  19 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
  20 ---
  21  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  525 ++++++++++++++++++++++++
  22  1 file changed, 525 insertions(+)
  23  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
  24
  25 --- /dev/null
  26 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
  27 @@ -0,0 +1,525 @@
  28 +/*
  29 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  30 + *
  31 + * Copyright 2014-2015, Freescale Semiconductor
  32 + *
  33 + * Mingkai Hu <Mingkai.hu@freescale.com>
  34 + *
  35 + * This file is dual-licensed: you can use it either under the terms
  36 + * of the GPLv2 or the X11 license, at your option. Note that this dual
  37 + * licensing only applies to this file, and not this project as a
  38 + * whole.
  39 + *
  40 + *  a) This library is free software; you can redistribute it and/or
  41 + *     modify it under the terms of the GNU General Public License as
  42 + *     published by the Free Software Foundation; either version 2 of the
  43 + *     License, or (at your option) any later version.
  44 + *
  45 + *     This library is distributed in the hope that it will be useful,
  46 + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  47 + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  48 + *     GNU General Public License for more details.
  49 + *
  50 + * Or, alternatively,
  51 + *
  52 + *  b) Permission is hereby granted, free of charge, to any person
  53 + *     obtaining a copy of this software and associated documentation
  54 + *     files (the "Software"), to deal in the Software without
  55 + *     restriction, including without limitation the rights to use,
  56 + *     copy, modify, merge, publish, distribute, sublicense, and/or
  57 + *     sell copies of the Software, and to permit persons to whom the
  58 + *     Software is furnished to do so, subject to the following
  59 + *     conditions:
  60 + *
  61 + *     The above copyright notice and this permission notice shall be
  62 + *     included in all copies or substantial portions of the Software.
  63 + *
  64 + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  65 + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  66 + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  67 + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  68 + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  69 + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  70 + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  71 + *     OTHER DEALINGS IN THE SOFTWARE.
  72 + */
  73 +
  74 +/ {
  75 +       compatible = "fsl,ls1043a";
  76 +       interrupt-parent = <&gic>;
  77 +       #address-cells = <2>;
  78 +       #size-cells = <2>;
  79 +
  80 +       cpus {
  81 +               #address-cells = <2>;
  82 +               #size-cells = <0>;
  83 +
  84 +               /*
  85 +                * We expect the enable-method for cpu's to be "psci", but this
  86 +                * is dependent on the SoC FW, which will fill this in.
  87 +                *
  88 +                * Currently supported enable-method is psci v0.2
  89 +                */
  90 +               cpu0: cpu@0 {
  91 +                       device_type = "cpu";
  92 +                       compatible = "arm,cortex-a53";
  93 +                       reg = <0x0 0x0>;
  94 +                       clocks = <&clockgen 1 0>;
  95 +               };
  96 +
  97 +               cpu1: cpu@1 {
  98 +                       device_type = "cpu";
  99 +                       compatible = "arm,cortex-a53";
 100 +                       reg = <0x0 0x1>;
 101 +                       clocks = <&clockgen 1 0>;
 102 +               };
 103 +
 104 +               cpu2: cpu@2 {
 105 +                       device_type = "cpu";
 106 +                       compatible = "arm,cortex-a53";
 107 +                       reg = <0x0 0x2>;
 108 +                       clocks = <&clockgen 1 0>;
 109 +               };
 110 +
 111 +               cpu3: cpu@3 {
 112 +                       device_type = "cpu";
 113 +                       compatible = "arm,cortex-a53";
 114 +                       reg = <0x0 0x3>;
 115 +                       clocks = <&clockgen 1 0>;
 116 +               };
 117 +       };
 118 +
 119 +       memory@80000000 {
 120 +               device_type = "memory";
 121 +               reg = <0x0 0x80000000 0 0x80000000>;
 122 +                     /* DRAM space 1, size: 2GiB DRAM */
 123 +       };
 124 +
 125 +       sysclk: sysclk {
 126 +               compatible = "fixed-clock";
 127 +               #clock-cells = <0>;
 128 +               clock-frequency = <100000000>;
 129 +               clock-output-names = "sysclk";
 130 +       };
 131 +
 132 +       timer {
 133 +               compatible = "arm,armv8-timer";
 134 +               interrupts = <1 13 0x1>, /* Physical Secure PPI */
 135 +                            <1 14 0x1>, /* Physical Non-Secure PPI */
 136 +                            <1 11 0x1>, /* Virtual PPI */
 137 +                            <1 10 0x1>; /* Hypervisor PPI */
 138 +       };
 139 +
 140 +       pmu {
 141 +               compatible = "arm,armv8-pmuv3";
 142 +               interrupts = <0 106 0x4>,
 143 +                            <0 107 0x4>,
 144 +                            <0 95 0x4>,
 145 +                            <0 97 0x4>;
 146 +               interrupt-affinity = <&cpu0>,
 147 +                                    <&cpu1>,
 148 +                                    <&cpu2>,
 149 +                                    <&cpu3>;
 150 +       };
 151 +
 152 +       gic: interrupt-controller@1400000 {
 153 +               compatible = "arm,gic-400";
 154 +               #interrupt-cells = <3>;
 155 +               interrupt-controller;
 156 +               reg = <0x0 0x1401000 0 0x1000>, /* GICD */
 157 +                     <0x0 0x1402000 0 0x2000>, /* GICC */
 158 +                     <0x0 0x1404000 0 0x2000>, /* GICH */
 159 +                     <0x0 0x1406000 0 0x2000>; /* GICV */
 160 +               interrupts = <1 9 0xf08>;
 161 +       };
 162 +
 163 +       soc {
 164 +               compatible = "simple-bus";
 165 +               #address-cells = <2>;
 166 +               #size-cells = <2>;
 167 +               ranges;
 168 +
 169 +               clockgen: clocking@1ee1000 {
 170 +                       compatible = "fsl,ls1043a-clockgen";
 171 +                       reg = <0x0 0x1ee1000 0x0 0x1000>;
 172 +                       #clock-cells = <2>;
 173 +                       clocks = <&sysclk>;
 174 +               };
 175 +
 176 +               scfg: scfg@1570000 {
 177 +                       compatible = "fsl,ls1043a-scfg", "syscon";
 178 +                       reg = <0x0 0x1570000 0x0 0x10000>;
 179 +                       big-endian;
 180 +               };
 181 +
 182 +               dcfg: dcfg@1ee0000 {
 183 +                       compatible = "fsl,ls1043a-dcfg", "syscon";
 184 +                       reg = <0x0 0x1ee0000 0x0 0x10000>;
 185 +               };
 186 +
 187 +               ifc: ifc@1530000 {
 188 +                       compatible = "fsl,ifc", "simple-bus";
 189 +                       reg = <0x0 0x1530000 0x0 0x10000>;
 190 +                       interrupts = <0 43 0x4>;
 191 +               };
 192 +
 193 +               esdhc: esdhc@1560000 {
 194 +                       compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
 195 +                       reg = <0x0 0x1560000 0x0 0x10000>;
 196 +                       interrupts = <0 62 0x4>;
 197 +                       clock-frequency = <0>;
 198 +                       voltage-ranges = <1800 1800 3300 3300>;
 199 +                       sdhci,auto-cmd12;
 200 +                       big-endian;
 201 +                       bus-width = <4>;
 202 +               };
 203 +
 204 +               dspi0: dspi@2100000 {
 205 +                       compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 206 +                       #address-cells = <1>;
 207 +                       #size-cells = <0>;
 208 +                       reg = <0x0 0x2100000 0x0 0x10000>;
 209 +                       interrupts = <0 64 0x4>;
 210 +                       clock-names = "dspi";
 211 +                       clocks = <&clockgen 4 0>;
 212 +                       spi-num-chipselects = <5>;
 213 +                       big-endian;
 214 +                       status = "disabled";
 215 +               };
 216 +
 217 +               dspi1: dspi@2110000 {
 218 +                       compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 219 +                       #address-cells = <1>;
 220 +                       #size-cells = <0>;
 221 +                       reg = <0x0 0x2110000 0x0 0x10000>;
 222 +                       interrupts = <0 65 0x4>;
 223 +                       clock-names = "dspi";
 224 +                       clocks = <&clockgen 4 0>;
 225 +                       spi-num-chipselects = <5>;
 226 +                       big-endian;
 227 +                       status = "disabled";
 228 +               };
 229 +
 230 +               i2c0: i2c@2180000 {
 231 +                       compatible = "fsl,vf610-i2c";
 232 +                       #address-cells = <1>;
 233 +                       #size-cells = <0>;
 234 +                       reg = <0x0 0x2180000 0x0 0x10000>;
 235 +                       interrupts = <0 56 0x4>;
 236 +                       clock-names = "i2c";
 237 +                       clocks = <&clockgen 4 0>;
 238 +                       dmas = <&edma0 1 39>,
 239 +                              <&edma0 1 38>;
 240 +                       dma-names = "tx", "rx";
 241 +                       status = "disabled";
 242 +               };
 243 +
 244 +               i2c1: i2c@2190000 {
 245 +                       compatible = "fsl,vf610-i2c";
 246 +                       #address-cells = <1>;
 247 +                       #size-cells = <0>;
 248 +                       reg = <0x0 0x2190000 0x0 0x10000>;
 249 +                       interrupts = <0 57 0x4>;
 250 +                       clock-names = "i2c";
 251 +                       clocks = <&clockgen 4 0>;
 252 +                       status = "disabled";
 253 +               };
 254 +
 255 +               i2c2: i2c@21a0000 {
 256 +                       compatible = "fsl,vf610-i2c";
 257 +                       #address-cells = <1>;
 258 +                       #size-cells = <0>;
 259 +                       reg = <0x0 0x21a0000 0x0 0x10000>;
 260 +                       interrupts = <0 58 0x4>;
 261 +                       clock-names = "i2c";
 262 +                       clocks = <&clockgen 4 0>;
 263 +                       status = "disabled";
 264 +               };
 265 +
 266 +               i2c3: i2c@21b0000 {
 267 +                       compatible = "fsl,vf610-i2c";
 268 +                       #address-cells = <1>;
 269 +                       #size-cells = <0>;
 270 +                       reg = <0x0 0x21b0000 0x0 0x10000>;
 271 +                       interrupts = <0 59 0x4>;
 272 +                       clock-names = "i2c";
 273 +                       clocks = <&clockgen 4 0>;
 274 +                       status = "disabled";
 275 +               };
 276 +
 277 +               duart0: serial@21c0500 {
 278 +                       compatible = "fsl,ns16550", "ns16550a";
 279 +                       reg = <0x00 0x21c0500 0x0 0x100>;
 280 +                       interrupts = <0 54 0x4>;
 281 +                       clocks = <&clockgen 4 0>;
 282 +               };
 283 +
 284 +               duart1: serial@21c0600 {
 285 +                       compatible = "fsl,ns16550", "ns16550a";
 286 +                       reg = <0x00 0x21c0600 0x0 0x100>;
 287 +                       interrupts = <0 54 0x4>;
 288 +                       clocks = <&clockgen 4 0>;
 289 +               };
 290 +
 291 +               duart2: serial@21d0500 {
 292 +                       compatible = "fsl,ns16550", "ns16550a";
 293 +                       reg = <0x0 0x21d0500 0x0 0x100>;
 294 +                       interrupts = <0 55 0x4>;
 295 +                       clocks = <&clockgen 4 0>;
 296 +               };
 297 +
 298 +               duart3: serial@21d0600 {
 299 +                       compatible = "fsl,ns16550", "ns16550a";
 300 +                       reg = <0x0 0x21d0600 0x0 0x100>;
 301 +                       interrupts = <0 55 0x4>;
 302 +                       clocks = <&clockgen 4 0>;
 303 +               };
 304 +
 305 +               gpio1: gpio@2300000 {
 306 +                       compatible = "fsl,ls1043a-gpio";
 307 +                       reg = <0x0 0x2300000 0x0 0x10000>;
 308 +                       interrupts = <0 66 0x4>;
 309 +                       gpio-controller;
 310 +                       #gpio-cells = <2>;
 311 +                       interrupt-controller;
 312 +                       #interrupt-cells = <2>;
 313 +               };
 314 +
 315 +               gpio2: gpio@2310000 {
 316 +                       compatible = "fsl,ls1043a-gpio";
 317 +                       reg = <0x0 0x2310000 0x0 0x10000>;
 318 +                       interrupts = <0 67 0x4>;
 319 +                       gpio-controller;
 320 +                       #gpio-cells = <2>;
 321 +                       interrupt-controller;
 322 +                       #interrupt-cells = <2>;
 323 +               };
 324 +
 325 +               gpio3: gpio@2320000 {
 326 +                       compatible = "fsl,ls1043a-gpio";
 327 +                       reg = <0x0 0x2320000 0x0 0x10000>;
 328 +                       interrupts = <0 68 0x4>;
 329 +                       gpio-controller;
 330 +                       #gpio-cells = <2>;
 331 +                       interrupt-controller;
 332 +                       #interrupt-cells = <2>;
 333 +               };
 334 +
 335 +               gpio4: gpio@2330000 {
 336 +                       compatible = "fsl,ls1043a-gpio";
 337 +                       reg = <0x0 0x2330000 0x0 0x10000>;
 338 +                       interrupts = <0 134 0x4>;
 339 +                       gpio-controller;
 340 +                       #gpio-cells = <2>;
 341 +                       interrupt-controller;
 342 +                       #interrupt-cells = <2>;
 343 +               };
 344 +
 345 +               lpuart0: serial@2950000 {
 346 +                       compatible = "fsl,ls1021a-lpuart";
 347 +                       reg = <0x0 0x2950000 0x0 0x1000>;
 348 +                       interrupts = <0 48 0x4>;
 349 +                       clocks = <&clockgen 0 0>;
 350 +                       clock-names = "ipg";
 351 +                       status = "disabled";
 352 +               };
 353 +
 354 +               lpuart1: serial@2960000 {
 355 +                       compatible = "fsl,ls1021a-lpuart";
 356 +                       reg = <0x0 0x2960000 0x0 0x1000>;
 357 +                       interrupts = <0 49 0x4>;
 358 +                       clocks = <&clockgen 4 0>;
 359 +                       clock-names = "ipg";
 360 +                       status = "disabled";
 361 +               };
 362 +
 363 +               lpuart2: serial@2970000 {
 364 +                       compatible = "fsl,ls1021a-lpuart";
 365 +                       reg = <0x0 0x2970000 0x0 0x1000>;
 366 +                       interrupts = <0 50 0x4>;
 367 +                       clocks = <&clockgen 4 0>;
 368 +                       clock-names = "ipg";
 369 +                       status = "disabled";
 370 +               };
 371 +
 372 +               lpuart3: serial@2980000 {
 373 +                       compatible = "fsl,ls1021a-lpuart";
 374 +                       reg = <0x0 0x2980000 0x0 0x1000>;
 375 +                       interrupts = <0 51 0x4>;
 376 +                       clocks = <&clockgen 4 0>;
 377 +                       clock-names = "ipg";
 378 +                       status = "disabled";
 379 +               };
 380 +
 381 +               lpuart4: serial@2990000 {
 382 +                       compatible = "fsl,ls1021a-lpuart";
 383 +                       reg = <0x0 0x2990000 0x0 0x1000>;
 384 +                       interrupts = <0 52 0x4>;
 385 +                       clocks = <&clockgen 4 0>;
 386 +                       clock-names = "ipg";
 387 +                       status = "disabled";
 388 +               };
 389 +
 390 +               lpuart5: serial@29a0000 {
 391 +                       compatible = "fsl,ls1021a-lpuart";
 392 +                       reg = <0x0 0x29a0000 0x0 0x1000>;
 393 +                       interrupts = <0 53 0x4>;
 394 +                       clocks = <&clockgen 4 0>;
 395 +                       clock-names = "ipg";
 396 +                       status = "disabled";
 397 +               };
 398 +
 399 +               wdog0: wdog@2ad0000 {
 400 +                       compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
 401 +                       reg = <0x0 0x2ad0000 0x0 0x10000>;
 402 +                       interrupts = <0 83 0x4>;
 403 +                       clocks = <&clockgen 4 0>;
 404 +                       clock-names = "wdog";
 405 +                       big-endian;
 406 +               };
 407 +
 408 +               edma0: edma@2c00000 {
 409 +                       #dma-cells = <2>;
 410 +                       compatible = "fsl,vf610-edma";
 411 +                       reg = <0x0 0x2c00000 0x0 0x10000>,
 412 +                             <0x0 0x2c10000 0x0 0x10000>,
 413 +                             <0x0 0x2c20000 0x0 0x10000>;
 414 +                       interrupts = <0 103 0x4>,
 415 +                                    <0 103 0x4>;
 416 +                       interrupt-names = "edma-tx", "edma-err";
 417 +                       dma-channels = <32>;
 418 +                       big-endian;
 419 +                       clock-names = "dmamux0", "dmamux1";
 420 +                       clocks = <&clockgen 4 0>,
 421 +                                <&clockgen 4 0>;
 422 +               };
 423 +
 424 +               usb0: usb3@2f00000 {
 425 +                       compatible = "snps,dwc3";
 426 +                       reg = <0x0 0x2f00000 0x0 0x10000>;
 427 +                       interrupts = <0 60 0x4>;
 428 +                       dr_mode = "host";
 429 +               };
 430 +
 431 +               usb1: usb3@3000000 {
 432 +                       compatible = "snps,dwc3";
 433 +                       reg = <0x0 0x3000000 0x0 0x10000>;
 434 +                       interrupts = <0 61 0x4>;
 435 +                       dr_mode = "host";
 436 +               };
 437 +
 438 +               usb2: usb3@3100000 {
 439 +                       compatible = "snps,dwc3";
 440 +                       reg = <0x0 0x3100000 0x0 0x10000>;
 441 +                       interrupts = <0 63 0x4>;
 442 +                       dr_mode = "host";
 443 +               };
 444 +
 445 +               sata: sata@3200000 {
 446 +                       compatible = "fsl,ls1043a-ahci";
 447 +                       reg = <0x0 0x3200000 0x0 0x10000>;
 448 +                       interrupts = <0 69 0x4>;
 449 +                       clocks = <&clockgen 4 0>;
 450 +               };
 451 +
 452 +               msi1: msi-controller1@1571000 {
 453 +                       compatible = "fsl,1s1043a-msi";
 454 +                       reg = <0x0 0x1571000 0x0 0x4>,
 455 +                             <0x0 0x1571004 0x0 0x4>;
 456 +                       reg-names = "msiir", "msir";
 457 +                       msi-controller;
 458 +                       interrupts = <0 116 0x4>;
 459 +               };
 460 +
 461 +               msi2: msi-controller2@1572000 {
 462 +                       compatible = "fsl,1s1043a-msi";
 463 +                       reg = <0x0 0x1572000 0x0 0x4>,
 464 +                             <0x0 0x1572004 0x0 0x4>;
 465 +                       reg-names = "msiir", "msir";
 466 +                       msi-controller;
 467 +                       interrupts = <0 126 0x4>;
 468 +               };
 469 +
 470 +               msi3: msi-controller3@1573000 {
 471 +                       compatible = "fsl,1s1043a-msi";
 472 +                       reg = <0x0 0x1573000 0x0 0x4>,
 473 +                             <0x0 0x1573004 0x0 0x4>;
 474 +                       reg-names = "msiir", "msir";
 475 +                       msi-controller;
 476 +                       interrupts = <0 160 0x4>;
 477 +               };
 478 +
 479 +               pcie@3400000 {
 480 +                       compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 481 +                       reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 482 +                              0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 483 +                       reg-names = "regs", "config";
 484 +                       interrupts = <0 118 0x4>, /* controller interrupt */
 485 +                                    <0 117 0x4>; /* PME interrupt */
 486 +                       interrupt-names = "intr", "pme";
 487 +                       #address-cells = <3>;
 488 +                       #size-cells = <2>;
 489 +                       device_type = "pci";
 490 +                       num-lanes = <4>;
 491 +                       bus-range = <0x0 0xff>;
 492 +                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 493 +                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 494 +                       msi-parent = <&msi1>;
 495 +                       #interrupt-cells = <1>;
 496 +                       interrupt-map-mask = <0 0 0 7>;
 497 +                       interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
 498 +                                       <0000 0 0 2 &gic 0 111 0x4>,
 499 +                                       <0000 0 0 3 &gic 0 112 0x4>,
 500 +                                       <0000 0 0 4 &gic 0 113 0x4>;
 501 +               };
 502 +
 503 +               pcie@3500000 {
 504 +                       compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 505 +                       reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 506 +                              0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 507 +                       reg-names = "regs", "config";
 508 +                       interrupts = <0 128 0x4>,
 509 +                                    <0 127 0x4>;
 510 +                       interrupt-names = "intr", "pme";
 511 +                       #address-cells = <3>;
 512 +                       #size-cells = <2>;
 513 +                       device_type = "pci";
 514 +                       num-lanes = <2>;
 515 +                       bus-range = <0x0 0xff>;
 516 +                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 517 +                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 518 +                       msi-parent = <&msi2>;
 519 +                       #interrupt-cells = <1>;
 520 +                       interrupt-map-mask = <0 0 0 7>;
 521 +                       interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
 522 +                                       <0000 0 0 2 &gic 0 121 0x4>,
 523 +                                       <0000 0 0 3 &gic 0 122 0x4>,
 524 +                                       <0000 0 0 4 &gic 0 123 0x4>;
 525 +               };
 526 +
 527 +               pcie@3600000 {
 528 +                       compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 529 +                       reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 530 +                              0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 531 +                       reg-names = "regs", "config";
 532 +                       interrupts = <0 162 0x4>,
 533 +                                    <0 161 0x4>;
 534 +                       interrupt-names = "intr", "pme";
 535 +                       #address-cells = <3>;
 536 +                       #size-cells = <2>;
 537 +                       device_type = "pci";
 538 +                       num-lanes = <2>;
 539 +                       bus-range = <0x0 0xff>;
 540 +                       ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 541 +                                 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 542 +                       msi-parent = <&msi3>;
 543 +                       #interrupt-cells = <1>;
 544 +                       interrupt-map-mask = <0 0 0 7>;
 545 +                       interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
 546 +                                       <0000 0 0 2 &gic 0 155 0x4>,
 547 +                                       <0000 0 0 3 &gic 0 156 0x4>,
 548 +                                       <0000 0 0 4 &gic 0 157 0x4>;
 549 +               };
 550 +       };
 551 +
 552 +};