target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch

   1 From 3970a709eb4c25e298e11cfe0ea7412bb2139197 Mon Sep 17 00:00:00 2001
   2 From: Alison Wang <alison.wang@nxp.com>
   3 Date: Fri, 8 Jul 2016 10:50:46 +0800
   4 Subject: [PATCH 03/70] arm64: dts: Update address-cells and reg properties of
   5  cpu nodes
   6
   7 commit 67161e229a59faf81732892b45a9ab3bae62ea18
   8 [context adjustment]
   9
  10 MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
  11 LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
  12 since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
  13 the #address-cells and reg properties accordingly.
  14
  15 Signed-off-by: Alison Wang <alison.wang@nxp.com>
  16 Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
  17 ---
  18  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |   10 +++++-----
  19  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |   18 +++++++++---------
  20  2 files changed, 14 insertions(+), 14 deletions(-)
  21
  22 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
  23 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
  24 @@ -51,7 +51,7 @@
  25         #size-cells = <2>;
  26
  27         cpus {
  28 -               #address-cells = <2>;
  29 +               #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 /*
  33 @@ -63,28 +63,28 @@
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53";
  37 -                       reg = <0x0 0x0>;
  38 +                       reg = <0x0>;
  39                         clocks = <&clockgen 1 0>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53";
  45 -                       reg = <0x0 0x1>;
  46 +                       reg = <0x1>;
  47                         clocks = <&clockgen 1 0>;
  48                 };
  49
  50                 cpu2: cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53";
  53 -                       reg = <0x0 0x2>;
  54 +                       reg = <0x2>;
  55                         clocks = <&clockgen 1 0>;
  56                 };
  57
  58                 cpu3: cpu@3 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53";
  61 -                       reg = <0x0 0x3>;
  62 +                       reg = <0x3>;
  63                         clocks = <&clockgen 1 0>;
  64                 };
  65         };
  66 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
  67 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
  68 @@ -51,7 +51,7 @@
  69         #size-cells = <2>;
  70
  71         cpus {
  72 -               #address-cells = <2>;
  73 +               #address-cells = <1>;
  74                 #size-cells = <0>;
  75
  76                 /*
  77 @@ -65,56 +65,56 @@
  78                 cpu@0 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a57";
  81 -                       reg = <0x0 0x0>;
  82 +                       reg = <0x0>;
  83                         clocks = <&clockgen 1 0>;
  84                 };
  85
  86                 cpu@1 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a57";
  89 -                       reg = <0x0 0x1>;
  90 +                       reg = <0x1>;
  91                         clocks = <&clockgen 1 0>;
  92                 };
  93
  94                 cpu@100 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a57";
  97 -                       reg = <0x0 0x100>;
  98 +                       reg = <0x100>;
  99                         clocks = <&clockgen 1 1>;
 100                 };
 101
 102                 cpu@101 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a57";
 105 -                       reg = <0x0 0x101>;
 106 +                       reg = <0x101>;
 107                         clocks = <&clockgen 1 1>;
 108                 };
 109
 110                 cpu@200 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a57";
 113 -                       reg = <0x0 0x200>;
 114 +                       reg = <0x200>;
 115                         clocks = <&clockgen 1 2>;
 116                 };
 117
 118                 cpu@201 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a57";
 121 -                       reg = <0x0 0x201>;
 122 +                       reg = <0x201>;
 123                         clocks = <&clockgen 1 2>;
 124                 };
 125
 126                 cpu@300 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a57";
 129 -                       reg = <0x0 0x300>;
 130 +                       reg = <0x300>;
 131                         clocks = <&clockgen 1 3>;
 132                 };
 133
 134                 cpu@301 {
 135                         device_type = "cpu";
 136                         compatible = "arm,cortex-a57";
 137 -                       reg = <0x0 0x301>;
 138 +                       reg = <0x301>;
 139                         clocks = <&clockgen 1 3>;
 140                 };
 141         };