target/linux/layerscape/patches-4.4/3135-arm64-Add-DTS-support-for-FSL-s-LS1088ARDB.patch

   1 From cbacf87fa6fb262c98033405f15697798c3a9c5d Mon Sep 17 00:00:00 2001
   2 From: Zhao Qiang <qiang.zhao@nxp.com>
   3 Date: Sun, 9 Oct 2016 14:31:50 +0800
   4 Subject: [PATCH 135/141] arm64: Add DTS support for FSL's LS1088ARDB
   5
   6 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
   7 ---
   8  arch/arm64/boot/dts/freescale/Makefile            |    1 +
   9  arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts |  203 ++++++++
  10  arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi    |  557 +++++++++++++++++++++
  11  3 files changed, 761 insertions(+)
  12  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
  13  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
  14
  15 --- a/arch/arm64/boot/dts/freescale/Makefile
  16 +++ b/arch/arm64/boot/dts/freescale/Makefile
  17 @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
  18  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
  19  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
  20  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
  21 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
  22
  23  always         := $(dtb-y)
  24  subdir-y       := $(dts-dirs)
  25 --- /dev/null
  26 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
  27 @@ -0,0 +1,203 @@
  28 +/*
  29 + * Device Tree file for Freescale LS1088a RDB board
  30 + *
  31 + * Copyright (C) 2015, Freescale Semiconductor
  32 + *
  33 + * This file is licensed under the terms of the GNU General Public
  34 + * License version 2.  This program is licensed "as is" without any
  35 + * warranty of any kind, whether express or implied.
  36 + */
  37 +
  38 +/dts-v1/;
  39 +
  40 +#include "fsl-ls1088a.dtsi"
  41 +
  42 +/ {
  43 +       model = "Freescale Layerscape 1088a RDB Board";
  44 +       compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
  45 +};
  46 +
  47 +&esdhc {
  48 +       status = "okay";
  49 +};
  50 +
  51 +&ifc {
  52 +       status = "disabled";
  53 +};
  54 +
  55 +&ftm0 {
  56 +       status = "okay";
  57 +};
  58 +
  59 +&i2c0 {
  60 +       status = "okay";
  61 +       pca9547@77 {
  62 +               compatible = "philips,pca9547";
  63 +               reg = <0x77>;
  64 +               #address-cells = <1>;
  65 +               #size-cells = <0>;
  66 +
  67 +               i2c@2 {
  68 +                       #address-cells = <1>;
  69 +                       #size-cells = <0>;
  70 +                       reg = <0x2>;
  71 +
  72 +                       ina220@40 {
  73 +                               compatible = "ti,ina220";
  74 +                               reg = <0x40>;
  75 +                               shunt-resistor = <1000>;
  76 +                       };
  77 +               };
  78 +
  79 +               i2c@3 {
  80 +                       #address-cells = <1>;
  81 +                       #size-cells = <0>;
  82 +                       reg = <0x3>;
  83 +
  84 +                       rtc@51 {
  85 +                               compatible = "nxp,pcf2129";
  86 +                               reg = <0x51>;
  87 +                               /* IRQ10_B */
  88 +                               interrupts = <0 150 0x4>;
  89 +                       };
  90 +
  91 +                       adt7461a@4c {
  92 +                               compatible = "adt7461a";
  93 +                               reg = <0x4c>;
  94 +                       };
  95 +               };
  96 +       };
  97 +};
  98 +
  99 +&i2c1 {
 100 +       status = "disabled";
 101 +};
 102 +
 103 +&i2c2 {
 104 +       status = "disabled";
 105 +};
 106 +
 107 +&i2c3 {
 108 +       status = "disabled";
 109 +};
 110 +
 111 +&dspi {
 112 +       status = "disabled";
 113 +};
 114 +
 115 +&qspi {
 116 +       status = "okay";
 117 +       qflash0: s25fs512s@0 {
 118 +               compatible = "spansion,m25p80";
 119 +               #address-cells = <1>;
 120 +               #size-cells = <1>;
 121 +               spi-max-frequency = <20000000>;
 122 +               reg = <0>;
 123 +       };
 124 +
 125 +       qflash1: s25fs512s@1 {
 126 +               compatible = "spansion,m25p80";
 127 +               #address-cells = <1>;
 128 +               #size-cells = <1>;
 129 +               spi-max-frequency = <20000000>;
 130 +               reg = <1>;
 131 +       };
 132 +};
 133 +
 134 +&sata0 {
 135 +       status = "okay";
 136 +};
 137 +
 138 +&usb0 {
 139 +       status = "okay";
 140 +};
 141 +
 142 +&usb1 {
 143 +       status = "okay";
 144 +};
 145 +
 146 +&serial0 {
 147 +       status = "okay";
 148 +};
 149 +
 150 +&serial1 {
 151 +       status = "okay";
 152 +};
 153 +
 154 +&emdio1 {
 155 +       /* Freescale F104 PHY1 */
 156 +       mdio1_phy1: emdio1_phy@1 {
 157 +               reg = <0x1c>;
 158 +               phy-connection-type = "qsgmii";
 159 +       };
 160 +       mdio1_phy2: emdio1_phy@2 {
 161 +               reg = <0x1d>;
 162 +               phy-connection-type = "qsgmii";
 163 +       };
 164 +       mdio1_phy3: emdio1_phy@3 {
 165 +               reg = <0x1e>;
 166 +               phy-connection-type = "qsgmii";
 167 +       };
 168 +       mdio1_phy4: emdio1_phy@4 {
 169 +               reg = <0x1f>;
 170 +               phy-connection-type = "qsgmii";
 171 +       };
 172 +       /* F104 PHY2 */
 173 +       mdio1_phy5: emdio1_phy@5 {
 174 +               reg = <0x0c>;
 175 +               phy-connection-type = "qsgmii";
 176 +       };
 177 +       mdio1_phy6: emdio1_phy@6 {
 178 +               reg = <0x0d>;
 179 +               phy-connection-type = "qsgmii";
 180 +       };
 181 +       mdio1_phy7: emdio1_phy@7 {
 182 +               reg = <0x0e>;
 183 +               phy-connection-type = "qsgmii";
 184 +       };
 185 +       mdio1_phy8: emdio1_phy@8 {
 186 +               reg = <0x0f>;
 187 +               phy-connection-type = "qsgmii";
 188 +       };
 189 +};
 190 +
 191 +&emdio2 {
 192 +       /* Aquantia AQR105 10G PHY */
 193 +       mdio2_phy1: emdio2_phy@1 {
 194 +               compatible = "ethernet-phy-ieee802.3-c45";
 195 +               reg = <0x0>;
 196 +               phy-connection-type = "xfi";
 197 +       };
 198 +};
 199 +
 200 +/* DPMAC connections to external PHYs
 201 + * based on LS1088A RM RevC - $24.1.2 SerDes Options
 202 + */
 203 +/* DPMAC1 is 10G SFP+, fixed link */
 204 +&dpmac2 {
 205 +       phy-handle = <&mdio2_phy1>;
 206 +};
 207 +&dpmac3 {
 208 +       phy-handle = <&mdio1_phy5>;
 209 +};
 210 +&dpmac4 {
 211 +       phy-handle = <&mdio1_phy6>;
 212 +};
 213 +&dpmac5 {
 214 +       phy-handle = <&mdio1_phy7>;
 215 +};
 216 +&dpmac6 {
 217 +       phy-handle = <&mdio1_phy8>;
 218 +};
 219 +&dpmac7 {
 220 +       phy-handle = <&mdio1_phy1>;
 221 +};
 222 +&dpmac8 {
 223 +       phy-handle = <&mdio1_phy2>;
 224 +};
 225 +&dpmac9 {
 226 +       phy-handle = <&mdio1_phy3>;
 227 +};
 228 +&dpmac10 {
 229 +       phy-handle = <&mdio1_phy4>;
 230 +};
 231 --- /dev/null
 232 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
 233 @@ -0,0 +1,557 @@
 234 +/*
 235 + * Device Tree Include file for Freescale Layerscape-1088A family SoC.
 236 + *
 237 + * Copyright (C) 2015, Freescale Semiconductor
 238 + *
 239 + */
 240 +
 241 +/memreserve/ 0x80000000 0x00010000;
 242 +
 243 +/ {
 244 +       compatible = "fsl,ls1088a";
 245 +       interrupt-parent = <&gic>;
 246 +       #address-cells = <2>;
 247 +       #size-cells = <2>;
 248 +
 249 +       cpus {
 250 +               #address-cells = <2>;
 251 +               #size-cells = <0>;
 252 +
 253 +               /* We have 2 clusters having 4 Cortex-A57 cores each */
 254 +               cpu0: cpu@0 {
 255 +                       device_type = "cpu";
 256 +                       compatible = "arm,cortex-a53";
 257 +                       reg = <0x0 0x0>;
 258 +                       clocks = <&clockgen 1 0>;
 259 +               };
 260 +
 261 +               cpu1: cpu@1 {
 262 +                       device_type = "cpu";
 263 +                       compatible = "arm,cortex-a53";
 264 +                       reg = <0x0 0x1>;
 265 +                       clocks = <&clockgen 1 0>;
 266 +               };
 267 +
 268 +               cpu2: cpu@2 {
 269 +                       device_type = "cpu";
 270 +                       compatible = "arm,cortex-a53";
 271 +                       reg = <0x0 0x2>;
 272 +                       clocks = <&clockgen 1 0>;
 273 +               };
 274 +
 275 +               cpu3: cpu@3 {
 276 +                       device_type = "cpu";
 277 +                       compatible = "arm,cortex-a53";
 278 +                       reg = <0x0 0x3>;
 279 +                       clocks = <&clockgen 1 0>;
 280 +               };
 281 +
 282 +               cpu4: cpu@100 {
 283 +                       device_type = "cpu";
 284 +                       compatible = "arm,cortex-a53";
 285 +                       reg = <0x0 0x100>;
 286 +                       clocks = <&clockgen 1 1>;
 287 +               };
 288 +
 289 +               cpu5: cpu@101 {
 290 +                       device_type = "cpu";
 291 +                       compatible = "arm,cortex-a53";
 292 +                       reg = <0x0 0x101>;
 293 +                       clocks = <&clockgen 1 1>;
 294 +               };
 295 +
 296 +               cpu6: cpu@102 {
 297 +                       device_type = "cpu";
 298 +                       compatible = "arm,cortex-a53";
 299 +                       reg = <0x0 0x102>;
 300 +                       clocks = <&clockgen 1 1>;
 301 +               };
 302 +
 303 +               cpu7: cpu@103 {
 304 +                       device_type = "cpu";
 305 +                       compatible = "arm,cortex-a53";
 306 +                       reg = <0x0 0x103>;
 307 +                       clocks = <&clockgen 1 1>;
 308 +               };
 309 +       };
 310 +
 311 +       pmu {
 312 +               compatible = "arm,armv8-pmuv3";
 313 +               interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
 314 +       };
 315 +
 316 +       gic: interrupt-controller@6000000 {
 317 +               compatible = "arm,gic-v3";
 318 +               reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 319 +                     <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
 320 +                     <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 321 +                     <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 322 +                     <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 323 +               #interrupt-cells = <3>;
 324 +               #address-cells = <2>;
 325 +               #size-cells = <2>;
 326 +               ranges;
 327 +               interrupt-controller;
 328 +               interrupts = <1 9 0x4>;
 329 +
 330 +               its: gic-its@6020000 {
 331 +                       compatible = "arm,gic-v3-its";
 332 +                       msi-controller;
 333 +                       reg = <0x0 0x6020000 0 0x20000>;
 334 +               };
 335 +       };
 336 +
 337 +       sysclk: sysclk {
 338 +               compatible = "fixed-clock";
 339 +               #clock-cells = <0>;
 340 +               clock-frequency = <100000000>;
 341 +               clock-output-names = "sysclk";
 342 +       };
 343 +
 344 +       clockgen: clocking@1300000 {
 345 +               compatible = "fsl,ls2080a-clockgen", "fsl,ls1088a-clockgen";
 346 +               reg = <0 0x1300000 0 0xa0000>;
 347 +               #clock-cells = <2>;
 348 +               clocks = <&sysclk>;
 349 +       };
 350 +
 351 +       serial0: serial@21c0500 {
 352 +               device_type = "serial";
 353 +               compatible = "fsl,ns16550", "ns16550a";
 354 +               reg = <0x0 0x21c0500 0x0 0x100>;
 355 +               clocks = <&clockgen 4 3>;
 356 +               interrupts = <0 32 0x4>; /* Level high type */
 357 +       };
 358 +
 359 +       serial1: serial@21c0600 {
 360 +               device_type = "serial";
 361 +               compatible = "fsl,ns16550", "ns16550a";
 362 +               reg = <0x0 0x21c0600 0x0 0x100>;
 363 +               clocks = <&clockgen 4 3>;
 364 +               interrupts = <0 32 0x4>; /* Level high type */
 365 +       };
 366 +
 367 +       gpio0: gpio@2300000 {
 368 +               compatible = "fsl,qoriq-gpio";
 369 +               reg = <0x0 0x2300000 0x0 0x10000>;
 370 +               interrupts = <0 36 0x4>; /* Level high type */
 371 +               gpio-controller;
 372 +               little-endian;
 373 +               #gpio-cells = <2>;
 374 +               interrupt-controller;
 375 +               #interrupt-cells = <2>;
 376 +       };
 377 +
 378 +       gpio1: gpio@2310000 {
 379 +               compatible = "fsl,qoriq-gpio";
 380 +               reg = <0x0 0x2310000 0x0 0x10000>;
 381 +               interrupts = <0 36 0x4>; /* Level high type */
 382 +               gpio-controller;
 383 +               little-endian;
 384 +               #gpio-cells = <2>;
 385 +               interrupt-controller;
 386 +               #interrupt-cells = <2>;
 387 +       };
 388 +
 389 +       gpio2: gpio@2320000 {
 390 +               compatible = "fsl,qoriq-gpio";
 391 +               reg = <0x0 0x2320000 0x0 0x10000>;
 392 +               interrupts = <0 37 0x4>; /* Level high type */
 393 +               gpio-controller;
 394 +               little-endian;
 395 +               #gpio-cells = <2>;
 396 +               interrupt-controller;
 397 +               #interrupt-cells = <2>;
 398 +       };
 399 +
 400 +       gpio3: gpio@2330000 {
 401 +               compatible = "fsl,qoriq-gpio";
 402 +               reg = <0x0 0x2330000 0x0 0x10000>;
 403 +               interrupts = <0 37 0x4>; /* Level high type */
 404 +               gpio-controller;
 405 +               little-endian;
 406 +               #gpio-cells = <2>;
 407 +               interrupt-controller;
 408 +               #interrupt-cells = <2>;
 409 +       };
 410 +
 411 +       /* TODO: WRIOP (CCSR?) */
 412 +       emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
 413 +               compatible = "fsl,fman-memac-mdio";
 414 +               reg = <0x0 0x8B96000 0x0 0x1000>;
 415 +               device_type = "mdio";
 416 +               little-endian;  /* force the driver in LE mode */
 417 +
 418 +               /* Not necessary on the QDS, but needed on the RDB */
 419 +               #address-cells = <1>;
 420 +               #size-cells = <0>;
 421 +       };
 422 +
 423 +       emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
 424 +               compatible = "fsl,fman-memac-mdio";
 425 +               reg = <0x0 0x8B97000 0x0 0x1000>;
 426 +               device_type = "mdio";
 427 +               little-endian;  /* force the driver in LE mode */
 428 +
 429 +               #address-cells = <1>;
 430 +               #size-cells = <0>;
 431 +       };
 432 +
 433 +       ifc: ifc@2240000 {
 434 +               compatible = "fsl,ifc", "simple-bus";
 435 +               reg = <0x0 0x2240000 0x0 0x20000>;
 436 +               interrupts = <0 21 0x4>; /* Level high type */
 437 +               little-endian;
 438 +               #address-cells = <2>;
 439 +               #size-cells = <1>;
 440 +
 441 +               ranges = <0 0 0x5 0x80000000 0x08000000
 442 +                         2 0 0x5 0x30000000 0x00010000
 443 +                         3 0 0x5 0x20000000 0x00010000>;
 444 +       };
 445 +
 446 +       esdhc: esdhc@2140000 {
 447 +               compatible = "fsl,ls2080a-esdhc", "fsl,ls1088a-esdhc", "fsl,esdhc";
 448 +               reg = <0x0 0x2140000 0x0 0x10000>;
 449 +               interrupts = <0 28 0x4>; /* Level high type */
 450 +               clock-frequency = <0>;
 451 +               voltage-ranges = <1800 1800 3300 3300>;
 452 +               sdhci,auto-cmd12;
 453 +               little-endian;
 454 +               bus-width = <4>;
 455 +       };
 456 +
 457 +       ftm0: ftm0@2800000 {
 458 +               compatible = "fsl,ftm-alarm";
 459 +               reg = <0x0 0x2800000 0x0 0x10000>;
 460 +               interrupts = <0 44 4>;
 461 +       };
 462 +
 463 +       reset: reset@1E60000 {
 464 +               compatible = "fsl,ls-reset";
 465 +               reg = <0x0 0x1E60000 0x0 0x10000>;
 466 +       };
 467 +
 468 +       dspi: dspi@2100000 {
 469 +               compatible = "fsl,ls2085a-dspi", "fsl,ls1088a-dspi";
 470 +               #address-cells = <1>;
 471 +               #size-cells = <0>;
 472 +               reg = <0x0 0x2100000 0x0 0x10000>;
 473 +               interrupts = <0 26 0x4>; /* Level high type */
 474 +               clocks = <&clockgen 4 3>;
 475 +               clock-names = "dspi";
 476 +               spi-num-chipselects = <5>;
 477 +               bus-num = <0>;
 478 +       };
 479 +
 480 +       i2c0: i2c@2000000 {
 481 +               compatible = "fsl,vf610-i2c";
 482 +               #address-cells = <1>;
 483 +               #size-cells = <0>;
 484 +               reg = <0x0 0x2000000 0x0 0x10000>;
 485 +               interrupts = <0 34 0x4>; /* Level high type */
 486 +               clock-names = "i2c";
 487 +               clocks = <&clockgen 4 3>;
 488 +       };
 489 +
 490 +       i2c1: i2c@2010000 {
 491 +               compatible = "fsl,vf610-i2c";
 492 +               #address-cells = <1>;
 493 +               #size-cells = <0>;
 494 +               reg = <0x0 0x2010000 0x0 0x10000>;
 495 +               interrupts = <0 34 0x4>; /* Level high type */
 496 +               clock-names = "i2c";
 497 +               clocks = <&clockgen 4 3>;
 498 +       };
 499 +
 500 +       i2c2: i2c@2020000 {
 501 +               compatible = "fsl,vf610-i2c";
 502 +               #address-cells = <1>;
 503 +               #size-cells = <0>;
 504 +               reg = <0x0 0x2020000 0x0 0x10000>;
 505 +               interrupts = <0 35 0x4>; /* Level high type */
 506 +               clock-names = "i2c";
 507 +               clocks = <&clockgen 4 3>;
 508 +       };
 509 +
 510 +       i2c3: i2c@2030000 {
 511 +               compatible = "fsl,vf610-i2c";
 512 +               #address-cells = <1>;
 513 +               #size-cells = <0>;
 514 +               reg = <0x0 0x2030000 0x0 0x10000>;
 515 +               interrupts = <0 35 0x4>; /* Level high type */
 516 +               clock-names = "i2c";
 517 +               clocks = <&clockgen 4 3>;
 518 +       };
 519 +
 520 +       qspi: quadspi@20c0000 {
 521 +               compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
 522 +               #address-cells = <1>;
 523 +               #size-cells = <0>;
 524 +               reg = <0x0 0x20c0000 0x0 0x10000>,
 525 +                     <0x0 0x20000000 0x0 0x10000000>;
 526 +               reg-names = "QuadSPI", "QuadSPI-memory";
 527 +               interrupts = <0 25 0x4>; /* Level high type */
 528 +               clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 529 +               clock-names = "qspi_en", "qspi";
 530 +       };
 531 +
 532 +       pcie@3400000 {
 533 +               compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
 534 +               reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 535 +                      0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 536 +               reg-names = "regs", "config";
 537 +               interrupts = <0 108 0x4>; /* aer interrupt */
 538 +               interrupt-names = "aer";
 539 +               #address-cells = <3>;
 540 +               #size-cells = <2>;
 541 +               device_type = "pci";
 542 +               dma-coherent;
 543 +               num-lanes = <4>;
 544 +               bus-range = <0x0 0xff>;
 545 +               ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
 546 +                         0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 547 +               msi-parent = <&its>;
 548 +               #interrupt-cells = <1>;
 549 +               interrupt-map-mask = <0 0 0 7>;
 550 +               interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
 551 +                               <0000 0 0 2 &gic 0 0 0 110 4>,
 552 +                               <0000 0 0 3 &gic 0 0 0 111 4>,
 553 +                               <0000 0 0 4 &gic 0 0 0 112 4>;
 554 +       };
 555 +       pcie@3500000 {
 556 +               compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
 557 +               reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 558 +                      0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 559 +               reg-names = "regs", "config";
 560 +               interrupts = <0 113 0x4>; /* aer interrupt */
 561 +               interrupt-names = "aer";
 562 +               #address-cells = <3>;
 563 +               #size-cells = <2>;
 564 +               device_type = "pci";
 565 +               dma-coherent;
 566 +               num-lanes = <4>;
 567 +               bus-range = <0x0 0xff>;
 568 +               ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
 569 +                         0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 570 +               msi-parent = <&its>;
 571 +               #interrupt-cells = <1>;
 572 +               interrupt-map-mask = <0 0 0 7>;
 573 +               interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
 574 +                               <0000 0 0 2 &gic 0 0 0 115 4>,
 575 +                               <0000 0 0 3 &gic 0 0 0 116 4>,
 576 +                               <0000 0 0 4 &gic 0 0 0 117 4>;
 577 +       };
 578 +
 579 +       pcie@3600000 {
 580 +               compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
 581 +               reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 582 +                      0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 583 +               reg-names = "regs", "config";
 584 +               interrupts = <0 118 0x4>; /* aer interrupt */
 585 +               interrupt-names = "aer";
 586 +               #address-cells = <3>;
 587 +               #size-cells = <2>;
 588 +               device_type = "pci";
 589 +               dma-coherent;
 590 +               num-lanes = <8>;
 591 +               bus-range = <0x0 0xff>;
 592 +               ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
 593 +                         0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 594 +               msi-parent = <&its>;
 595 +               #interrupt-cells = <1>;
 596 +               interrupt-map-mask = <0 0 0 7>;
 597 +               interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
 598 +                               <0000 0 0 2 &gic 0 0 0 120 4>,
 599 +                               <0000 0 0 3 &gic 0 0 0 121 4>,
 600 +                               <0000 0 0 4 &gic 0 0 0 122 4>;
 601 +       };
 602 +
 603 +       sata0: sata@3200000 {
 604 +               compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
 605 +               reg = <0x0 0x3200000 0x0 0x10000>;
 606 +               interrupts = <0 133 0x4>; /* Level high type */
 607 +               clocks = <&clockgen 4 3>;
 608 +       };
 609 +
 610 +       usb0: usb3@3100000 {
 611 +               compatible = "snps,dwc3";
 612 +               reg = <0x0 0x3100000 0x0 0x10000>;
 613 +               interrupts = <0 80 0x4>; /* Level high type */
 614 +               dr_mode = "host";
 615 +               configure-gfladj;
 616 +               snps,dis_rxdet_inp3_quirk;
 617 +       };
 618 +
 619 +       usb1: usb3@3110000 {
 620 +               compatible = "snps,dwc3";
 621 +               reg = <0x0 0x3110000 0x0 0x10000>;
 622 +               interrupts = <0 81 0x4>; /* Level high type */
 623 +               dr_mode = "host";
 624 +               configure-gfladj;
 625 +               snps,dis_rxdet_inp3_quirk;
 626 +       };
 627 +
 628 +       smmu: iommu@5000000 {
 629 +               compatible = "arm,mmu-500";
 630 +               reg = <0 0x5000000 0 0x800000>;
 631 +               #global-interrupts = <12>;
 632 +               interrupts = <0 13 4>, /* global secure fault */
 633 +                            <0 14 4>, /* combined secure interrupt */
 634 +                            <0 15 4>, /* global non-secure fault */
 635 +                            <0 16 4>, /* combined non-secure interrupt */
 636 +                       /* performance counter interrupts 0-7 */
 637 +                            <0 211 4>,
 638 +                            <0 212 4>,
 639 +                            <0 213 4>,
 640 +                            <0 214 4>,
 641 +                            <0 215 4>,
 642 +                            <0 216 4>,
 643 +                            <0 217 4>,
 644 +                            <0 218 4>,
 645 +                       /* per context interrupt, 64 interrupts */
 646 +                            <0 146 4>,
 647 +                            <0 147 4>,
 648 +                            <0 148 4>,
 649 +                            <0 149 4>,
 650 +                            <0 150 4>,
 651 +                            <0 151 4>,
 652 +                            <0 152 4>,
 653 +                            <0 153 4>,
 654 +                            <0 154 4>,
 655 +                            <0 155 4>,
 656 +                            <0 156 4>,
 657 +                            <0 157 4>,
 658 +                            <0 158 4>,
 659 +                            <0 159 4>,
 660 +                            <0 160 4>,
 661 +                            <0 161 4>,
 662 +                            <0 162 4>,
 663 +                            <0 163 4>,
 664 +                            <0 164 4>,
 665 +                            <0 165 4>,
 666 +                            <0 166 4>,
 667 +                            <0 167 4>,
 668 +                            <0 168 4>,
 669 +                            <0 169 4>,
 670 +                            <0 170 4>,
 671 +                            <0 171 4>,
 672 +                            <0 172 4>,
 673 +                            <0 173 4>,
 674 +                            <0 174 4>,
 675 +                            <0 175 4>,
 676 +                            <0 176 4>,
 677 +                            <0 177 4>,
 678 +                            <0 178 4>,
 679 +                            <0 179 4>,
 680 +                            <0 180 4>,
 681 +                            <0 181 4>,
 682 +                            <0 182 4>,
 683 +                            <0 183 4>,
 684 +                            <0 184 4>,
 685 +                            <0 185 4>,
 686 +                            <0 186 4>,
 687 +                            <0 187 4>,
 688 +                            <0 188 4>,
 689 +                            <0 189 4>,
 690 +                            <0 190 4>,
 691 +                            <0 191 4>,
 692 +                            <0 192 4>,
 693 +                            <0 193 4>,
 694 +                            <0 194 4>,
 695 +                            <0 195 4>,
 696 +                            <0 196 4>,
 697 +                            <0 197 4>,
 698 +                            <0 198 4>,
 699 +                            <0 199 4>,
 700 +                            <0 200 4>,
 701 +                            <0 201 4>,
 702 +                            <0 202 4>,
 703 +                            <0 203 4>,
 704 +                            <0 204 4>,
 705 +                            <0 205 4>,
 706 +                            <0 206 4>,
 707 +                            <0 207 4>,
 708 +                            <0 208 4>,
 709 +                            <0 209 4>;
 710 +               mmu-masters = <&fsl_mc 0x300 0>;
 711 +       };
 712 +
 713 +       timer {
 714 +               compatible = "arm,armv8-timer";
 715 +               interrupts = <1 13 0x1>,/*Phy Secure PPI, edge triggered*/
 716 +                            <1 14 0x1>, /*Phy Non-Secure PPI, edge triggered*/
 717 +                            <1 11 0x1>, /*Virtual PPI, edge triggered */
 718 +                            <1 10 0x1>; /*Hypervisor PPI, edge triggered */
 719 +       };
 720 +
 721 +       fsl_mc: fsl-mc@80c000000 {
 722 +               compatible = "fsl,qoriq-mc";
 723 +               #stream-id-cells = <2>;
 724 +               reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 725 +                     <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 726 +               msi-parent = <&its>;
 727 +               #address-cells = <3>;
 728 +               #size-cells = <1>;
 729 +
 730 +               /*
 731 +                * Region type 0x0 - MC portals
 732 +                * Region type 0x1 - QBMAN portals
 733 +                */
 734 +               ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 735 +                         0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 736 +
 737 +               dpmacs {
 738 +                       #address-cells = <1>;
 739 +                       #size-cells = <0>;
 740 +
 741 +                       dpmac1: dpmac@1 {
 742 +                               compatible = "fsl,qoriq-mc-dpmac";
 743 +                               reg = <1>;
 744 +                       };
 745 +                       dpmac2: dpmac@2 {
 746 +                               compatible = "fsl,qoriq-mc-dpmac";
 747 +                               reg = <2>;
 748 +                       };
 749 +                       dpmac3: dpmac@3 {
 750 +                               compatible = "fsl,qoriq-mc-dpmac";
 751 +                               reg = <3>;
 752 +                       };
 753 +                       dpmac4: dpmac@4 {
 754 +                               compatible = "fsl,qoriq-mc-dpmac";
 755 +                               reg = <4>;
 756 +                       };
 757 +                       dpmac5: dpmac@5 {
 758 +                               compatible = "fsl,qoriq-mc-dpmac";
 759 +                               reg = <5>;
 760 +                       };
 761 +                       dpmac6: dpmac@6 {
 762 +                               compatible = "fsl,qoriq-mc-dpmac";
 763 +                               reg = <6>;
 764 +                       };
 765 +                       dpmac7: dpmac@7 {
 766 +                               compatible = "fsl,qoriq-mc-dpmac";
 767 +                               reg = <7>;
 768 +                       };
 769 +                       dpmac8: dpmac@8 {
 770 +                               compatible = "fsl,qoriq-mc-dpmac";
 771 +                               reg = <8>;
 772 +                       };
 773 +                       dpmac9: dpmac@9 {
 774 +                               compatible = "fsl,qoriq-mc-dpmac";
 775 +                               reg = <9>;
 776 +                       };
 777 +                       dpmac10: dpmac@10 {
 778 +                               compatible = "fsl,qoriq-mc-dpmac";
 779 +                               reg = <0xa>;
 780 +                       };
 781 +               };
 782 +       };
 783 +
 784 +
 785 +       memory@80000000 {
 786 +               device_type = "memory";
 787 +               reg = <0x00000000 0x80000000 0 0x80000000>;
 788 +                     /* DRAM space 1 - 2 GB DRAM */
 789 +       };
 790 +};