target/linux/layerscape/patches-4.4/3233-arm64-dts-ls1046a-update-MSI-dts-node.patch

   1 From 1569c166572f9576c6726472b5a726a1a56900bd Mon Sep 17 00:00:00 2001
   2 From: Yangbo Lu <yangbo.lu@nxp.com>
   3 Date: Thu, 16 Feb 2017 18:00:14 +0800
   4 Subject: [PATCH] arm64: dts: ls1046a: update MSI dts node
   5
   6 Update MSI dts node according to below patchwork patch.
   7
   8 arm64: dts: ls1046a: add MSI dts node
   9 https://patchwork.kernel.org/patch/9520299
  10
  11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  12 ---
  13  arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 58 +++++++++++++-------------
  14  1 file changed, 30 insertions(+), 28 deletions(-)
  15
  16 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
  17 index 179c38b..f96be34 100644
  18 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
  19 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
  20 @@ -44,6 +44,8 @@
  21   *     OTHER DEALINGS IN THE SOFTWARE.
  22   */
  23
  24 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  25 +
  26  / {
  27         compatible = "fsl,ls1046a";
  28         interrupt-parent = <&gic>;
  29 @@ -870,34 +872,34 @@
  30                         big-endian;
  31                 };
  32
  33 -               msi: msi-controller@1580000 {
  34 +               msi1: msi-controller@1580000 {
  35                         compatible = "fsl,ls1046a-msi";
  36 -                       #address-cells = <2>;
  37 -                       #size-cells = <2>;
  38 -                       ranges;
  39                         msi-controller;
  40 +                       reg = <0x0 0x1580000 0x0 0x10000>;
  41 +                       interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  42 +                                    <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
  43 +                                    <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
  44 +                                    <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  45 +               };
  46
  47 -                       msi-bank@1580000 {
  48 -                               reg = <0x0 0x1580000 0x0 0x10000>;
  49 -                               interrupts = <0 116 0x4>,
  50 -                                            <0 111 0x4>,
  51 -                                            <0 112 0x4>,
  52 -                                            <0 113 0x4>;
  53 -                       };
  54 -                       msi-bank@1590000 {
  55 -                               reg = <0x0 0x1590000 0x0 0x10000>;
  56 -                               interrupts = <0 126 0x4>,
  57 -                                            <0 121 0x4>,
  58 -                                            <0 122 0x4>,
  59 -                                            <0 123 0x4>;
  60 -                       };
  61 -                       msi-bank@15a0000 {
  62 -                               reg = <0x0 0x15a0000 0x0 0x10000>;
  63 -                               interrupts = <0 160 0x4>,
  64 -                                            <0 155 0x4>,
  65 -                                            <0 156 0x4>,
  66 -                                            <0 157 0x4>;
  67 -                       };
  68 +               msi2: msi-controller@1590000 {
  69 +                       compatible = "fsl,ls1046a-msi";
  70 +                       msi-controller;
  71 +                       reg = <0x0 0x1590000 0x0 0x10000>;
  72 +                       interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  73 +                                    <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  74 +                                    <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  75 +                                    <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
  76 +               };
  77 +
  78 +               msi3: msi-controller@15a0000 {
  79 +                       compatible = "fsl,ls1046a-msi";
  80 +                       msi-controller;
  81 +                       reg = <0x0 0x15a0000 0x0 0x10000>;
  82 +                       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
  83 +                                    <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
  84 +                                    <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
  85 +                                    <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  86                 };
  87
  88                 pcie@3400000 {
  89 @@ -916,7 +918,7 @@
  90                         bus-range = <0x0 0xff>;
  91                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
  92                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  93 -                       msi-parent = <&msi>;
  94 +                       msi-parent = <&msi1>, <&msi2>, <&msi3>;
  95                         #interrupt-cells = <1>;
  96                         interrupt-map-mask = <0 0 0 7>;
  97                         interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
  98 @@ -941,7 +943,7 @@
  99                         bus-range = <0x0 0xff>;
 100                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 101                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 102 -                       msi-parent = <&msi>;
 103 +                       msi-parent = <&msi1>, <&msi2>, <&msi3>;
 104                         #interrupt-cells = <1>;
 105                         interrupt-map-mask = <0 0 0 7>;
 106                         interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
 107 @@ -966,7 +968,7 @@
 108                         bus-range = <0x0 0xff>;
 109                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 110                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 111 -                       msi-parent = <&msi>;
 112 +                       msi-parent = <&msi1>, <&msi2>, <&msi3>;
 113                         #interrupt-cells = <1>;
 114                         interrupt-map-mask = <0 0 0 7>;
 115                         interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
 116 --
 117 2.1.0.27.g96db324
 118