target/linux/layerscape/patches-4.4/4046-mtd-ifc-Segregate-IFC-fcm-and-runtime-registers.patch

   1 From 1c62b9982b7f6cb560d1237d2658945c070c91d4 Mon Sep 17 00:00:00 2001
   2 From: Raghav Dogra <raghav@freescale.com>
   3 Date: Wed, 20 Jan 2016 13:06:32 +0530
   4 Subject: [PATCH 46/70] mtd/ifc: Segregate IFC fcm and runtime registers
   5
   6 IFC has two set of registers viz FCM (Flash control machine)
   7 aka global and run time registers. These set are defined in two
   8 memory map PAGES. Upto IFC 1.4 PAGE size is 4 KB and from IFC2.0
   9 PAGE size is 64KB
  10
  11 Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
  12 Signed-off-by: Raghav Dogra <raghav@freescale.com>
  13 ---
  14  drivers/memory/fsl_ifc.c        |  251 ++++++++++++++++++++-------------------
  15  drivers/mtd/nand/fsl_ifc_nand.c |   72 ++++++-----
  16  include/linux/fsl_ifc.h         |   48 +++++---
  17  3 files changed, 203 insertions(+), 168 deletions(-)
  18
  19 --- a/drivers/memory/fsl_ifc.c
  20 +++ b/drivers/memory/fsl_ifc.c
  21 @@ -64,11 +64,11 @@ int fsl_ifc_find(phys_addr_t addr_base)
  22  {
  23         int i = 0;
  24
  25 -       if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
  26 +       if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
  27                 return -ENODEV;
  28
  29         for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
  30 -               u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
  31 +               u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
  32                 if (cspr & CSPR_V && (cspr & CSPR_BA) ==
  33                                 convert_ifc_address(addr_base))
  34                         return i;
  35 @@ -80,7 +80,7 @@ EXPORT_SYMBOL(fsl_ifc_find);
  36
  37  static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
  38  {
  39 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  40 +       struct fsl_ifc_fcm __iomem *ifc = ctrl->gregs;
  41
  42         /*
  43          * Clear all the common status and event registers
  44 @@ -109,7 +109,7 @@ static int fsl_ifc_ctrl_remove(struct pl
  45         irq_dispose_mapping(ctrl->nand_irq);
  46         irq_dispose_mapping(ctrl->irq);
  47
  48 -       iounmap(ctrl->regs);
  49 +       iounmap(ctrl->gregs);
  50
  51         dev_set_drvdata(&dev->dev, NULL);
  52         kfree(ctrl);
  53 @@ -127,7 +127,7 @@ static DEFINE_SPINLOCK(nand_irq_lock);
  54
  55  static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
  56  {
  57 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  58 +       struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
  59         unsigned long flags;
  60         u32 stat;
  61
  62 @@ -162,7 +162,7 @@ static irqreturn_t fsl_ifc_nand_irq(int
  63  static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
  64  {
  65         struct fsl_ifc_ctrl *ctrl = data;
  66 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  67 +       struct fsl_ifc_fcm __iomem *ifc = ctrl->gregs;
  68         u32 err_axiid, err_srcid, status, cs_err, err_addr;
  69         irqreturn_t ret = IRQ_NONE;
  70
  71 @@ -220,6 +220,7 @@ static int fsl_ifc_ctrl_probe(struct pla
  72  {
  73         int ret = 0;
  74         int version, banks;
  75 +       void __iomem *addr;
  76
  77         dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
  78
  79 @@ -230,22 +231,13 @@ static int fsl_ifc_ctrl_probe(struct pla
  80         dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
  81
  82         /* IOMAP the entire IFC region */
  83 -       fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
  84 -       if (!fsl_ifc_ctrl_dev->regs) {
  85 +       fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
  86 +       if (!fsl_ifc_ctrl_dev->gregs) {
  87                 dev_err(&dev->dev, "failed to get memory region\n");
  88                 ret = -ENODEV;
  89                 goto err;
  90         }
  91
  92 -       version = ifc_in32(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
  93 -                       FSL_IFC_VERSION_MASK;
  94 -       banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
  95 -       dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
  96 -               version >> 24, (version >> 16) & 0xf, banks);
  97 -
  98 -       fsl_ifc_ctrl_dev->version = version;
  99 -       fsl_ifc_ctrl_dev->banks = banks;
 100 -
 101         if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
 102                 fsl_ifc_ctrl_dev->little_endian = true;
 103                 dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
 104 @@ -254,8 +246,9 @@ static int fsl_ifc_ctrl_probe(struct pla
 105                 dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
 106         }
 107
 108 -       version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
 109 +       version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
 110                         FSL_IFC_VERSION_MASK;
 111 +
 112         banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
 113         dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
 114                 version >> 24, (version >> 16) & 0xf, banks);
 115 @@ -263,6 +256,14 @@ static int fsl_ifc_ctrl_probe(struct pla
 116         fsl_ifc_ctrl_dev->version = version;
 117         fsl_ifc_ctrl_dev->banks = banks;
 118
 119 +       addr = fsl_ifc_ctrl_dev->gregs;
 120 +       if (version >= FSL_IFC_VERSION_2_0_0)
 121 +               fsl_ifc_ctrl_dev->rregs =
 122 +                       (struct fsl_ifc_runtime *)(addr + PGOFFSET_64K);
 123 +       else
 124 +               fsl_ifc_ctrl_dev->rregs =
 125 +                       (struct fsl_ifc_runtime *)(addr + PGOFFSET_4K);
 126 +
 127         /* get the Controller level irq */
 128         fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
 129         if (fsl_ifc_ctrl_dev->irq == 0) {
 130 @@ -319,33 +320,39 @@ err:
 131  static int fsl_ifc_suspend(struct device *dev)
 132  {
 133         struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
 134 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 135 +       struct fsl_ifc_fcm __iomem *fcm = ctrl->gregs;
 136 +       struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
 137         __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
 138                                                          gpcm_evter_intr_en;
 139
 140 -       ctrl->saved_regs = kzalloc(sizeof(struct fsl_ifc_regs), GFP_KERNEL);
 141 -       if (!ctrl->saved_regs)
 142 +       ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_fcm), GFP_KERNEL);
 143 +       if (!ctrl->saved_gregs)
 144 +               return -ENOMEM;
 145 +       ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
 146 +       if (!ctrl->saved_rregs)
 147                 return -ENOMEM;
 148
 149 -       cm_evter_intr_en = ifc_in32(&ifc->cm_evter_intr_en);
 150 -       nand_evter_intr_en = ifc_in32(&ifc->ifc_nand.nand_evter_intr_en);
 151 -       nor_evter_intr_en = ifc_in32(&ifc->ifc_nor.nor_evter_intr_en);
 152 -       gpcm_evter_intr_en = ifc_in32(&ifc->ifc_gpcm.gpcm_evter_intr_en);
 153 +       cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
 154 +       nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
 155 +       nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
 156 +       gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
 157
 158  /* IFC interrupts disabled */
 159
 160 -       ifc_out32(0x0, &ifc->cm_evter_intr_en);
 161 -       ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en);
 162 -       ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en);
 163 -       ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en);
 164 -
 165 -       memcpy_fromio(ctrl->saved_regs, ifc, sizeof(struct fsl_ifc_regs));
 166 +       ifc_out32(0x0, &fcm->cm_evter_intr_en);
 167 +       ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
 168 +       ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
 169 +       ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
 170 +
 171 +       memcpy_fromio(ctrl->saved_gregs, fcm, sizeof(struct fsl_ifc_fcm));
 172 +       memcpy_fromio(ctrl->saved_rregs, runtime,
 173 +                                       sizeof(struct fsl_ifc_runtime));
 174
 175  /* save the interrupt values */
 176 -       ctrl->saved_regs->cm_evter_intr_en = cm_evter_intr_en;
 177 -       ctrl->saved_regs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
 178 -       ctrl->saved_regs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
 179 -       ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
 180 +       ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
 181 +       ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
 182 +       ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
 183 +       ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
 184
 185         return 0;
 186  }
 187 @@ -354,110 +361,116 @@ static int fsl_ifc_suspend(struct device
 188  static int fsl_ifc_resume(struct device *dev)
 189  {
 190         struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
 191 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 192 -       struct fsl_ifc_regs *savd_regs = ctrl->saved_regs;
 193 +       struct fsl_ifc_fcm __iomem *fcm = ctrl->gregs;
 194 +       struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
 195 +       struct fsl_ifc_fcm *savd_gregs = ctrl->saved_gregs;
 196 +       struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
 197         uint32_t ver = 0, ncfgr, status, ifc_bank, i;
 198
 199  /*
 200   * IFC interrupts disabled
 201   */
 202 -       ifc_out32(0x0, &ifc->cm_evter_intr_en);
 203 -       ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en);
 204 -       ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en);
 205 -       ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en);
 206 +       ifc_out32(0x0, &fcm->cm_evter_intr_en);
 207 +       ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
 208 +       ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
 209 +       ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
 210
 211
 212 -       if (ctrl->saved_regs) {
 213 +       if (ctrl->saved_gregs) {
 214                 for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
 215 -                       ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr_ext,
 216 -                                       &ifc->cspr_cs[ifc_bank].cspr_ext);
 217 -                       ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr,
 218 -                                       &ifc->cspr_cs[ifc_bank].cspr);
 219 -                       ifc_out32(savd_regs->amask_cs[ifc_bank].amask,
 220 -                                       &ifc->amask_cs[ifc_bank].amask);
 221 -                       ifc_out32(savd_regs->csor_cs[ifc_bank].csor_ext,
 222 -                                       &ifc->csor_cs[ifc_bank].csor_ext);
 223 -                       ifc_out32(savd_regs->csor_cs[ifc_bank].csor,
 224 -                                       &ifc->csor_cs[ifc_bank].csor);
 225 +                       ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
 226 +                                       &fcm->cspr_cs[ifc_bank].cspr_ext);
 227 +                       ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
 228 +                                       &fcm->cspr_cs[ifc_bank].cspr);
 229 +                       ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
 230 +                                       &fcm->amask_cs[ifc_bank].amask);
 231 +                       ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
 232 +                                       &fcm->csor_cs[ifc_bank].csor_ext);
 233 +                       ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
 234 +                                       &fcm->csor_cs[ifc_bank].csor);
 235                         for (i = 0; i < 4; i++) {
 236 -                               ifc_out32(savd_regs->ftim_cs[ifc_bank].ftim[i],
 237 -                                       &ifc->ftim_cs[ifc_bank].ftim[i]);
 238 +                               ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
 239 +                                       &fcm->ftim_cs[ifc_bank].ftim[i]);
 240                         }
 241                 }
 242 -               ifc_out32(savd_regs->ifc_gcr, &ifc->ifc_gcr);
 243 -               ifc_out32(savd_regs->cm_evter_en, &ifc->cm_evter_en);
 244 -
 245 -/*
 246 -* IFC controller NAND machine registers
 247 -*/
 248 -               ifc_out32(savd_regs->ifc_nand.ncfgr, &ifc->ifc_nand.ncfgr);
 249 -               ifc_out32(savd_regs->ifc_nand.nand_fcr0,
 250 -                                               &ifc->ifc_nand.nand_fcr0);
 251 -               ifc_out32(savd_regs->ifc_nand.nand_fcr1,
 252 -                                               &ifc->ifc_nand.nand_fcr1);
 253 -               ifc_out32(savd_regs->ifc_nand.row0, &ifc->ifc_nand.row0);
 254 -               ifc_out32(savd_regs->ifc_nand.row1, &ifc->ifc_nand.row1);
 255 -               ifc_out32(savd_regs->ifc_nand.col0, &ifc->ifc_nand.col0);
 256 -               ifc_out32(savd_regs->ifc_nand.col1, &ifc->ifc_nand.col1);
 257 -               ifc_out32(savd_regs->ifc_nand.row2, &ifc->ifc_nand.row2);
 258 -               ifc_out32(savd_regs->ifc_nand.col2, &ifc->ifc_nand.col2);
 259 -               ifc_out32(savd_regs->ifc_nand.row3, &ifc->ifc_nand.row3);
 260 -               ifc_out32(savd_regs->ifc_nand.col3, &ifc->ifc_nand.col3);
 261 -               ifc_out32(savd_regs->ifc_nand.nand_fbcr,
 262 -                                               &ifc->ifc_nand.nand_fbcr);
 263 -               ifc_out32(savd_regs->ifc_nand.nand_fir0,
 264 -                                               &ifc->ifc_nand.nand_fir0);
 265 -               ifc_out32(savd_regs->ifc_nand.nand_fir1,
 266 -                                               &ifc->ifc_nand.nand_fir1);
 267 -               ifc_out32(savd_regs->ifc_nand.nand_fir2,
 268 -                                               &ifc->ifc_nand.nand_fir2);
 269 -               ifc_out32(savd_regs->ifc_nand.nand_csel,
 270 -                                               &ifc->ifc_nand.nand_csel);
 271 -               ifc_out32(savd_regs->ifc_nand.nandseq_strt,
 272 -                                               &ifc->ifc_nand.nandseq_strt);
 273 -               ifc_out32(savd_regs->ifc_nand.nand_evter_en,
 274 -                                               &ifc->ifc_nand.nand_evter_en);
 275 -               ifc_out32(savd_regs->ifc_nand.nanndcr, &ifc->ifc_nand.nanndcr);
 276 -
 277 -/*
 278 -* IFC controller NOR machine registers
 279 -*/
 280 -               ifc_out32(savd_regs->ifc_nor.nor_evter_en,
 281 -                                       &ifc->ifc_nor.nor_evter_en);
 282 -               ifc_out32(savd_regs->ifc_nor.norcr, &ifc->ifc_nor.norcr);
 283 -
 284 -/*
 285 - * IFC controller GPCM Machine registers
 286 - */
 287 -               ifc_out32(savd_regs->ifc_gpcm.gpcm_evter_en,
 288 -                                       &ifc->ifc_gpcm.gpcm_evter_en);
 289 -
 290 -
 291 -
 292 -/*
 293 - * IFC interrupts enabled
 294 - */
 295 -       ifc_out32(ctrl->saved_regs->cm_evter_intr_en, &ifc->cm_evter_intr_en);
 296 -       ifc_out32(ctrl->saved_regs->ifc_nand.nand_evter_intr_en,
 297 -                                       &ifc->ifc_nand.nand_evter_intr_en);
 298 -       ifc_out32(ctrl->saved_regs->ifc_nor.nor_evter_intr_en,
 299 -                                       &ifc->ifc_nor.nor_evter_intr_en);
 300 -       ifc_out32(ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en,
 301 -                                       &ifc->ifc_gpcm.gpcm_evter_intr_en);
 302 +               ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
 303 +               ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
 304 +               ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
 305 +               ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
 306 +               ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
 307 +       }
 308
 309 -               kfree(ctrl->saved_regs);
 310 -               ctrl->saved_regs = NULL;
 311 +       if (ctrl->saved_rregs) {
 312 +               /* IFC controller NAND machine registers */
 313 +               ifc_out32(savd_rregs->ifc_nand.ncfgr,
 314 +                                               &runtime->ifc_nand.ncfgr);
 315 +               ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
 316 +                                               &runtime->ifc_nand.nand_fcr0);
 317 +               ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
 318 +                                               &runtime->ifc_nand.nand_fcr1);
 319 +               ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
 320 +               ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
 321 +               ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
 322 +               ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
 323 +               ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
 324 +               ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
 325 +               ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
 326 +               ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
 327 +               ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
 328 +                                               &runtime->ifc_nand.nand_fbcr);
 329 +               ifc_out32(savd_rregs->ifc_nand.nand_fir0,
 330 +                                               &runtime->ifc_nand.nand_fir0);
 331 +               ifc_out32(savd_rregs->ifc_nand.nand_fir1,
 332 +                                               &runtime->ifc_nand.nand_fir1);
 333 +               ifc_out32(savd_rregs->ifc_nand.nand_fir2,
 334 +                                               &runtime->ifc_nand.nand_fir2);
 335 +               ifc_out32(savd_rregs->ifc_nand.nand_csel,
 336 +                                               &runtime->ifc_nand.nand_csel);
 337 +               ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
 338 +                                       &runtime->ifc_nand.nandseq_strt);
 339 +               ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
 340 +                                       &runtime->ifc_nand.nand_evter_en);
 341 +               ifc_out32(savd_rregs->ifc_nand.nanndcr,
 342 +                                       &runtime->ifc_nand.nanndcr);
 343 +               ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
 344 +                                       &runtime->ifc_nand.nand_dll_lowcfg0);
 345 +               ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
 346 +                                       &runtime->ifc_nand.nand_dll_lowcfg1);
 347 +
 348 +               /* IFC controller NOR machine registers */
 349 +               ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
 350 +                                       &runtime->ifc_nor.nor_evter_en);
 351 +               ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
 352 +
 353 +               /* IFC controller GPCM Machine registers */
 354 +               ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
 355 +                                       &runtime->ifc_gpcm.gpcm_evter_en);
 356 +
 357 +               /* IFC interrupts enabled */
 358 +               ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
 359 +                                       &fcm->cm_evter_intr_en);
 360 +               ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
 361 +                                       &runtime->ifc_nand.nand_evter_intr_en);
 362 +               ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
 363 +                                       &runtime->ifc_nor.nor_evter_intr_en);
 364 +               ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
 365 +                                       &runtime->ifc_gpcm.gpcm_evter_intr_en);
 366 +
 367 +               kfree(ctrl->saved_gregs);
 368 +               kfree(ctrl->saved_rregs);
 369 +               ctrl->saved_gregs = NULL;
 370 +               ctrl->saved_rregs = NULL;
 371         }
 372
 373 -       ver = ifc_in32(&ctrl->regs->ifc_rev);
 374 -       ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
 375 +       ver = ifc_in32(&fcm->ifc_rev);
 376 +       ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
 377         if (ver >= FSL_IFC_V1_3_0) {
 378
 379                 ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
 380 -                                       &ifc->ifc_nand.ncfgr);
 381 +                                       &runtime->ifc_nand.ncfgr);
 382                 /* wait for  SRAM_INIT bit to be clear or timeout */
 383                 status = spin_event_timeout(
 384 -                                       !(ifc_in32(&ifc->ifc_nand.ncfgr)
 385 +                                       !(ifc_in32(&runtime->ifc_nand.ncfgr)
 386                                         & IFC_NAND_SRAM_INIT_EN),
 387                                         IFC_TIMEOUT_MSECS, 0);
 388
 389 --- a/drivers/mtd/nand/fsl_ifc_nand.c
 390 +++ b/drivers/mtd/nand/fsl_ifc_nand.c
 391 @@ -233,7 +233,7 @@ static void set_addr(struct mtd_info *mt
 392         struct nand_chip *chip = mtd->priv;
 393         struct fsl_ifc_mtd *priv = chip->priv;
 394         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 395 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 396 +       struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 397         int buf_num;
 398
 399         ifc_nand_ctrl->page = page_addr;
 400 @@ -296,7 +296,7 @@ static void fsl_ifc_run_command(struct m
 401         struct fsl_ifc_mtd *priv = chip->priv;
 402         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 403         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 404 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 405 +       struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 406         u32 eccstat[4];
 407         int i;
 408
 409 @@ -372,7 +372,7 @@ static void fsl_ifc_do_read(struct nand_
 410  {
 411         struct fsl_ifc_mtd *priv = chip->priv;
 412         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 413 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 414 +       struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 415
 416         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 417         if (mtd->writesize > 512) {
 418 @@ -412,7 +412,7 @@ static void fsl_ifc_cmdfunc(struct mtd_i
 419         struct nand_chip *chip = mtd->priv;
 420         struct fsl_ifc_mtd *priv = chip->priv;
 421         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 422 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 423 +       struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 424
 425         /* clear the read buffer */
 426         ifc_nand_ctrl->read_bytes = 0;
 427 @@ -724,7 +724,7 @@ static int fsl_ifc_wait(struct mtd_info
 428  {
 429         struct fsl_ifc_mtd *priv = chip->priv;
 430         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 431 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 432 +       struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 433         u32 nand_fsr;
 434
 435         /* Use READ_STATUS command, but wait for the device to be ready */
 436 @@ -826,39 +826,42 @@ static int fsl_ifc_chip_init_tail(struct
 437  static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
 438  {
 439         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 440 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 441 +       struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
 442 +       struct fsl_ifc_fcm __iomem *ifc_global = ctrl->gregs;
 443         uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
 444         uint32_t cs = priv->bank;
 445
 446         /* Save CSOR and CSOR_ext */
 447 -       csor = ifc_in32(&ifc->csor_cs[cs].csor);
 448 -       csor_ext = ifc_in32(&ifc->csor_cs[cs].csor_ext);
 449 +       csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
 450 +       csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
 451
 452         /* chage PageSize 8K and SpareSize 1K*/
 453         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 454 -       ifc_out32(csor_8k, &ifc->csor_cs[cs].csor);
 455 -       ifc_out32(0x0000400, &ifc->csor_cs[cs].csor_ext);
 456 +       ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
 457 +       ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
 458
 459         /* READID */
 460         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 461 -                 (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 462 -                 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
 463 -                 &ifc->ifc_nand.nand_fir0);
 464 +                   (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 465 +                   (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
 466 +                   &ifc_runtime->ifc_nand.nand_fir0);
 467         ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
 468 -                 &ifc->ifc_nand.nand_fcr0);
 469 -       ifc_out32(0x0, &ifc->ifc_nand.row3);
 470 +                   &ifc_runtime->ifc_nand.nand_fcr0);
 471 +       ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
 472
 473 -       ifc_out32(0x0, &ifc->ifc_nand.nand_fbcr);
 474 +       ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
 475
 476         /* Program ROW0/COL0 */
 477 -       ifc_out32(0x0, &ifc->ifc_nand.row0);
 478 -       ifc_out32(0x0, &ifc->ifc_nand.col0);
 479 +       ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
 480 +       ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
 481
 482         /* set the chip select for NAND Transaction */
 483 -       ifc_out32(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
 484 +       ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
 485 +               &ifc_runtime->ifc_nand.nand_csel);
 486
 487         /* start read seq */
 488 -       ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
 489 +       ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
 490 +               &ifc_runtime->ifc_nand.nandseq_strt);
 491
 492         /* wait for command complete flag or timeout */
 493         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 494 @@ -868,14 +871,15 @@ static void fsl_ifc_sram_init(struct fsl
 495                 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
 496
 497         /* Restore CSOR and CSOR_ext */
 498 -       ifc_out32(csor, &ifc->csor_cs[cs].csor);
 499 -       ifc_out32(csor_ext, &ifc->csor_cs[cs].csor_ext);
 500 +       ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
 501 +       ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
 502  }
 503
 504  static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 505  {
 506         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 507 -       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 508 +       struct fsl_ifc_fcm __iomem *ifc_global = ctrl->gregs;
 509 +       struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
 510         struct nand_chip *chip = &priv->chip;
 511         struct nand_ecclayout *layout;
 512         u32 csor;
 513 @@ -886,7 +890,8 @@ static int fsl_ifc_chip_init(struct fsl_
 514
 515         /* fill in nand_chip structure */
 516         /* set up function call table */
 517 -       if ((ifc_in32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
 518 +       if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
 519 +               & CSPR_PORT_SIZE_16)
 520                 chip->read_byte = fsl_ifc_read_byte16;
 521         else
 522                 chip->read_byte = fsl_ifc_read_byte;
 523 @@ -900,13 +905,14 @@ static int fsl_ifc_chip_init(struct fsl_
 524         chip->bbt_td = &bbt_main_descr;
 525         chip->bbt_md = &bbt_mirror_descr;
 526
 527 -       ifc_out32(0x0, &ifc->ifc_nand.ncfgr);
 528 +       ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
 529
 530         /* set up nand options */
 531         chip->bbt_options = NAND_BBT_USE_FLASH;
 532         chip->options = NAND_NO_SUBPAGE_WRITE;
 533
 534 -       if (ifc_in32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
 535 +       if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
 536 +               & CSPR_PORT_SIZE_16) {
 537                 chip->read_byte = fsl_ifc_read_byte16;
 538                 chip->options |= NAND_BUSWIDTH_16;
 539         } else {
 540 @@ -919,7 +925,7 @@ static int fsl_ifc_chip_init(struct fsl_
 541         chip->ecc.read_page = fsl_ifc_read_page;
 542         chip->ecc.write_page = fsl_ifc_write_page;
 543
 544 -       csor = ifc_in32(&ifc->csor_cs[priv->bank].csor);
 545 +       csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
 546
 547         /* Hardware generates ECC per 512 Bytes */
 548         chip->ecc.size = 512;
 549 @@ -1005,10 +1011,10 @@ static int fsl_ifc_chip_remove(struct fs
 550         return 0;
 551  }
 552
 553 -static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
 554 +static int match_bank(struct fsl_ifc_fcm __iomem *ifc_global, int bank,
 555                       phys_addr_t addr)
 556  {
 557 -       u32 cspr = ifc_in32(&ifc->cspr_cs[bank].cspr);
 558 +       u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
 559
 560         if (!(cspr & CSPR_V))
 561                 return 0;
 562 @@ -1022,7 +1028,7 @@ static DEFINE_MUTEX(fsl_ifc_nand_mutex);
 563
 564  static int fsl_ifc_nand_probe(struct platform_device *dev)
 565  {
 566 -       struct fsl_ifc_regs __iomem *ifc;
 567 +       struct fsl_ifc_runtime __iomem *ifc;
 568         struct fsl_ifc_mtd *priv;
 569         struct resource res;
 570         static const char *part_probe_types[]
 571 @@ -1033,9 +1039,9 @@ static int fsl_ifc_nand_probe(struct pla
 572         struct mtd_part_parser_data ppdata;
 573
 574         ppdata.of_node = dev->dev.of_node;
 575 -       if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
 576 +       if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
 577                 return -ENODEV;
 578 -       ifc = fsl_ifc_ctrl_dev->regs;
 579 +       ifc = fsl_ifc_ctrl_dev->rregs;
 580
 581         /* get, allocate and map the memory resource */
 582         ret = of_address_to_resource(node, 0, &res);
 583 @@ -1046,7 +1052,7 @@ static int fsl_ifc_nand_probe(struct pla
 584
 585         /* find which chip select it is connected to */
 586         for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
 587 -               if (match_bank(ifc, bank, res.start))
 588 +               if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
 589                         break;
 590         }
 591
 592 --- a/include/linux/fsl_ifc.h
 593 +++ b/include/linux/fsl_ifc.h
 594 @@ -39,6 +39,10 @@
 595  #define FSL_IFC_VERSION_MASK   0x0F0F0000
 596  #define FSL_IFC_VERSION_1_0_0  0x01000000
 597  #define FSL_IFC_VERSION_1_1_0  0x01010000
 598 +#define FSL_IFC_VERSION_2_0_0  0x02000000
 599 +
 600 +#define PGOFFSET_64K   (64*1024)
 601 +#define PGOFFSET_4K    (4*1024)
 602
 603  /*
 604   * CSPR - Chip Select Property Register
 605 @@ -725,20 +729,26 @@ struct fsl_ifc_nand {
 606         __be32 nand_evter_en;
 607         u32 res17[0x2];
 608         __be32 nand_evter_intr_en;
 609 -       u32 res18[0x2];
 610 +       __be32 nand_vol_addr_stat;
 611 +       u32 res18;
 612         __be32 nand_erattr0;
 613         __be32 nand_erattr1;
 614         u32 res19[0x10];
 615         __be32 nand_fsr;
 616 -       u32 res20;
 617 -       __be32 nand_eccstat[4];
 618 -       u32 res21[0x20];
 619 +       u32 res20[0x3];
 620 +       __be32 nand_eccstat[6];
 621 +       u32 res21[0x1c];
 622         __be32 nanndcr;
 623         u32 res22[0x2];
 624         __be32 nand_autoboot_trgr;
 625         u32 res23;
 626         __be32 nand_mdr;
 627 -       u32 res24[0x5C];
 628 +       u32 res24[0x1C];
 629 +       __be32 nand_dll_lowcfg0;
 630 +       __be32 nand_dll_lowcfg1;
 631 +       u32 res25;
 632 +       __be32 nand_dll_lowstat;
 633 +       u32 res26[0x3c];
 634  };
 635
 636  /*
 637 @@ -773,13 +783,12 @@ struct fsl_ifc_gpcm {
 638         __be32 gpcm_erattr1;
 639         __be32 gpcm_erattr2;
 640         __be32 gpcm_stat;
 641 -       u32 res4[0x1F3];
 642  };
 643
 644  /*
 645   * IFC Controller Registers
 646   */
 647 -struct fsl_ifc_regs {
 648 +struct fsl_ifc_fcm {
 649         __be32 ifc_rev;
 650         u32 res1[0x2];
 651         struct {
 652 @@ -805,21 +814,26 @@ struct fsl_ifc_regs {
 653         } ftim_cs[FSL_IFC_BANK_COUNT];
 654         u32 res9[0x30];
 655         __be32 rb_stat;
 656 -       u32 res10[0x2];
 657 +       __be32 rb_map;
 658 +       __be32 wb_map;
 659         __be32 ifc_gcr;
 660 -       u32 res11[0x2];
 661 +       u32 res10[0x2];
 662         __be32 cm_evter_stat;
 663 -       u32 res12[0x2];
 664 +       u32 res11[0x2];
 665         __be32 cm_evter_en;
 666 -       u32 res13[0x2];
 667 +       u32 res12[0x2];
 668         __be32 cm_evter_intr_en;
 669 -       u32 res14[0x2];
 670 +       u32 res13[0x2];
 671         __be32 cm_erattr0;
 672         __be32 cm_erattr1;
 673 -       u32 res15[0x2];
 674 +       u32 res14[0x2];
 675         __be32 ifc_ccr;
 676         __be32 ifc_csr;
 677 -       u32 res16[0x2EB];
 678 +       __be32 ddr_ccr_low;
 679 +};
 680 +
 681 +
 682 +struct fsl_ifc_runtime {
 683         struct fsl_ifc_nand ifc_nand;
 684         struct fsl_ifc_nor ifc_nor;
 685         struct fsl_ifc_gpcm ifc_gpcm;
 686 @@ -833,7 +847,8 @@ extern int fsl_ifc_find(phys_addr_t addr
 687  struct fsl_ifc_ctrl {
 688         /* device info */
 689         struct device                   *dev;
 690 -       struct fsl_ifc_regs __iomem     *regs;
 691 +       struct fsl_ifc_fcm __iomem      *gregs;
 692 +       struct fsl_ifc_runtime __iomem  *rregs;
 693         int                             irq;
 694         int                             nand_irq;
 695         spinlock_t                      lock;
 696 @@ -846,7 +861,8 @@ struct fsl_ifc_ctrl {
 697         bool little_endian;
 698  #ifdef CONFIG_PM_SLEEP
 699         /*save regs when system goes to deep sleep*/
 700 -       struct fsl_ifc_regs             *saved_regs;
 701 +       struct fsl_ifc_fcm              *saved_gregs;
 702 +       struct fsl_ifc_runtime          *saved_rregs;
 703  #endif
 704  };
 705