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kernel: update kernel 4.4 to version 4.4.30
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.4 / 7014-temp-QE-headers-are-needed-by-FMD.patch
1 From 03c463111e16f9bae8a659408e5f02333af13239 Mon Sep 17 00:00:00 2001
2 From: Madalin Bucur <madalin.bucur@freescale.com>
3 Date: Tue, 5 Jan 2016 15:41:28 +0200
4 Subject: [PATCH 14/70] temp: QE headers are needed by FMD
5
6 Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
7 ---
8 include/linux/fsl/immap_qe.h | 488 +++++++++++++++++++++++++
9 include/linux/fsl/qe.h | 810 ++++++++++++++++++++++++++++++++++++++++++
10 2 files changed, 1298 insertions(+)
11 create mode 100644 include/linux/fsl/immap_qe.h
12 create mode 100644 include/linux/fsl/qe.h
13
14 --- /dev/null
15 +++ b/include/linux/fsl/immap_qe.h
16 @@ -0,0 +1,488 @@
17 +/*
18 + * QUICC Engine (QE) Internal Memory Map.
19 + * The Internal Memory Map for devices with QE on them. This
20 + * is the superset of all QE devices (8360, etc.).
21 + * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved.
22 + *
23 + * Authors:
24 + * Shlomi Gridish <gridish@freescale.com>
25 + * Li Yang <leoli@freescale.com>
26 + *
27 + * This program is free software; you can redistribute it and/or modify it
28 + * under the terms of the GNU General Public License as published by the
29 + * Free Software Foundation; either version 2 of the License, or (at your
30 + * option) any later version.
31 + */
32 +#ifndef _ASM_POWERPC_IMMAP_QE_H
33 +#define _ASM_POWERPC_IMMAP_QE_H
34 +#ifdef __KERNEL__
35 +
36 +#include <linux/kernel.h>
37 +#include <linux/io.h>
38 +
39 +#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
40 +
41 +/* QE I-RAM */
42 +struct qe_iram {
43 + __be32 iadd; /* I-RAM Address Register */
44 + __be32 idata; /* I-RAM Data Register */
45 + u8 res0[0x04];
46 + __be32 iready; /* I-RAM Ready Register */
47 + u8 res1[0x70];
48 +} __packed;
49 +
50 +/* QE Interrupt Controller */
51 +struct qe_ic_regs {
52 + __be32 qicr;
53 + __be32 qivec;
54 + __be32 qripnr;
55 + __be32 qipnr;
56 + __be32 qipxcc;
57 + __be32 qipycc;
58 + __be32 qipwcc;
59 + __be32 qipzcc;
60 + __be32 qimr;
61 + __be32 qrimr;
62 + __be32 qicnr;
63 + u8 res0[0x4];
64 + __be32 qiprta;
65 + __be32 qiprtb;
66 + u8 res1[0x4];
67 + __be32 qricr;
68 + u8 res2[0x20];
69 + __be32 qhivec;
70 + u8 res3[0x1C];
71 +} __packed;
72 +
73 +/* Communications Processor */
74 +struct cp_qe {
75 + __be32 cecr; /* QE command register */
76 + __be32 ceccr; /* QE controller configuration register */
77 + __be32 cecdr; /* QE command data register */
78 + u8 res0[0xA];
79 + __be16 ceter; /* QE timer event register */
80 + u8 res1[0x2];
81 + __be16 cetmr; /* QE timers mask register */
82 + __be32 cetscr; /* QE time-stamp timer control register */
83 + __be32 cetsr1; /* QE time-stamp register 1 */
84 + __be32 cetsr2; /* QE time-stamp register 2 */
85 + u8 res2[0x8];
86 + __be32 cevter; /* QE virtual tasks event register */
87 + __be32 cevtmr; /* QE virtual tasks mask register */
88 + __be16 cercr; /* QE RAM control register */
89 + u8 res3[0x2];
90 + u8 res4[0x24];
91 + __be16 ceexe1; /* QE external request 1 event register */
92 + u8 res5[0x2];
93 + __be16 ceexm1; /* QE external request 1 mask register */
94 + u8 res6[0x2];
95 + __be16 ceexe2; /* QE external request 2 event register */
96 + u8 res7[0x2];
97 + __be16 ceexm2; /* QE external request 2 mask register */
98 + u8 res8[0x2];
99 + __be16 ceexe3; /* QE external request 3 event register */
100 + u8 res9[0x2];
101 + __be16 ceexm3; /* QE external request 3 mask register */
102 + u8 res10[0x2];
103 + __be16 ceexe4; /* QE external request 4 event register */
104 + u8 res11[0x2];
105 + __be16 ceexm4; /* QE external request 4 mask register */
106 + u8 res12[0x3A];
107 + __be32 ceurnr; /* QE microcode revision number register */
108 + u8 res13[0x244];
109 +} __packed;
110 +
111 +/* QE Multiplexer */
112 +struct qe_mux {
113 + __be32 cmxgcr; /* CMX general clock route register */
114 + __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
115 + __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
116 + __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
117 + __be32 cmxucr[4]; /* CMX UCCx clock route registers */
118 + __be32 cmxupcr; /* CMX UPC clock route register */
119 + u8 res0[0x1C];
120 +} __packed;
121 +
122 +/* QE Timers */
123 +struct qe_timers {
124 + u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
125 + u8 res0[0x3];
126 + u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
127 + u8 res1[0xB];
128 + __be16 gtmdr1; /* Timer 1 mode register */
129 + __be16 gtmdr2; /* Timer 2 mode register */
130 + __be16 gtrfr1; /* Timer 1 reference register */
131 + __be16 gtrfr2; /* Timer 2 reference register */
132 + __be16 gtcpr1; /* Timer 1 capture register */
133 + __be16 gtcpr2; /* Timer 2 capture register */
134 + __be16 gtcnr1; /* Timer 1 counter */
135 + __be16 gtcnr2; /* Timer 2 counter */
136 + __be16 gtmdr3; /* Timer 3 mode register */
137 + __be16 gtmdr4; /* Timer 4 mode register */
138 + __be16 gtrfr3; /* Timer 3 reference register */
139 + __be16 gtrfr4; /* Timer 4 reference register */
140 + __be16 gtcpr3; /* Timer 3 capture register */
141 + __be16 gtcpr4; /* Timer 4 capture register */
142 + __be16 gtcnr3; /* Timer 3 counter */
143 + __be16 gtcnr4; /* Timer 4 counter */
144 + __be16 gtevr1; /* Timer 1 event register */
145 + __be16 gtevr2; /* Timer 2 event register */
146 + __be16 gtevr3; /* Timer 3 event register */
147 + __be16 gtevr4; /* Timer 4 event register */
148 + __be16 gtps; /* Timer 1 prescale register */
149 + u8 res2[0x46];
150 +} __packed;
151 +
152 +/* BRG */
153 +struct qe_brg {
154 + __be32 brgc[16]; /* BRG configuration registers */
155 + u8 res0[0x40];
156 +} __packed;
157 +
158 +/* SPI */
159 +struct spi {
160 + u8 res0[0x20];
161 + __be32 spmode; /* SPI mode register */
162 + u8 res1[0x2];
163 + u8 spie; /* SPI event register */
164 + u8 res2[0x1];
165 + u8 res3[0x2];
166 + u8 spim; /* SPI mask register */
167 + u8 res4[0x1];
168 + u8 res5[0x1];
169 + u8 spcom; /* SPI command register */
170 + u8 res6[0x2];
171 + __be32 spitd; /* SPI transmit data register (cpu mode) */
172 + __be32 spird; /* SPI receive data register (cpu mode) */
173 + u8 res7[0x8];
174 +} __packed;
175 +
176 +/* SI */
177 +struct si1 {
178 + __be16 sixmr1[4]; /* SI1 TDMx (x = A B C D) mode register */
179 + u8 siglmr1_h; /* SI1 global mode register high */
180 + u8 res0[0x1];
181 + u8 sicmdr1_h; /* SI1 command register high */
182 + u8 res2[0x1];
183 + u8 sistr1_h; /* SI1 status register high */
184 + u8 res3[0x1];
185 + __be16 sirsr1_h; /* SI1 RAM shadow address register high */
186 + u8 sitarc1; /* SI1 RAM counter Tx TDMA */
187 + u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
188 + u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
189 + u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
190 + u8 sirarc1; /* SI1 RAM counter Rx TDMA */
191 + u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
192 + u8 sircrc1; /* SI1 RAM counter Rx TDMC */
193 + u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
194 + u8 res4[0x8];
195 + __be16 siemr1; /* SI1 TDME mode register 16 bits */
196 + __be16 sifmr1; /* SI1 TDMF mode register 16 bits */
197 + __be16 sigmr1; /* SI1 TDMG mode register 16 bits */
198 + __be16 sihmr1; /* SI1 TDMH mode register 16 bits */
199 + u8 siglmg1_l; /* SI1 global mode register low 8 bits */
200 + u8 res5[0x1];
201 + u8 sicmdr1_l; /* SI1 command register low 8 bits */
202 + u8 res6[0x1];
203 + u8 sistr1_l; /* SI1 status register low 8 bits */
204 + u8 res7[0x1];
205 + __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
206 + u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
207 + u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
208 + u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
209 + u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
210 + u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
211 + u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
212 + u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
213 + u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
214 + u8 res8[0x8];
215 + __be32 siml1; /* SI1 multiframe limit register */
216 + u8 siedm1; /* SI1 extended diagnostic mode register */
217 + u8 res9[0xBB];
218 +} __packed;
219 +
220 +/* SI Routing Tables */
221 +struct sir {
222 + u8 tx[0x400];
223 + u8 rx[0x400];
224 + u8 res0[0x800];
225 +} __packed;
226 +
227 +/* USB Controller */
228 +struct qe_usb_ctlr {
229 + u8 usb_usmod;
230 + u8 usb_usadr;
231 + u8 usb_uscom;
232 + u8 res1[1];
233 + __be16 usb_usep[4];
234 + u8 res2[4];
235 + __be16 usb_usber;
236 + u8 res3[2];
237 + __be16 usb_usbmr;
238 + u8 res4[1];
239 + u8 usb_usbs;
240 + __be16 usb_ussft;
241 + u8 res5[2];
242 + __be16 usb_usfrn;
243 + u8 res6[0x22];
244 +} __packed;
245 +
246 +/* MCC */
247 +struct qe_mcc {
248 + __be32 mcce; /* MCC event register */
249 + __be32 mccm; /* MCC mask register */
250 + __be32 mccf; /* MCC configuration register */
251 + __be32 merl; /* MCC emergency request level register */
252 + u8 res0[0xF0];
253 +} __packed;
254 +
255 +/* QE UCC Slow */
256 +struct ucc_slow {
257 + __be32 gumr_l; /* UCCx general mode register (low) */
258 + __be32 gumr_h; /* UCCx general mode register (high) */
259 + __be16 upsmr; /* UCCx protocol-specific mode register */
260 + u8 res0[0x2];
261 + __be16 utodr; /* UCCx transmit on demand register */
262 + __be16 udsr; /* UCCx data synchronization register */
263 + __be16 ucce; /* UCCx event register */
264 + u8 res1[0x2];
265 + __be16 uccm; /* UCCx mask register */
266 + u8 res2[0x1];
267 + u8 uccs; /* UCCx status register */
268 + u8 res3[0x24];
269 + __be16 utpt;
270 + u8 res4[0x52];
271 + u8 guemr; /* UCC general extended mode register */
272 +} __packed;
273 +
274 +/* QE UCC Fast */
275 +struct ucc_fast {
276 + __be32 gumr; /* UCCx general mode register */
277 + __be32 upsmr; /* UCCx protocol-specific mode register */
278 + __be16 utodr; /* UCCx transmit on demand register */
279 + u8 res0[0x2];
280 + __be16 udsr; /* UCCx data synchronization register */
281 + u8 res1[0x2];
282 + __be32 ucce; /* UCCx event register */
283 + __be32 uccm; /* UCCx mask register */
284 + u8 uccs; /* UCCx status register */
285 + u8 res2[0x7];
286 + __be32 urfb; /* UCC receive FIFO base */
287 + __be16 urfs; /* UCC receive FIFO size */
288 + u8 res3[0x2];
289 + __be16 urfet; /* UCC receive FIFO emergency threshold */
290 + __be16 urfset; /* UCC receive FIFO special emergency
291 + threshold */
292 + __be32 utfb; /* UCC transmit FIFO base */
293 + __be16 utfs; /* UCC transmit FIFO size */
294 + u8 res4[0x2];
295 + __be16 utfet; /* UCC transmit FIFO emergency threshold */
296 + u8 res5[0x2];
297 + __be16 utftt; /* UCC transmit FIFO transmit threshold */
298 + u8 res6[0x2];
299 + __be16 utpt; /* UCC transmit polling timer */
300 + u8 res7[0x2];
301 + __be32 urtry; /* UCC retry counter register */
302 + u8 res8[0x4C];
303 + u8 guemr; /* UCC general extended mode register */
304 +} __packed;
305 +
306 +struct ucc {
307 + union {
308 + struct ucc_slow slow;
309 + struct ucc_fast fast;
310 + u8 res[0x200]; /* UCC blocks are 512 bytes each */
311 + };
312 +} __packed;
313 +
314 +/* MultiPHY UTOPIA POS Controllers (UPC) */
315 +struct upc {
316 + __be32 upgcr; /* UTOPIA/POS general configuration register */
317 + __be32 uplpa; /* UTOPIA/POS last PHY address */
318 + __be32 uphec; /* ATM HEC register */
319 + __be32 upuc; /* UTOPIA/POS UCC configuration */
320 + __be32 updc1; /* UTOPIA/POS device 1 configuration */
321 + __be32 updc2; /* UTOPIA/POS device 2 configuration */
322 + __be32 updc3; /* UTOPIA/POS device 3 configuration */
323 + __be32 updc4; /* UTOPIA/POS device 4 configuration */
324 + __be32 upstpa; /* UTOPIA/POS STPA threshold */
325 + u8 res0[0xC];
326 + __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
327 + __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
328 + __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
329 + __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
330 + __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
331 + __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
332 + __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
333 + __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
334 + __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
335 + __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
336 + __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
337 + __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
338 + __be32 upde1; /* UTOPIA/POS device 1 event */
339 + __be32 upde2; /* UTOPIA/POS device 2 event */
340 + __be32 upde3; /* UTOPIA/POS device 3 event */
341 + __be32 upde4; /* UTOPIA/POS device 4 event */
342 + __be16 uprp1;
343 + __be16 uprp2;
344 + __be16 uprp3;
345 + __be16 uprp4;
346 + u8 res1[0x8];
347 + __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
348 + __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
349 + __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
350 + __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
351 + __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
352 + __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
353 + __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
354 + __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
355 + __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
356 + __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
357 + __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
358 + __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
359 + __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
360 + __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
361 + __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
362 + __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
363 + __be32 uper1; /* Device 1 port enable register */
364 + __be32 uper2; /* Device 2 port enable register */
365 + __be32 uper3; /* Device 3 port enable register */
366 + __be32 uper4; /* Device 4 port enable register */
367 + u8 res2[0x150];
368 +} __packed;
369 +
370 +/* SDMA */
371 +struct sdma {
372 + __be32 sdsr; /* Serial DMA status register */
373 + __be32 sdmr; /* Serial DMA mode register */
374 + __be32 sdtr1; /* SDMA system bus threshold register */
375 + __be32 sdtr2; /* SDMA secondary bus threshold register */
376 + __be32 sdhy1; /* SDMA system bus hysteresis register */
377 + __be32 sdhy2; /* SDMA secondary bus hysteresis register */
378 + __be32 sdta1; /* SDMA system bus address register */
379 + __be32 sdta2; /* SDMA secondary bus address register */
380 + __be32 sdtm1; /* SDMA system bus MSNUM register */
381 + __be32 sdtm2; /* SDMA secondary bus MSNUM register */
382 + u8 res0[0x10];
383 + __be32 sdaqr; /* SDMA address bus qualify register */
384 + __be32 sdaqmr; /* SDMA address bus qualify mask register */
385 + u8 res1[0x4];
386 + __be32 sdebcr; /* SDMA CAM entries base register */
387 + u8 res2[0x38];
388 +} __packed;
389 +
390 +/* Debug Space */
391 +struct dbg {
392 + __be32 bpdcr; /* Breakpoint debug command register */
393 + __be32 bpdsr; /* Breakpoint debug status register */
394 + __be32 bpdmr; /* Breakpoint debug mask register */
395 + __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
396 + __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
397 + u8 res0[0x8];
398 + __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
399 + __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
400 + u8 res1[0x8];
401 + __be32 bprmir; /* Breakpoint request mode immediate register */
402 + __be32 bprmsr; /* Breakpoint request mode serial register */
403 + __be32 bpemr; /* Breakpoint exit mode register */
404 + u8 res2[0x48];
405 +} __packed;
406 +
407 +/*
408 + * RISC Special Registers (Trap and Breakpoint). These are described in
409 + * the QE Developer's Handbook.
410 + */
411 +struct rsp {
412 + __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
413 + u8 res0[64];
414 + __be32 ibcr0;
415 + __be32 ibs0;
416 + __be32 ibcnr0;
417 + u8 res1[4];
418 + __be32 ibcr1;
419 + __be32 ibs1;
420 + __be32 ibcnr1;
421 + __be32 npcr;
422 + __be32 dbcr;
423 + __be32 dbar;
424 + __be32 dbamr;
425 + __be32 dbsr;
426 + __be32 dbcnr;
427 + u8 res2[12];
428 + __be32 dbdr_h;
429 + __be32 dbdr_l;
430 + __be32 dbdmr_h;
431 + __be32 dbdmr_l;
432 + __be32 bsr;
433 + __be32 bor;
434 + __be32 bior;
435 + u8 res3[4];
436 + __be32 iatr[4];
437 + __be32 eccr; /* Exception control configuration register */
438 + __be32 eicr;
439 + u8 res4[0x100-0xf8];
440 +} __packed;
441 +
442 +struct qe_immap {
443 + struct qe_iram iram; /* I-RAM */
444 + struct qe_ic_regs ic; /* Interrupt Controller */
445 + struct cp_qe cp; /* Communications Processor */
446 + struct qe_mux qmx; /* QE Multiplexer */
447 + struct qe_timers qet; /* QE Timers */
448 + struct spi spi[0x2]; /* spi */
449 + struct qe_mcc mcc; /* mcc */
450 + struct qe_brg brg; /* brg */
451 + struct qe_usb_ctlr usb; /* USB */
452 + struct si1 si1; /* SI */
453 + u8 res11[0x800];
454 + struct sir sir; /* SI Routing Tables */
455 + struct ucc ucc1; /* ucc1 */
456 + struct ucc ucc3; /* ucc3 */
457 + struct ucc ucc5; /* ucc5 */
458 + struct ucc ucc7; /* ucc7 */
459 + u8 res12[0x600];
460 + struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
461 + struct ucc ucc2; /* ucc2 */
462 + struct ucc ucc4; /* ucc4 */
463 + struct ucc ucc6; /* ucc6 */
464 + struct ucc ucc8; /* ucc8 */
465 + u8 res13[0x600];
466 + struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
467 + struct sdma sdma; /* SDMA */
468 + struct dbg dbg; /* 0x104080 - 0x1040FF
469 + Debug Space */
470 + struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
471 + RISC Special Registers
472 + (Trap and Breakpoint) */
473 + u8 res14[0x300]; /* 0x104300 - 0x1045FF */
474 + u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
475 + u8 res16[0x8000]; /* 0x108000 - 0x110000 */
476 + u8 muram[0xC000]; /* 0x110000 - 0x11C000
477 + Multi-user RAM */
478 + u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
479 + u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
480 +} __packed;
481 +
482 +extern struct qe_immap __iomem *qe_immr;
483 +extern phys_addr_t get_qe_base(void);
484 +
485 +/*
486 + * Returns the offset within the QE address space of the given pointer.
487 + *
488 + * Note that the QE does not support 36-bit physical addresses, so if
489 + * get_qe_base() returns a number above 4GB, the caller will probably fail.
490 + */
491 +static inline phys_addr_t immrbar_virt_to_phys(void *address)
492 +{
493 + void *q = (void *)qe_immr;
494 +
495 + /* Is it a MURAM address? */
496 + if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
497 + return get_qe_base() + (address - q);
498 +
499 + /* It's an address returned by kmalloc */
500 + return virt_to_phys(address);
501 +}
502 +
503 +#endif /* __KERNEL__ */
504 +#endif /* _ASM_POWERPC_IMMAP_QE_H */
505 --- /dev/null
506 +++ b/include/linux/fsl/qe.h
507 @@ -0,0 +1,810 @@
508 +/*
509 + * Copyright (C) 2006, 2012 Freescale Semiconductor, Inc. All rights reserved.
510 + *
511 + * Authors: Shlomi Gridish <gridish@freescale.com>
512 + * Li Yang <leoli@freescale.com>
513 + *
514 + * Description:
515 + * QUICC Engine (QE) external definitions and structure.
516 + *
517 + * This program is free software; you can redistribute it and/or modify it
518 + * under the terms of the GNU General Public License as published by the
519 + * Free Software Foundation; either version 2 of the License, or (at your
520 + * option) any later version.
521 + */
522 +#ifndef _ASM_POWERPC_QE_H
523 +#define _ASM_POWERPC_QE_H
524 +#ifdef __KERNEL__
525 +
526 +#include <linux/spinlock.h>
527 +#include <linux/errno.h>
528 +#include <linux/err.h>
529 +#include <linux/of.h>
530 +#include <linux/of_address.h>
531 +#include <linux/fsl/immap_qe.h>
532 +
533 +#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
534 +#define QE_NUM_OF_BRGS 16
535 +#define QE_NUM_OF_PORTS 1024
536 +
537 +/* Memory partitions
538 +*/
539 +#define MEM_PART_SYSTEM 0
540 +#define MEM_PART_SECONDARY 1
541 +#define MEM_PART_MURAM 2
542 +
543 +extern int siram_init_flag;
544 +
545 +/* Clocks and BRGs */
546 +enum qe_clock {
547 + QE_CLK_NONE = 0,
548 + QE_BRG1, /* Baud Rate Generator 1 */
549 + QE_BRG2, /* Baud Rate Generator 2 */
550 + QE_BRG3, /* Baud Rate Generator 3 */
551 + QE_BRG4, /* Baud Rate Generator 4 */
552 + QE_BRG5, /* Baud Rate Generator 5 */
553 + QE_BRG6, /* Baud Rate Generator 6 */
554 + QE_BRG7, /* Baud Rate Generator 7 */
555 + QE_BRG8, /* Baud Rate Generator 8 */
556 + QE_BRG9, /* Baud Rate Generator 9 */
557 + QE_BRG10, /* Baud Rate Generator 10 */
558 + QE_BRG11, /* Baud Rate Generator 11 */
559 + QE_BRG12, /* Baud Rate Generator 12 */
560 + QE_BRG13, /* Baud Rate Generator 13 */
561 + QE_BRG14, /* Baud Rate Generator 14 */
562 + QE_BRG15, /* Baud Rate Generator 15 */
563 + QE_BRG16, /* Baud Rate Generator 16 */
564 + QE_CLK1, /* Clock 1 */
565 + QE_CLK2, /* Clock 2 */
566 + QE_CLK3, /* Clock 3 */
567 + QE_CLK4, /* Clock 4 */
568 + QE_CLK5, /* Clock 5 */
569 + QE_CLK6, /* Clock 6 */
570 + QE_CLK7, /* Clock 7 */
571 + QE_CLK8, /* Clock 8 */
572 + QE_CLK9, /* Clock 9 */
573 + QE_CLK10, /* Clock 10 */
574 + QE_CLK11, /* Clock 11 */
575 + QE_CLK12, /* Clock 12 */
576 + QE_CLK13, /* Clock 13 */
577 + QE_CLK14, /* Clock 14 */
578 + QE_CLK15, /* Clock 15 */
579 + QE_CLK16, /* Clock 16 */
580 + QE_CLK17, /* Clock 17 */
581 + QE_CLK18, /* Clock 18 */
582 + QE_CLK19, /* Clock 19 */
583 + QE_CLK20, /* Clock 20 */
584 + QE_CLK21, /* Clock 21 */
585 + QE_CLK22, /* Clock 22 */
586 + QE_CLK23, /* Clock 23 */
587 + QE_CLK24, /* Clock 24 */
588 + QE_RSYNC_PIN, /* RSYNC from pin */
589 + QE_TSYNC_PIN, /* TSYNC from pin */
590 + QE_CLK_DUMMY
591 +};
592 +
593 +static inline bool qe_clock_is_brg(enum qe_clock clk)
594 +{
595 + return clk >= QE_BRG1 && clk <= QE_BRG16;
596 +}
597 +
598 +extern spinlock_t cmxgcr_lock;
599 +
600 +/* Export QE common operations */
601 +#ifdef CONFIG_QUICC_ENGINE
602 +extern void qe_reset(void);
603 +#else
604 +static inline void qe_reset(void) {}
605 +#endif
606 +
607 +/* QE PIO */
608 +#define QE_PIO_PINS 32
609 +
610 +struct qe_pio_regs {
611 + __be32 cpodr; /* Open drain register */
612 + __be32 cpdata; /* Data register */
613 + __be32 cpdir1; /* Direction register */
614 + __be32 cpdir2; /* Direction register */
615 + __be32 cppar1; /* Pin assignment register */
616 + __be32 cppar2; /* Pin assignment register */
617 +#ifdef CONFIG_PPC_85xx
618 + u8 pad[8];
619 +#endif
620 +};
621 +
622 +#define QE_PIO_DIR_IN 2
623 +#define QE_PIO_DIR_OUT 1
624 +extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
625 + int dir, int open_drain, int assignment,
626 + int has_irq);
627 +#ifdef CONFIG_QUICC_ENGINE
628 +extern int par_io_init(struct device_node *np);
629 +extern int par_io_of_config(struct device_node *np);
630 +extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
631 + int assignment, int has_irq);
632 +extern int par_io_data_set(u8 port, u8 pin, u8 val);
633 +#else
634 +static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
635 +static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
636 +static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
637 + int assignment, int has_irq) { return -ENOSYS; }
638 +static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
639 +#endif /* CONFIG_QUICC_ENGINE */
640 +
641 +/*
642 + * Pin multiplexing functions.
643 + */
644 +struct qe_pin;
645 +#ifdef CONFIG_QE_GPIO
646 +extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
647 +extern void qe_pin_free(struct qe_pin *qe_pin);
648 +extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
649 +extern void qe_pin_set_dedicated(struct qe_pin *pin);
650 +#else
651 +static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
652 +{
653 + return ERR_PTR(-ENOSYS);
654 +}
655 +static inline void qe_pin_free(struct qe_pin *qe_pin) {}
656 +static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
657 +static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
658 +#endif /* CONFIG_QE_GPIO */
659 +
660 +#ifdef CONFIG_QUICC_ENGINE
661 +int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
662 +#else
663 +static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
664 + u32 cmd_input)
665 +{
666 + return -ENOSYS;
667 +}
668 +#endif /* CONFIG_QUICC_ENGINE */
669 +
670 +/* QE internal API */
671 +enum qe_clock qe_clock_source(const char *source);
672 +unsigned int qe_get_brg_clk(void);
673 +int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
674 +int qe_get_snum(void);
675 +void qe_put_snum(u8 snum);
676 +unsigned int qe_get_num_of_risc(void);
677 +unsigned int qe_get_num_of_snums(void);
678 +
679 +static inline int qe_alive_during_sleep(void)
680 +{
681 + /*
682 + * MPC8568E reference manual says:
683 + *
684 + * "...power down sequence waits for all I/O interfaces to become idle.
685 + * In some applications this may happen eventually without actively
686 + * shutting down interfaces, but most likely, software will have to
687 + * take steps to shut down the eTSEC, QUICC Engine Block, and PCI
688 + * interfaces before issuing the command (either the write to the core
689 + * MSR[WE] as described above or writing to POWMGTCSR) to put the
690 + * device into sleep state."
691 + *
692 + * MPC8569E reference manual has a similar paragraph.
693 + */
694 +#ifdef CONFIG_PPC_85xx
695 + return 0;
696 +#else
697 + return 1;
698 +#endif
699 +}
700 +
701 +int qe_muram_init(void);
702 +
703 +#if defined(CONFIG_QUICC_ENGINE)
704 +unsigned long qe_muram_alloc(unsigned long size, unsigned long align);
705 +int qe_muram_free(unsigned long offset);
706 +unsigned long qe_muram_alloc_fixed(unsigned long offset, unsigned long size);
707 +void __iomem *qe_muram_addr(unsigned long offset);
708 +unsigned long qe_muram_offset(void __iomem *addr);
709 +dma_addr_t qe_muram_dma(void __iomem *addr);
710 +#else
711 +static inline unsigned long qe_muram_alloc(unsigned long size,
712 + unsigned long align)
713 +{
714 + return -ENOSYS;
715 +}
716 +
717 +static inline int qe_muram_free(unsigned long offset)
718 +{
719 + return -ENOSYS;
720 +}
721 +
722 +static inline unsigned long qe_muram_alloc_fixed(unsigned long offset,
723 + unsigned long size)
724 +{
725 + return -ENOSYS;
726 +}
727 +
728 +static inline void __iomem *qe_muram_addr(unsigned long offset)
729 +{
730 + return NULL;
731 +}
732 +
733 +static inline unsigned long qe_muram_offset(void __iomem *addr)
734 +{
735 + return -ENOSYS;
736 +}
737 +
738 +static inline dma_addr_t qe_muram_dma(void __iomem *addr)
739 +{
740 + return 0;
741 +}
742 +#endif /* defined(CONFIG_QUICC_ENGINE) */
743 +
744 +/* Structure that defines QE firmware binary files.
745 + *
746 + * See Documentation/powerpc/qe_firmware.txt for a description of these
747 + * fields.
748 + */
749 +struct qe_firmware {
750 + struct qe_header {
751 + __be32 length; /* Length of the entire structure, in bytes */
752 + u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
753 + u8 version; /* Version of this layout. First ver is '1' */
754 + } header;
755 + u8 id[62]; /* Null-terminated identifier string */
756 + u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
757 + u8 count; /* Number of microcode[] structures */
758 + struct {
759 + __be16 model; /* The SOC model */
760 + u8 major; /* The SOC revision major */
761 + u8 minor; /* The SOC revision minor */
762 + } __packed soc;
763 + u8 padding[4]; /* Reserved, for alignment */
764 + __be64 extended_modes; /* Extended modes */
765 + __be32 vtraps[8]; /* Virtual trap addresses */
766 + u8 reserved[4]; /* Reserved, for future expansion */
767 + struct qe_microcode {
768 + u8 id[32]; /* Null-terminated identifier */
769 + __be32 traps[16]; /* Trap addresses, 0 == ignore */
770 + __be32 eccr; /* The value for the ECCR register */
771 + __be32 iram_offset; /* Offset into I-RAM for the code */
772 + __be32 count; /* Number of 32-bit words of the code */
773 + __be32 code_offset; /* Offset of the actual microcode */
774 + u8 major; /* The microcode version major */
775 + u8 minor; /* The microcode version minor */
776 + u8 revision; /* The microcode version revision */
777 + u8 padding; /* Reserved, for alignment */
778 + u8 reserved[4]; /* Reserved, for future expansion */
779 + } __packed microcode[1];
780 + /* All microcode binaries should be located here */
781 + /* CRC32 should be located here, after the microcode binaries */
782 +} __packed;
783 +
784 +struct qe_firmware_info {
785 + char id[64]; /* Firmware name */
786 + u32 vtraps[8]; /* Virtual trap addresses */
787 + u64 extended_modes; /* Extended modes */
788 +};
789 +
790 +#ifdef CONFIG_QUICC_ENGINE
791 +/* Upload a firmware to the QE */
792 +int qe_upload_firmware(const struct qe_firmware *firmware);
793 +#else
794 +static inline int qe_upload_firmware(const struct qe_firmware *firmware)
795 +{
796 + return -ENOSYS;
797 +}
798 +#endif /* CONFIG_QUICC_ENGINE */
799 +
800 +/* Obtain information on the uploaded firmware */
801 +struct qe_firmware_info *qe_get_firmware_info(void);
802 +
803 +/* QE USB */
804 +int qe_usb_clock_set(enum qe_clock clk, int rate);
805 +
806 +/* Buffer descriptors */
807 +struct qe_bd {
808 + __be16 status;
809 + __be16 length;
810 + __be32 buf;
811 +} __packed;
812 +
813 +#define BD_STATUS_MASK 0xffff0000
814 +#define BD_LENGTH_MASK 0x0000ffff
815 +
816 +/* Buffer descriptor control/status used by serial
817 + */
818 +
819 +#define BD_SC_EMPTY (0x8000) /* Receive is empty */
820 +#define BD_SC_READY (0x8000) /* Transmit is ready */
821 +#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
822 +#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
823 +#define BD_SC_LAST (0x0800) /* Last buffer in frame */
824 +#define BD_SC_TC (0x0400) /* Transmit CRC */
825 +#define BD_SC_CM (0x0200) /* Continuous mode */
826 +#define BD_SC_ID (0x0100) /* Rec'd too many idles */
827 +#define BD_SC_P (0x0100) /* xmt preamble */
828 +#define BD_SC_BR (0x0020) /* Break received */
829 +#define BD_SC_FR (0x0010) /* Framing error */
830 +#define BD_SC_PR (0x0008) /* Parity error */
831 +#define BD_SC_NAK (0x0004) /* NAK - did not respond */
832 +#define BD_SC_OV (0x0002) /* Overrun */
833 +#define BD_SC_UN (0x0002) /* Underrun */
834 +#define BD_SC_CD (0x0001) /* */
835 +#define BD_SC_CL (0x0001) /* Collision */
836 +
837 +/* Alignment */
838 +#define QE_INTR_TABLE_ALIGN 16 /* ??? */
839 +#define QE_ALIGNMENT_OF_BD 8
840 +#define QE_ALIGNMENT_OF_PRAM 64
841 +
842 +/* RISC allocation */
843 +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
844 +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
845 +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
846 +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
847 +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
848 + QE_RISC_ALLOCATION_RISC2)
849 +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
850 + QE_RISC_ALLOCATION_RISC2 | \
851 + QE_RISC_ALLOCATION_RISC3 | \
852 + QE_RISC_ALLOCATION_RISC4)
853 +
854 +/* QE extended filtering Table Lookup Key Size */
855 +enum qe_fltr_tbl_lookup_key_size {
856 + QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
857 + = 0x3f, /* LookupKey parsed by the Generate LookupKey
858 + CMD is truncated to 8 bytes */
859 + QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
860 + = 0x5f, /* LookupKey parsed by the Generate LookupKey
861 + CMD is truncated to 16 bytes */
862 +};
863 +
864 +/* QE FLTR extended filtering Largest External Table Lookup Key Size */
865 +enum qe_fltr_largest_external_tbl_lookup_key_size {
866 + QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
867 + = 0x0,/* not used */
868 + QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
869 + = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
870 + QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
871 + = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
872 +};
873 +
874 +/* structure representing QE parameter RAM */
875 +struct qe_timer_tables {
876 + u16 tm_base; /* QE timer table base adr */
877 + u16 tm_ptr; /* QE timer table pointer */
878 + u16 r_tmr; /* QE timer mode register */
879 + u16 r_tmv; /* QE timer valid register */
880 + u32 tm_cmd; /* QE timer cmd register */
881 + u32 tm_cnt; /* QE timer internal cnt */
882 +} __packed;
883 +
884 +#define QE_FLTR_TAD_SIZE 8
885 +
886 +/* QE extended filtering Termination Action Descriptor (TAD) */
887 +struct qe_fltr_tad {
888 + u8 serialized[QE_FLTR_TAD_SIZE];
889 +} __packed;
890 +
891 +/* Communication Direction */
892 +enum comm_dir {
893 + COMM_DIR_NONE = 0,
894 + COMM_DIR_RX = 1,
895 + COMM_DIR_TX = 2,
896 + COMM_DIR_RX_AND_TX = 3
897 +};
898 +
899 +/* QE CMXUCR Registers.
900 + * There are two UCCs represented in each of the four CMXUCR registers.
901 + * These values are for the UCC in the LSBs
902 + */
903 +#define QE_CMXUCR_MII_ENET_MNG 0x00007000
904 +#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
905 +#define QE_CMXUCR_GRANT 0x00008000
906 +#define QE_CMXUCR_TSA 0x00004000
907 +#define QE_CMXUCR_BKPT 0x00000100
908 +#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
909 +
910 +/* QE CMXGCR Registers.
911 +*/
912 +#define QE_CMXGCR_MII_ENET_MNG 0x00007000
913 +#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
914 +#define QE_CMXGCR_USBCS 0x0000000f
915 +#define QE_CMXGCR_USBCS_CLK3 0x1
916 +#define QE_CMXGCR_USBCS_CLK5 0x2
917 +#define QE_CMXGCR_USBCS_CLK7 0x3
918 +#define QE_CMXGCR_USBCS_CLK9 0x4
919 +#define QE_CMXGCR_USBCS_CLK13 0x5
920 +#define QE_CMXGCR_USBCS_CLK17 0x6
921 +#define QE_CMXGCR_USBCS_CLK19 0x7
922 +#define QE_CMXGCR_USBCS_CLK21 0x8
923 +#define QE_CMXGCR_USBCS_BRG9 0x9
924 +#define QE_CMXGCR_USBCS_BRG10 0xa
925 +
926 +/* QE CECR Commands.
927 +*/
928 +#define QE_CR_FLG 0x00010000
929 +#define QE_RESET 0x80000000
930 +#define QE_INIT_TX_RX 0x00000000
931 +#define QE_INIT_RX 0x00000001
932 +#define QE_INIT_TX 0x00000002
933 +#define QE_ENTER_HUNT_MODE 0x00000003
934 +#define QE_STOP_TX 0x00000004
935 +#define QE_GRACEFUL_STOP_TX 0x00000005
936 +#define QE_RESTART_TX 0x00000006
937 +#define QE_CLOSE_RX_BD 0x00000007
938 +#define QE_SWITCH_COMMAND 0x00000007
939 +#define QE_SET_GROUP_ADDRESS 0x00000008
940 +#define QE_START_IDMA 0x00000009
941 +#define QE_MCC_STOP_RX 0x00000009
942 +#define QE_ATM_TRANSMIT 0x0000000a
943 +#define QE_HPAC_CLEAR_ALL 0x0000000b
944 +#define QE_GRACEFUL_STOP_RX 0x0000001a
945 +#define QE_RESTART_RX 0x0000001b
946 +#define QE_HPAC_SET_PRIORITY 0x0000010b
947 +#define QE_HPAC_STOP_TX 0x0000020b
948 +#define QE_HPAC_STOP_RX 0x0000030b
949 +#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
950 +#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
951 +#define QE_HPAC_START_TX 0x0000060b
952 +#define QE_HPAC_START_RX 0x0000070b
953 +#define QE_USB_STOP_TX 0x0000000a
954 +#define QE_USB_RESTART_TX 0x0000000c
955 +#define QE_QMC_STOP_TX 0x0000000c
956 +#define QE_QMC_STOP_RX 0x0000000d
957 +#define QE_SS7_SU_FIL_RESET 0x0000000e
958 +/* jonathbr added from here down for 83xx */
959 +#define QE_RESET_BCS 0x0000000a
960 +#define QE_MCC_INIT_TX_RX_16 0x00000003
961 +#define QE_MCC_STOP_TX 0x00000004
962 +#define QE_MCC_INIT_TX_1 0x00000005
963 +#define QE_MCC_INIT_RX_1 0x00000006
964 +#define QE_MCC_RESET 0x00000007
965 +#define QE_SET_TIMER 0x00000008
966 +#define QE_RANDOM_NUMBER 0x0000000c
967 +#define QE_ATM_MULTI_THREAD_INIT 0x00000011
968 +#define QE_ASSIGN_PAGE 0x00000012
969 +#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
970 +#define QE_START_FLOW_CONTROL 0x00000014
971 +#define QE_STOP_FLOW_CONTROL 0x00000015
972 +#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
973 +
974 +#define QE_ASSIGN_RISC 0x00000010
975 +#define QE_CR_MCN_NORMAL_SHIFT 6
976 +#define QE_CR_MCN_USB_SHIFT 4
977 +#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
978 +#define QE_CR_SNUM_SHIFT 17
979 +
980 +/* QE CECR Sub Block - sub block of QE command.
981 +*/
982 +#define QE_CR_SUBBLOCK_INVALID 0x00000000
983 +#define QE_CR_SUBBLOCK_USB 0x03200000
984 +#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
985 +#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
986 +#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
987 +#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
988 +#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
989 +#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
990 +#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
991 +#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
992 +#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
993 +#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
994 +#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
995 +#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
996 +#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
997 +#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
998 +#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
999 +#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
1000 +#define QE_CR_SUBBLOCK_MCC1 0x03800000
1001 +#define QE_CR_SUBBLOCK_MCC2 0x03a00000
1002 +#define QE_CR_SUBBLOCK_MCC3 0x03000000
1003 +#define QE_CR_SUBBLOCK_IDMA1 0x02800000
1004 +#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
1005 +#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
1006 +#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
1007 +#define QE_CR_SUBBLOCK_HPAC 0x01e00000
1008 +#define QE_CR_SUBBLOCK_SPI1 0x01400000
1009 +#define QE_CR_SUBBLOCK_SPI2 0x01600000
1010 +#define QE_CR_SUBBLOCK_RAND 0x01c00000
1011 +#define QE_CR_SUBBLOCK_TIMER 0x01e00000
1012 +#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
1013 +
1014 +/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
1015 +#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
1016 +#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
1017 +#define QE_CR_PROTOCOL_QMC 0x02
1018 +#define QE_CR_PROTOCOL_UART 0x04
1019 +#define QE_CR_PROTOCOL_ATM_POS 0x0A
1020 +#define QE_CR_PROTOCOL_ETHERNET 0x0C
1021 +#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
1022 +
1023 +/* BRG configuration register */
1024 +#define QE_BRGC_ENABLE 0x00010000
1025 +#define QE_BRGC_DIVISOR_SHIFT 1
1026 +#define QE_BRGC_DIVISOR_MAX 0xFFF
1027 +#define QE_BRGC_DIV16 1
1028 +
1029 +/* QE Timers registers */
1030 +#define QE_GTCFR1_PCAS 0x80
1031 +#define QE_GTCFR1_STP2 0x20
1032 +#define QE_GTCFR1_RST2 0x10
1033 +#define QE_GTCFR1_GM2 0x08
1034 +#define QE_GTCFR1_GM1 0x04
1035 +#define QE_GTCFR1_STP1 0x02
1036 +#define QE_GTCFR1_RST1 0x01
1037 +
1038 +/* SDMA registers */
1039 +#define QE_SDSR_BER1 0x02000000
1040 +#define QE_SDSR_BER2 0x01000000
1041 +
1042 +#define QE_SDMR_GLB_1_MSK 0x80000000
1043 +#define QE_SDMR_ADR_SEL 0x20000000
1044 +#define QE_SDMR_BER1_MSK 0x02000000
1045 +#define QE_SDMR_BER2_MSK 0x01000000
1046 +#define QE_SDMR_EB1_MSK 0x00800000
1047 +#define QE_SDMR_ER1_MSK 0x00080000
1048 +#define QE_SDMR_ER2_MSK 0x00040000
1049 +#define QE_SDMR_CEN_MASK 0x0000E000
1050 +#define QE_SDMR_SBER_1 0x00000200
1051 +#define QE_SDMR_SBER_2 0x00000200
1052 +#define QE_SDMR_EB1_PR_MASK 0x000000C0
1053 +#define QE_SDMR_ER1_PR 0x00000008
1054 +
1055 +#define QE_SDMR_CEN_SHIFT 13
1056 +#define QE_SDMR_EB1_PR_SHIFT 6
1057 +
1058 +#define QE_SDTM_MSNUM_SHIFT 24
1059 +
1060 +#define QE_SDEBCR_BA_MASK 0x01FFFFFF
1061 +
1062 +/* Communication Processor */
1063 +#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
1064 +#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
1065 +#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
1066 +
1067 +/* I-RAM */
1068 +#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
1069 +#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
1070 +#define QE_IRAM_READY 0x80000000 /* Ready */
1071 +
1072 +/* UPC */
1073 +#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
1074 +#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
1075 +#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
1076 +#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
1077 +#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
1078 +
1079 +/* UCC GUEMR register */
1080 +#define UCC_GUEMR_MODE_MASK_RX 0x02
1081 +#define UCC_GUEMR_MODE_FAST_RX 0x02
1082 +#define UCC_GUEMR_MODE_SLOW_RX 0x00
1083 +#define UCC_GUEMR_MODE_MASK_TX 0x01
1084 +#define UCC_GUEMR_MODE_FAST_TX 0x01
1085 +#define UCC_GUEMR_MODE_SLOW_TX 0x00
1086 +#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
1087 +#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
1088 + must be set 1 */
1089 +
1090 +/* structure representing UCC SLOW parameter RAM */
1091 +struct ucc_slow_pram {
1092 + __be16 rbase; /* RX BD base address */
1093 + __be16 tbase; /* TX BD base address */
1094 + u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
1095 + u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
1096 + __be16 mrblr; /* Rx buffer length */
1097 + __be32 rstate; /* Rx internal state */
1098 + __be32 rptr; /* Rx internal data pointer */
1099 + __be16 rbptr; /* rb BD Pointer */
1100 + __be16 rcount; /* Rx internal byte count */
1101 + __be32 rtemp; /* Rx temp */
1102 + __be32 tstate; /* Tx internal state */
1103 + __be32 tptr; /* Tx internal data pointer */
1104 + __be16 tbptr; /* Tx BD pointer */
1105 + __be16 tcount; /* Tx byte count */
1106 + __be32 ttemp; /* Tx temp */
1107 + __be32 rcrc; /* temp receive CRC */
1108 + __be32 tcrc; /* temp transmit CRC */
1109 +} __packed;
1110 +
1111 +/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
1112 +#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
1113 +#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
1114 +#define UCC_SLOW_GUMR_H_REVD 0x00002000
1115 +#define UCC_SLOW_GUMR_H_TRX 0x00001000
1116 +#define UCC_SLOW_GUMR_H_TTX 0x00000800
1117 +#define UCC_SLOW_GUMR_H_CDP 0x00000400
1118 +#define UCC_SLOW_GUMR_H_CTSP 0x00000200
1119 +#define UCC_SLOW_GUMR_H_CDS 0x00000100
1120 +#define UCC_SLOW_GUMR_H_CTSS 0x00000080
1121 +#define UCC_SLOW_GUMR_H_TFL 0x00000040
1122 +#define UCC_SLOW_GUMR_H_RFW 0x00000020
1123 +#define UCC_SLOW_GUMR_H_TXSY 0x00000010
1124 +#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
1125 +#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
1126 +#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
1127 +#define UCC_SLOW_GUMR_H_RTSM 0x00000002
1128 +#define UCC_SLOW_GUMR_H_RSYN 0x00000001
1129 +
1130 +#define UCC_SLOW_GUMR_L_TCI 0x10000000
1131 +#define UCC_SLOW_GUMR_L_RINV 0x02000000
1132 +#define UCC_SLOW_GUMR_L_TINV 0x01000000
1133 +#define UCC_SLOW_GUMR_L_TEND 0x00040000
1134 +#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
1135 +#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
1136 +#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
1137 +#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
1138 +#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
1139 +#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
1140 +#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
1141 +#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
1142 +#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
1143 +#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
1144 +#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
1145 +#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
1146 +#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
1147 +#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
1148 +#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
1149 +#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
1150 +#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
1151 +#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
1152 +#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
1153 +#define UCC_SLOW_GUMR_L_ENR 0x00000020
1154 +#define UCC_SLOW_GUMR_L_ENT 0x00000010
1155 +#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
1156 +#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
1157 +#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
1158 +#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
1159 +#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
1160 +
1161 +/* General UCC FAST Mode Register */
1162 +#define UCC_FAST_GUMR_TCI 0x20000000
1163 +#define UCC_FAST_GUMR_TRX 0x10000000
1164 +#define UCC_FAST_GUMR_TTX 0x08000000
1165 +#define UCC_FAST_GUMR_CDP 0x04000000
1166 +#define UCC_FAST_GUMR_CTSP 0x02000000
1167 +#define UCC_FAST_GUMR_CDS 0x01000000
1168 +#define UCC_FAST_GUMR_CTSS 0x00800000
1169 +#define UCC_FAST_GUMR_TXSY 0x00020000
1170 +#define UCC_FAST_GUMR_RSYN 0x00010000
1171 +#define UCC_FAST_GUMR_RTSM 0x00002000
1172 +#define UCC_FAST_GUMR_REVD 0x00000400
1173 +#define UCC_FAST_GUMR_ENR 0x00000020
1174 +#define UCC_FAST_GUMR_ENT 0x00000010
1175 +
1176 +/* UART Slow UCC Event Register (UCCE) */
1177 +#define UCC_UART_UCCE_AB 0x0200
1178 +#define UCC_UART_UCCE_IDLE 0x0100
1179 +#define UCC_UART_UCCE_GRA 0x0080
1180 +#define UCC_UART_UCCE_BRKE 0x0040
1181 +#define UCC_UART_UCCE_BRKS 0x0020
1182 +#define UCC_UART_UCCE_CCR 0x0008
1183 +#define UCC_UART_UCCE_BSY 0x0004
1184 +#define UCC_UART_UCCE_TX 0x0002
1185 +#define UCC_UART_UCCE_RX 0x0001
1186 +
1187 +/* HDLC Slow UCC Event Register (UCCE) */
1188 +#define UCC_HDLC_UCCE_GLR 0x1000
1189 +#define UCC_HDLC_UCCE_GLT 0x0800
1190 +#define UCC_HDLC_UCCE_IDLE 0x0100
1191 +#define UCC_HDLC_UCCE_BRKE 0x0040
1192 +#define UCC_HDLC_UCCE_BRKS 0x0020
1193 +#define UCC_HDLC_UCCE_TXE 0x0010
1194 +#define UCC_HDLC_UCCE_RXF 0x0008
1195 +#define UCC_HDLC_UCCE_BSY 0x0004
1196 +#define UCC_HDLC_UCCE_TXB 0x0002
1197 +#define UCC_HDLC_UCCE_RXB 0x0001
1198 +
1199 +/* BISYNC Slow UCC Event Register (UCCE) */
1200 +#define UCC_BISYNC_UCCE_GRA 0x0080
1201 +#define UCC_BISYNC_UCCE_TXE 0x0010
1202 +#define UCC_BISYNC_UCCE_RCH 0x0008
1203 +#define UCC_BISYNC_UCCE_BSY 0x0004
1204 +#define UCC_BISYNC_UCCE_TXB 0x0002
1205 +#define UCC_BISYNC_UCCE_RXB 0x0001
1206 +
1207 +/* Transparent UCC Event Register (UCCE) */
1208 +#define UCC_TRANS_UCCE_GRA 0x0080
1209 +#define UCC_TRANS_UCCE_TXE 0x0010
1210 +#define UCC_TRANS_UCCE_RXF 0x0008
1211 +#define UCC_TRANS_UCCE_BSY 0x0004
1212 +#define UCC_TRANS_UCCE_TXB 0x0002
1213 +#define UCC_TRANS_UCCE_RXB 0x0001
1214 +
1215 +
1216 +/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
1217 +#define UCC_GETH_UCCE_MPD 0x80000000
1218 +#define UCC_GETH_UCCE_SCAR 0x40000000
1219 +#define UCC_GETH_UCCE_GRA 0x20000000
1220 +#define UCC_GETH_UCCE_CBPR 0x10000000
1221 +#define UCC_GETH_UCCE_BSY 0x08000000
1222 +#define UCC_GETH_UCCE_RXC 0x04000000
1223 +#define UCC_GETH_UCCE_TXC 0x02000000
1224 +#define UCC_GETH_UCCE_TXE 0x01000000
1225 +#define UCC_GETH_UCCE_TXB7 0x00800000
1226 +#define UCC_GETH_UCCE_TXB6 0x00400000
1227 +#define UCC_GETH_UCCE_TXB5 0x00200000
1228 +#define UCC_GETH_UCCE_TXB4 0x00100000
1229 +#define UCC_GETH_UCCE_TXB3 0x00080000
1230 +#define UCC_GETH_UCCE_TXB2 0x00040000
1231 +#define UCC_GETH_UCCE_TXB1 0x00020000
1232 +#define UCC_GETH_UCCE_TXB0 0x00010000
1233 +#define UCC_GETH_UCCE_RXB7 0x00008000
1234 +#define UCC_GETH_UCCE_RXB6 0x00004000
1235 +#define UCC_GETH_UCCE_RXB5 0x00002000
1236 +#define UCC_GETH_UCCE_RXB4 0x00001000
1237 +#define UCC_GETH_UCCE_RXB3 0x00000800
1238 +#define UCC_GETH_UCCE_RXB2 0x00000400
1239 +#define UCC_GETH_UCCE_RXB1 0x00000200
1240 +#define UCC_GETH_UCCE_RXB0 0x00000100
1241 +#define UCC_GETH_UCCE_RXF7 0x00000080
1242 +#define UCC_GETH_UCCE_RXF6 0x00000040
1243 +#define UCC_GETH_UCCE_RXF5 0x00000020
1244 +#define UCC_GETH_UCCE_RXF4 0x00000010
1245 +#define UCC_GETH_UCCE_RXF3 0x00000008
1246 +#define UCC_GETH_UCCE_RXF2 0x00000004
1247 +#define UCC_GETH_UCCE_RXF1 0x00000002
1248 +#define UCC_GETH_UCCE_RXF0 0x00000001
1249 +
1250 +/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
1251 +#define UCC_UART_UPSMR_FLC 0x8000
1252 +#define UCC_UART_UPSMR_SL 0x4000
1253 +#define UCC_UART_UPSMR_CL_MASK 0x3000
1254 +#define UCC_UART_UPSMR_CL_8 0x3000
1255 +#define UCC_UART_UPSMR_CL_7 0x2000
1256 +#define UCC_UART_UPSMR_CL_6 0x1000
1257 +#define UCC_UART_UPSMR_CL_5 0x0000
1258 +#define UCC_UART_UPSMR_UM_MASK 0x0c00
1259 +#define UCC_UART_UPSMR_UM_NORMAL 0x0000
1260 +#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
1261 +#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
1262 +#define UCC_UART_UPSMR_FRZ 0x0200
1263 +#define UCC_UART_UPSMR_RZS 0x0100
1264 +#define UCC_UART_UPSMR_SYN 0x0080
1265 +#define UCC_UART_UPSMR_DRT 0x0040
1266 +#define UCC_UART_UPSMR_PEN 0x0010
1267 +#define UCC_UART_UPSMR_RPM_MASK 0x000c
1268 +#define UCC_UART_UPSMR_RPM_ODD 0x0000
1269 +#define UCC_UART_UPSMR_RPM_LOW 0x0004
1270 +#define UCC_UART_UPSMR_RPM_EVEN 0x0008
1271 +#define UCC_UART_UPSMR_RPM_HIGH 0x000C
1272 +#define UCC_UART_UPSMR_TPM_MASK 0x0003
1273 +#define UCC_UART_UPSMR_TPM_ODD 0x0000
1274 +#define UCC_UART_UPSMR_TPM_LOW 0x0001
1275 +#define UCC_UART_UPSMR_TPM_EVEN 0x0002
1276 +#define UCC_UART_UPSMR_TPM_HIGH 0x0003
1277 +
1278 +/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
1279 +#define UCC_GETH_UPSMR_FTFE 0x80000000
1280 +#define UCC_GETH_UPSMR_PTPE 0x40000000
1281 +#define UCC_GETH_UPSMR_ECM 0x04000000
1282 +#define UCC_GETH_UPSMR_HSE 0x02000000
1283 +#define UCC_GETH_UPSMR_PRO 0x00400000
1284 +#define UCC_GETH_UPSMR_CAP 0x00200000
1285 +#define UCC_GETH_UPSMR_RSH 0x00100000
1286 +#define UCC_GETH_UPSMR_RPM 0x00080000
1287 +#define UCC_GETH_UPSMR_R10M 0x00040000
1288 +#define UCC_GETH_UPSMR_RLPB 0x00020000
1289 +#define UCC_GETH_UPSMR_TBIM 0x00010000
1290 +#define UCC_GETH_UPSMR_RES1 0x00002000
1291 +#define UCC_GETH_UPSMR_RMM 0x00001000
1292 +#define UCC_GETH_UPSMR_CAM 0x00000400
1293 +#define UCC_GETH_UPSMR_BRO 0x00000200
1294 +#define UCC_GETH_UPSMR_SMM 0x00000080
1295 +#define UCC_GETH_UPSMR_SGMM 0x00000020
1296 +
1297 +/* UCC Transmit On Demand Register (UTODR) */
1298 +#define UCC_SLOW_TOD 0x8000
1299 +#define UCC_FAST_TOD 0x8000
1300 +
1301 +/* UCC Bus Mode Register masks */
1302 +/* Not to be confused with the Bundle Mode Register */
1303 +#define UCC_BMR_GBL 0x20
1304 +#define UCC_BMR_BO_BE 0x10
1305 +#define UCC_BMR_CETM 0x04
1306 +#define UCC_BMR_DTB 0x02
1307 +#define UCC_BMR_BDB 0x01
1308 +
1309 +/* Function code masks */
1310 +#define FC_GBL 0x20
1311 +#define FC_DTB_LCL 0x02
1312 +#define UCC_FAST_FUNCTION_CODE_GBL 0x20
1313 +#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
1314 +#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
1315 +
1316 +#endif /* __KERNEL__ */
1317 +#endif /* _ASM_POWERPC_QE_H */
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