kernel: bump 4.9 to 4.9.63
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 302-dts-support-layercape.patch
1 From bfa4a794f91162cfeccfa4d59121cde9a84e32a3 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 10:02:10 +0800
4 Subject: [PATCH] dts: support layercape
5
6 This is a integrated patch for layerscape dts support.
7
8 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 Signed-off-by: Li Yang <leoyang.li@nxp.com>
11 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
12 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
15 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
18 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
19 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
20 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
21 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
22 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
23 Signed-off-by: Meng Yi <meng.yi@nxp.com>
24 Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
25 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
26 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
27 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
28 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
29 ---
30 arch/arm/boot/dts/alpine.dtsi | 2 +-
31 arch/arm/boot/dts/axm55xx.dtsi | 2 +-
32 arch/arm/boot/dts/ecx-2000.dts | 2 +-
33 arch/arm/boot/dts/imx6ul.dtsi | 4 +-
34 arch/arm/boot/dts/keystone.dtsi | 4 +-
35 arch/arm/boot/dts/ls1021a-qds.dts | 13 +
36 arch/arm/boot/dts/ls1021a-twr.dts | 13 +
37 arch/arm/boot/dts/ls1021a.dtsi | 155 ++--
38 arch/arm/boot/dts/mt6580.dtsi | 2 +-
39 arch/arm/boot/dts/mt6589.dtsi | 2 +-
40 arch/arm/boot/dts/mt8127.dtsi | 2 +-
41 arch/arm/boot/dts/mt8135.dtsi | 2 +-
42 arch/arm/boot/dts/rk3288.dtsi | 2 +-
43 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
44 arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
45 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
46 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
47 arch/arm64/boot/dts/freescale/Makefile | 16 +
48 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 177 ++++
49 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 198 +++++
50 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 134 +++
51 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 594 ++++++++++++++
52 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi | 45 +
53 .../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 69 ++
54 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 171 +++-
55 .../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 69 ++
56 .../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
57 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 113 ++-
58 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 302 ++++++-
59 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi | 48 ++
60 .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 109 +++
61 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 363 ++++++++
62 .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 76 ++
63 .../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
64 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 218 +++++
65 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 793 ++++++++++++++++++
66 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 173 ++++
67 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 236 ++++++
68 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 818 ++++++++++++++++++
69 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 191 ++---
70 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 169 ++--
71 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 9 +-
72 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 763 +++--------------
73 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++
74 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 162 ++++
75 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 140 ++++
76 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 195 +++++
77 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
78 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
79 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 912 +++++++++++++++++++++
80 .../boot/dts/freescale/qoriq-bman1-portals.dtsi | 81 ++
81 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 66 ++
82 .../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
83 .../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
84 .../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
85 .../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 +
86 .../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 +
87 .../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 +
88 .../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 +
89 .../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 +
90 .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++
91 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++
92 .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 104 +++
93 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
94 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
95 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
96 66 files changed, 7988 insertions(+), 1021 deletions(-)
97 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
98 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
99 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
100 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
101 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
102 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
103 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
104 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
105 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
106 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
107 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
108 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
109 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
110 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
111 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
112 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
113 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
114 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
115 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
116 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
117 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
118 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
119 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
120 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
121 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
122 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
123 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
124 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
125 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
126 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
127 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
128 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
129 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
130 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
131 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
132 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
133 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
134 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
135
136 --- a/arch/arm/boot/dts/alpine.dtsi
137 +++ b/arch/arm/boot/dts/alpine.dtsi
138 @@ -93,7 +93,7 @@
139 interrupt-controller;
140 reg = <0x0 0xfb001000 0x0 0x1000>,
141 <0x0 0xfb002000 0x0 0x2000>,
142 - <0x0 0xfb004000 0x0 0x1000>,
143 + <0x0 0xfb004000 0x0 0x2000>,
144 <0x0 0xfb006000 0x0 0x2000>;
145 interrupts =
146 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
147 --- a/arch/arm/boot/dts/axm55xx.dtsi
148 +++ b/arch/arm/boot/dts/axm55xx.dtsi
149 @@ -62,7 +62,7 @@
150 #address-cells = <0>;
151 interrupt-controller;
152 reg = <0x20 0x01001000 0 0x1000>,
153 - <0x20 0x01002000 0 0x1000>,
154 + <0x20 0x01002000 0 0x2000>,
155 <0x20 0x01004000 0 0x2000>,
156 <0x20 0x01006000 0 0x2000>;
157 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
158 --- a/arch/arm/boot/dts/ecx-2000.dts
159 +++ b/arch/arm/boot/dts/ecx-2000.dts
160 @@ -99,7 +99,7 @@
161 interrupt-controller;
162 interrupts = <1 9 0xf04>;
163 reg = <0xfff11000 0x1000>,
164 - <0xfff12000 0x1000>,
165 + <0xfff12000 0x2000>,
166 <0xfff14000 0x2000>,
167 <0xfff16000 0x2000>;
168 };
169 --- a/arch/arm/boot/dts/imx6ul.dtsi
170 +++ b/arch/arm/boot/dts/imx6ul.dtsi
171 @@ -89,11 +89,11 @@
172 };
173
174 intc: interrupt-controller@00a01000 {
175 - compatible = "arm,cortex-a7-gic";
176 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
177 #interrupt-cells = <3>;
178 interrupt-controller;
179 reg = <0x00a01000 0x1000>,
180 - <0x00a02000 0x1000>,
181 + <0x00a02000 0x2000>,
182 <0x00a04000 0x2000>,
183 <0x00a06000 0x2000>;
184 };
185 --- a/arch/arm/boot/dts/keystone.dtsi
186 +++ b/arch/arm/boot/dts/keystone.dtsi
187 @@ -30,12 +30,12 @@
188 };
189
190 gic: interrupt-controller {
191 - compatible = "arm,cortex-a15-gic";
192 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
193 #interrupt-cells = <3>;
194 interrupt-controller;
195 reg = <0x0 0x02561000 0x0 0x1000>,
196 <0x0 0x02562000 0x0 0x2000>,
197 - <0x0 0x02564000 0x0 0x1000>,
198 + <0x0 0x02564000 0x0 0x2000>,
199 <0x0 0x02566000 0x0 0x2000>;
200 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
201 IRQ_TYPE_LEVEL_HIGH)>;
202 --- a/arch/arm/boot/dts/ls1021a-qds.dts
203 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
204 @@ -124,6 +124,19 @@
205 };
206 };
207
208 +&qspi {
209 + num-cs = <2>;
210 + status = "okay";
211 +
212 + qflash0: s25fl128s@0 {
213 + compatible = "spansion,m25p80";
214 + #address-cells = <1>;
215 + #size-cells = <1>;
216 + spi-max-frequency = <20000000>;
217 + reg = <0>;
218 + };
219 +};
220 +
221 &enet0 {
222 tbi-handle = <&tbi0>;
223 phy-handle = <&sgmii_phy1c>;
224 --- a/arch/arm/boot/dts/ls1021a-twr.dts
225 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
226 @@ -142,6 +142,19 @@
227 };
228 };
229
230 +&qspi {
231 + num-cs = <2>;
232 + status = "okay";
233 +
234 + qflash0: n25q128a13@0 {
235 + compatible = "n25q128a13", "jedec,spi-nor";
236 + #address-cells = <1>;
237 + #size-cells = <1>;
238 + spi-max-frequency = <20000000>;
239 + reg = <0>;
240 + };
241 +};
242 +
243 &enet0 {
244 tbi-handle = <&tbi1>;
245 phy-handle = <&sgmii_phy2>;
246 --- a/arch/arm/boot/dts/ls1021a.dtsi
247 +++ b/arch/arm/boot/dts/ls1021a.dtsi
248 @@ -74,17 +74,24 @@
249 compatible = "arm,cortex-a7";
250 device_type = "cpu";
251 reg = <0xf00>;
252 - clocks = <&cluster1_clk>;
253 + clocks = <&clockgen 1 0>;
254 };
255
256 cpu@f01 {
257 compatible = "arm,cortex-a7";
258 device_type = "cpu";
259 reg = <0xf01>;
260 - clocks = <&cluster1_clk>;
261 + clocks = <&clockgen 1 0>;
262 };
263 };
264
265 + sysclk: sysclk {
266 + compatible = "fixed-clock";
267 + #clock-cells = <0>;
268 + clock-frequency = <100000000>;
269 + clock-output-names = "sysclk";
270 + };
271 +
272 timer {
273 compatible = "arm,armv7-timer";
274 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
275 @@ -108,11 +115,11 @@
276 ranges;
277
278 gic: interrupt-controller@1400000 {
279 - compatible = "arm,cortex-a7-gic";
280 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
281 #interrupt-cells = <3>;
282 interrupt-controller;
283 reg = <0x0 0x1401000 0x0 0x1000>,
284 - <0x0 0x1402000 0x0 0x1000>,
285 + <0x0 0x1402000 0x0 0x2000>,
286 <0x0 0x1404000 0x0 0x2000>,
287 <0x0 0x1406000 0x0 0x2000>;
288 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
289 @@ -120,14 +127,14 @@
290 };
291
292 msi1: msi-controller@1570e00 {
293 - compatible = "fsl,1s1021a-msi";
294 + compatible = "fsl,ls1021a-msi";
295 reg = <0x0 0x1570e00 0x0 0x8>;
296 msi-controller;
297 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
298 };
299
300 msi2: msi-controller@1570e08 {
301 - compatible = "fsl,1s1021a-msi";
302 + compatible = "fsl,ls1021a-msi";
303 reg = <0x0 0x1570e08 0x0 0x8>;
304 msi-controller;
305 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
306 @@ -137,11 +144,12 @@
307 compatible = "fsl,ifc", "simple-bus";
308 reg = <0x0 0x1530000 0x0 0x10000>;
309 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
310 + big-endian;
311 };
312
313 dcfg: dcfg@1ee0000 {
314 compatible = "fsl,ls1021a-dcfg", "syscon";
315 - reg = <0x0 0x1ee0000 0x0 0x10000>;
316 + reg = <0x0 0x1ee0000 0x0 0x1000>;
317 big-endian;
318 };
319
320 @@ -163,7 +171,7 @@
321 <0x0 0x20220520 0x0 0x4>;
322 reg-names = "ahci", "sata-ecc";
323 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
324 - clocks = <&platform_clk 1>;
325 + clocks = <&clockgen 4 1>;
326 dma-coherent;
327 status = "disabled";
328 };
329 @@ -214,41 +222,10 @@
330 };
331
332 clockgen: clocking@1ee1000 {
333 - #address-cells = <1>;
334 - #size-cells = <1>;
335 - ranges = <0x0 0x0 0x1ee1000 0x10000>;
336 -
337 - sysclk: sysclk {
338 - compatible = "fixed-clock";
339 - #clock-cells = <0>;
340 - clock-output-names = "sysclk";
341 - };
342 -
343 - cga_pll1: pll@800 {
344 - compatible = "fsl,qoriq-core-pll-2.0";
345 - #clock-cells = <1>;
346 - reg = <0x800 0x10>;
347 - clocks = <&sysclk>;
348 - clock-output-names = "cga-pll1", "cga-pll1-div2",
349 - "cga-pll1-div4";
350 - };
351 -
352 - platform_clk: pll@c00 {
353 - compatible = "fsl,qoriq-core-pll-2.0";
354 - #clock-cells = <1>;
355 - reg = <0xc00 0x10>;
356 - clocks = <&sysclk>;
357 - clock-output-names = "platform-clk", "platform-clk-div2";
358 - };
359 -
360 - cluster1_clk: clk0c0@0 {
361 - compatible = "fsl,qoriq-core-mux-2.0";
362 - #clock-cells = <0>;
363 - reg = <0x0 0x10>;
364 - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
365 - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
366 - clock-output-names = "cluster1-clk";
367 - };
368 + compatible = "fsl,ls1021a-clockgen";
369 + reg = <0x0 0x1ee1000 0x0 0x1000>;
370 + #clock-cells = <2>;
371 + clocks = <&sysclk>;
372 };
373
374 dspi0: dspi@2100000 {
375 @@ -258,7 +235,7 @@
376 reg = <0x0 0x2100000 0x0 0x10000>;
377 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
378 clock-names = "dspi";
379 - clocks = <&platform_clk 1>;
380 + clocks = <&clockgen 4 1>;
381 spi-num-chipselects = <6>;
382 big-endian;
383 status = "disabled";
384 @@ -271,12 +248,27 @@
385 reg = <0x0 0x2110000 0x0 0x10000>;
386 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
387 clock-names = "dspi";
388 - clocks = <&platform_clk 1>;
389 + clocks = <&clockgen 4 1>;
390 spi-num-chipselects = <6>;
391 big-endian;
392 status = "disabled";
393 };
394
395 + qspi: quadspi@1550000 {
396 + compatible = "fsl,ls1021a-qspi";
397 + #address-cells = <1>;
398 + #size-cells = <0>;
399 + reg = <0x0 0x1550000 0x0 0x10000>,
400 + <0x0 0x40000000 0x0 0x4000000>;
401 + reg-names = "QuadSPI", "QuadSPI-memory";
402 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
403 + clock-names = "qspi_en", "qspi";
404 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
405 + big-endian;
406 + amba-base = <0x40000000>;
407 + status = "disabled";
408 + };
409 +
410 i2c0: i2c@2180000 {
411 compatible = "fsl,vf610-i2c";
412 #address-cells = <1>;
413 @@ -284,7 +276,7 @@
414 reg = <0x0 0x2180000 0x0 0x10000>;
415 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
416 clock-names = "i2c";
417 - clocks = <&platform_clk 1>;
418 + clocks = <&clockgen 4 1>;
419 status = "disabled";
420 };
421
422 @@ -295,7 +287,7 @@
423 reg = <0x0 0x2190000 0x0 0x10000>;
424 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
425 clock-names = "i2c";
426 - clocks = <&platform_clk 1>;
427 + clocks = <&clockgen 4 1>;
428 status = "disabled";
429 };
430
431 @@ -306,7 +298,7 @@
432 reg = <0x0 0x21a0000 0x0 0x10000>;
433 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
434 clock-names = "i2c";
435 - clocks = <&platform_clk 1>;
436 + clocks = <&clockgen 4 1>;
437 status = "disabled";
438 };
439
440 @@ -399,7 +391,7 @@
441 compatible = "fsl,ls1021a-lpuart";
442 reg = <0x0 0x2960000 0x0 0x1000>;
443 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
444 - clocks = <&platform_clk 1>;
445 + clocks = <&clockgen 4 1>;
446 clock-names = "ipg";
447 status = "disabled";
448 };
449 @@ -408,7 +400,7 @@
450 compatible = "fsl,ls1021a-lpuart";
451 reg = <0x0 0x2970000 0x0 0x1000>;
452 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
453 - clocks = <&platform_clk 1>;
454 + clocks = <&clockgen 4 1>;
455 clock-names = "ipg";
456 status = "disabled";
457 };
458 @@ -417,7 +409,7 @@
459 compatible = "fsl,ls1021a-lpuart";
460 reg = <0x0 0x2980000 0x0 0x1000>;
461 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
462 - clocks = <&platform_clk 1>;
463 + clocks = <&clockgen 4 1>;
464 clock-names = "ipg";
465 status = "disabled";
466 };
467 @@ -426,7 +418,7 @@
468 compatible = "fsl,ls1021a-lpuart";
469 reg = <0x0 0x2990000 0x0 0x1000>;
470 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
471 - clocks = <&platform_clk 1>;
472 + clocks = <&clockgen 4 1>;
473 clock-names = "ipg";
474 status = "disabled";
475 };
476 @@ -435,16 +427,26 @@
477 compatible = "fsl,ls1021a-lpuart";
478 reg = <0x0 0x29a0000 0x0 0x1000>;
479 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
480 - clocks = <&platform_clk 1>;
481 + clocks = <&clockgen 4 1>;
482 clock-names = "ipg";
483 status = "disabled";
484 };
485
486 + ftm0: ftm0@29d0000 {
487 + compatible = "fsl,ls1021a-ftm";
488 + reg = <0x0 0x29d0000 0x0 0x10000>,
489 + <0x0 0x1ee2140 0x0 0x4>;
490 + reg-names = "ftm", "FlexTimer1";
491 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
492 + big-endian;
493 + status = "okay";
494 + };
495 +
496 wdog0: watchdog@2ad0000 {
497 compatible = "fsl,imx21-wdt";
498 reg = <0x0 0x2ad0000 0x0 0x10000>;
499 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
500 - clocks = <&platform_clk 1>;
501 + clocks = <&clockgen 4 1>;
502 clock-names = "wdog-en";
503 big-endian;
504 };
505 @@ -454,8 +456,8 @@
506 compatible = "fsl,vf610-sai";
507 reg = <0x0 0x2b50000 0x0 0x10000>;
508 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
509 - clocks = <&platform_clk 1>, <&platform_clk 1>,
510 - <&platform_clk 1>, <&platform_clk 1>;
511 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
512 + <&clockgen 4 1>, <&clockgen 4 1>;
513 clock-names = "bus", "mclk1", "mclk2", "mclk3";
514 dma-names = "tx", "rx";
515 dmas = <&edma0 1 47>,
516 @@ -468,8 +470,8 @@
517 compatible = "fsl,vf610-sai";
518 reg = <0x0 0x2b60000 0x0 0x10000>;
519 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
520 - clocks = <&platform_clk 1>, <&platform_clk 1>,
521 - <&platform_clk 1>, <&platform_clk 1>;
522 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
523 + <&clockgen 4 1>, <&clockgen 4 1>;
524 clock-names = "bus", "mclk1", "mclk2", "mclk3";
525 dma-names = "tx", "rx";
526 dmas = <&edma0 1 45>,
527 @@ -489,16 +491,31 @@
528 dma-channels = <32>;
529 big-endian;
530 clock-names = "dmamux0", "dmamux1";
531 - clocks = <&platform_clk 1>,
532 - <&platform_clk 1>;
533 + clocks = <&clockgen 4 1>,
534 + <&clockgen 4 1>;
535 + };
536 +
537 + qdma: qdma@8390000 {
538 + compatible = "fsl,ls1021a-qdma";
539 + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
540 + <0x0 0x8389000 0x0 0x1000>, /* Status regs */
541 + <0x0 0x838a000 0x0 0x2000>; /* Block regs */
542 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
543 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
544 + interrupt-names = "qdma-error", "qdma-queue";
545 + channels = <8>;
546 + queues = <2>;
547 + status-sizes = <64>;
548 + queue-sizes = <64 64>;
549 + big-endian;
550 };
551
552 dcu: dcu@2ce0000 {
553 compatible = "fsl,ls1021a-dcu";
554 reg = <0x0 0x2ce0000 0x0 0x10000>;
555 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
556 - clocks = <&platform_clk 0>,
557 - <&platform_clk 0>;
558 + clocks = <&clockgen 4 0>,
559 + <&clockgen 4 0>;
560 clock-names = "dcu", "pix";
561 big-endian;
562 status = "disabled";
563 @@ -626,6 +643,8 @@
564 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
565 dr_mode = "host";
566 snps,quirk-frame-length-adjustment = <0x20>;
567 + configure-gfladj;
568 + dma-coherent;
569 snps,dis_rxdet_inp3_quirk;
570 };
571
572 @@ -634,7 +653,9 @@
573 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
574 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
575 reg-names = "regs", "config";
576 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
577 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
578 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
579 + interrupt-names = "pme", "aer";
580 fsl,pcie-scfg = <&scfg 0>;
581 #address-cells = <3>;
582 #size-cells = <2>;
583 @@ -643,7 +664,7 @@
584 bus-range = <0x0 0xff>;
585 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
586 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
587 - msi-parent = <&msi1>;
588 + msi-parent = <&msi1>, <&msi2>;
589 #interrupt-cells = <1>;
590 interrupt-map-mask = <0 0 0 7>;
591 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
592 @@ -657,7 +678,9 @@
593 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
594 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
595 reg-names = "regs", "config";
596 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
597 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
598 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
599 + interrupt-names = "pme", "aer";
600 fsl,pcie-scfg = <&scfg 1>;
601 #address-cells = <3>;
602 #size-cells = <2>;
603 @@ -666,7 +689,7 @@
604 bus-range = <0x0 0xff>;
605 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
606 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
607 - msi-parent = <&msi2>;
608 + msi-parent = <&msi1>, <&msi2>;
609 #interrupt-cells = <1>;
610 interrupt-map-mask = <0 0 0 7>;
611 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
612 --- a/arch/arm/boot/dts/mt6580.dtsi
613 +++ b/arch/arm/boot/dts/mt6580.dtsi
614 @@ -91,7 +91,7 @@
615 #interrupt-cells = <3>;
616 interrupt-parent = <&gic>;
617 reg = <0x10211000 0x1000>,
618 - <0x10212000 0x1000>,
619 + <0x10212000 0x2000>,
620 <0x10214000 0x2000>,
621 <0x10216000 0x2000>;
622 };
623 --- a/arch/arm/boot/dts/mt6589.dtsi
624 +++ b/arch/arm/boot/dts/mt6589.dtsi
625 @@ -102,7 +102,7 @@
626 #interrupt-cells = <3>;
627 interrupt-parent = <&gic>;
628 reg = <0x10211000 0x1000>,
629 - <0x10212000 0x1000>,
630 + <0x10212000 0x2000>,
631 <0x10214000 0x2000>,
632 <0x10216000 0x2000>;
633 };
634 --- a/arch/arm/boot/dts/mt8127.dtsi
635 +++ b/arch/arm/boot/dts/mt8127.dtsi
636 @@ -129,7 +129,7 @@
637 #interrupt-cells = <3>;
638 interrupt-parent = <&gic>;
639 reg = <0 0x10211000 0 0x1000>,
640 - <0 0x10212000 0 0x1000>,
641 + <0 0x10212000 0 0x2000>,
642 <0 0x10214000 0 0x2000>,
643 <0 0x10216000 0 0x2000>;
644 };
645 --- a/arch/arm/boot/dts/mt8135.dtsi
646 +++ b/arch/arm/boot/dts/mt8135.dtsi
647 @@ -221,7 +221,7 @@
648 #interrupt-cells = <3>;
649 interrupt-parent = <&gic>;
650 reg = <0 0x10211000 0 0x1000>,
651 - <0 0x10212000 0 0x1000>,
652 + <0 0x10212000 0 0x2000>,
653 <0 0x10214000 0 0x2000>,
654 <0 0x10216000 0 0x2000>;
655 };
656 --- a/arch/arm/boot/dts/rk3288.dtsi
657 +++ b/arch/arm/boot/dts/rk3288.dtsi
658 @@ -1109,7 +1109,7 @@
659 #address-cells = <0>;
660
661 reg = <0xffc01000 0x1000>,
662 - <0xffc02000 0x1000>,
663 + <0xffc02000 0x2000>,
664 <0xffc04000 0x2000>,
665 <0xffc06000 0x2000>;
666 interrupts = <GIC_PPI 9 0xf04>;
667 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
668 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
669 @@ -791,7 +791,7 @@
670 gic: interrupt-controller@01c81000 {
671 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
672 reg = <0x01c81000 0x1000>,
673 - <0x01c82000 0x1000>,
674 + <0x01c82000 0x2000>,
675 <0x01c84000 0x2000>,
676 <0x01c86000 0x2000>;
677 interrupt-controller;
678 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
679 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
680 @@ -1685,9 +1685,9 @@
681 };
682
683 gic: interrupt-controller@01c81000 {
684 - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
685 + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
686 reg = <0x01c81000 0x1000>,
687 - <0x01c82000 0x1000>,
688 + <0x01c82000 0x2000>,
689 <0x01c84000 0x2000>,
690 <0x01c86000 0x2000>;
691 interrupt-controller;
692 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
693 +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
694 @@ -488,7 +488,7 @@
695 gic: interrupt-controller@01c81000 {
696 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
697 reg = <0x01c81000 0x1000>,
698 - <0x01c82000 0x1000>,
699 + <0x01c82000 0x2000>,
700 <0x01c84000 0x2000>,
701 <0x01c86000 0x2000>;
702 interrupt-controller;
703 --- a/arch/arm/boot/dts/sun9i-a80.dtsi
704 +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
705 @@ -613,7 +613,7 @@
706 gic: interrupt-controller@01c41000 {
707 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
708 reg = <0x01c41000 0x1000>,
709 - <0x01c42000 0x1000>,
710 + <0x01c42000 0x2000>,
711 <0x01c44000 0x2000>,
712 <0x01c46000 0x2000>;
713 interrupt-controller;
714 --- a/arch/arm64/boot/dts/freescale/Makefile
715 +++ b/arch/arm64/boot/dts/freescale/Makefile
716 @@ -1,8 +1,24 @@
717 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
718 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
719 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
720 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
721 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
722 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
723 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
724 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
725 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
726 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
727 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
728 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
729 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
730 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
731 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
732 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
733 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
734 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
735 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
736 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
737 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
738
739 always := $(dtb-y)
740 subdir-y := $(dts-dirs)
741 --- /dev/null
742 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
743 @@ -0,0 +1,177 @@
744 +/*
745 + * Device Tree file for Freescale LS1012A Freedom Board.
746 + *
747 + * Copyright 2016 Freescale Semiconductor, Inc.
748 + *
749 + * This file is dual-licensed: you can use it either under the terms
750 + * of the GPLv2 or the X11 license, at your option. Note that this dual
751 + * licensing only applies to this file, and not this project as a
752 + * whole.
753 + *
754 + * a) This library is free software; you can redistribute it and/or
755 + * modify it under the terms of the GNU General Public License as
756 + * published by the Free Software Foundation; either version 2 of the
757 + * License, or (at your option) any later version.
758 + *
759 + * This library is distributed in the hope that it will be useful,
760 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
761 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
762 + * GNU General Public License for more details.
763 + *
764 + * Or, alternatively,
765 + *
766 + * b) Permission is hereby granted, free of charge, to any person
767 + * obtaining a copy of this software and associated documentation
768 + * files (the "Software"), to deal in the Software without
769 + * restriction, including without limitation the rights to use,
770 + * copy, modify, merge, publish, distribute, sublicense, and/or
771 + * sell copies of the Software, and to permit persons to whom the
772 + * Software is furnished to do so, subject to the following
773 + * conditions:
774 + *
775 + * The above copyright notice and this permission notice shall be
776 + * included in all copies or substantial portions of the Software.
777 + *
778 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
779 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
780 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
781 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
782 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
783 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
784 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
785 + * OTHER DEALINGS IN THE SOFTWARE.
786 + */
787 +/dts-v1/;
788 +
789 +#include "fsl-ls1012a.dtsi"
790 +
791 +/ {
792 + model = "LS1012A Freedom Board";
793 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
794 +
795 + aliases {
796 + ethernet0 = &pfe_mac0;
797 + ethernet1 = &pfe_mac1;
798 + };
799 +
800 + sys_mclk: clock-mclk {
801 + compatible = "fixed-clock";
802 + #clock-cells = <0>;
803 + clock-frequency = <25000000>;
804 + };
805 +
806 + reg_1p8v: regulator-1p8v {
807 + compatible = "regulator-fixed";
808 + regulator-name = "1P8V";
809 + regulator-min-microvolt = <1800000>;
810 + regulator-max-microvolt = <1800000>;
811 + regulator-always-on;
812 + };
813 +
814 + sound {
815 + compatible = "simple-audio-card";
816 + simple-audio-card,format = "i2s";
817 + simple-audio-card,widgets =
818 + "Microphone", "Microphone Jack",
819 + "Headphone", "Headphone Jack",
820 + "Speaker", "Speaker Ext",
821 + "Line", "Line In Jack";
822 + simple-audio-card,routing =
823 + "MIC_IN", "Microphone Jack",
824 + "Microphone Jack", "Mic Bias",
825 + "LINE_IN", "Line In Jack",
826 + "Headphone Jack", "HP_OUT",
827 + "Speaker Ext", "LINE_OUT";
828 +
829 + simple-audio-card,cpu {
830 + sound-dai = <&sai2>;
831 + frame-master;
832 + bitclock-master;
833 + };
834 +
835 + simple-audio-card,codec {
836 + sound-dai = <&codec>;
837 + frame-master;
838 + bitclock-master;
839 + system-clock-frequency = <25000000>;
840 + };
841 + };
842 +};
843 +
844 +&duart0 {
845 + status = "okay";
846 +};
847 +
848 +&i2c0 {
849 + status = "okay";
850 +
851 + codec: sgtl5000@a {
852 + #sound-dai-cells = <0>;
853 + compatible = "fsl,sgtl5000";
854 + reg = <0xa>;
855 + VDDA-supply = <&reg_1p8v>;
856 + VDDIO-supply = <&reg_1p8v>;
857 + clocks = <&sys_mclk>;
858 + };
859 +};
860 +
861 +&qspi {
862 + num-cs = <1>;
863 + bus-num = <0>;
864 + status = "okay";
865 +
866 + qflash0: s25fs512s@0 {
867 + compatible = "spansion,m25p80";
868 + #address-cells = <1>;
869 + #size-cells = <1>;
870 + m25p,fast-read;
871 + spi-max-frequency = <20000000>;
872 + reg = <0>;
873 + };
874 +};
875 +
876 +&pfe {
877 + status = "okay";
878 + #address-cells = <1>;
879 + #size-cells = <0>;
880 +
881 + ethernet@0 {
882 + compatible = "fsl,pfe-gemac-port";
883 + #address-cells = <1>;
884 + #size-cells = <0>;
885 + reg = <0x0>; /* GEM_ID */
886 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
887 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
888 + fsl,mdio-mux-val = <0x0>;
889 + phy-mode = "sgmii";
890 + fsl,pfe-phy-if-flags = <0x0>;
891 +
892 + mdio@0 {
893 + reg = <0x1>; /* enabled/disabled */
894 + };
895 + };
896 +
897 + ethernet@1 {
898 + compatible = "fsl,pfe-gemac-port";
899 + #address-cells = <1>;
900 + #size-cells = <0>;
901 + reg = <0x1>; /* GEM_ID */
902 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
903 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
904 + fsl,mdio-mux-val = <0x0>;
905 + phy-mode = "sgmii";
906 + fsl,pfe-phy-if-flags = <0x0>;
907 +
908 + mdio@0 {
909 + reg = <0x0>; /* enabled/disabled */
910 + };
911 + };
912 +};
913 +
914 +&sai2 {
915 + status = "okay";
916 +};
917 +
918 +&sata {
919 + status = "okay";
920 +};
921 --- /dev/null
922 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
923 @@ -0,0 +1,198 @@
924 +/*
925 + * Device Tree file for Freescale LS1012A QDS Board.
926 + *
927 + * Copyright 2016 Freescale Semiconductor, Inc.
928 + *
929 + * This file is dual-licensed: you can use it either under the terms
930 + * of the GPLv2 or the X11 license, at your option. Note that this dual
931 + * licensing only applies to this file, and not this project as a
932 + * whole.
933 + *
934 + * a) This library is free software; you can redistribute it and/or
935 + * modify it under the terms of the GNU General Public License as
936 + * published by the Free Software Foundation; either version 2 of the
937 + * License, or (at your option) any later version.
938 + *
939 + * This library is distributed in the hope that it will be useful,
940 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
941 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
942 + * GNU General Public License for more details.
943 + *
944 + * Or, alternatively,
945 + *
946 + * b) Permission is hereby granted, free of charge, to any person
947 + * obtaining a copy of this software and associated documentation
948 + * files (the "Software"), to deal in the Software without
949 + * restriction, including without limitation the rights to use,
950 + * copy, modify, merge, publish, distribute, sublicense, and/or
951 + * sell copies of the Software, and to permit persons to whom the
952 + * Software is furnished to do so, subject to the following
953 + * conditions:
954 + *
955 + * The above copyright notice and this permission notice shall be
956 + * included in all copies or substantial portions of the Software.
957 + *
958 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
959 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
960 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
961 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
962 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
963 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
964 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
965 + * OTHER DEALINGS IN THE SOFTWARE.
966 + */
967 +/dts-v1/;
968 +
969 +#include "fsl-ls1012a.dtsi"
970 +
971 +/ {
972 + model = "LS1012A QDS Board";
973 + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
974 +
975 + aliases {
976 + ethernet0 = &pfe_mac0;
977 + ethernet1 = &pfe_mac1;
978 + };
979 +
980 + sys_mclk: clock-mclk {
981 + compatible = "fixed-clock";
982 + #clock-cells = <0>;
983 + clock-frequency = <24576000>;
984 + };
985 +
986 + reg_3p3v: regulator-3p3v {
987 + compatible = "regulator-fixed";
988 + regulator-name = "3P3V";
989 + regulator-min-microvolt = <3300000>;
990 + regulator-max-microvolt = <3300000>;
991 + regulator-always-on;
992 + };
993 +
994 + sound {
995 + compatible = "simple-audio-card";
996 + simple-audio-card,format = "i2s";
997 + simple-audio-card,widgets =
998 + "Microphone", "Microphone Jack",
999 + "Headphone", "Headphone Jack",
1000 + "Speaker", "Speaker Ext",
1001 + "Line", "Line In Jack";
1002 + simple-audio-card,routing =
1003 + "MIC_IN", "Microphone Jack",
1004 + "Microphone Jack", "Mic Bias",
1005 + "LINE_IN", "Line In Jack",
1006 + "Headphone Jack", "HP_OUT",
1007 + "Speaker Ext", "LINE_OUT";
1008 +
1009 + simple-audio-card,cpu {
1010 + sound-dai = <&sai2>;
1011 + frame-master;
1012 + bitclock-master;
1013 + };
1014 +
1015 + simple-audio-card,codec {
1016 + sound-dai = <&codec>;
1017 + frame-master;
1018 + bitclock-master;
1019 + system-clock-frequency = <24576000>;
1020 + };
1021 + };
1022 +};
1023 +
1024 +&duart0 {
1025 + status = "okay";
1026 +};
1027 +
1028 +&i2c0 {
1029 + status = "okay";
1030 +
1031 + pca9547@77 {
1032 + compatible = "nxp,pca9547";
1033 + reg = <0x77>;
1034 + #address-cells = <1>;
1035 + #size-cells = <0>;
1036 +
1037 + i2c@4 {
1038 + #address-cells = <1>;
1039 + #size-cells = <0>;
1040 + reg = <0x4>;
1041 +
1042 + codec: sgtl5000@a {
1043 + #sound-dai-cells = <0>;
1044 + compatible = "fsl,sgtl5000";
1045 + reg = <0xa>;
1046 + VDDA-supply = <&reg_3p3v>;
1047 + VDDIO-supply = <&reg_3p3v>;
1048 + clocks = <&sys_mclk>;
1049 + };
1050 + };
1051 + };
1052 +};
1053 +
1054 +&qspi {
1055 + num-cs = <2>;
1056 + bus-num = <0>;
1057 + status = "okay";
1058 +
1059 + qflash0: s25fs512s@0 {
1060 + compatible = "spansion,m25p80";
1061 + #address-cells = <1>;
1062 + #size-cells = <1>;
1063 + spi-max-frequency = <20000000>;
1064 + m25p,fast-read;
1065 + reg = <0>;
1066 + };
1067 +};
1068 +
1069 +&pfe {
1070 + status = "okay";
1071 + #address-cells = <1>;
1072 + #size-cells = <0>;
1073 +
1074 + ethernet@0 {
1075 + compatible = "fsl,pfe-gemac-port";
1076 + #address-cells = <1>;
1077 + #size-cells = <0>;
1078 + reg = <0x0>; /* GEM_ID */
1079 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1080 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1081 + fsl,mdio-mux-val = <0x2>;
1082 + phy-mode = "sgmii-2500";
1083 + fsl,pfe-phy-if-flags = <0x0>;
1084 +
1085 + mdio@0 {
1086 + reg = <0x1>; /* enabled/disabled */
1087 + };
1088 + };
1089 +
1090 + ethernet@1 {
1091 + compatible = "fsl,pfe-gemac-port";
1092 + #address-cells = <1>;
1093 + #size-cells = <0>;
1094 + reg = <0x1>; /* GEM_ID */
1095 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1096 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1097 + fsl,mdio-mux-val = <0x3>;
1098 + phy-mode = "sgmii-2500";
1099 + fsl,pfe-phy-if-flags = <0x0>;
1100 +
1101 + mdio@0 {
1102 + reg = <0x0>; /* enabled/disabled */
1103 + };
1104 + };
1105 +};
1106 +
1107 +&sai2 {
1108 + status = "okay";
1109 +};
1110 +
1111 +&sata {
1112 + status = "okay";
1113 +};
1114 +
1115 +&esdhc0 {
1116 + status = "okay";
1117 +};
1118 +
1119 +&esdhc1 {
1120 + status = "okay";
1121 +};
1122 --- /dev/null
1123 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1124 @@ -0,0 +1,134 @@
1125 +/*
1126 + * Device Tree file for Freescale LS1012A RDB Board.
1127 + *
1128 + * Copyright 2016 Freescale Semiconductor, Inc.
1129 + *
1130 + * This file is dual-licensed: you can use it either under the terms
1131 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1132 + * licensing only applies to this file, and not this project as a
1133 + * whole.
1134 + *
1135 + * a) This library is free software; you can redistribute it and/or
1136 + * modify it under the terms of the GNU General Public License as
1137 + * published by the Free Software Foundation; either version 2 of the
1138 + * License, or (at your option) any later version.
1139 + *
1140 + * This library is distributed in the hope that it will be useful,
1141 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1142 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1143 + * GNU General Public License for more details.
1144 + *
1145 + * Or, alternatively,
1146 + *
1147 + * b) Permission is hereby granted, free of charge, to any person
1148 + * obtaining a copy of this software and associated documentation
1149 + * files (the "Software"), to deal in the Software without
1150 + * restriction, including without limitation the rights to use,
1151 + * copy, modify, merge, publish, distribute, sublicense, and/or
1152 + * sell copies of the Software, and to permit persons to whom the
1153 + * Software is furnished to do so, subject to the following
1154 + * conditions:
1155 + *
1156 + * The above copyright notice and this permission notice shall be
1157 + * included in all copies or substantial portions of the Software.
1158 + *
1159 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1160 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1161 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1162 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1163 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1164 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1165 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1166 + * OTHER DEALINGS IN THE SOFTWARE.
1167 + */
1168 +/dts-v1/;
1169 +
1170 +#include "fsl-ls1012a.dtsi"
1171 +
1172 +/ {
1173 + model = "LS1012A RDB Board";
1174 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1175 +
1176 + aliases {
1177 + ethernet0 = &pfe_mac0;
1178 + ethernet1 = &pfe_mac1;
1179 + };
1180 +};
1181 +
1182 +&duart0 {
1183 + status = "okay";
1184 +};
1185 +
1186 +&i2c0 {
1187 + status = "okay";
1188 +};
1189 +
1190 +&qspi {
1191 + num-cs = <2>;
1192 + bus-num = <0>;
1193 + status = "okay";
1194 +
1195 + qflash0: s25fs512s@0 {
1196 + compatible = "spansion,m25p80";
1197 + #address-cells = <1>;
1198 + #size-cells = <1>;
1199 + spi-max-frequency = <20000000>;
1200 + m25p,fast-read;
1201 + reg = <0>;
1202 + };
1203 +};
1204 +
1205 +&sata {
1206 + status = "okay";
1207 +};
1208 +
1209 +&esdhc0 {
1210 + sd-uhs-sdr104;
1211 + sd-uhs-sdr50;
1212 + sd-uhs-sdr25;
1213 + sd-uhs-sdr12;
1214 + status = "okay";
1215 +};
1216 +
1217 +&esdhc1 {
1218 + mmc-hs200-1_8v;
1219 + status = "okay";
1220 +};
1221 +
1222 +&pfe {
1223 + status = "okay";
1224 + #address-cells = <1>;
1225 + #size-cells = <0>;
1226 +
1227 + ethernet@0 {
1228 + compatible = "fsl,pfe-gemac-port";
1229 + #address-cells = <1>;
1230 + #size-cells = <0>;
1231 + reg = <0x0>; /* GEM_ID */
1232 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1233 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1234 + fsl,mdio-mux-val = <0x0>;
1235 + phy-mode = "sgmii";
1236 + fsl,pfe-phy-if-flags = <0x0>;
1237 +
1238 + mdio@0 {
1239 + reg = <0x1>; /* enabled/disabled */
1240 + };
1241 + };
1242 +
1243 + ethernet@1 {
1244 + compatible = "fsl,pfe-gemac-port";
1245 + #address-cells = <1>;
1246 + #size-cells = <0>;
1247 + reg = <0x1>; /* GEM_ID */
1248 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
1249 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
1250 + fsl,mdio-mux-val = <0x0>;
1251 + phy-mode = "rgmii-txid";
1252 + fsl,pfe-phy-if-flags = <0x0>;
1253 +
1254 + mdio@0 {
1255 + reg = <0x0>; /* enabled/disabled */
1256 + };
1257 + };
1258 +};
1259 --- /dev/null
1260 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1261 @@ -0,0 +1,594 @@
1262 +/*
1263 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
1264 + *
1265 + * Copyright 2016 Freescale Semiconductor, Inc.
1266 + *
1267 + * This file is dual-licensed: you can use it either under the terms
1268 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1269 + * licensing only applies to this file, and not this project as a
1270 + * whole.
1271 + *
1272 + * a) This library is free software; you can redistribute it and/or
1273 + * modify it under the terms of the GNU General Public License as
1274 + * published by the Free Software Foundation; either version 2 of the
1275 + * License, or (at your option) any later version.
1276 + *
1277 + * This library is distributed in the hope that it will be useful,
1278 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1279 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1280 + * GNU General Public License for more details.
1281 + *
1282 + * Or, alternatively,
1283 + *
1284 + * b) Permission is hereby granted, free of charge, to any person
1285 + * obtaining a copy of this software and associated documentation
1286 + * files (the "Software"), to deal in the Software without
1287 + * restriction, including without limitation the rights to use,
1288 + * copy, modify, merge, publish, distribute, sublicense, and/or
1289 + * sell copies of the Software, and to permit persons to whom the
1290 + * Software is furnished to do so, subject to the following
1291 + * conditions:
1292 + *
1293 + * The above copyright notice and this permission notice shall be
1294 + * included in all copies or substantial portions of the Software.
1295 + *
1296 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1297 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1298 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1299 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1300 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1301 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1302 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1303 + * OTHER DEALINGS IN THE SOFTWARE.
1304 + */
1305 +
1306 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1307 +#include <dt-bindings/thermal/thermal.h>
1308 +
1309 +/ {
1310 + compatible = "fsl,ls1012a";
1311 + interrupt-parent = <&gic>;
1312 + #address-cells = <2>;
1313 + #size-cells = <2>;
1314 +
1315 + aliases {
1316 + crypto = &crypto;
1317 + rtic_a = &rtic_a;
1318 + rtic_b = &rtic_b;
1319 + rtic_c = &rtic_c;
1320 + rtic_d = &rtic_d;
1321 + sec_mon = &sec_mon;
1322 + };
1323 +
1324 + cpus {
1325 + #address-cells = <1>;
1326 + #size-cells = <0>;
1327 +
1328 + cpu0: cpu@0 {
1329 + device_type = "cpu";
1330 + compatible = "arm,cortex-a53";
1331 + reg = <0x0>;
1332 + clocks = <&clockgen 1 0>;
1333 + #cooling-cells = <2>;
1334 + cpu-idle-states = <&CPU_PH20>;
1335 + };
1336 + };
1337 +
1338 + idle-states {
1339 + /*
1340 + * PSCI node is not added default, U-boot will add missing
1341 + * parts if it determines to use PSCI.
1342 + */
1343 + entry-method = "arm,psci";
1344 +
1345 + CPU_PH20: cpu-ph20 {
1346 + compatible = "arm,idle-state";
1347 + idle-state-name = "PH20";
1348 + arm,psci-suspend-param = <0x0>;
1349 + entry-latency-us = <1000>;
1350 + exit-latency-us = <1000>;
1351 + min-residency-us = <3000>;
1352 + };
1353 + };
1354 +
1355 + sysclk: sysclk {
1356 + compatible = "fixed-clock";
1357 + #clock-cells = <0>;
1358 + clock-frequency = <125000000>;
1359 + clock-output-names = "sysclk";
1360 + };
1361 +
1362 + coreclk: coreclk {
1363 + compatible = "fixed-clock";
1364 + #clock-cells = <0>;
1365 + clock-frequency = <100000000>;
1366 + clock-output-names = "coreclk";
1367 + };
1368 +
1369 + timer {
1370 + compatible = "arm,armv8-timer";
1371 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
1372 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
1373 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
1374 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
1375 + };
1376 +
1377 + pmu {
1378 + compatible = "arm,armv8-pmuv3";
1379 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1380 + };
1381 +
1382 + gic: interrupt-controller@1400000 {
1383 + compatible = "arm,gic-400";
1384 + #interrupt-cells = <3>;
1385 + interrupt-controller;
1386 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
1387 + <0x0 0x1402000 0 0x2000>, /* GICC */
1388 + <0x0 0x1404000 0 0x2000>, /* GICH */
1389 + <0x0 0x1406000 0 0x2000>; /* GICV */
1390 + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
1391 + };
1392 +
1393 + reboot {
1394 + compatible = "syscon-reboot";
1395 + regmap = <&dcfg>;
1396 + offset = <0xb0>;
1397 + mask = <0x02>;
1398 + };
1399 +
1400 + soc {
1401 + compatible = "simple-bus";
1402 + #address-cells = <2>;
1403 + #size-cells = <2>;
1404 + ranges;
1405 +
1406 + scfg: scfg@1570000 {
1407 + compatible = "fsl,ls1012a-scfg", "syscon";
1408 + reg = <0x0 0x1570000 0x0 0x10000>;
1409 + big-endian;
1410 + };
1411 +
1412 + crypto: crypto@1700000 {
1413 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
1414 + "fsl,sec-v4.0";
1415 + fsl,sec-era = <8>;
1416 + #address-cells = <1>;
1417 + #size-cells = <1>;
1418 + ranges = <0x0 0x00 0x1700000 0x100000>;
1419 + reg = <0x00 0x1700000 0x0 0x100000>;
1420 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1421 +
1422 + sec_jr0: jr@10000 {
1423 + compatible = "fsl,sec-v5.4-job-ring",
1424 + "fsl,sec-v5.0-job-ring",
1425 + "fsl,sec-v4.0-job-ring";
1426 + reg = <0x10000 0x10000>;
1427 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1428 + };
1429 +
1430 + sec_jr1: jr@20000 {
1431 + compatible = "fsl,sec-v5.4-job-ring",
1432 + "fsl,sec-v5.0-job-ring",
1433 + "fsl,sec-v4.0-job-ring";
1434 + reg = <0x20000 0x10000>;
1435 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1436 + };
1437 +
1438 + sec_jr2: jr@30000 {
1439 + compatible = "fsl,sec-v5.4-job-ring",
1440 + "fsl,sec-v5.0-job-ring",
1441 + "fsl,sec-v4.0-job-ring";
1442 + reg = <0x30000 0x10000>;
1443 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1444 + };
1445 +
1446 + sec_jr3: jr@40000 {
1447 + compatible = "fsl,sec-v5.4-job-ring",
1448 + "fsl,sec-v5.0-job-ring",
1449 + "fsl,sec-v4.0-job-ring";
1450 + reg = <0x40000 0x10000>;
1451 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1452 + };
1453 +
1454 + caam-dma {
1455 + compatible = "fsl,sec-v5.4-dma",
1456 + "fsl,sec-v5.0-dma",
1457 + "fsl,sec-v4.0-dma";
1458 + };
1459 +
1460 + rtic@60000 {
1461 + compatible = "fsl,sec-v5.4-rtic",
1462 + "fsl,sec-v5.0-rtic",
1463 + "fsl,sec-v4.0-rtic";
1464 + #address-cells = <1>;
1465 + #size-cells = <1>;
1466 + reg = <0x60000 0x100 0x60e00 0x18>;
1467 + ranges = <0x0 0x60100 0x500>;
1468 +
1469 + rtic_a: rtic-a@0 {
1470 + compatible = "fsl,sec-v5.4-rtic-memory",
1471 + "fsl,sec-v5.0-rtic-memory",
1472 + "fsl,sec-v4.0-rtic-memory";
1473 + reg = <0x00 0x20 0x100 0x100>;
1474 + };
1475 +
1476 + rtic_b: rtic-b@20 {
1477 + compatible = "fsl,sec-v5.4-rtic-memory",
1478 + "fsl,sec-v5.0-rtic-memory",
1479 + "fsl,sec-v4.0-rtic-memory";
1480 + reg = <0x20 0x20 0x200 0x100>;
1481 + };
1482 +
1483 + rtic_c: rtic-c@40 {
1484 + compatible = "fsl,sec-v5.4-rtic-memory",
1485 + "fsl,sec-v5.0-rtic-memory",
1486 + "fsl,sec-v4.0-rtic-memory";
1487 + reg = <0x40 0x20 0x300 0x100>;
1488 + };
1489 +
1490 + rtic_d: rtic-d@60 {
1491 + compatible = "fsl,sec-v5.4-rtic-memory",
1492 + "fsl,sec-v5.0-rtic-memory",
1493 + "fsl,sec-v4.0-rtic-memory";
1494 + reg = <0x60 0x20 0x400 0x100>;
1495 + };
1496 + };
1497 + };
1498 +
1499 + sec_mon: sec_mon@1e90000 {
1500 + compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
1501 + "fsl,sec-v4.0-mon";
1502 + reg = <0x0 0x1e90000 0x0 0x10000>;
1503 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
1504 + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1505 + };
1506 +
1507 + dcfg: dcfg@1ee0000 {
1508 + compatible = "fsl,ls1012a-dcfg",
1509 + "syscon";
1510 + reg = <0x0 0x1ee0000 0x0 0x10000>;
1511 + big-endian;
1512 + };
1513 +
1514 + clockgen: clocking@1ee1000 {
1515 + compatible = "fsl,ls1012a-clockgen";
1516 + reg = <0x0 0x1ee1000 0x0 0x1000>;
1517 + #clock-cells = <2>;
1518 + clocks = <&sysclk &coreclk>;
1519 + clock-names = "sysclk", "coreclk";
1520 + };
1521 +
1522 + tmu: tmu@1f00000 {
1523 + compatible = "fsl,qoriq-tmu";
1524 + reg = <0x0 0x1f00000 0x0 0x10000>;
1525 + interrupts = <0 33 0x4>;
1526 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
1527 + fsl,tmu-calibration = <0x00000000 0x00000026
1528 + 0x00000001 0x0000002d
1529 + 0x00000002 0x00000032
1530 + 0x00000003 0x00000039
1531 + 0x00000004 0x0000003f
1532 + 0x00000005 0x00000046
1533 + 0x00000006 0x0000004d
1534 + 0x00000007 0x00000054
1535 + 0x00000008 0x0000005a
1536 + 0x00000009 0x00000061
1537 + 0x0000000a 0x0000006a
1538 + 0x0000000b 0x00000071
1539 +
1540 + 0x00010000 0x00000025
1541 + 0x00010001 0x0000002c
1542 + 0x00010002 0x00000035
1543 + 0x00010003 0x0000003d
1544 + 0x00010004 0x00000045
1545 + 0x00010005 0x0000004e
1546 + 0x00010006 0x00000057
1547 + 0x00010007 0x00000061
1548 + 0x00010008 0x0000006b
1549 + 0x00010009 0x00000076
1550 +
1551 + 0x00020000 0x00000029
1552 + 0x00020001 0x00000033
1553 + 0x00020002 0x0000003d
1554 + 0x00020003 0x00000049
1555 + 0x00020004 0x00000056
1556 + 0x00020005 0x00000061
1557 + 0x00020006 0x0000006d
1558 +
1559 + 0x00030000 0x00000021
1560 + 0x00030001 0x0000002a
1561 + 0x00030002 0x0000003c
1562 + 0x00030003 0x0000004e>;
1563 + big-endian;
1564 + #thermal-sensor-cells = <1>;
1565 + };
1566 +
1567 + thermal-zones {
1568 + cpu_thermal: cpu-thermal {
1569 + polling-delay-passive = <1000>;
1570 + polling-delay = <5000>;
1571 + thermal-sensors = <&tmu 0>;
1572 +
1573 + trips {
1574 + cpu_alert: cpu-alert {
1575 + temperature = <85000>;
1576 + hysteresis = <2000>;
1577 + type = "passive";
1578 + };
1579 +
1580 + cpu_crit: cpu-crit {
1581 + temperature = <95000>;
1582 + hysteresis = <2000>;
1583 + type = "critical";
1584 + };
1585 + };
1586 +
1587 + cooling-maps {
1588 + map0 {
1589 + trip = <&cpu_alert>;
1590 + cooling-device =
1591 + <&cpu0 THERMAL_NO_LIMIT
1592 + THERMAL_NO_LIMIT>;
1593 + };
1594 + };
1595 + };
1596 + };
1597 +
1598 + esdhc0: esdhc@1560000 {
1599 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1600 + reg = <0x0 0x1560000 0x0 0x10000>;
1601 + interrupts = <0 62 0x4>;
1602 + clocks = <&clockgen 4 0>;
1603 + voltage-ranges = <1800 1800 3300 3300>;
1604 + sdhci,auto-cmd12;
1605 + big-endian;
1606 + bus-width = <4>;
1607 + status = "disabled";
1608 + };
1609 +
1610 + esdhc1: esdhc@1580000 {
1611 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1612 + reg = <0x0 0x1580000 0x0 0x10000>;
1613 + interrupts = <0 65 0x4>;
1614 + clocks = <&clockgen 4 0>;
1615 + voltage-ranges = <1800 1800 3300 3300>;
1616 + sdhci,auto-cmd12;
1617 + big-endian;
1618 + broken-cd;
1619 + bus-width = <4>;
1620 + status = "disabled";
1621 + };
1622 +
1623 + rcpm: rcpm@1ee2000 {
1624 + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
1625 + reg = <0x0 0x1ee2000 0x0 0x1000>;
1626 + fsl,#rcpm-wakeup-cells = <1>;
1627 + };
1628 +
1629 + ftm0: ftm0@29d0000 {
1630 + compatible = "fsl,ls1012a-ftm";
1631 + reg = <0x0 0x29d0000 0x0 0x10000>,
1632 + <0x0 0x1ee2140 0x0 0x4>;
1633 + reg-names = "ftm", "FlexTimer1";
1634 + interrupts = <0 86 0x4>;
1635 + big-endian;
1636 + };
1637 +
1638 + i2c0: i2c@2180000 {
1639 + compatible = "fsl,vf610-i2c";
1640 + #address-cells = <1>;
1641 + #size-cells = <0>;
1642 + reg = <0x0 0x2180000 0x0 0x10000>;
1643 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
1644 + clocks = <&clockgen 4 0>;
1645 + status = "disabled";
1646 + };
1647 +
1648 + i2c1: i2c@2190000 {
1649 + compatible = "fsl,vf610-i2c";
1650 + #address-cells = <1>;
1651 + #size-cells = <0>;
1652 + reg = <0x0 0x2190000 0x0 0x10000>;
1653 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
1654 + clocks = <&clockgen 4 0>;
1655 + status = "disabled";
1656 + };
1657 +
1658 + duart0: serial@21c0500 {
1659 + compatible = "fsl,ns16550", "ns16550a";
1660 + reg = <0x00 0x21c0500 0x0 0x100>;
1661 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1662 + clocks = <&clockgen 4 0>;
1663 + status = "disabled";
1664 + };
1665 +
1666 + duart1: serial@21c0600 {
1667 + compatible = "fsl,ns16550", "ns16550a";
1668 + reg = <0x00 0x21c0600 0x0 0x100>;
1669 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1670 + clocks = <&clockgen 4 0>;
1671 + status = "disabled";
1672 + };
1673 +
1674 + gpio0: gpio@2300000 {
1675 + compatible = "fsl,qoriq-gpio";
1676 + reg = <0x0 0x2300000 0x0 0x10000>;
1677 + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
1678 + gpio-controller;
1679 + #gpio-cells = <2>;
1680 + interrupt-controller;
1681 + #interrupt-cells = <2>;
1682 + };
1683 +
1684 + gpio1: gpio@2310000 {
1685 + compatible = "fsl,qoriq-gpio";
1686 + reg = <0x0 0x2310000 0x0 0x10000>;
1687 + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
1688 + gpio-controller;
1689 + #gpio-cells = <2>;
1690 + interrupt-controller;
1691 + #interrupt-cells = <2>;
1692 + };
1693 +
1694 + qspi: quadspi@1550000 {
1695 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
1696 + #address-cells = <1>;
1697 + #size-cells = <0>;
1698 + reg = <0x0 0x1550000 0x0 0x10000>,
1699 + <0x0 0x40000000 0x0 0x10000000>;
1700 + reg-names = "QuadSPI", "QuadSPI-memory";
1701 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1702 + clock-names = "qspi_en", "qspi";
1703 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
1704 + big-endian;
1705 + fsl,qspi-has-second-chip;
1706 + status = "disabled";
1707 + };
1708 +
1709 + wdog0: wdog@2ad0000 {
1710 + compatible = "fsl,ls1012a-wdt",
1711 + "fsl,imx21-wdt";
1712 + reg = <0x0 0x2ad0000 0x0 0x10000>;
1713 + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
1714 + clocks = <&clockgen 4 0>;
1715 + big-endian;
1716 + };
1717 +
1718 + sai1: sai@2b50000 {
1719 + #sound-dai-cells = <0>;
1720 + compatible = "fsl,vf610-sai";
1721 + reg = <0x0 0x2b50000 0x0 0x10000>;
1722 + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
1723 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1724 + <&clockgen 4 3>, <&clockgen 4 3>;
1725 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1726 + dma-names = "tx", "rx";
1727 + dmas = <&edma0 1 47>,
1728 + <&edma0 1 46>;
1729 + status = "disabled";
1730 + };
1731 +
1732 + sai2: sai@2b60000 {
1733 + #sound-dai-cells = <0>;
1734 + compatible = "fsl,vf610-sai";
1735 + reg = <0x0 0x2b60000 0x0 0x10000>;
1736 + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
1737 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1738 + <&clockgen 4 3>, <&clockgen 4 3>;
1739 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1740 + dma-names = "tx", "rx";
1741 + dmas = <&edma0 1 45>,
1742 + <&edma0 1 44>;
1743 + status = "disabled";
1744 + };
1745 +
1746 + edma0: edma@2c00000 {
1747 + #dma-cells = <2>;
1748 + compatible = "fsl,vf610-edma";
1749 + reg = <0x0 0x2c00000 0x0 0x10000>,
1750 + <0x0 0x2c10000 0x0 0x10000>,
1751 + <0x0 0x2c20000 0x0 0x10000>;
1752 + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
1753 + <0 103 IRQ_TYPE_LEVEL_HIGH>;
1754 + interrupt-names = "edma-tx", "edma-err";
1755 + dma-channels = <32>;
1756 + big-endian;
1757 + clock-names = "dmamux0", "dmamux1";
1758 + clocks = <&clockgen 4 3>,
1759 + <&clockgen 4 3>;
1760 + };
1761 +
1762 + usb0: usb3@2f00000 {
1763 + compatible = "snps,dwc3";
1764 + reg = <0x0 0x2f00000 0x0 0x10000>;
1765 + interrupts = <0 60 0x4>;
1766 + dr_mode = "host";
1767 + snps,quirk-frame-length-adjustment = <0x20>;
1768 + snps,dis_rxdet_inp3_quirk;
1769 + };
1770 +
1771 + usb1: usb2@8600000 {
1772 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
1773 + reg = <0x0 0x8600000 0x0 0x1000>;
1774 + interrupts = <0 139 0x4>;
1775 + dr_mode = "host";
1776 + phy_type = "ulpi";
1777 + };
1778 +
1779 + sata: sata@3200000 {
1780 + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
1781 + reg = <0x0 0x3200000 0x0 0x10000>,
1782 + <0x0 0x20140520 0x0 0x4>;
1783 + reg-names = "ahci", "sata-ecc";
1784 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
1785 + clocks = <&clockgen 4 0>;
1786 + dma-coherent;
1787 + status = "disabled";
1788 + };
1789 +
1790 + msi: msi-controller1@1572000 {
1791 + compatible = "fsl,ls1012a-msi";
1792 + reg = <0x0 0x1572000 0x0 0x8>;
1793 + msi-controller;
1794 + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
1795 + };
1796 +
1797 + pcie@3400000 {
1798 + compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
1799 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
1800 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
1801 + reg-names = "regs", "config";
1802 + interrupts = <0 118 0x4>, /* AER interrupt */
1803 + <0 117 0x4>; /* PME interrupt */
1804 + interrupt-names = "aer", "pme";
1805 + #address-cells = <3>;
1806 + #size-cells = <2>;
1807 + device_type = "pci";
1808 + num-lanes = <4>;
1809 + bus-range = <0x0 0xff>;
1810 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
1811 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1812 + msi-parent = <&msi>;
1813 + #interrupt-cells = <1>;
1814 + interrupt-map-mask = <0 0 0 7>;
1815 + interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
1816 + <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
1817 + <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
1818 + <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1819 + };
1820 + };
1821 +
1822 + reserved-memory {
1823 + #address-cells = <2>;
1824 + #size-cells = <2>;
1825 + ranges;
1826 +
1827 + pfe_reserved: packetbuffer@83400000 {
1828 + reg = <0 0x83400000 0 0xc00000>;
1829 + };
1830 + };
1831 +
1832 + pfe: pfe@04000000 {
1833 + compatible = "fsl,pfe";
1834 + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
1835 + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
1836 + reg-names = "pfe", "pfe-ddr";
1837 + fsl,pfe-num-interfaces = <0x2>;
1838 + interrupts = <0 172 0x4>, /* HIF interrupt */
1839 + <0 173 0x4>, /*HIF_NOCPY interrupt */
1840 + <0 174 0x4>; /* WoL interrupt */
1841 + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
1842 + memory-region = <&pfe_reserved>;
1843 + fsl,pfe-scfg = <&scfg 0>;
1844 + fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
1845 + clocks = <&clockgen 4 0>;
1846 + clock-names = "pfe";
1847 +
1848 + status = "okay";
1849 + pfe_mac0: ethernet@0 {
1850 + };
1851 +
1852 + pfe_mac1: ethernet@1 {
1853 + };
1854 + };
1855 +};
1856 --- /dev/null
1857 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
1858 @@ -0,0 +1,45 @@
1859 +/*
1860 + * QorIQ FMan v3 device tree nodes for ls1043
1861 + *
1862 + * Copyright 2015-2016 Freescale Semiconductor Inc.
1863 + *
1864 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
1865 + */
1866 +
1867 +&soc {
1868 +
1869 +/* include used FMan blocks */
1870 +#include "qoriq-fman3-0.dtsi"
1871 +#include "qoriq-fman3-0-1g-0.dtsi"
1872 +#include "qoriq-fman3-0-1g-1.dtsi"
1873 +#include "qoriq-fman3-0-1g-2.dtsi"
1874 +#include "qoriq-fman3-0-1g-3.dtsi"
1875 +#include "qoriq-fman3-0-1g-4.dtsi"
1876 +#include "qoriq-fman3-0-1g-5.dtsi"
1877 +#include "qoriq-fman3-0-10g-0.dtsi"
1878 +
1879 +};
1880 +
1881 +&fman0 {
1882 + /* these aliases provide the FMan ports mapping */
1883 + enet0: ethernet@e0000 {
1884 + };
1885 +
1886 + enet1: ethernet@e2000 {
1887 + };
1888 +
1889 + enet2: ethernet@e4000 {
1890 + };
1891 +
1892 + enet3: ethernet@e6000 {
1893 + };
1894 +
1895 + enet4: ethernet@e8000 {
1896 + };
1897 +
1898 + enet5: ethernet@ea000 {
1899 + };
1900 +
1901 + enet6: ethernet@f0000 {
1902 + };
1903 +};
1904 --- /dev/null
1905 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
1906 @@ -0,0 +1,69 @@
1907 +/*
1908 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1909 + *
1910 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1911 + *
1912 + * Mingkai Hu <Mingkai.hu@freescale.com>
1913 + *
1914 + * This file is dual-licensed: you can use it either under the terms
1915 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1916 + * licensing only applies to this file, and not this project as a
1917 + * whole.
1918 + *
1919 + * a) This library is free software; you can redistribute it and/or
1920 + * modify it under the terms of the GNU General Public License as
1921 + * published by the Free Software Foundation; either version 2 of the
1922 + * License, or (at your option) any later version.
1923 + *
1924 + * This library is distributed in the hope that it will be useful,
1925 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1926 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1927 + * GNU General Public License for more details.
1928 + *
1929 + * Or, alternatively,
1930 + *
1931 + * b) Permission is hereby granted, free of charge, to any person
1932 + * obtaining a copy of this software and associated documentation
1933 + * files (the "Software"), to deal in the Software without
1934 + * restriction, including without limitation the rights to use,
1935 + * copy, modify, merge, publish, distribute, sublicense, and/or
1936 + * sell copies of the Software, and to permit persons to whom the
1937 + * Software is furnished to do so, subject to the following
1938 + * conditions:
1939 + *
1940 + * The above copyright notice and this permission notice shall be
1941 + * included in all copies or substantial portions of the Software.
1942 + *
1943 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1944 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1945 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1946 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1947 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1948 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1949 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1950 + * OTHER DEALINGS IN THE SOFTWARE.
1951 + */
1952 +
1953 +#include "fsl-ls1043a-qds.dts"
1954 +
1955 +&bman_fbpr {
1956 + compatible = "fsl,bman-fbpr";
1957 + alloc-ranges = <0 0 0x10000 0>;
1958 +};
1959 +&qman_fqd {
1960 + compatible = "fsl,qman-fqd";
1961 + alloc-ranges = <0 0 0x10000 0>;
1962 +};
1963 +&qman_pfdr {
1964 + compatible = "fsl,qman-pfdr";
1965 + alloc-ranges = <0 0 0x10000 0>;
1966 +};
1967 +
1968 +&soc {
1969 +#include "qoriq-dpaa-eth.dtsi"
1970 +#include "qoriq-fman3-0-6oh.dtsi"
1971 +};
1972 +
1973 +&fman0 {
1974 + compatible = "fsl,fman", "simple-bus";
1975 +};
1976 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
1977 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
1978 @@ -1,7 +1,7 @@
1979 /*
1980 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1981 *
1982 - * Copyright 2014-2015, Freescale Semiconductor
1983 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1984 *
1985 * Mingkai Hu <Mingkai.hu@freescale.com>
1986 *
1987 @@ -45,7 +45,7 @@
1988 */
1989
1990 /dts-v1/;
1991 -/include/ "fsl-ls1043a.dtsi"
1992 +#include "fsl-ls1043a.dtsi"
1993
1994 / {
1995 model = "LS1043A QDS Board";
1996 @@ -60,6 +60,22 @@
1997 serial1 = &duart1;
1998 serial2 = &duart2;
1999 serial3 = &duart3;
2000 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
2001 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
2002 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
2003 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
2004 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
2005 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
2006 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
2007 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
2008 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
2009 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
2010 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
2011 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
2012 + emi1_slot1 = &ls1043mdio_s1;
2013 + emi1_slot2 = &ls1043mdio_s2;
2014 + emi1_slot3 = &ls1043mdio_s3;
2015 + emi1_slot4 = &ls1043mdio_s4;
2016 };
2017
2018 chosen {
2019 @@ -97,8 +113,11 @@
2020 };
2021
2022 fpga: board-control@2,0 {
2023 - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
2024 + #address-cells = <1>;
2025 + #size-cells = <1>;
2026 + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
2027 reg = <0x2 0x0 0x0000100>;
2028 + ranges = <0 2 0 0x100>;
2029 };
2030 };
2031
2032 @@ -181,3 +200,149 @@
2033 reg = <0>;
2034 };
2035 };
2036 +
2037 +#include "fsl-ls1043-post.dtsi"
2038 +
2039 +&fman0 {
2040 + ethernet@e0000 {
2041 + phy-handle = <&qsgmii_phy_s2_p1>;
2042 + phy-connection-type = "sgmii";
2043 + };
2044 +
2045 + ethernet@e2000 {
2046 + phy-handle = <&qsgmii_phy_s2_p2>;
2047 + phy-connection-type = "sgmii";
2048 + };
2049 +
2050 + ethernet@e4000 {
2051 + phy-handle = <&rgmii_phy1>;
2052 + phy-connection-type = "rgmii";
2053 + };
2054 +
2055 + ethernet@e6000 {
2056 + phy-handle = <&rgmii_phy2>;
2057 + phy-connection-type = "rgmii";
2058 + };
2059 +
2060 + ethernet@e8000 {
2061 + phy-handle = <&qsgmii_phy_s2_p3>;
2062 + phy-connection-type = "sgmii";
2063 + };
2064 +
2065 + ethernet@ea000 {
2066 + phy-handle = <&qsgmii_phy_s2_p4>;
2067 + phy-connection-type = "sgmii";
2068 + };
2069 +
2070 + ethernet@f0000 { /* DTSEC9/10GEC1 */
2071 + fixed-link = <1 1 10000 0 0>;
2072 + phy-connection-type = "xgmii";
2073 + };
2074 +};
2075 +
2076 +&fpga {
2077 + mdio-mux-emi1 {
2078 + compatible = "mdio-mux-mmioreg", "mdio-mux";
2079 + mdio-parent-bus = <&mdio0>;
2080 + #address-cells = <1>;
2081 + #size-cells = <0>;
2082 + reg = <0x54 1>; /* BRDCFG4 */
2083 + mux-mask = <0xe0>; /* EMI1 */
2084 +
2085 + /* On-board RGMII1 PHY */
2086 + ls1043mdio0: mdio@0 {
2087 + reg = <0>;
2088 + #address-cells = <1>;
2089 + #size-cells = <0>;
2090 +
2091 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
2092 + reg = <0x1>;
2093 + };
2094 + };
2095 +
2096 + /* On-board RGMII2 PHY */
2097 + ls1043mdio1: mdio@1 {
2098 + reg = <0x20>;
2099 + #address-cells = <1>;
2100 + #size-cells = <0>;
2101 +
2102 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
2103 + reg = <0x2>;
2104 + };
2105 + };
2106 +
2107 + /* Slot 1 */
2108 + ls1043mdio_s1: mdio@2 {
2109 + reg = <0x40>;
2110 + #address-cells = <1>;
2111 + #size-cells = <0>;
2112 + status = "disabled";
2113 +
2114 + qsgmii_phy_s1_p1: ethernet-phy@4 {
2115 + reg = <0x4>;
2116 + };
2117 + qsgmii_phy_s1_p2: ethernet-phy@5 {
2118 + reg = <0x5>;
2119 + };
2120 + qsgmii_phy_s1_p3: ethernet-phy@6 {
2121 + reg = <0x6>;
2122 + };
2123 + qsgmii_phy_s1_p4: ethernet-phy@7 {
2124 + reg = <0x7>;
2125 + };
2126 +
2127 + sgmii_phy_s1_p1: ethernet-phy@1c {
2128 + reg = <0x1c>;
2129 + };
2130 + };
2131 +
2132 + /* Slot 2 */
2133 + ls1043mdio_s2: mdio@3 {
2134 + reg = <0x60>;
2135 + #address-cells = <1>;
2136 + #size-cells = <0>;
2137 + status = "disabled";
2138 +
2139 + qsgmii_phy_s2_p1: ethernet-phy@8 {
2140 + reg = <0x8>;
2141 + };
2142 + qsgmii_phy_s2_p2: ethernet-phy@9 {
2143 + reg = <0x9>;
2144 + };
2145 + qsgmii_phy_s2_p3: ethernet-phy@a {
2146 + reg = <0xa>;
2147 + };
2148 + qsgmii_phy_s2_p4: ethernet-phy@b {
2149 + reg = <0xb>;
2150 + };
2151 +
2152 + sgmii_phy_s2_p1: ethernet-phy@1c {
2153 + reg = <0x1c>;
2154 + };
2155 + };
2156 +
2157 + /* Slot 3 */
2158 + ls1043mdio_s3: mdio@4 {
2159 + reg = <0x80>;
2160 + #address-cells = <1>;
2161 + #size-cells = <0>;
2162 + status = "disabled";
2163 +
2164 + sgmii_phy_s3_p1: ethernet-phy@1c {
2165 + reg = <0x1c>;
2166 + };
2167 + };
2168 +
2169 + /* Slot 4 */
2170 + ls1043mdio_s4: mdio@5 {
2171 + reg = <0xa0>;
2172 + #address-cells = <1>;
2173 + #size-cells = <0>;
2174 + status = "disabled";
2175 +
2176 + sgmii_phy_s4_p1: ethernet-phy@1c {
2177 + reg = <0x1c>;
2178 + };
2179 + };
2180 + };
2181 +};
2182 --- /dev/null
2183 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2184 @@ -0,0 +1,69 @@
2185 +/*
2186 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2187 + *
2188 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2189 + *
2190 + * Mingkai Hu <Mingkai.hu@freescale.com>
2191 + *
2192 + * This file is dual-licensed: you can use it either under the terms
2193 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2194 + * licensing only applies to this file, and not this project as a
2195 + * whole.
2196 + *
2197 + * a) This library is free software; you can redistribute it and/or
2198 + * modify it under the terms of the GNU General Public License as
2199 + * published by the Free Software Foundation; either version 2 of the
2200 + * License, or (at your option) any later version.
2201 + *
2202 + * This library is distributed in the hope that it will be useful,
2203 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2204 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2205 + * GNU General Public License for more details.
2206 + *
2207 + * Or, alternatively,
2208 + *
2209 + * b) Permission is hereby granted, free of charge, to any person
2210 + * obtaining a copy of this software and associated documentation
2211 + * files (the "Software"), to deal in the Software without
2212 + * restriction, including without limitation the rights to use,
2213 + * copy, modify, merge, publish, distribute, sublicense, and/or
2214 + * sell copies of the Software, and to permit persons to whom the
2215 + * Software is furnished to do so, subject to the following
2216 + * conditions:
2217 + *
2218 + * The above copyright notice and this permission notice shall be
2219 + * included in all copies or substantial portions of the Software.
2220 + *
2221 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2222 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2223 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2224 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2225 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2226 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2227 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2228 + * OTHER DEALINGS IN THE SOFTWARE.
2229 + */
2230 +
2231 +#include "fsl-ls1043a-rdb.dts"
2232 +
2233 +&bman_fbpr {
2234 + compatible = "fsl,bman-fbpr";
2235 + alloc-ranges = <0 0 0x10000 0>;
2236 +};
2237 +&qman_fqd {
2238 + compatible = "fsl,qman-fqd";
2239 + alloc-ranges = <0 0 0x10000 0>;
2240 +};
2241 +&qman_pfdr {
2242 + compatible = "fsl,qman-pfdr";
2243 + alloc-ranges = <0 0 0x10000 0>;
2244 +};
2245 +
2246 +&soc {
2247 +#include "qoriq-dpaa-eth.dtsi"
2248 +#include "qoriq-fman3-0-6oh.dtsi"
2249 +};
2250 +
2251 +&fman0 {
2252 + compatible = "fsl,fman", "simple-bus";
2253 +};
2254 --- /dev/null
2255 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2256 @@ -0,0 +1,117 @@
2257 +/*
2258 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2259 + *
2260 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2261 + *
2262 + * This file is licensed under the terms of the GNU General Public
2263 + * License version 2. This program is licensed "as is" without any
2264 + * warranty of any kind, whether express or implied.
2265 + */
2266 +
2267 +#include "fsl-ls1043a-rdb-sdk.dts"
2268 +
2269 +&soc {
2270 + bp7: buffer-pool@7 {
2271 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2272 + fsl,bpid = <7>;
2273 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
2274 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
2275 + };
2276 +
2277 + bp8: buffer-pool@8 {
2278 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2279 + fsl,bpid = <8>;
2280 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
2281 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2282 + };
2283 +
2284 + bp9: buffer-pool@9 {
2285 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2286 + fsl,bpid = <9>;
2287 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
2288 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2289 + };
2290 +
2291 + fsl,dpaa {
2292 + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
2293 +
2294 + ethernet@0 {
2295 + compatible = "fsl,dpa-ethernet-init";
2296 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2297 + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
2298 + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
2299 + };
2300 +
2301 + ethernet@1 {
2302 + compatible = "fsl,dpa-ethernet-init";
2303 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2304 + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
2305 + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
2306 + };
2307 +
2308 + ethernet@2 {
2309 + compatible = "fsl,dpa-ethernet-init";
2310 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2311 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
2312 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
2313 + };
2314 +
2315 + ethernet@3 {
2316 + compatible = "fsl,dpa-ethernet-init";
2317 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2318 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
2319 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
2320 + };
2321 +
2322 + ethernet@4 {
2323 + compatible = "fsl,dpa-ethernet-init";
2324 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2325 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
2326 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
2327 + };
2328 +
2329 + ethernet@5 {
2330 + compatible = "fsl,dpa-ethernet-init";
2331 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2332 + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
2333 + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
2334 + };
2335 +
2336 + ethernet@8 {
2337 + compatible = "fsl,dpa-ethernet-init";
2338 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2339 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
2340 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
2341 +
2342 + };
2343 + dpa-fman0-oh@2 {
2344 + compatible = "fsl,dpa-oh";
2345 + /* Define frame queues for the OH port*/
2346 + /* <OH Rx error, OH Rx default> */
2347 + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
2348 + fsl,fman-oh-port = <&fman0_oh2>;
2349 + };
2350 + };
2351 +};
2352 +/ {
2353 + reserved-memory {
2354 + #address-cells = <2>;
2355 + #size-cells = <2>;
2356 + ranges;
2357 +
2358 + usdpaa_mem: usdpaa_mem {
2359 + compatible = "fsl,usdpaa-mem";
2360 + alloc-ranges = <0 0 0x10000 0>;
2361 + size = <0 0x10000000>;
2362 + alignment = <0 0x10000000>;
2363 + };
2364 + };
2365 +};
2366 +
2367 +&fman0 {
2368 + fman0_oh2: port@83000 {
2369 + cell-index = <1>;
2370 + compatible = "fsl,fman-port-oh";
2371 + reg = <0x83000 0x1000>;
2372 + };
2373 +};
2374 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2375 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2376 @@ -1,7 +1,7 @@
2377 /*
2378 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2379 *
2380 - * Copyright 2014-2015, Freescale Semiconductor
2381 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2382 *
2383 * Mingkai Hu <Mingkai.hu@freescale.com>
2384 *
2385 @@ -45,7 +45,7 @@
2386 */
2387
2388 /dts-v1/;
2389 -/include/ "fsl-ls1043a.dtsi"
2390 +#include "fsl-ls1043a.dtsi"
2391
2392 / {
2393 model = "LS1043A RDB Board";
2394 @@ -86,6 +86,10 @@
2395 compatible = "pericom,pt7c4338";
2396 reg = <0x68>;
2397 };
2398 + rtc@51 {
2399 + compatible = "nxp,pcf85263";
2400 + reg = <0x51>;
2401 + };
2402 };
2403
2404 &ifc {
2405 @@ -130,6 +134,38 @@
2406 reg = <0>;
2407 spi-max-frequency = <1000000>; /* input clock */
2408 };
2409 +
2410 + slic@2 {
2411 + compatible = "maxim,ds26522";
2412 + reg = <2>;
2413 + spi-max-frequency = <2000000>;
2414 + fsl,spi-cs-sck-delay = <100>;
2415 + fsl,spi-sck-cs-delay = <50>;
2416 + };
2417 +
2418 + slic@3 {
2419 + compatible = "maxim,ds26522";
2420 + reg = <3>;
2421 + spi-max-frequency = <2000000>;
2422 + fsl,spi-cs-sck-delay = <100>;
2423 + fsl,spi-sck-cs-delay = <50>;
2424 + };
2425 +};
2426 +
2427 +&uqe {
2428 + ucc_hdlc: ucc@2000 {
2429 + compatible = "fsl,ucc-hdlc";
2430 + rx-clock-name = "clk8";
2431 + tx-clock-name = "clk9";
2432 + fsl,rx-sync-clock = "rsync_pin";
2433 + fsl,tx-sync-clock = "tsync_pin";
2434 + fsl,tx-timeslot-mask = <0xfffffffe>;
2435 + fsl,rx-timeslot-mask = <0xfffffffe>;
2436 + fsl,tdm-framer-type = "e1";
2437 + fsl,tdm-id = <0>;
2438 + fsl,siram-entry-id = <0>;
2439 + fsl,tdm-interface;
2440 + };
2441 };
2442
2443 &duart0 {
2444 @@ -139,3 +175,76 @@
2445 &duart1 {
2446 status = "okay";
2447 };
2448 +
2449 +#include "fsl-ls1043-post.dtsi"
2450 +
2451 +&fman0 {
2452 + ethernet@e0000 {
2453 + phy-handle = <&qsgmii_phy1>;
2454 + phy-connection-type = "qsgmii";
2455 + };
2456 +
2457 + ethernet@e2000 {
2458 + phy-handle = <&qsgmii_phy2>;
2459 + phy-connection-type = "qsgmii";
2460 + };
2461 +
2462 + ethernet@e4000 {
2463 + phy-handle = <&rgmii_phy1>;
2464 + phy-connection-type = "rgmii-txid";
2465 + };
2466 +
2467 + ethernet@e6000 {
2468 + phy-handle = <&rgmii_phy2>;
2469 + phy-connection-type = "rgmii-txid";
2470 + };
2471 +
2472 + ethernet@e8000 {
2473 + phy-handle = <&qsgmii_phy3>;
2474 + phy-connection-type = "qsgmii";
2475 + };
2476 +
2477 + ethernet@ea000 {
2478 + phy-handle = <&qsgmii_phy4>;
2479 + phy-connection-type = "qsgmii";
2480 + };
2481 +
2482 + ethernet@f0000 { /* 10GEC1 */
2483 + phy-handle = <&aqr105_phy>;
2484 + phy-connection-type = "xgmii";
2485 + };
2486 +
2487 + mdio@fc000 {
2488 + rgmii_phy1: ethernet-phy@1 {
2489 + reg = <0x1>;
2490 + };
2491 +
2492 + rgmii_phy2: ethernet-phy@2 {
2493 + reg = <0x2>;
2494 + };
2495 +
2496 + qsgmii_phy1: ethernet-phy@4 {
2497 + reg = <0x4>;
2498 + };
2499 +
2500 + qsgmii_phy2: ethernet-phy@5 {
2501 + reg = <0x5>;
2502 + };
2503 +
2504 + qsgmii_phy3: ethernet-phy@6 {
2505 + reg = <0x6>;
2506 + };
2507 +
2508 + qsgmii_phy4: ethernet-phy@7 {
2509 + reg = <0x7>;
2510 + };
2511 + };
2512 +
2513 + mdio@fd000 {
2514 + aqr105_phy: ethernet-phy@1 {
2515 + compatible = "ethernet-phy-ieee802.3-c45";
2516 + interrupts = <0 132 4>;
2517 + reg = <0x1>;
2518 + };
2519 + };
2520 +};
2521 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2522 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2523 @@ -1,7 +1,7 @@
2524 /*
2525 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2526 *
2527 - * Copyright 2014-2015, Freescale Semiconductor
2528 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2529 *
2530 * Mingkai Hu <Mingkai.hu@freescale.com>
2531 *
2532 @@ -44,12 +44,25 @@
2533 * OTHER DEALINGS IN THE SOFTWARE.
2534 */
2535
2536 +#include <dt-bindings/thermal/thermal.h>
2537 +
2538 / {
2539 compatible = "fsl,ls1043a";
2540 interrupt-parent = <&gic>;
2541 #address-cells = <2>;
2542 #size-cells = <2>;
2543
2544 + aliases {
2545 + fman0 = &fman0;
2546 + ethernet0 = &enet0;
2547 + ethernet1 = &enet1;
2548 + ethernet2 = &enet2;
2549 + ethernet3 = &enet3;
2550 + ethernet4 = &enet4;
2551 + ethernet5 = &enet5;
2552 + ethernet6 = &enet6;
2553 + };
2554 +
2555 cpus {
2556 #address-cells = <1>;
2557 #size-cells = <0>;
2558 @@ -66,6 +79,8 @@
2559 reg = <0x0>;
2560 clocks = <&clockgen 1 0>;
2561 next-level-cache = <&l2>;
2562 + #cooling-cells = <2>;
2563 + cpu-idle-states = <&CPU_PH20>;
2564 };
2565
2566 cpu1: cpu@1 {
2567 @@ -74,6 +89,7 @@
2568 reg = <0x1>;
2569 clocks = <&clockgen 1 0>;
2570 next-level-cache = <&l2>;
2571 + cpu-idle-states = <&CPU_PH20>;
2572 };
2573
2574 cpu2: cpu@2 {
2575 @@ -82,6 +98,7 @@
2576 reg = <0x2>;
2577 clocks = <&clockgen 1 0>;
2578 next-level-cache = <&l2>;
2579 + cpu-idle-states = <&CPU_PH20>;
2580 };
2581
2582 cpu3: cpu@3 {
2583 @@ -90,6 +107,7 @@
2584 reg = <0x3>;
2585 clocks = <&clockgen 1 0>;
2586 next-level-cache = <&l2>;
2587 + cpu-idle-states = <&CPU_PH20>;
2588 };
2589
2590 l2: l2-cache {
2591 @@ -97,12 +115,56 @@
2592 };
2593 };
2594
2595 + idle-states {
2596 + /*
2597 + * PSCI node is not added default, U-boot will add missing
2598 + * parts if it determines to use PSCI.
2599 + */
2600 + entry-method = "arm,psci";
2601 +
2602 + CPU_PH20: cpu-ph20 {
2603 + compatible = "arm,idle-state";
2604 + idle-state-name = "PH20";
2605 + arm,psci-suspend-param = <0x0>;
2606 + entry-latency-us = <1000>;
2607 + exit-latency-us = <1000>;
2608 + min-residency-us = <3000>;
2609 + };
2610 + };
2611 +
2612 memory@80000000 {
2613 device_type = "memory";
2614 reg = <0x0 0x80000000 0 0x80000000>;
2615 /* DRAM space 1, size: 2GiB DRAM */
2616 };
2617
2618 + reserved-memory {
2619 + #address-cells = <2>;
2620 + #size-cells = <2>;
2621 + ranges;
2622 +
2623 + bman_fbpr: bman-fbpr {
2624 + compatible = "shared-dma-pool";
2625 + size = <0 0x1000000>;
2626 + alignment = <0 0x1000000>;
2627 + no-map;
2628 + };
2629 +
2630 + qman_fqd: qman-fqd {
2631 + compatible = "shared-dma-pool";
2632 + size = <0 0x400000>;
2633 + alignment = <0 0x400000>;
2634 + no-map;
2635 + };
2636 +
2637 + qman_pfdr: qman-pfdr {
2638 + compatible = "shared-dma-pool";
2639 + size = <0 0x2000000>;
2640 + alignment = <0 0x2000000>;
2641 + no-map;
2642 + };
2643 + };
2644 +
2645 sysclk: sysclk {
2646 compatible = "fixed-clock";
2647 #clock-cells = <0>;
2648 @@ -149,7 +211,7 @@
2649 interrupts = <1 9 0xf08>;
2650 };
2651
2652 - soc {
2653 + soc: soc {
2654 compatible = "simple-bus";
2655 #address-cells = <2>;
2656 #size-cells = <2>;
2657 @@ -213,13 +275,14 @@
2658
2659 dcfg: dcfg@1ee0000 {
2660 compatible = "fsl,ls1043a-dcfg", "syscon";
2661 - reg = <0x0 0x1ee0000 0x0 0x10000>;
2662 + reg = <0x0 0x1ee0000 0x0 0x1000>;
2663 big-endian;
2664 };
2665
2666 ifc: ifc@1530000 {
2667 compatible = "fsl,ifc", "simple-bus";
2668 reg = <0x0 0x1530000 0x0 0x10000>;
2669 + big-endian;
2670 interrupts = <0 43 0x4>;
2671 };
2672
2673 @@ -255,6 +318,103 @@
2674 big-endian;
2675 };
2676
2677 + tmu: tmu@1f00000 {
2678 + compatible = "fsl,qoriq-tmu";
2679 + reg = <0x0 0x1f00000 0x0 0x10000>;
2680 + interrupts = <0 33 0x4>;
2681 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
2682 + fsl,tmu-calibration = <0x00000000 0x00000026
2683 + 0x00000001 0x0000002d
2684 + 0x00000002 0x00000032
2685 + 0x00000003 0x00000039
2686 + 0x00000004 0x0000003f
2687 + 0x00000005 0x00000046
2688 + 0x00000006 0x0000004d
2689 + 0x00000007 0x00000054
2690 + 0x00000008 0x0000005a
2691 + 0x00000009 0x00000061
2692 + 0x0000000a 0x0000006a
2693 + 0x0000000b 0x00000071
2694 +
2695 + 0x00010000 0x00000025
2696 + 0x00010001 0x0000002c
2697 + 0x00010002 0x00000035
2698 + 0x00010003 0x0000003d
2699 + 0x00010004 0x00000045
2700 + 0x00010005 0x0000004e
2701 + 0x00010006 0x00000057
2702 + 0x00010007 0x00000061
2703 + 0x00010008 0x0000006b
2704 + 0x00010009 0x00000076
2705 +
2706 + 0x00020000 0x00000029
2707 + 0x00020001 0x00000033
2708 + 0x00020002 0x0000003d
2709 + 0x00020003 0x00000049
2710 + 0x00020004 0x00000056
2711 + 0x00020005 0x00000061
2712 + 0x00020006 0x0000006d
2713 +
2714 + 0x00030000 0x00000021
2715 + 0x00030001 0x0000002a
2716 + 0x00030002 0x0000003c
2717 + 0x00030003 0x0000004e>;
2718 + #thermal-sensor-cells = <1>;
2719 + };
2720 +
2721 + thermal-zones {
2722 + cpu_thermal: cpu-thermal {
2723 + polling-delay-passive = <1000>;
2724 + polling-delay = <5000>;
2725 +
2726 + thermal-sensors = <&tmu 3>;
2727 +
2728 + trips {
2729 + cpu_alert: cpu-alert {
2730 + temperature = <85000>;
2731 + hysteresis = <2000>;
2732 + type = "passive";
2733 + };
2734 + cpu_crit: cpu-crit {
2735 + temperature = <95000>;
2736 + hysteresis = <2000>;
2737 + type = "critical";
2738 + };
2739 + };
2740 +
2741 + cooling-maps {
2742 + map0 {
2743 + trip = <&cpu_alert>;
2744 + cooling-device =
2745 + <&cpu0 THERMAL_NO_LIMIT
2746 + THERMAL_NO_LIMIT>;
2747 + };
2748 + };
2749 + };
2750 + };
2751 +
2752 + qman: qman@1880000 {
2753 + compatible = "fsl,qman";
2754 + reg = <0x00 0x1880000 0x0 0x10000>;
2755 + interrupts = <0 45 0x4>;
2756 + memory-region = <&qman_fqd &qman_pfdr>;
2757 + };
2758 +
2759 + bman: bman@1890000 {
2760 + compatible = "fsl,bman";
2761 + reg = <0x00 0x1890000 0x0 0x10000>;
2762 + interrupts = <0 45 0x4>;
2763 + memory-region = <&bman_fbpr>;
2764 + };
2765 +
2766 + bportals: bman-portals@508000000 {
2767 + ranges = <0x0 0x5 0x08000000 0x8000000>;
2768 + };
2769 +
2770 + qportals: qman-portals@500000000 {
2771 + ranges = <0x0 0x5 0x00000000 0x8000000>;
2772 + };
2773 +
2774 dspi0: dspi@2100000 {
2775 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
2776 #address-cells = <1>;
2777 @@ -396,6 +556,72 @@
2778 #interrupt-cells = <2>;
2779 };
2780
2781 + uqe: uqe@2400000 {
2782 + #address-cells = <1>;
2783 + #size-cells = <1>;
2784 + device_type = "qe";
2785 + compatible = "fsl,qe", "simple-bus";
2786 + ranges = <0x0 0x0 0x2400000 0x40000>;
2787 + reg = <0x0 0x2400000 0x0 0x480>;
2788 + brg-frequency = <100000000>;
2789 + bus-frequency = <200000000>;
2790 +
2791 + fsl,qe-num-riscs = <1>;
2792 + fsl,qe-num-snums = <28>;
2793 +
2794 + qeic: qeic@80 {
2795 + compatible = "fsl,qe-ic";
2796 + reg = <0x80 0x80>;
2797 + #address-cells = <0>;
2798 + interrupt-controller;
2799 + #interrupt-cells = <1>;
2800 + interrupts = <0 77 0x04 0 77 0x04>;
2801 + };
2802 +
2803 + si1: si@700 {
2804 + #address-cells = <1>;
2805 + #size-cells = <0>;
2806 + compatible = "fsl,ls1043-qe-si",
2807 + "fsl,t1040-qe-si";
2808 + reg = <0x700 0x80>;
2809 + };
2810 +
2811 + siram1: siram@1000 {
2812 + #address-cells = <1>;
2813 + #size-cells = <1>;
2814 + compatible = "fsl,ls1043-qe-siram",
2815 + "fsl,t1040-qe-siram";
2816 + reg = <0x1000 0x800>;
2817 + };
2818 +
2819 + ucc@2000 {
2820 + cell-index = <1>;
2821 + reg = <0x2000 0x200>;
2822 + interrupts = <32>;
2823 + interrupt-parent = <&qeic>;
2824 + };
2825 +
2826 + ucc@2200 {
2827 + cell-index = <3>;
2828 + reg = <0x2200 0x200>;
2829 + interrupts = <34>;
2830 + interrupt-parent = <&qeic>;
2831 + };
2832 +
2833 + muram@10000 {
2834 + #address-cells = <1>;
2835 + #size-cells = <1>;
2836 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
2837 + ranges = <0x0 0x10000 0x6000>;
2838 +
2839 + data-only@0 {
2840 + compatible = "fsl,qe-muram-data",
2841 + "fsl,cpm-muram-data";
2842 + reg = <0x0 0x6000>;
2843 + };
2844 + };
2845 + };
2846 +
2847 lpuart0: serial@2950000 {
2848 compatible = "fsl,ls1021a-lpuart";
2849 reg = <0x0 0x2950000 0x0 0x1000>;
2850 @@ -450,6 +676,16 @@
2851 status = "disabled";
2852 };
2853
2854 + ftm0: ftm0@29d0000 {
2855 + compatible = "fsl,ls1043a-ftm";
2856 + reg = <0x0 0x29d0000 0x0 0x10000>,
2857 + <0x0 0x1ee2140 0x0 0x4>;
2858 + reg-names = "ftm", "FlexTimer1";
2859 + interrupts = <0 86 0x4>;
2860 + big-endian;
2861 + status = "okay";
2862 + };
2863 +
2864 wdog0: wdog@2ad0000 {
2865 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
2866 reg = <0x0 0x2ad0000 0x0 0x10000>;
2867 @@ -482,6 +718,8 @@
2868 dr_mode = "host";
2869 snps,quirk-frame-length-adjustment = <0x20>;
2870 snps,dis_rxdet_inp3_quirk;
2871 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2872 + snps,dma-snooping;
2873 };
2874
2875 usb1: usb3@3000000 {
2876 @@ -491,6 +729,9 @@
2877 dr_mode = "host";
2878 snps,quirk-frame-length-adjustment = <0x20>;
2879 snps,dis_rxdet_inp3_quirk;
2880 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2881 + snps,dma-snooping;
2882 + configure-gfladj;
2883 };
2884
2885 usb2: usb3@3100000 {
2886 @@ -500,32 +741,52 @@
2887 dr_mode = "host";
2888 snps,quirk-frame-length-adjustment = <0x20>;
2889 snps,dis_rxdet_inp3_quirk;
2890 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2891 + snps,dma-snooping;
2892 + configure-gfladj;
2893 };
2894
2895 sata: sata@3200000 {
2896 compatible = "fsl,ls1043a-ahci";
2897 - reg = <0x0 0x3200000 0x0 0x10000>;
2898 + reg = <0x0 0x3200000 0x0 0x10000>,
2899 + <0x0 0x20140520 0x0 0x4>;
2900 + reg-names = "ahci", "sata-ecc";
2901 interrupts = <0 69 0x4>;
2902 clocks = <&clockgen 4 0>;
2903 dma-coherent;
2904 };
2905
2906 + qdma: qdma@8380000 {
2907 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
2908 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
2909 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
2910 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
2911 + interrupts = <0 152 0x4>,
2912 + <0 39 0x4>;
2913 + interrupt-names = "qdma-error", "qdma-queue";
2914 + channels = <8>;
2915 + queues = <2>;
2916 + status-sizes = <64>;
2917 + queue-sizes = <64 64>;
2918 + big-endian;
2919 + };
2920 +
2921 msi1: msi-controller1@1571000 {
2922 - compatible = "fsl,1s1043a-msi";
2923 + compatible = "fsl,ls1043a-msi";
2924 reg = <0x0 0x1571000 0x0 0x8>;
2925 msi-controller;
2926 interrupts = <0 116 0x4>;
2927 };
2928
2929 msi2: msi-controller2@1572000 {
2930 - compatible = "fsl,1s1043a-msi";
2931 + compatible = "fsl,ls1043a-msi";
2932 reg = <0x0 0x1572000 0x0 0x8>;
2933 msi-controller;
2934 interrupts = <0 126 0x4>;
2935 };
2936
2937 msi3: msi-controller3@1573000 {
2938 - compatible = "fsl,1s1043a-msi";
2939 + compatible = "fsl,ls1043a-msi";
2940 reg = <0x0 0x1573000 0x0 0x8>;
2941 msi-controller;
2942 interrupts = <0 160 0x4>;
2943 @@ -536,9 +797,9 @@
2944 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
2945 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
2946 reg-names = "regs", "config";
2947 - interrupts = <0 118 0x4>, /* controller interrupt */
2948 - <0 117 0x4>; /* PME interrupt */
2949 - interrupt-names = "intr", "pme";
2950 + interrupts = <0 117 0x4>, /* PME interrupt */
2951 + <0 118 0x4>; /* aer interrupt */
2952 + interrupt-names = "pme", "aer";
2953 #address-cells = <3>;
2954 #size-cells = <2>;
2955 device_type = "pci";
2956 @@ -547,7 +808,7 @@
2957 bus-range = <0x0 0xff>;
2958 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
2959 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2960 - msi-parent = <&msi1>;
2961 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2962 #interrupt-cells = <1>;
2963 interrupt-map-mask = <0 0 0 7>;
2964 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
2965 @@ -561,9 +822,9 @@
2966 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
2967 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
2968 reg-names = "regs", "config";
2969 - interrupts = <0 128 0x4>,
2970 - <0 127 0x4>;
2971 - interrupt-names = "intr", "pme";
2972 + interrupts = <0 127 0x4>,
2973 + <0 128 0x4>;
2974 + interrupt-names = "pme", "aer";
2975 #address-cells = <3>;
2976 #size-cells = <2>;
2977 device_type = "pci";
2978 @@ -572,7 +833,7 @@
2979 bus-range = <0x0 0xff>;
2980 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
2981 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2982 - msi-parent = <&msi2>;
2983 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2984 #interrupt-cells = <1>;
2985 interrupt-map-mask = <0 0 0 7>;
2986 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
2987 @@ -586,9 +847,9 @@
2988 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
2989 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
2990 reg-names = "regs", "config";
2991 - interrupts = <0 162 0x4>,
2992 - <0 161 0x4>;
2993 - interrupt-names = "intr", "pme";
2994 + interrupts = <0 161 0x4>,
2995 + <0 162 0x4>;
2996 + interrupt-names = "pme", "aer";
2997 #address-cells = <3>;
2998 #size-cells = <2>;
2999 device_type = "pci";
3000 @@ -597,7 +858,7 @@
3001 bus-range = <0x0 0xff>;
3002 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
3003 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3004 - msi-parent = <&msi3>;
3005 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3006 #interrupt-cells = <1>;
3007 interrupt-map-mask = <0 0 0 7>;
3008 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
3009 @@ -608,3 +869,6 @@
3010 };
3011
3012 };
3013 +
3014 +#include "qoriq-qman1-portals.dtsi"
3015 +#include "qoriq-bman1-portals.dtsi"
3016 --- /dev/null
3017 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
3018 @@ -0,0 +1,48 @@
3019 +/*
3020 + * QorIQ FMan v3 device tree nodes for ls1046
3021 + *
3022 + * Copyright 2015-2016 Freescale Semiconductor Inc.
3023 + *
3024 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3025 + */
3026 +
3027 +&soc {
3028 +
3029 +/* include used FMan blocks */
3030 +#include "qoriq-fman3-0.dtsi"
3031 +#include "qoriq-fman3-0-1g-0.dtsi"
3032 +#include "qoriq-fman3-0-1g-1.dtsi"
3033 +#include "qoriq-fman3-0-1g-2.dtsi"
3034 +#include "qoriq-fman3-0-1g-3.dtsi"
3035 +#include "qoriq-fman3-0-1g-4.dtsi"
3036 +#include "qoriq-fman3-0-1g-5.dtsi"
3037 +#include "qoriq-fman3-0-10g-0.dtsi"
3038 +#include "qoriq-fman3-0-10g-1.dtsi"
3039 +};
3040 +
3041 +&fman0 {
3042 + /* these aliases provide the FMan ports mapping */
3043 + enet0: ethernet@e0000 {
3044 + };
3045 +
3046 + enet1: ethernet@e2000 {
3047 + };
3048 +
3049 + enet2: ethernet@e4000 {
3050 + };
3051 +
3052 + enet3: ethernet@e6000 {
3053 + };
3054 +
3055 + enet4: ethernet@e8000 {
3056 + };
3057 +
3058 + enet5: ethernet@ea000 {
3059 + };
3060 +
3061 + enet6: ethernet@f0000 {
3062 + };
3063 +
3064 + enet7: ethernet@f2000 {
3065 + };
3066 +};
3067 --- /dev/null
3068 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
3069 @@ -0,0 +1,109 @@
3070 +/*
3071 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3072 + *
3073 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3074 + *
3075 + * Mingkai Hu <Mingkai.hu@freescale.com>
3076 + *
3077 + * This file is dual-licensed: you can use it either under the terms
3078 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3079 + * licensing only applies to this file, and not this project as a
3080 + * whole.
3081 + *
3082 + * a) This library is free software; you can redistribute it and/or
3083 + * modify it under the terms of the GNU General Public License as
3084 + * published by the Free Software Foundation; either version 2 of the
3085 + * License, or (at your option) any later version.
3086 + *
3087 + * This library is distributed in the hope that it will be useful,
3088 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3089 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3090 + * GNU General Public License for more details.
3091 + *
3092 + * Or, alternatively,
3093 + *
3094 + * b) Permission is hereby granted, free of charge, to any person
3095 + * obtaining a copy of this software and associated documentation
3096 + * files (the "Software"), to deal in the Software without
3097 + * restriction, including without limitation the rights to use,
3098 + * copy, modify, merge, publish, distribute, sublicense, and/or
3099 + * sell copies of the Software, and to permit persons to whom the
3100 + * Software is furnished to do so, subject to the following
3101 + * conditions:
3102 + *
3103 + * The above copyright notice and this permission notice shall be
3104 + * included in all copies or substantial portions of the Software.
3105 + *
3106 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3107 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3108 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3109 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3110 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3111 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3112 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3113 + * OTHER DEALINGS IN THE SOFTWARE.
3114 + */
3115 +
3116 +#include "fsl-ls1046a-qds.dts"
3117 +
3118 +&bman_fbpr {
3119 + compatible = "fsl,bman-fbpr";
3120 + alloc-ranges = <0 0 0x10000 0>;
3121 +};
3122 +&qman_fqd {
3123 + compatible = "fsl,qman-fqd";
3124 + alloc-ranges = <0 0 0x10000 0>;
3125 +};
3126 +&qman_pfdr {
3127 + compatible = "fsl,qman-pfdr";
3128 + alloc-ranges = <0 0 0x10000 0>;
3129 +};
3130 +
3131 +&soc {
3132 +#include "qoriq-dpaa-eth.dtsi"
3133 +#include "qoriq-fman3-0-6oh.dtsi"
3134 +};
3135 +
3136 +&fsldpaa {
3137 + ethernet@9 {
3138 + compatible = "fsl,dpa-ethernet";
3139 + fsl,fman-mac = <&enet7>;
3140 + };
3141 +};
3142 +
3143 +&fman0 {
3144 + compatible = "fsl,fman", "simple-bus";
3145 +};
3146 +
3147 +&dspi {
3148 + bus-num = <0>;
3149 + status = "okay";
3150 +
3151 + flash@0 {
3152 + #address-cells = <1>;
3153 + #size-cells = <1>;
3154 + compatible = "n25q128a11", "jedec,spi-nor";
3155 + reg = <0>;
3156 + spi-max-frequency = <10000000>;
3157 + };
3158 +
3159 + flash@1 {
3160 + #address-cells = <1>;
3161 + #size-cells = <1>;
3162 + compatible = "sst25wf040b", "jedec,spi-nor";
3163 + spi-cpol;
3164 + spi-cpha;
3165 + reg = <1>;
3166 + spi-max-frequency = <10000000>;
3167 + };
3168 +
3169 + flash@2 {
3170 + #address-cells = <1>;
3171 + #size-cells = <1>;
3172 + compatible = "en25s64", "jedec,spi-nor";
3173 + spi-cpol;
3174 + spi-cpha;
3175 + reg = <2>;
3176 + spi-max-frequency = <10000000>;
3177 + };
3178 +};
3179 --- /dev/null
3180 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3181 @@ -0,0 +1,363 @@
3182 +/*
3183 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3184 + *
3185 + * Copyright 2016 Freescale Semiconductor, Inc.
3186 + *
3187 + * Shaohui Xie <Shaohui.Xie@nxp.com>
3188 + *
3189 + * This file is dual-licensed: you can use it either under the terms
3190 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3191 + * licensing only applies to this file, and not this project as a
3192 + * whole.
3193 + *
3194 + * a) This library is free software; you can redistribute it and/or
3195 + * modify it under the terms of the GNU General Public License as
3196 + * published by the Free Software Foundation; either version 2 of the
3197 + * License, or (at your option) any later version.
3198 + *
3199 + * This library is distributed in the hope that it will be useful,
3200 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3201 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3202 + * GNU General Public License for more details.
3203 + *
3204 + * Or, alternatively,
3205 + *
3206 + * b) Permission is hereby granted, free of charge, to any person
3207 + * obtaining a copy of this software and associated documentation
3208 + * files (the "Software"), to deal in the Software without
3209 + * restriction, including without limitation the rights to use,
3210 + * copy, modify, merge, publish, distribute, sublicense, and/or
3211 + * sell copies of the Software, and to permit persons to whom the
3212 + * Software is furnished to do so, subject to the following
3213 + * conditions:
3214 + *
3215 + * The above copyright notice and this permission notice shall be
3216 + * included in all copies or substantial portions of the Software.
3217 + *
3218 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3219 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3220 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3221 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3222 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3223 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3224 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3225 + * OTHER DEALINGS IN THE SOFTWARE.
3226 + */
3227 +
3228 +/dts-v1/;
3229 +
3230 +#include "fsl-ls1046a.dtsi"
3231 +
3232 +/ {
3233 + model = "LS1046A QDS Board";
3234 + compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
3235 +
3236 + aliases {
3237 + gpio0 = &gpio0;
3238 + gpio1 = &gpio1;
3239 + gpio2 = &gpio2;
3240 + gpio3 = &gpio3;
3241 + serial0 = &duart0;
3242 + serial1 = &duart1;
3243 + serial2 = &duart2;
3244 + serial3 = &duart3;
3245 +
3246 + emi1_slot1 = &ls1046mdio_s1;
3247 + emi1_slot2 = &ls1046mdio_s2;
3248 + emi1_slot4 = &ls1046mdio_s4;
3249 +
3250 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
3251 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
3252 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
3253 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
3254 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
3255 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
3256 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
3257 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
3258 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
3259 + };
3260 +
3261 + chosen {
3262 + stdout-path = "serial0:115200n8";
3263 + };
3264 +};
3265 +
3266 +&dspi {
3267 + bus-num = <0>;
3268 + status = "okay";
3269 +
3270 + flash@0 {
3271 + #address-cells = <1>;
3272 + #size-cells = <1>;
3273 + compatible = "n25q128a11", "jedec,spi-nor";
3274 + reg = <0>;
3275 + spi-max-frequency = <10000000>;
3276 + };
3277 +
3278 + flash@1 {
3279 + #address-cells = <1>;
3280 + #size-cells = <1>;
3281 + compatible = "sst25wf040b", "jedec,spi-nor";
3282 + spi-cpol;
3283 + spi-cpha;
3284 + reg = <1>;
3285 + spi-max-frequency = <10000000>;
3286 + };
3287 +
3288 + flash@2 {
3289 + #address-cells = <1>;
3290 + #size-cells = <1>;
3291 + compatible = "en25s64", "jedec,spi-nor";
3292 + spi-cpol;
3293 + spi-cpha;
3294 + reg = <2>;
3295 + spi-max-frequency = <10000000>;
3296 + };
3297 +};
3298 +
3299 +&duart0 {
3300 + status = "okay";
3301 +};
3302 +
3303 +&duart1 {
3304 + status = "okay";
3305 +};
3306 +
3307 +&i2c0 {
3308 + status = "okay";
3309 +
3310 + pca9547@77 {
3311 + compatible = "nxp,pca9547";
3312 + reg = <0x77>;
3313 + #address-cells = <1>;
3314 + #size-cells = <0>;
3315 +
3316 + i2c@2 {
3317 + #address-cells = <1>;
3318 + #size-cells = <0>;
3319 + reg = <0x2>;
3320 +
3321 + ina220@40 {
3322 + compatible = "ti,ina220";
3323 + reg = <0x40>;
3324 + shunt-resistor = <1000>;
3325 + };
3326 +
3327 + ina220@41 {
3328 + compatible = "ti,ina220";
3329 + reg = <0x41>;
3330 + shunt-resistor = <1000>;
3331 + };
3332 + };
3333 +
3334 + i2c@3 {
3335 + #address-cells = <1>;
3336 + #size-cells = <0>;
3337 + reg = <0x3>;
3338 +
3339 + rtc@51 {
3340 + compatible = "nxp,pcf2129";
3341 + reg = <0x51>;
3342 + /* IRQ10_B */
3343 + interrupts = <0 150 0x4>;
3344 + };
3345 +
3346 + eeprom@56 {
3347 + compatible = "atmel,24c512";
3348 + reg = <0x56>;
3349 + };
3350 +
3351 + eeprom@57 {
3352 + compatible = "atmel,24c512";
3353 + reg = <0x57>;
3354 + };
3355 +
3356 + temp-sensor@4c {
3357 + compatible = "adi,adt7461a";
3358 + reg = <0x4c>;
3359 + };
3360 + };
3361 + };
3362 +};
3363 +
3364 +&ifc {
3365 + #address-cells = <2>;
3366 + #size-cells = <1>;
3367 + /* NOR, NAND Flashes and FPGA on board */
3368 + ranges = <0x0 0x0 0x0 0x60000000 0x08000000
3369 + 0x1 0x0 0x0 0x7e800000 0x00010000
3370 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3371 + status = "okay";
3372 +
3373 + nor@0,0 {
3374 + compatible = "cfi-flash";
3375 + reg = <0x0 0x0 0x8000000>;
3376 + bank-width = <2>;
3377 + device-width = <1>;
3378 + };
3379 +
3380 + nand@1,0 {
3381 + compatible = "fsl,ifc-nand";
3382 + reg = <0x1 0x0 0x10000>;
3383 + };
3384 +
3385 + fpga: board-control@2,0 {
3386 + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
3387 + reg = <0x2 0x0 0x0000100>;
3388 + ranges = <0 2 0 0x100>;
3389 + };
3390 +};
3391 +
3392 +&lpuart0 {
3393 + status = "okay";
3394 +};
3395 +
3396 +&qspi {
3397 + num-cs = <2>;
3398 + bus-num = <0>;
3399 + status = "okay";
3400 +
3401 + qflash0: s25fl128s@0 {
3402 + compatible = "spansion,m25p80";
3403 + #address-cells = <1>;
3404 + #size-cells = <1>;
3405 + spi-max-frequency = <20000000>;
3406 + reg = <0>;
3407 + };
3408 +};
3409 +
3410 +#include "fsl-ls1046-post.dtsi"
3411 +
3412 +&fman0 {
3413 + ethernet@e0000 {
3414 + phy-handle = <&qsgmii_phy_s2_p1>;
3415 + phy-connection-type = "sgmii";
3416 + };
3417 +
3418 + ethernet@e2000 {
3419 + phy-handle = <&sgmii_phy_s4_p1>;
3420 + phy-connection-type = "sgmii";
3421 + };
3422 +
3423 + ethernet@e4000 {
3424 + phy-handle = <&rgmii_phy1>;
3425 + phy-connection-type = "rgmii";
3426 + };
3427 +
3428 + ethernet@e6000 {
3429 + phy-handle = <&rgmii_phy2>;
3430 + phy-connection-type = "rgmii";
3431 + };