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layerscape: refresh patches
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 302-dts-support-layercape.patch
1 From 2b2e3b9a0d2abf276b40843f75d97b623e4ee109 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 10:02:10 +0800
4 Subject: [PATCH] dts: support layercape
5
6 This is a integrated patch for layerscape dts support.
7
8 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 Signed-off-by: Li Yang <leoyang.li@nxp.com>
11 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
12 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
15 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
18 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
19 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
20 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
21 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
22 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
23 Signed-off-by: Meng Yi <meng.yi@nxp.com>
24 Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
25 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
26 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
27 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
28 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
29 ---
30 arch/arm/boot/dts/alpine.dtsi | 2 +-
31 arch/arm/boot/dts/axm55xx.dtsi | 2 +-
32 arch/arm/boot/dts/ecx-2000.dts | 2 +-
33 arch/arm/boot/dts/imx6ul.dtsi | 4 +-
34 arch/arm/boot/dts/keystone.dtsi | 4 +-
35 arch/arm/boot/dts/ls1021a-qds.dts | 13 +
36 arch/arm/boot/dts/ls1021a-twr.dts | 13 +
37 arch/arm/boot/dts/ls1021a.dtsi | 155 ++--
38 arch/arm/boot/dts/mt6580.dtsi | 2 +-
39 arch/arm/boot/dts/mt6589.dtsi | 2 +-
40 arch/arm/boot/dts/mt8127.dtsi | 2 +-
41 arch/arm/boot/dts/mt8135.dtsi | 2 +-
42 arch/arm/boot/dts/rk3288.dtsi | 2 +-
43 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
44 arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
45 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
46 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
47 arch/arm64/boot/dts/freescale/Makefile | 16 +
48 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 134 +++
49 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 155 ++++
50 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 91 +++
51 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 517 ++++++++++++
52 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi | 45 +
53 .../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 69 ++
54 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 171 +++-
55 .../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 69 ++
56 .../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
57 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 113 ++-
58 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 302 ++++++-
59 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi | 48 ++
60 .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 109 +++
61 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 363 ++++++++
62 .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 76 ++
63 .../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
64 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 218 +++++
65 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 793 ++++++++++++++++++
66 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 173 ++++
67 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 236 ++++++
68 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 816 ++++++++++++++++++
69 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 191 ++---
70 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 169 ++--
71 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 9 +-
72 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 763 +++--------------
73 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++
74 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 162 ++++
75 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 140 ++++
76 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 195 +++++
77 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
78 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
79 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 910 +++++++++++++++++++++
80 .../boot/dts/freescale/qoriq-bman1-portals.dtsi | 81 ++
81 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 66 ++
82 .../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
83 .../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
84 .../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
85 .../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 +
86 .../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 +
87 .../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 +
88 .../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 +
89 .../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 +
90 .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++
91 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++
92 .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 104 +++
93 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
94 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
95 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
96 66 files changed, 7778 insertions(+), 1021 deletions(-)
97 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
98 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
99 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
100 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
101 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
102 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
103 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
104 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
105 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
106 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
107 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
108 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
109 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
110 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
111 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
112 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
113 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
114 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
115 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
116 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
117 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
118 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
119 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
120 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
121 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
122 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
123 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
124 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
125 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
126 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
127 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
128 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
129 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
130 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
131 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
132 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
133 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
134 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
135
136 --- a/arch/arm/boot/dts/alpine.dtsi
137 +++ b/arch/arm/boot/dts/alpine.dtsi
138 @@ -93,7 +93,7 @@
139 interrupt-controller;
140 reg = <0x0 0xfb001000 0x0 0x1000>,
141 <0x0 0xfb002000 0x0 0x2000>,
142 - <0x0 0xfb004000 0x0 0x1000>,
143 + <0x0 0xfb004000 0x0 0x2000>,
144 <0x0 0xfb006000 0x0 0x2000>;
145 interrupts =
146 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
147 --- a/arch/arm/boot/dts/axm55xx.dtsi
148 +++ b/arch/arm/boot/dts/axm55xx.dtsi
149 @@ -62,7 +62,7 @@
150 #address-cells = <0>;
151 interrupt-controller;
152 reg = <0x20 0x01001000 0 0x1000>,
153 - <0x20 0x01002000 0 0x1000>,
154 + <0x20 0x01002000 0 0x2000>,
155 <0x20 0x01004000 0 0x2000>,
156 <0x20 0x01006000 0 0x2000>;
157 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
158 --- a/arch/arm/boot/dts/ecx-2000.dts
159 +++ b/arch/arm/boot/dts/ecx-2000.dts
160 @@ -99,7 +99,7 @@
161 interrupt-controller;
162 interrupts = <1 9 0xf04>;
163 reg = <0xfff11000 0x1000>,
164 - <0xfff12000 0x1000>,
165 + <0xfff12000 0x2000>,
166 <0xfff14000 0x2000>,
167 <0xfff16000 0x2000>;
168 };
169 --- a/arch/arm/boot/dts/imx6ul.dtsi
170 +++ b/arch/arm/boot/dts/imx6ul.dtsi
171 @@ -89,11 +89,11 @@
172 };
173
174 intc: interrupt-controller@00a01000 {
175 - compatible = "arm,cortex-a7-gic";
176 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
177 #interrupt-cells = <3>;
178 interrupt-controller;
179 reg = <0x00a01000 0x1000>,
180 - <0x00a02000 0x1000>,
181 + <0x00a02000 0x2000>,
182 <0x00a04000 0x2000>,
183 <0x00a06000 0x2000>;
184 };
185 --- a/arch/arm/boot/dts/keystone.dtsi
186 +++ b/arch/arm/boot/dts/keystone.dtsi
187 @@ -30,12 +30,12 @@
188 };
189
190 gic: interrupt-controller {
191 - compatible = "arm,cortex-a15-gic";
192 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
193 #interrupt-cells = <3>;
194 interrupt-controller;
195 reg = <0x0 0x02561000 0x0 0x1000>,
196 <0x0 0x02562000 0x0 0x2000>,
197 - <0x0 0x02564000 0x0 0x1000>,
198 + <0x0 0x02564000 0x0 0x2000>,
199 <0x0 0x02566000 0x0 0x2000>;
200 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
201 IRQ_TYPE_LEVEL_HIGH)>;
202 --- a/arch/arm/boot/dts/ls1021a-qds.dts
203 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
204 @@ -124,6 +124,19 @@
205 };
206 };
207
208 +&qspi {
209 + num-cs = <2>;
210 + status = "okay";
211 +
212 + qflash0: s25fl128s@0 {
213 + compatible = "spansion,m25p80";
214 + #address-cells = <1>;
215 + #size-cells = <1>;
216 + spi-max-frequency = <20000000>;
217 + reg = <0>;
218 + };
219 +};
220 +
221 &enet0 {
222 tbi-handle = <&tbi0>;
223 phy-handle = <&sgmii_phy1c>;
224 --- a/arch/arm/boot/dts/ls1021a-twr.dts
225 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
226 @@ -142,6 +142,19 @@
227 };
228 };
229
230 +&qspi {
231 + num-cs = <2>;
232 + status = "okay";
233 +
234 + qflash0: n25q128a13@0 {
235 + compatible = "n25q128a13", "jedec,spi-nor";
236 + #address-cells = <1>;
237 + #size-cells = <1>;
238 + spi-max-frequency = <20000000>;
239 + reg = <0>;
240 + };
241 +};
242 +
243 &enet0 {
244 tbi-handle = <&tbi1>;
245 phy-handle = <&sgmii_phy2>;
246 --- a/arch/arm/boot/dts/ls1021a.dtsi
247 +++ b/arch/arm/boot/dts/ls1021a.dtsi
248 @@ -74,17 +74,24 @@
249 compatible = "arm,cortex-a7";
250 device_type = "cpu";
251 reg = <0xf00>;
252 - clocks = <&cluster1_clk>;
253 + clocks = <&clockgen 1 0>;
254 };
255
256 cpu@f01 {
257 compatible = "arm,cortex-a7";
258 device_type = "cpu";
259 reg = <0xf01>;
260 - clocks = <&cluster1_clk>;
261 + clocks = <&clockgen 1 0>;
262 };
263 };
264
265 + sysclk: sysclk {
266 + compatible = "fixed-clock";
267 + #clock-cells = <0>;
268 + clock-frequency = <100000000>;
269 + clock-output-names = "sysclk";
270 + };
271 +
272 timer {
273 compatible = "arm,armv7-timer";
274 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
275 @@ -108,11 +115,11 @@
276 ranges;
277
278 gic: interrupt-controller@1400000 {
279 - compatible = "arm,cortex-a7-gic";
280 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
281 #interrupt-cells = <3>;
282 interrupt-controller;
283 reg = <0x0 0x1401000 0x0 0x1000>,
284 - <0x0 0x1402000 0x0 0x1000>,
285 + <0x0 0x1402000 0x0 0x2000>,
286 <0x0 0x1404000 0x0 0x2000>,
287 <0x0 0x1406000 0x0 0x2000>;
288 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
289 @@ -120,14 +127,14 @@
290 };
291
292 msi1: msi-controller@1570e00 {
293 - compatible = "fsl,1s1021a-msi";
294 + compatible = "fsl,ls1021a-msi";
295 reg = <0x0 0x1570e00 0x0 0x8>;
296 msi-controller;
297 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
298 };
299
300 msi2: msi-controller@1570e08 {
301 - compatible = "fsl,1s1021a-msi";
302 + compatible = "fsl,ls1021a-msi";
303 reg = <0x0 0x1570e08 0x0 0x8>;
304 msi-controller;
305 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
306 @@ -137,11 +144,12 @@
307 compatible = "fsl,ifc", "simple-bus";
308 reg = <0x0 0x1530000 0x0 0x10000>;
309 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
310 + big-endian;
311 };
312
313 dcfg: dcfg@1ee0000 {
314 compatible = "fsl,ls1021a-dcfg", "syscon";
315 - reg = <0x0 0x1ee0000 0x0 0x10000>;
316 + reg = <0x0 0x1ee0000 0x0 0x1000>;
317 big-endian;
318 };
319
320 @@ -163,7 +171,7 @@
321 <0x0 0x20220520 0x0 0x4>;
322 reg-names = "ahci", "sata-ecc";
323 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
324 - clocks = <&platform_clk 1>;
325 + clocks = <&clockgen 4 1>;
326 dma-coherent;
327 status = "disabled";
328 };
329 @@ -214,41 +222,10 @@
330 };
331
332 clockgen: clocking@1ee1000 {
333 - #address-cells = <1>;
334 - #size-cells = <1>;
335 - ranges = <0x0 0x0 0x1ee1000 0x10000>;
336 -
337 - sysclk: sysclk {
338 - compatible = "fixed-clock";
339 - #clock-cells = <0>;
340 - clock-output-names = "sysclk";
341 - };
342 -
343 - cga_pll1: pll@800 {
344 - compatible = "fsl,qoriq-core-pll-2.0";
345 - #clock-cells = <1>;
346 - reg = <0x800 0x10>;
347 - clocks = <&sysclk>;
348 - clock-output-names = "cga-pll1", "cga-pll1-div2",
349 - "cga-pll1-div4";
350 - };
351 -
352 - platform_clk: pll@c00 {
353 - compatible = "fsl,qoriq-core-pll-2.0";
354 - #clock-cells = <1>;
355 - reg = <0xc00 0x10>;
356 - clocks = <&sysclk>;
357 - clock-output-names = "platform-clk", "platform-clk-div2";
358 - };
359 -
360 - cluster1_clk: clk0c0@0 {
361 - compatible = "fsl,qoriq-core-mux-2.0";
362 - #clock-cells = <0>;
363 - reg = <0x0 0x10>;
364 - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
365 - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
366 - clock-output-names = "cluster1-clk";
367 - };
368 + compatible = "fsl,ls1021a-clockgen";
369 + reg = <0x0 0x1ee1000 0x0 0x1000>;
370 + #clock-cells = <2>;
371 + clocks = <&sysclk>;
372 };
373
374 dspi0: dspi@2100000 {
375 @@ -258,7 +235,7 @@
376 reg = <0x0 0x2100000 0x0 0x10000>;
377 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
378 clock-names = "dspi";
379 - clocks = <&platform_clk 1>;
380 + clocks = <&clockgen 4 1>;
381 spi-num-chipselects = <6>;
382 big-endian;
383 status = "disabled";
384 @@ -271,12 +248,27 @@
385 reg = <0x0 0x2110000 0x0 0x10000>;
386 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
387 clock-names = "dspi";
388 - clocks = <&platform_clk 1>;
389 + clocks = <&clockgen 4 1>;
390 spi-num-chipselects = <6>;
391 big-endian;
392 status = "disabled";
393 };
394
395 + qspi: quadspi@1550000 {
396 + compatible = "fsl,ls1021a-qspi";
397 + #address-cells = <1>;
398 + #size-cells = <0>;
399 + reg = <0x0 0x1550000 0x0 0x10000>,
400 + <0x0 0x40000000 0x0 0x4000000>;
401 + reg-names = "QuadSPI", "QuadSPI-memory";
402 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
403 + clock-names = "qspi_en", "qspi";
404 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
405 + big-endian;
406 + amba-base = <0x40000000>;
407 + status = "disabled";
408 + };
409 +
410 i2c0: i2c@2180000 {
411 compatible = "fsl,vf610-i2c";
412 #address-cells = <1>;
413 @@ -284,7 +276,7 @@
414 reg = <0x0 0x2180000 0x0 0x10000>;
415 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
416 clock-names = "i2c";
417 - clocks = <&platform_clk 1>;
418 + clocks = <&clockgen 4 1>;
419 status = "disabled";
420 };
421
422 @@ -295,7 +287,7 @@
423 reg = <0x0 0x2190000 0x0 0x10000>;
424 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
425 clock-names = "i2c";
426 - clocks = <&platform_clk 1>;
427 + clocks = <&clockgen 4 1>;
428 status = "disabled";
429 };
430
431 @@ -306,7 +298,7 @@
432 reg = <0x0 0x21a0000 0x0 0x10000>;
433 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
434 clock-names = "i2c";
435 - clocks = <&platform_clk 1>;
436 + clocks = <&clockgen 4 1>;
437 status = "disabled";
438 };
439
440 @@ -399,7 +391,7 @@
441 compatible = "fsl,ls1021a-lpuart";
442 reg = <0x0 0x2960000 0x0 0x1000>;
443 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
444 - clocks = <&platform_clk 1>;
445 + clocks = <&clockgen 4 1>;
446 clock-names = "ipg";
447 status = "disabled";
448 };
449 @@ -408,7 +400,7 @@
450 compatible = "fsl,ls1021a-lpuart";
451 reg = <0x0 0x2970000 0x0 0x1000>;
452 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
453 - clocks = <&platform_clk 1>;
454 + clocks = <&clockgen 4 1>;
455 clock-names = "ipg";
456 status = "disabled";
457 };
458 @@ -417,7 +409,7 @@
459 compatible = "fsl,ls1021a-lpuart";
460 reg = <0x0 0x2980000 0x0 0x1000>;
461 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
462 - clocks = <&platform_clk 1>;
463 + clocks = <&clockgen 4 1>;
464 clock-names = "ipg";
465 status = "disabled";
466 };
467 @@ -426,7 +418,7 @@
468 compatible = "fsl,ls1021a-lpuart";
469 reg = <0x0 0x2990000 0x0 0x1000>;
470 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
471 - clocks = <&platform_clk 1>;
472 + clocks = <&clockgen 4 1>;
473 clock-names = "ipg";
474 status = "disabled";
475 };
476 @@ -435,16 +427,26 @@
477 compatible = "fsl,ls1021a-lpuart";
478 reg = <0x0 0x29a0000 0x0 0x1000>;
479 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
480 - clocks = <&platform_clk 1>;
481 + clocks = <&clockgen 4 1>;
482 clock-names = "ipg";
483 status = "disabled";
484 };
485
486 + ftm0: ftm0@29d0000 {
487 + compatible = "fsl,ftm-alarm";
488 + reg = <0x0 0x29d0000 0x0 0x10000>,
489 + <0x0 0x1ee2140 0x0 0x4>;
490 + reg-names = "ftm", "FlexTimer1";
491 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
492 + big-endian;
493 + status = "okay";
494 + };
495 +
496 wdog0: watchdog@2ad0000 {
497 compatible = "fsl,imx21-wdt";
498 reg = <0x0 0x2ad0000 0x0 0x10000>;
499 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
500 - clocks = <&platform_clk 1>;
501 + clocks = <&clockgen 4 1>;
502 clock-names = "wdog-en";
503 big-endian;
504 };
505 @@ -454,8 +456,8 @@
506 compatible = "fsl,vf610-sai";
507 reg = <0x0 0x2b50000 0x0 0x10000>;
508 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
509 - clocks = <&platform_clk 1>, <&platform_clk 1>,
510 - <&platform_clk 1>, <&platform_clk 1>;
511 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
512 + <&clockgen 4 1>, <&clockgen 4 1>;
513 clock-names = "bus", "mclk1", "mclk2", "mclk3";
514 dma-names = "tx", "rx";
515 dmas = <&edma0 1 47>,
516 @@ -468,8 +470,8 @@
517 compatible = "fsl,vf610-sai";
518 reg = <0x0 0x2b60000 0x0 0x10000>;
519 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
520 - clocks = <&platform_clk 1>, <&platform_clk 1>,
521 - <&platform_clk 1>, <&platform_clk 1>;
522 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
523 + <&clockgen 4 1>, <&clockgen 4 1>;
524 clock-names = "bus", "mclk1", "mclk2", "mclk3";
525 dma-names = "tx", "rx";
526 dmas = <&edma0 1 45>,
527 @@ -489,16 +491,31 @@
528 dma-channels = <32>;
529 big-endian;
530 clock-names = "dmamux0", "dmamux1";
531 - clocks = <&platform_clk 1>,
532 - <&platform_clk 1>;
533 + clocks = <&clockgen 4 1>,
534 + <&clockgen 4 1>;
535 + };
536 +
537 + qdma: qdma@8390000 {
538 + compatible = "fsl,ls1021a-qdma";
539 + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
540 + <0x0 0x8389000 0x0 0x1000>, /* Status regs */
541 + <0x0 0x838a000 0x0 0x2000>; /* Block regs */
542 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
543 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
544 + interrupt-names = "qdma-error", "qdma-queue";
545 + channels = <8>;
546 + queues = <2>;
547 + status-sizes = <64>;
548 + queue-sizes = <64 64>;
549 + big-endian;
550 };
551
552 dcu: dcu@2ce0000 {
553 compatible = "fsl,ls1021a-dcu";
554 reg = <0x0 0x2ce0000 0x0 0x10000>;
555 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
556 - clocks = <&platform_clk 0>,
557 - <&platform_clk 0>;
558 + clocks = <&clockgen 4 0>,
559 + <&clockgen 4 0>;
560 clock-names = "dcu", "pix";
561 big-endian;
562 status = "disabled";
563 @@ -626,6 +643,8 @@
564 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
565 dr_mode = "host";
566 snps,quirk-frame-length-adjustment = <0x20>;
567 + configure-gfladj;
568 + dma-coherent;
569 snps,dis_rxdet_inp3_quirk;
570 };
571
572 @@ -634,7 +653,9 @@
573 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
574 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
575 reg-names = "regs", "config";
576 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
577 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
578 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
579 + interrupt-names = "pme", "aer";
580 fsl,pcie-scfg = <&scfg 0>;
581 #address-cells = <3>;
582 #size-cells = <2>;
583 @@ -643,7 +664,7 @@
584 bus-range = <0x0 0xff>;
585 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
586 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
587 - msi-parent = <&msi1>;
588 + msi-parent = <&msi1>, <&msi2>;
589 #interrupt-cells = <1>;
590 interrupt-map-mask = <0 0 0 7>;
591 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
592 @@ -657,7 +678,9 @@
593 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
594 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
595 reg-names = "regs", "config";
596 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
597 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
598 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
599 + interrupt-names = "pme", "aer";
600 fsl,pcie-scfg = <&scfg 1>;
601 #address-cells = <3>;
602 #size-cells = <2>;
603 @@ -666,7 +689,7 @@
604 bus-range = <0x0 0xff>;
605 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
606 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
607 - msi-parent = <&msi2>;
608 + msi-parent = <&msi1>, <&msi2>;
609 #interrupt-cells = <1>;
610 interrupt-map-mask = <0 0 0 7>;
611 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
612 --- a/arch/arm/boot/dts/mt6580.dtsi
613 +++ b/arch/arm/boot/dts/mt6580.dtsi
614 @@ -91,7 +91,7 @@
615 #interrupt-cells = <3>;
616 interrupt-parent = <&gic>;
617 reg = <0x10211000 0x1000>,
618 - <0x10212000 0x1000>,
619 + <0x10212000 0x2000>,
620 <0x10214000 0x2000>,
621 <0x10216000 0x2000>;
622 };
623 --- a/arch/arm/boot/dts/mt6589.dtsi
624 +++ b/arch/arm/boot/dts/mt6589.dtsi
625 @@ -102,7 +102,7 @@
626 #interrupt-cells = <3>;
627 interrupt-parent = <&gic>;
628 reg = <0x10211000 0x1000>,
629 - <0x10212000 0x1000>,
630 + <0x10212000 0x2000>,
631 <0x10214000 0x2000>,
632 <0x10216000 0x2000>;
633 };
634 --- a/arch/arm/boot/dts/mt8127.dtsi
635 +++ b/arch/arm/boot/dts/mt8127.dtsi
636 @@ -129,7 +129,7 @@
637 #interrupt-cells = <3>;
638 interrupt-parent = <&gic>;
639 reg = <0 0x10211000 0 0x1000>,
640 - <0 0x10212000 0 0x1000>,
641 + <0 0x10212000 0 0x2000>,
642 <0 0x10214000 0 0x2000>,
643 <0 0x10216000 0 0x2000>;
644 };
645 --- a/arch/arm/boot/dts/mt8135.dtsi
646 +++ b/arch/arm/boot/dts/mt8135.dtsi
647 @@ -221,7 +221,7 @@
648 #interrupt-cells = <3>;
649 interrupt-parent = <&gic>;
650 reg = <0 0x10211000 0 0x1000>,
651 - <0 0x10212000 0 0x1000>,
652 + <0 0x10212000 0 0x2000>,
653 <0 0x10214000 0 0x2000>,
654 <0 0x10216000 0 0x2000>;
655 };
656 --- a/arch/arm/boot/dts/rk3288.dtsi
657 +++ b/arch/arm/boot/dts/rk3288.dtsi
658 @@ -1109,7 +1109,7 @@
659 #address-cells = <0>;
660
661 reg = <0xffc01000 0x1000>,
662 - <0xffc02000 0x1000>,
663 + <0xffc02000 0x2000>,
664 <0xffc04000 0x2000>,
665 <0xffc06000 0x2000>;
666 interrupts = <GIC_PPI 9 0xf04>;
667 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
668 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
669 @@ -791,7 +791,7 @@
670 gic: interrupt-controller@01c81000 {
671 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
672 reg = <0x01c81000 0x1000>,
673 - <0x01c82000 0x1000>,
674 + <0x01c82000 0x2000>,
675 <0x01c84000 0x2000>,
676 <0x01c86000 0x2000>;
677 interrupt-controller;
678 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
679 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
680 @@ -1685,9 +1685,9 @@
681 };
682
683 gic: interrupt-controller@01c81000 {
684 - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
685 + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
686 reg = <0x01c81000 0x1000>,
687 - <0x01c82000 0x1000>,
688 + <0x01c82000 0x2000>,
689 <0x01c84000 0x2000>,
690 <0x01c86000 0x2000>;
691 interrupt-controller;
692 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
693 +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
694 @@ -488,7 +488,7 @@
695 gic: interrupt-controller@01c81000 {
696 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
697 reg = <0x01c81000 0x1000>,
698 - <0x01c82000 0x1000>,
699 + <0x01c82000 0x2000>,
700 <0x01c84000 0x2000>,
701 <0x01c86000 0x2000>;
702 interrupt-controller;
703 --- a/arch/arm/boot/dts/sun9i-a80.dtsi
704 +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
705 @@ -613,7 +613,7 @@
706 gic: interrupt-controller@01c41000 {
707 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
708 reg = <0x01c41000 0x1000>,
709 - <0x01c42000 0x1000>,
710 + <0x01c42000 0x2000>,
711 <0x01c44000 0x2000>,
712 <0x01c46000 0x2000>;
713 interrupt-controller;
714 --- a/arch/arm64/boot/dts/freescale/Makefile
715 +++ b/arch/arm64/boot/dts/freescale/Makefile
716 @@ -1,8 +1,24 @@
717 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
718 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
719 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
720 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
721 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
722 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
723 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
724 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
725 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
726 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
727 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
728 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
729 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
730 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
731 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
732 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
733 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
734 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
735 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
736 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
737 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
738
739 always := $(dtb-y)
740 subdir-y := $(dts-dirs)
741 --- /dev/null
742 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
743 @@ -0,0 +1,134 @@
744 +/*
745 + * Device Tree file for Freescale LS1012A Freedom Board.
746 + *
747 + * Copyright 2016 Freescale Semiconductor, Inc.
748 + *
749 + * This file is dual-licensed: you can use it either under the terms
750 + * of the GPLv2 or the X11 license, at your option. Note that this dual
751 + * licensing only applies to this file, and not this project as a
752 + * whole.
753 + *
754 + * a) This library is free software; you can redistribute it and/or
755 + * modify it under the terms of the GNU General Public License as
756 + * published by the Free Software Foundation; either version 2 of the
757 + * License, or (at your option) any later version.
758 + *
759 + * This library is distributed in the hope that it will be useful,
760 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
761 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
762 + * GNU General Public License for more details.
763 + *
764 + * Or, alternatively,
765 + *
766 + * b) Permission is hereby granted, free of charge, to any person
767 + * obtaining a copy of this software and associated documentation
768 + * files (the "Software"), to deal in the Software without
769 + * restriction, including without limitation the rights to use,
770 + * copy, modify, merge, publish, distribute, sublicense, and/or
771 + * sell copies of the Software, and to permit persons to whom the
772 + * Software is furnished to do so, subject to the following
773 + * conditions:
774 + *
775 + * The above copyright notice and this permission notice shall be
776 + * included in all copies or substantial portions of the Software.
777 + *
778 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
779 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
780 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
781 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
782 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
783 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
784 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
785 + * OTHER DEALINGS IN THE SOFTWARE.
786 + */
787 +/dts-v1/;
788 +
789 +#include "fsl-ls1012a.dtsi"
790 +
791 +/ {
792 + model = "LS1012A Freedom Board";
793 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
794 +
795 + sys_mclk: clock-mclk {
796 + compatible = "fixed-clock";
797 + #clock-cells = <0>;
798 + clock-frequency = <25000000>;
799 + };
800 +
801 + reg_1p8v: regulator-1p8v {
802 + compatible = "regulator-fixed";
803 + regulator-name = "1P8V";
804 + regulator-min-microvolt = <1800000>;
805 + regulator-max-microvolt = <1800000>;
806 + regulator-always-on;
807 + };
808 +
809 + sound {
810 + compatible = "simple-audio-card";
811 + simple-audio-card,format = "i2s";
812 + simple-audio-card,widgets =
813 + "Microphone", "Microphone Jack",
814 + "Headphone", "Headphone Jack",
815 + "Speaker", "Speaker Ext",
816 + "Line", "Line In Jack";
817 + simple-audio-card,routing =
818 + "MIC_IN", "Microphone Jack",
819 + "Microphone Jack", "Mic Bias",
820 + "LINE_IN", "Line In Jack",
821 + "Headphone Jack", "HP_OUT",
822 + "Speaker Ext", "LINE_OUT";
823 +
824 + simple-audio-card,cpu {
825 + sound-dai = <&sai2>;
826 + frame-master;
827 + bitclock-master;
828 + };
829 +
830 + simple-audio-card,codec {
831 + sound-dai = <&codec>;
832 + frame-master;
833 + bitclock-master;
834 + system-clock-frequency = <25000000>;
835 + };
836 + };
837 +};
838 +
839 +&duart0 {
840 + status = "okay";
841 +};
842 +
843 +&i2c0 {
844 + status = "okay";
845 +
846 + codec: sgtl5000@a {
847 + #sound-dai-cells = <0>;
848 + compatible = "fsl,sgtl5000";
849 + reg = <0xa>;
850 + VDDA-supply = <&reg_1p8v>;
851 + VDDIO-supply = <&reg_1p8v>;
852 + clocks = <&sys_mclk>;
853 + };
854 +};
855 +
856 +&qspi {
857 + num-cs = <1>;
858 + bus-num = <0>;
859 + status = "okay";
860 +
861 + qflash0: s25fs512s@0 {
862 + compatible = "spansion,m25p80";
863 + #address-cells = <1>;
864 + #size-cells = <1>;
865 + m25p,fast-read;
866 + spi-max-frequency = <20000000>;
867 + reg = <0>;
868 + };
869 +};
870 +
871 +&sai2 {
872 + status = "okay";
873 +};
874 +
875 +&sata {
876 + status = "okay";
877 +};
878 --- /dev/null
879 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
880 @@ -0,0 +1,155 @@
881 +/*
882 + * Device Tree file for Freescale LS1012A QDS Board.
883 + *
884 + * Copyright 2016 Freescale Semiconductor, Inc.
885 + *
886 + * This file is dual-licensed: you can use it either under the terms
887 + * of the GPLv2 or the X11 license, at your option. Note that this dual
888 + * licensing only applies to this file, and not this project as a
889 + * whole.
890 + *
891 + * a) This library is free software; you can redistribute it and/or
892 + * modify it under the terms of the GNU General Public License as
893 + * published by the Free Software Foundation; either version 2 of the
894 + * License, or (at your option) any later version.
895 + *
896 + * This library is distributed in the hope that it will be useful,
897 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
898 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
899 + * GNU General Public License for more details.
900 + *
901 + * Or, alternatively,
902 + *
903 + * b) Permission is hereby granted, free of charge, to any person
904 + * obtaining a copy of this software and associated documentation
905 + * files (the "Software"), to deal in the Software without
906 + * restriction, including without limitation the rights to use,
907 + * copy, modify, merge, publish, distribute, sublicense, and/or
908 + * sell copies of the Software, and to permit persons to whom the
909 + * Software is furnished to do so, subject to the following
910 + * conditions:
911 + *
912 + * The above copyright notice and this permission notice shall be
913 + * included in all copies or substantial portions of the Software.
914 + *
915 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
916 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
917 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
918 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
919 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
920 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
921 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
922 + * OTHER DEALINGS IN THE SOFTWARE.
923 + */
924 +/dts-v1/;
925 +
926 +#include "fsl-ls1012a.dtsi"
927 +
928 +/ {
929 + model = "LS1012A QDS Board";
930 + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
931 +
932 + sys_mclk: clock-mclk {
933 + compatible = "fixed-clock";
934 + #clock-cells = <0>;
935 + clock-frequency = <24576000>;
936 + };
937 +
938 + reg_3p3v: regulator-3p3v {
939 + compatible = "regulator-fixed";
940 + regulator-name = "3P3V";
941 + regulator-min-microvolt = <3300000>;
942 + regulator-max-microvolt = <3300000>;
943 + regulator-always-on;
944 + };
945 +
946 + sound {
947 + compatible = "simple-audio-card";
948 + simple-audio-card,format = "i2s";
949 + simple-audio-card,widgets =
950 + "Microphone", "Microphone Jack",
951 + "Headphone", "Headphone Jack",
952 + "Speaker", "Speaker Ext",
953 + "Line", "Line In Jack";
954 + simple-audio-card,routing =
955 + "MIC_IN", "Microphone Jack",
956 + "Microphone Jack", "Mic Bias",
957 + "LINE_IN", "Line In Jack",
958 + "Headphone Jack", "HP_OUT",
959 + "Speaker Ext", "LINE_OUT";
960 +
961 + simple-audio-card,cpu {
962 + sound-dai = <&sai2>;
963 + frame-master;
964 + bitclock-master;
965 + };
966 +
967 + simple-audio-card,codec {
968 + sound-dai = <&codec>;
969 + frame-master;
970 + bitclock-master;
971 + system-clock-frequency = <24576000>;
972 + };
973 + };
974 +};
975 +
976 +&duart0 {
977 + status = "okay";
978 +};
979 +
980 +&i2c0 {
981 + status = "okay";
982 +
983 + pca9547@77 {
984 + compatible = "nxp,pca9547";
985 + reg = <0x77>;
986 + #address-cells = <1>;
987 + #size-cells = <0>;
988 +
989 + i2c@4 {
990 + #address-cells = <1>;
991 + #size-cells = <0>;
992 + reg = <0x4>;
993 +
994 + codec: sgtl5000@a {
995 + #sound-dai-cells = <0>;
996 + compatible = "fsl,sgtl5000";
997 + reg = <0xa>;
998 + VDDA-supply = <&reg_3p3v>;
999 + VDDIO-supply = <&reg_3p3v>;
1000 + clocks = <&sys_mclk>;
1001 + };
1002 + };
1003 + };
1004 +};
1005 +
1006 +&qspi {
1007 + num-cs = <2>;
1008 + bus-num = <0>;
1009 + status = "okay";
1010 +
1011 + qflash0: s25fs512s@0 {
1012 + compatible = "spansion,m25p80";
1013 + #address-cells = <1>;
1014 + #size-cells = <1>;
1015 + spi-max-frequency = <20000000>;
1016 + m25p,fast-read;
1017 + reg = <0>;
1018 + };
1019 +};
1020 +
1021 +&sai2 {
1022 + status = "okay";
1023 +};
1024 +
1025 +&sata {
1026 + status = "okay";
1027 +};
1028 +
1029 +&esdhc0 {
1030 + status = "okay";
1031 +};
1032 +
1033 +&esdhc1 {
1034 + status = "okay";
1035 +};
1036 --- /dev/null
1037 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1038 @@ -0,0 +1,91 @@
1039 +/*
1040 + * Device Tree file for Freescale LS1012A RDB Board.
1041 + *
1042 + * Copyright 2016 Freescale Semiconductor, Inc.
1043 + *
1044 + * This file is dual-licensed: you can use it either under the terms
1045 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1046 + * licensing only applies to this file, and not this project as a
1047 + * whole.
1048 + *
1049 + * a) This library is free software; you can redistribute it and/or
1050 + * modify it under the terms of the GNU General Public License as
1051 + * published by the Free Software Foundation; either version 2 of the
1052 + * License, or (at your option) any later version.
1053 + *
1054 + * This library is distributed in the hope that it will be useful,
1055 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1056 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1057 + * GNU General Public License for more details.
1058 + *
1059 + * Or, alternatively,
1060 + *
1061 + * b) Permission is hereby granted, free of charge, to any person
1062 + * obtaining a copy of this software and associated documentation
1063 + * files (the "Software"), to deal in the Software without
1064 + * restriction, including without limitation the rights to use,
1065 + * copy, modify, merge, publish, distribute, sublicense, and/or
1066 + * sell copies of the Software, and to permit persons to whom the
1067 + * Software is furnished to do so, subject to the following
1068 + * conditions:
1069 + *
1070 + * The above copyright notice and this permission notice shall be
1071 + * included in all copies or substantial portions of the Software.
1072 + *
1073 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1074 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1075 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1076 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1077 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1078 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1079 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1080 + * OTHER DEALINGS IN THE SOFTWARE.
1081 + */
1082 +/dts-v1/;
1083 +
1084 +#include "fsl-ls1012a.dtsi"
1085 +
1086 +/ {
1087 + model = "LS1012A RDB Board";
1088 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1089 +};
1090 +
1091 +&duart0 {
1092 + status = "okay";
1093 +};
1094 +
1095 +&i2c0 {
1096 + status = "okay";
1097 +};
1098 +
1099 +&qspi {
1100 + num-cs = <2>;
1101 + bus-num = <0>;
1102 + status = "okay";
1103 +
1104 + qflash0: s25fs512s@0 {
1105 + compatible = "spansion,m25p80";
1106 + #address-cells = <1>;
1107 + #size-cells = <1>;
1108 + spi-max-frequency = <20000000>;
1109 + m25p,fast-read;
1110 + reg = <0>;
1111 + };
1112 +};
1113 +
1114 +&sata {
1115 + status = "okay";
1116 +};
1117 +
1118 +&esdhc0 {
1119 + sd-uhs-sdr104;
1120 + sd-uhs-sdr50;
1121 + sd-uhs-sdr25;
1122 + sd-uhs-sdr12;
1123 + status = "okay";
1124 +};
1125 +
1126 +&esdhc1 {
1127 + mmc-hs200-1_8v;
1128 + status = "okay";
1129 +};
1130 --- /dev/null
1131 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1132 @@ -0,0 +1,517 @@
1133 +/*
1134 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
1135 + *
1136 + * Copyright 2016 Freescale Semiconductor, Inc.
1137 + *
1138 + * This file is dual-licensed: you can use it either under the terms
1139 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1140 + * licensing only applies to this file, and not this project as a
1141 + * whole.
1142 + *
1143 + * a) This library is free software; you can redistribute it and/or
1144 + * modify it under the terms of the GNU General Public License as
1145 + * published by the Free Software Foundation; either version 2 of the
1146 + * License, or (at your option) any later version.
1147 + *
1148 + * This library is distributed in the hope that it will be useful,
1149 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1150 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1151 + * GNU General Public License for more details.
1152 + *
1153 + * Or, alternatively,
1154 + *
1155 + * b) Permission is hereby granted, free of charge, to any person
1156 + * obtaining a copy of this software and associated documentation
1157 + * files (the "Software"), to deal in the Software without
1158 + * restriction, including without limitation the rights to use,
1159 + * copy, modify, merge, publish, distribute, sublicense, and/or
1160 + * sell copies of the Software, and to permit persons to whom the
1161 + * Software is furnished to do so, subject to the following
1162 + * conditions:
1163 + *
1164 + * The above copyright notice and this permission notice shall be
1165 + * included in all copies or substantial portions of the Software.
1166 + *
1167 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1168 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1169 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1170 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1171 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1172 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1173 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1174 + * OTHER DEALINGS IN THE SOFTWARE.
1175 + */
1176 +
1177 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1178 +#include <dt-bindings/thermal/thermal.h>
1179 +
1180 +/ {
1181 + compatible = "fsl,ls1012a";
1182 + interrupt-parent = <&gic>;
1183 + #address-cells = <2>;
1184 + #size-cells = <2>;
1185 +
1186 + aliases {
1187 + crypto = &crypto;
1188 + rtic_a = &rtic_a;
1189 + rtic_b = &rtic_b;
1190 + rtic_c = &rtic_c;
1191 + rtic_d = &rtic_d;
1192 + sec_mon = &sec_mon;
1193 + };
1194 +
1195 + cpus {
1196 + #address-cells = <1>;
1197 + #size-cells = <0>;
1198 +
1199 + cpu0: cpu@0 {
1200 + device_type = "cpu";
1201 + compatible = "arm,cortex-a53";
1202 + reg = <0x0>;
1203 + clocks = <&clockgen 1 0>;
1204 + #cooling-cells = <2>;
1205 + cpu-idle-states = <&CPU_PH20>;
1206 + };
1207 + };
1208 +
1209 + idle-states {
1210 + /*
1211 + * PSCI node is not added default, U-boot will add missing
1212 + * parts if it determines to use PSCI.
1213 + */
1214 + entry-method = "arm,psci";
1215 +
1216 + CPU_PH20: cpu-ph20 {
1217 + compatible = "arm,idle-state";
1218 + idle-state-name = "PH20";
1219 + arm,psci-suspend-param = <0x0>;
1220 + entry-latency-us = <1000>;
1221 + exit-latency-us = <1000>;
1222 + min-residency-us = <3000>;
1223 + };
1224 + };
1225 +
1226 + sysclk: sysclk {
1227 + compatible = "fixed-clock";
1228 + #clock-cells = <0>;
1229 + clock-frequency = <125000000>;
1230 + clock-output-names = "sysclk";
1231 + };
1232 +
1233 + coreclk: coreclk {
1234 + compatible = "fixed-clock";
1235 + #clock-cells = <0>;
1236 + clock-frequency = <100000000>;
1237 + clock-output-names = "coreclk";
1238 + };
1239 +
1240 + timer {
1241 + compatible = "arm,armv8-timer";
1242 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
1243 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
1244 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
1245 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
1246 + };
1247 +
1248 + pmu {
1249 + compatible = "arm,armv8-pmuv3";
1250 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1251 + };
1252 +
1253 + gic: interrupt-controller@1400000 {
1254 + compatible = "arm,gic-400";
1255 + #interrupt-cells = <3>;
1256 + interrupt-controller;
1257 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
1258 + <0x0 0x1402000 0 0x2000>, /* GICC */
1259 + <0x0 0x1404000 0 0x2000>, /* GICH */
1260 + <0x0 0x1406000 0 0x2000>; /* GICV */
1261 + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
1262 + };
1263 +
1264 + reboot {
1265 + compatible = "syscon-reboot";
1266 + regmap = <&dcfg>;
1267 + offset = <0xb0>;
1268 + mask = <0x02>;
1269 + };
1270 +
1271 + soc {
1272 + compatible = "simple-bus";
1273 + #address-cells = <2>;
1274 + #size-cells = <2>;
1275 + ranges;
1276 +
1277 + scfg: scfg@1570000 {
1278 + compatible = "fsl,ls1012a-scfg", "syscon";
1279 + reg = <0x0 0x1570000 0x0 0x10000>;
1280 + big-endian;
1281 + };
1282 +
1283 + crypto: crypto@1700000 {
1284 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
1285 + "fsl,sec-v4.0";
1286 + fsl,sec-era = <8>;
1287 + #address-cells = <1>;
1288 + #size-cells = <1>;
1289 + ranges = <0x0 0x00 0x1700000 0x100000>;
1290 + reg = <0x00 0x1700000 0x0 0x100000>;
1291 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1292 +
1293 + sec_jr0: jr@10000 {
1294 + compatible = "fsl,sec-v5.4-job-ring",
1295 + "fsl,sec-v5.0-job-ring",
1296 + "fsl,sec-v4.0-job-ring";
1297 + reg = <0x10000 0x10000>;
1298 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1299 + };
1300 +
1301 + sec_jr1: jr@20000 {
1302 + compatible = "fsl,sec-v5.4-job-ring",
1303 + "fsl,sec-v5.0-job-ring",
1304 + "fsl,sec-v4.0-job-ring";
1305 + reg = <0x20000 0x10000>;
1306 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1307 + };
1308 +
1309 + sec_jr2: jr@30000 {
1310 + compatible = "fsl,sec-v5.4-job-ring",
1311 + "fsl,sec-v5.0-job-ring",
1312 + "fsl,sec-v4.0-job-ring";
1313 + reg = <0x30000 0x10000>;
1314 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1315 + };
1316 +
1317 + sec_jr3: jr@40000 {
1318 + compatible = "fsl,sec-v5.4-job-ring",
1319 + "fsl,sec-v5.0-job-ring",
1320 + "fsl,sec-v4.0-job-ring";
1321 + reg = <0x40000 0x10000>;
1322 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1323 + };
1324 +
1325 + rtic@60000 {
1326 + compatible = "fsl,sec-v5.4-rtic",
1327 + "fsl,sec-v5.0-rtic",
1328 + "fsl,sec-v4.0-rtic";
1329 + #address-cells = <1>;
1330 + #size-cells = <1>;
1331 + reg = <0x60000 0x100 0x60e00 0x18>;
1332 + ranges = <0x0 0x60100 0x500>;
1333 +
1334 + rtic_a: rtic-a@0 {
1335 + compatible = "fsl,sec-v5.4-rtic-memory",
1336 + "fsl,sec-v5.0-rtic-memory",
1337 + "fsl,sec-v4.0-rtic-memory";
1338 + reg = <0x00 0x20 0x100 0x100>;
1339 + };
1340 +
1341 + rtic_b: rtic-b@20 {
1342 + compatible = "fsl,sec-v5.4-rtic-memory",
1343 + "fsl,sec-v5.0-rtic-memory",
1344 + "fsl,sec-v4.0-rtic-memory";
1345 + reg = <0x20 0x20 0x200 0x100>;
1346 + };
1347 +
1348 + rtic_c: rtic-c@40 {
1349 + compatible = "fsl,sec-v5.4-rtic-memory",
1350 + "fsl,sec-v5.0-rtic-memory",
1351 + "fsl,sec-v4.0-rtic-memory";
1352 + reg = <0x40 0x20 0x300 0x100>;
1353 + };
1354 +
1355 + rtic_d: rtic-d@60 {
1356 + compatible = "fsl,sec-v5.4-rtic-memory",
1357 + "fsl,sec-v5.0-rtic-memory",
1358 + "fsl,sec-v4.0-rtic-memory";
1359 + reg = <0x60 0x20 0x400 0x100>;
1360 + };
1361 + };
1362 + };
1363 +
1364 + sec_mon: sec_mon@1e90000 {
1365 + compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
1366 + "fsl,sec-v4.0-mon";
1367 + reg = <0x0 0x1e90000 0x0 0x10000>;
1368 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
1369 + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1370 + };
1371 +
1372 + dcfg: dcfg@1ee0000 {
1373 + compatible = "fsl,ls1012a-dcfg",
1374 + "syscon";
1375 + reg = <0x0 0x1ee0000 0x0 0x10000>;
1376 + big-endian;
1377 + };
1378 +
1379 + clockgen: clocking@1ee1000 {
1380 + compatible = "fsl,ls1012a-clockgen";
1381 + reg = <0x0 0x1ee1000 0x0 0x1000>;
1382 + #clock-cells = <2>;
1383 + clocks = <&sysclk &coreclk>;
1384 + clock-names = "sysclk", "coreclk";
1385 + };
1386 +
1387 + tmu: tmu@1f00000 {
1388 + compatible = "fsl,qoriq-tmu";
1389 + reg = <0x0 0x1f00000 0x0 0x10000>;
1390 + interrupts = <0 33 0x4>;
1391 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
1392 + fsl,tmu-calibration = <0x00000000 0x00000026
1393 + 0x00000001 0x0000002d
1394 + 0x00000002 0x00000032
1395 + 0x00000003 0x00000039
1396 + 0x00000004 0x0000003f
1397 + 0x00000005 0x00000046
1398 + 0x00000006 0x0000004d
1399 + 0x00000007 0x00000054
1400 + 0x00000008 0x0000005a
1401 + 0x00000009 0x00000061
1402 + 0x0000000a 0x0000006a
1403 + 0x0000000b 0x00000071
1404 +
1405 + 0x00010000 0x00000025
1406 + 0x00010001 0x0000002c
1407 + 0x00010002 0x00000035
1408 + 0x00010003 0x0000003d
1409 + 0x00010004 0x00000045
1410 + 0x00010005 0x0000004e
1411 + 0x00010006 0x00000057
1412 + 0x00010007 0x00000061
1413 + 0x00010008 0x0000006b
1414 + 0x00010009 0x00000076
1415 +
1416 + 0x00020000 0x00000029
1417 + 0x00020001 0x00000033
1418 + 0x00020002 0x0000003d
1419 + 0x00020003 0x00000049
1420 + 0x00020004 0x00000056
1421 + 0x00020005 0x00000061
1422 + 0x00020006 0x0000006d
1423 +
1424 + 0x00030000 0x00000021
1425 + 0x00030001 0x0000002a
1426 + 0x00030002 0x0000003c
1427 + 0x00030003 0x0000004e>;
1428 + big-endian;
1429 + #thermal-sensor-cells = <1>;
1430 + };
1431 +
1432 + thermal-zones {
1433 + cpu_thermal: cpu-thermal {
1434 + polling-delay-passive = <1000>;
1435 + polling-delay = <5000>;
1436 + thermal-sensors = <&tmu 0>;
1437 +
1438 + trips {
1439 + cpu_alert: cpu-alert {
1440 + temperature = <85000>;
1441 + hysteresis = <2000>;
1442 + type = "passive";
1443 + };
1444 +
1445 + cpu_crit: cpu-crit {
1446 + temperature = <95000>;
1447 + hysteresis = <2000>;
1448 + type = "critical";
1449 + };
1450 + };
1451 +
1452 + cooling-maps {
1453 + map0 {
1454 + trip = <&cpu_alert>;
1455 + cooling-device =
1456 + <&cpu0 THERMAL_NO_LIMIT
1457 + THERMAL_NO_LIMIT>;
1458 + };
1459 + };
1460 + };
1461 + };
1462 +
1463 + esdhc0: esdhc@1560000 {
1464 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1465 + reg = <0x0 0x1560000 0x0 0x10000>;
1466 + interrupts = <0 62 0x4>;
1467 + clocks = <&clockgen 4 0>;
1468 + voltage-ranges = <1800 1800 3300 3300>;
1469 + sdhci,auto-cmd12;
1470 + big-endian;
1471 + bus-width = <4>;
1472 + status = "disabled";
1473 + };
1474 +
1475 + esdhc1: esdhc@1580000 {
1476 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1477 + reg = <0x0 0x1580000 0x0 0x10000>;
1478 + interrupts = <0 65 0x4>;
1479 + clocks = <&clockgen 4 0>;
1480 + voltage-ranges = <1800 1800 3300 3300>;
1481 + sdhci,auto-cmd12;
1482 + big-endian;
1483 + broken-cd;
1484 + bus-width = <4>;
1485 + status = "disabled";
1486 + };
1487 +
1488 + ftm0: ftm0@29d0000 {
1489 + compatible = "fsl,ftm-alarm";
1490 + reg = <0x0 0x29d0000 0x0 0x10000>,
1491 + <0x0 0x1ee2140 0x0 0x4>;
1492 + reg-names = "ftm", "FlexTimer1";
1493 + interrupts = <0 86 0x4>;
1494 + big-endian;
1495 + };
1496 +
1497 + i2c0: i2c@2180000 {
1498 + compatible = "fsl,vf610-i2c";
1499 + #address-cells = <1>;
1500 + #size-cells = <0>;
1501 + reg = <0x0 0x2180000 0x0 0x10000>;
1502 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
1503 + clocks = <&clockgen 4 0>;
1504 + status = "disabled";
1505 + };
1506 +
1507 + i2c1: i2c@2190000 {
1508 + compatible = "fsl,vf610-i2c";
1509 + #address-cells = <1>;
1510 + #size-cells = <0>;
1511 + reg = <0x0 0x2190000 0x0 0x10000>;
1512 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
1513 + clocks = <&clockgen 4 0>;
1514 + status = "disabled";
1515 + };
1516 +
1517 + duart0: serial@21c0500 {
1518 + compatible = "fsl,ns16550", "ns16550a";
1519 + reg = <0x00 0x21c0500 0x0 0x100>;
1520 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1521 + clocks = <&clockgen 4 0>;
1522 + status = "disabled";
1523 + };
1524 +
1525 + duart1: serial@21c0600 {
1526 + compatible = "fsl,ns16550", "ns16550a";
1527 + reg = <0x00 0x21c0600 0x0 0x100>;
1528 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1529 + clocks = <&clockgen 4 0>;
1530 + status = "disabled";
1531 + };
1532 +
1533 + gpio0: gpio@2300000 {
1534 + compatible = "fsl,qoriq-gpio";
1535 + reg = <0x0 0x2300000 0x0 0x10000>;
1536 + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
1537 + gpio-controller;
1538 + #gpio-cells = <2>;
1539 + interrupt-controller;
1540 + #interrupt-cells = <2>;
1541 + };
1542 +
1543 + gpio1: gpio@2310000 {
1544 + compatible = "fsl,qoriq-gpio";
1545 + reg = <0x0 0x2310000 0x0 0x10000>;
1546 + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
1547 + gpio-controller;
1548 + #gpio-cells = <2>;
1549 + interrupt-controller;
1550 + #interrupt-cells = <2>;
1551 + };
1552 +
1553 + qspi: quadspi@1550000 {
1554 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
1555 + #address-cells = <1>;
1556 + #size-cells = <0>;
1557 + reg = <0x0 0x1550000 0x0 0x10000>,
1558 + <0x0 0x40000000 0x0 0x10000000>;
1559 + reg-names = "QuadSPI", "QuadSPI-memory";
1560 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1561 + clock-names = "qspi_en", "qspi";
1562 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
1563 + big-endian;
1564 + fsl,qspi-has-second-chip;
1565 + status = "disabled";
1566 + };
1567 +
1568 + wdog0: wdog@2ad0000 {
1569 + compatible = "fsl,ls1012a-wdt",
1570 + "fsl,imx21-wdt";
1571 + reg = <0x0 0x2ad0000 0x0 0x10000>;
1572 + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
1573 + clocks = <&clockgen 4 0>;
1574 + big-endian;
1575 + };
1576 +
1577 + sai1: sai@2b50000 {
1578 + #sound-dai-cells = <0>;
1579 + compatible = "fsl,vf610-sai";
1580 + reg = <0x0 0x2b50000 0x0 0x10000>;
1581 + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
1582 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1583 + <&clockgen 4 3>, <&clockgen 4 3>;
1584 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1585 + dma-names = "tx", "rx";
1586 + dmas = <&edma0 1 47>,
1587 + <&edma0 1 46>;
1588 + status = "disabled";
1589 + };
1590 +
1591 + sai2: sai@2b60000 {
1592 + #sound-dai-cells = <0>;
1593 + compatible = "fsl,vf610-sai";
1594 + reg = <0x0 0x2b60000 0x0 0x10000>;
1595 + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
1596 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1597 + <&clockgen 4 3>, <&clockgen 4 3>;
1598 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1599 + dma-names = "tx", "rx";
1600 + dmas = <&edma0 1 45>,
1601 + <&edma0 1 44>;
1602 + status = "disabled";
1603 + };
1604 +
1605 + edma0: edma@2c00000 {
1606 + #dma-cells = <2>;
1607 + compatible = "fsl,vf610-edma";
1608 + reg = <0x0 0x2c00000 0x0 0x10000>,
1609 + <0x0 0x2c10000 0x0 0x10000>,
1610 + <0x0 0x2c20000 0x0 0x10000>;
1611 + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
1612 + <0 103 IRQ_TYPE_LEVEL_HIGH>;
1613 + interrupt-names = "edma-tx", "edma-err";
1614 + dma-channels = <32>;
1615 + big-endian;
1616 + clock-names = "dmamux0", "dmamux1";
1617 + clocks = <&clockgen 4 3>,
1618 + <&clockgen 4 3>;
1619 + };
1620 +
1621 + usb0: usb3@2f00000 {
1622 + compatible = "snps,dwc3";
1623 + reg = <0x0 0x2f00000 0x0 0x10000>;
1624 + interrupts = <0 60 0x4>;
1625 + dr_mode = "host";
1626 + snps,quirk-frame-length-adjustment = <0x20>;
1627 + snps,dis_rxdet_inp3_quirk;
1628 + };
1629 +
1630 + usb1: usb2@8600000 {
1631 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
1632 + reg = <0x0 0x8600000 0x0 0x1000>;
1633 + interrupts = <0 139 0x4>;
1634 + dr_mode = "host";
1635 + phy_type = "ulpi";
1636 + };
1637 +
1638 + sata: sata@3200000 {
1639 + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
1640 + reg = <0x0 0x3200000 0x0 0x10000>,
1641 + <0x0 0x20140520 0x0 0x4>;
1642 + reg-names = "ahci", "sata-ecc";
1643 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
1644 + clocks = <&clockgen 4 0>;
1645 + dma-coherent;
1646 + status = "disabled";
1647 + };
1648 + };
1649 +};
1650 --- /dev/null
1651 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
1652 @@ -0,0 +1,45 @@
1653 +/*
1654 + * QorIQ FMan v3 device tree nodes for ls1043
1655 + *
1656 + * Copyright 2015-2016 Freescale Semiconductor Inc.
1657 + *
1658 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
1659 + */
1660 +
1661 +&soc {
1662 +
1663 +/* include used FMan blocks */
1664 +#include "qoriq-fman3-0.dtsi"
1665 +#include "qoriq-fman3-0-1g-0.dtsi"
1666 +#include "qoriq-fman3-0-1g-1.dtsi"
1667 +#include "qoriq-fman3-0-1g-2.dtsi"
1668 +#include "qoriq-fman3-0-1g-3.dtsi"
1669 +#include "qoriq-fman3-0-1g-4.dtsi"
1670 +#include "qoriq-fman3-0-1g-5.dtsi"
1671 +#include "qoriq-fman3-0-10g-0.dtsi"
1672 +
1673 +};
1674 +
1675 +&fman0 {
1676 + /* these aliases provide the FMan ports mapping */
1677 + enet0: ethernet@e0000 {
1678 + };
1679 +
1680 + enet1: ethernet@e2000 {
1681 + };
1682 +
1683 + enet2: ethernet@e4000 {
1684 + };
1685 +
1686 + enet3: ethernet@e6000 {
1687 + };
1688 +
1689 + enet4: ethernet@e8000 {
1690 + };
1691 +
1692 + enet5: ethernet@ea000 {
1693 + };
1694 +
1695 + enet6: ethernet@f0000 {
1696 + };
1697 +};
1698 --- /dev/null
1699 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
1700 @@ -0,0 +1,69 @@
1701 +/*
1702 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1703 + *
1704 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1705 + *
1706 + * Mingkai Hu <Mingkai.hu@freescale.com>
1707 + *
1708 + * This file is dual-licensed: you can use it either under the terms
1709 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1710 + * licensing only applies to this file, and not this project as a
1711 + * whole.
1712 + *
1713 + * a) This library is free software; you can redistribute it and/or
1714 + * modify it under the terms of the GNU General Public License as
1715 + * published by the Free Software Foundation; either version 2 of the
1716 + * License, or (at your option) any later version.
1717 + *
1718 + * This library is distributed in the hope that it will be useful,
1719 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1720 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1721 + * GNU General Public License for more details.
1722 + *
1723 + * Or, alternatively,
1724 + *
1725 + * b) Permission is hereby granted, free of charge, to any person
1726 + * obtaining a copy of this software and associated documentation
1727 + * files (the "Software"), to deal in the Software without
1728 + * restriction, including without limitation the rights to use,
1729 + * copy, modify, merge, publish, distribute, sublicense, and/or
1730 + * sell copies of the Software, and to permit persons to whom the
1731 + * Software is furnished to do so, subject to the following
1732 + * conditions:
1733 + *
1734 + * The above copyright notice and this permission notice shall be
1735 + * included in all copies or substantial portions of the Software.
1736 + *
1737 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1738 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1739 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1740 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1741 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1742 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1743 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1744 + * OTHER DEALINGS IN THE SOFTWARE.
1745 + */
1746 +
1747 +#include "fsl-ls1043a-qds.dts"
1748 +
1749 +&bman_fbpr {
1750 + compatible = "fsl,bman-fbpr";
1751 + alloc-ranges = <0 0 0x10000 0>;
1752 +};
1753 +&qman_fqd {
1754 + compatible = "fsl,qman-fqd";
1755 + alloc-ranges = <0 0 0x10000 0>;
1756 +};
1757 +&qman_pfdr {
1758 + compatible = "fsl,qman-pfdr";
1759 + alloc-ranges = <0 0 0x10000 0>;
1760 +};
1761 +
1762 +&soc {
1763 +#include "qoriq-dpaa-eth.dtsi"
1764 +#include "qoriq-fman3-0-6oh.dtsi"
1765 +};
1766 +
1767 +&fman0 {
1768 + compatible = "fsl,fman", "simple-bus";
1769 +};
1770 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
1771 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
1772 @@ -1,7 +1,7 @@
1773 /*
1774 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1775 *
1776 - * Copyright 2014-2015, Freescale Semiconductor
1777 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1778 *
1779 * Mingkai Hu <Mingkai.hu@freescale.com>
1780 *
1781 @@ -45,7 +45,7 @@
1782 */
1783
1784 /dts-v1/;
1785 -/include/ "fsl-ls1043a.dtsi"
1786 +#include "fsl-ls1043a.dtsi"
1787
1788 / {
1789 model = "LS1043A QDS Board";
1790 @@ -60,6 +60,22 @@
1791 serial1 = &duart1;
1792 serial2 = &duart2;
1793 serial3 = &duart3;
1794 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
1795 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
1796 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
1797 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
1798 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
1799 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
1800 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
1801 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
1802 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
1803 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
1804 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
1805 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
1806 + emi1_slot1 = &ls1043mdio_s1;
1807 + emi1_slot2 = &ls1043mdio_s2;
1808 + emi1_slot3 = &ls1043mdio_s3;
1809 + emi1_slot4 = &ls1043mdio_s4;
1810 };
1811
1812 chosen {
1813 @@ -97,8 +113,11 @@
1814 };
1815
1816 fpga: board-control@2,0 {
1817 - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
1818 + #address-cells = <1>;
1819 + #size-cells = <1>;
1820 + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
1821 reg = <0x2 0x0 0x0000100>;
1822 + ranges = <0 2 0 0x100>;
1823 };
1824 };
1825
1826 @@ -181,3 +200,149 @@
1827 reg = <0>;
1828 };
1829 };
1830 +
1831 +#include "fsl-ls1043-post.dtsi"
1832 +
1833 +&fman0 {
1834 + ethernet@e0000 {
1835 + phy-handle = <&qsgmii_phy_s2_p1>;
1836 + phy-connection-type = "sgmii";
1837 + };
1838 +
1839 + ethernet@e2000 {
1840 + phy-handle = <&qsgmii_phy_s2_p2>;
1841 + phy-connection-type = "sgmii";
1842 + };
1843 +
1844 + ethernet@e4000 {
1845 + phy-handle = <&rgmii_phy1>;
1846 + phy-connection-type = "rgmii";
1847 + };
1848 +
1849 + ethernet@e6000 {
1850 + phy-handle = <&rgmii_phy2>;
1851 + phy-connection-type = "rgmii";
1852 + };
1853 +
1854 + ethernet@e8000 {
1855 + phy-handle = <&qsgmii_phy_s2_p3>;
1856 + phy-connection-type = "sgmii";
1857 + };
1858 +
1859 + ethernet@ea000 {
1860 + phy-handle = <&qsgmii_phy_s2_p4>;
1861 + phy-connection-type = "sgmii";
1862 + };
1863 +
1864 + ethernet@f0000 { /* DTSEC9/10GEC1 */
1865 + fixed-link = <1 1 10000 0 0>;
1866 + phy-connection-type = "xgmii";
1867 + };
1868 +};
1869 +
1870 +&fpga {
1871 + mdio-mux-emi1 {
1872 + compatible = "mdio-mux-mmioreg", "mdio-mux";
1873 + mdio-parent-bus = <&mdio0>;
1874 + #address-cells = <1>;
1875 + #size-cells = <0>;
1876 + reg = <0x54 1>; /* BRDCFG4 */
1877 + mux-mask = <0xe0>; /* EMI1 */
1878 +
1879 + /* On-board RGMII1 PHY */
1880 + ls1043mdio0: mdio@0 {
1881 + reg = <0>;
1882 + #address-cells = <1>;
1883 + #size-cells = <0>;
1884 +
1885 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
1886 + reg = <0x1>;
1887 + };
1888 + };
1889 +
1890 + /* On-board RGMII2 PHY */
1891 + ls1043mdio1: mdio@1 {
1892 + reg = <0x20>;
1893 + #address-cells = <1>;
1894 + #size-cells = <0>;
1895 +
1896 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
1897 + reg = <0x2>;
1898 + };
1899 + };
1900 +
1901 + /* Slot 1 */
1902 + ls1043mdio_s1: mdio@2 {
1903 + reg = <0x40>;
1904 + #address-cells = <1>;
1905 + #size-cells = <0>;
1906 + status = "disabled";
1907 +
1908 + qsgmii_phy_s1_p1: ethernet-phy@4 {
1909 + reg = <0x4>;
1910 + };
1911 + qsgmii_phy_s1_p2: ethernet-phy@5 {
1912 + reg = <0x5>;
1913 + };
1914 + qsgmii_phy_s1_p3: ethernet-phy@6 {
1915 + reg = <0x6>;
1916 + };
1917 + qsgmii_phy_s1_p4: ethernet-phy@7 {
1918 + reg = <0x7>;
1919 + };
1920 +
1921 + sgmii_phy_s1_p1: ethernet-phy@1c {
1922 + reg = <0x1c>;
1923 + };
1924 + };
1925 +
1926 + /* Slot 2 */
1927 + ls1043mdio_s2: mdio@3 {
1928 + reg = <0x60>;
1929 + #address-cells = <1>;
1930 + #size-cells = <0>;
1931 + status = "disabled";
1932 +
1933 + qsgmii_phy_s2_p1: ethernet-phy@8 {
1934 + reg = <0x8>;
1935 + };
1936 + qsgmii_phy_s2_p2: ethernet-phy@9 {
1937 + reg = <0x9>;
1938 + };
1939 + qsgmii_phy_s2_p3: ethernet-phy@a {
1940 + reg = <0xa>;
1941 + };
1942 + qsgmii_phy_s2_p4: ethernet-phy@b {
1943 + reg = <0xb>;
1944 + };
1945 +
1946 + sgmii_phy_s2_p1: ethernet-phy@1c {
1947 + reg = <0x1c>;
1948 + };
1949 + };
1950 +
1951 + /* Slot 3 */
1952 + ls1043mdio_s3: mdio@4 {
1953 + reg = <0x80>;
1954 + #address-cells = <1>;
1955 + #size-cells = <0>;
1956 + status = "disabled";
1957 +
1958 + sgmii_phy_s3_p1: ethernet-phy@1c {
1959 + reg = <0x1c>;
1960 + };
1961 + };
1962 +
1963 + /* Slot 4 */
1964 + ls1043mdio_s4: mdio@5 {
1965 + reg = <0xa0>;
1966 + #address-cells = <1>;
1967 + #size-cells = <0>;
1968 + status = "disabled";
1969 +
1970 + sgmii_phy_s4_p1: ethernet-phy@1c {
1971 + reg = <0x1c>;
1972 + };
1973 + };
1974 + };
1975 +};
1976 --- /dev/null
1977 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
1978 @@ -0,0 +1,69 @@
1979 +/*
1980 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1981 + *
1982 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1983 + *
1984 + * Mingkai Hu <Mingkai.hu@freescale.com>
1985 + *
1986 + * This file is dual-licensed: you can use it either under the terms
1987 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1988 + * licensing only applies to this file, and not this project as a
1989 + * whole.
1990 + *
1991 + * a) This library is free software; you can redistribute it and/or
1992 + * modify it under the terms of the GNU General Public License as
1993 + * published by the Free Software Foundation; either version 2 of the
1994 + * License, or (at your option) any later version.
1995 + *
1996 + * This library is distributed in the hope that it will be useful,
1997 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1998 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1999 + * GNU General Public License for more details.
2000 + *
2001 + * Or, alternatively,
2002 + *
2003 + * b) Permission is hereby granted, free of charge, to any person
2004 + * obtaining a copy of this software and associated documentation
2005 + * files (the "Software"), to deal in the Software without
2006 + * restriction, including without limitation the rights to use,
2007 + * copy, modify, merge, publish, distribute, sublicense, and/or
2008 + * sell copies of the Software, and to permit persons to whom the
2009 + * Software is furnished to do so, subject to the following
2010 + * conditions:
2011 + *
2012 + * The above copyright notice and this permission notice shall be
2013 + * included in all copies or substantial portions of the Software.
2014 + *
2015 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2016 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2017 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2018 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2019 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2020 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2021 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2022 + * OTHER DEALINGS IN THE SOFTWARE.
2023 + */
2024 +
2025 +#include "fsl-ls1043a-rdb.dts"
2026 +
2027 +&bman_fbpr {
2028 + compatible = "fsl,bman-fbpr";
2029 + alloc-ranges = <0 0 0x10000 0>;
2030 +};
2031 +&qman_fqd {
2032 + compatible = "fsl,qman-fqd";
2033 + alloc-ranges = <0 0 0x10000 0>;
2034 +};
2035 +&qman_pfdr {
2036 + compatible = "fsl,qman-pfdr";
2037 + alloc-ranges = <0 0 0x10000 0>;
2038 +};
2039 +
2040 +&soc {
2041 +#include "qoriq-dpaa-eth.dtsi"
2042 +#include "qoriq-fman3-0-6oh.dtsi"
2043 +};
2044 +
2045 +&fman0 {
2046 + compatible = "fsl,fman", "simple-bus";
2047 +};
2048 --- /dev/null
2049 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2050 @@ -0,0 +1,117 @@
2051 +/*
2052 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2053 + *
2054 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2055 + *
2056 + * This file is licensed under the terms of the GNU General Public
2057 + * License version 2. This program is licensed "as is" without any
2058 + * warranty of any kind, whether express or implied.
2059 + */
2060 +
2061 +#include "fsl-ls1043a-rdb-sdk.dts"
2062 +
2063 +&soc {
2064 + bp7: buffer-pool@7 {
2065 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2066 + fsl,bpid = <7>;
2067 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
2068 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
2069 + };
2070 +
2071 + bp8: buffer-pool@8 {
2072 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2073 + fsl,bpid = <8>;
2074 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
2075 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2076 + };
2077 +
2078 + bp9: buffer-pool@9 {
2079 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2080 + fsl,bpid = <9>;
2081 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
2082 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2083 + };
2084 +
2085 + fsl,dpaa {
2086 + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
2087 +
2088 + ethernet@0 {
2089 + compatible = "fsl,dpa-ethernet-init";
2090 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2091 + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
2092 + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
2093 + };
2094 +
2095 + ethernet@1 {
2096 + compatible = "fsl,dpa-ethernet-init";
2097 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2098 + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
2099 + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
2100 + };
2101 +
2102 + ethernet@2 {
2103 + compatible = "fsl,dpa-ethernet-init";
2104 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2105 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
2106 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
2107 + };
2108 +
2109 + ethernet@3 {
2110 + compatible = "fsl,dpa-ethernet-init";
2111 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2112 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
2113 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
2114 + };
2115 +
2116 + ethernet@4 {
2117 + compatible = "fsl,dpa-ethernet-init";
2118 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2119 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
2120 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
2121 + };
2122 +
2123 + ethernet@5 {
2124 + compatible = "fsl,dpa-ethernet-init";
2125 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2126 + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
2127 + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
2128 + };
2129 +
2130 + ethernet@8 {
2131 + compatible = "fsl,dpa-ethernet-init";
2132 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2133 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
2134 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
2135 +
2136 + };
2137 + dpa-fman0-oh@2 {
2138 + compatible = "fsl,dpa-oh";
2139 + /* Define frame queues for the OH port*/
2140 + /* <OH Rx error, OH Rx default> */
2141 + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
2142 + fsl,fman-oh-port = <&fman0_oh2>;
2143 + };
2144 + };
2145 +};
2146 +/ {
2147 + reserved-memory {
2148 + #address-cells = <2>;
2149 + #size-cells = <2>;
2150 + ranges;
2151 +
2152 + usdpaa_mem: usdpaa_mem {
2153 + compatible = "fsl,usdpaa-mem";
2154 + alloc-ranges = <0 0 0x10000 0>;
2155 + size = <0 0x10000000>;
2156 + alignment = <0 0x10000000>;
2157 + };
2158 + };
2159 +};
2160 +
2161 +&fman0 {
2162 + fman0_oh2: port@83000 {
2163 + cell-index = <1>;
2164 + compatible = "fsl,fman-port-oh";
2165 + reg = <0x83000 0x1000>;
2166 + };
2167 +};
2168 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2169 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2170 @@ -1,7 +1,7 @@
2171 /*
2172 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2173 *
2174 - * Copyright 2014-2015, Freescale Semiconductor
2175 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2176 *
2177 * Mingkai Hu <Mingkai.hu@freescale.com>
2178 *
2179 @@ -45,7 +45,7 @@
2180 */
2181
2182 /dts-v1/;
2183 -/include/ "fsl-ls1043a.dtsi"
2184 +#include "fsl-ls1043a.dtsi"
2185
2186 / {
2187 model = "LS1043A RDB Board";
2188 @@ -86,6 +86,10 @@
2189 compatible = "pericom,pt7c4338";
2190 reg = <0x68>;
2191 };
2192 + rtc@51 {
2193 + compatible = "nxp,pcf85263";
2194 + reg = <0x51>;
2195 + };
2196 };
2197
2198 &ifc {
2199 @@ -130,6 +134,38 @@
2200 reg = <0>;
2201 spi-max-frequency = <1000000>; /* input clock */
2202 };
2203 +
2204 + slic@2 {
2205 + compatible = "maxim,ds26522";
2206 + reg = <2>;
2207 + spi-max-frequency = <2000000>;
2208 + fsl,spi-cs-sck-delay = <100>;
2209 + fsl,spi-sck-cs-delay = <50>;
2210 + };
2211 +
2212 + slic@3 {
2213 + compatible = "maxim,ds26522";
2214 + reg = <3>;
2215 + spi-max-frequency = <2000000>;
2216 + fsl,spi-cs-sck-delay = <100>;
2217 + fsl,spi-sck-cs-delay = <50>;
2218 + };
2219 +};
2220 +
2221 +&uqe {
2222 + ucc_hdlc: ucc@2000 {
2223 + compatible = "fsl,ucc-hdlc";
2224 + rx-clock-name = "clk8";
2225 + tx-clock-name = "clk9";
2226 + fsl,rx-sync-clock = "rsync_pin";
2227 + fsl,tx-sync-clock = "tsync_pin";
2228 + fsl,tx-timeslot-mask = <0xfffffffe>;
2229 + fsl,rx-timeslot-mask = <0xfffffffe>;
2230 + fsl,tdm-framer-type = "e1";
2231 + fsl,tdm-id = <0>;
2232 + fsl,siram-entry-id = <0>;
2233 + fsl,tdm-interface;
2234 + };
2235 };
2236
2237 &duart0 {
2238 @@ -139,3 +175,76 @@
2239 &duart1 {
2240 status = "okay";
2241 };
2242 +
2243 +#include "fsl-ls1043-post.dtsi"
2244 +
2245 +&fman0 {
2246 + ethernet@e0000 {
2247 + phy-handle = <&qsgmii_phy1>;
2248 + phy-connection-type = "qsgmii";
2249 + };
2250 +
2251 + ethernet@e2000 {
2252 + phy-handle = <&qsgmii_phy2>;
2253 + phy-connection-type = "qsgmii";
2254 + };
2255 +
2256 + ethernet@e4000 {
2257 + phy-handle = <&rgmii_phy1>;
2258 + phy-connection-type = "rgmii-txid";
2259 + };
2260 +
2261 + ethernet@e6000 {
2262 + phy-handle = <&rgmii_phy2>;
2263 + phy-connection-type = "rgmii-txid";
2264 + };
2265 +
2266 + ethernet@e8000 {
2267 + phy-handle = <&qsgmii_phy3>;
2268 + phy-connection-type = "qsgmii";
2269 + };
2270 +
2271 + ethernet@ea000 {
2272 + phy-handle = <&qsgmii_phy4>;
2273 + phy-connection-type = "qsgmii";
2274 + };
2275 +
2276 + ethernet@f0000 { /* 10GEC1 */
2277 + phy-handle = <&aqr105_phy>;
2278 + phy-connection-type = "xgmii";
2279 + };
2280 +
2281 + mdio@fc000 {
2282 + rgmii_phy1: ethernet-phy@1 {
2283 + reg = <0x1>;
2284 + };
2285 +
2286 + rgmii_phy2: ethernet-phy@2 {
2287 + reg = <0x2>;
2288 + };
2289 +
2290 + qsgmii_phy1: ethernet-phy@4 {
2291 + reg = <0x4>;
2292 + };
2293 +
2294 + qsgmii_phy2: ethernet-phy@5 {
2295 + reg = <0x5>;
2296 + };
2297 +
2298 + qsgmii_phy3: ethernet-phy@6 {
2299 + reg = <0x6>;
2300 + };
2301 +
2302 + qsgmii_phy4: ethernet-phy@7 {
2303 + reg = <0x7>;
2304 + };
2305 + };
2306 +
2307 + mdio@fd000 {
2308 + aqr105_phy: ethernet-phy@1 {
2309 + compatible = "ethernet-phy-ieee802.3-c45";
2310 + interrupts = <0 132 4>;
2311 + reg = <0x1>;
2312 + };
2313 + };
2314 +};
2315 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2316 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2317 @@ -1,7 +1,7 @@
2318 /*
2319 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2320 *
2321 - * Copyright 2014-2015, Freescale Semiconductor
2322 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2323 *
2324 * Mingkai Hu <Mingkai.hu@freescale.com>
2325 *
2326 @@ -44,12 +44,25 @@
2327 * OTHER DEALINGS IN THE SOFTWARE.
2328 */
2329
2330 +#include <dt-bindings/thermal/thermal.h>
2331 +
2332 / {
2333 compatible = "fsl,ls1043a";
2334 interrupt-parent = <&gic>;
2335 #address-cells = <2>;
2336 #size-cells = <2>;
2337
2338 + aliases {
2339 + fman0 = &fman0;
2340 + ethernet0 = &enet0;
2341 + ethernet1 = &enet1;
2342 + ethernet2 = &enet2;
2343 + ethernet3 = &enet3;
2344 + ethernet4 = &enet4;
2345 + ethernet5 = &enet5;
2346 + ethernet6 = &enet6;
2347 + };
2348 +
2349 cpus {
2350 #address-cells = <1>;
2351 #size-cells = <0>;
2352 @@ -66,6 +79,8 @@
2353 reg = <0x0>;
2354 clocks = <&clockgen 1 0>;
2355 next-level-cache = <&l2>;
2356 + #cooling-cells = <2>;
2357 + cpu-idle-states = <&CPU_PH20>;
2358 };
2359
2360 cpu1: cpu@1 {
2361 @@ -74,6 +89,7 @@
2362 reg = <0x1>;
2363 clocks = <&clockgen 1 0>;
2364 next-level-cache = <&l2>;
2365 + cpu-idle-states = <&CPU_PH20>;
2366 };
2367
2368 cpu2: cpu@2 {
2369 @@ -82,6 +98,7 @@
2370 reg = <0x2>;
2371 clocks = <&clockgen 1 0>;
2372 next-level-cache = <&l2>;
2373 + cpu-idle-states = <&CPU_PH20>;
2374 };
2375
2376 cpu3: cpu@3 {
2377 @@ -90,6 +107,7 @@
2378 reg = <0x3>;
2379 clocks = <&clockgen 1 0>;
2380 next-level-cache = <&l2>;
2381 + cpu-idle-states = <&CPU_PH20>;
2382 };
2383
2384 l2: l2-cache {
2385 @@ -97,12 +115,56 @@
2386 };
2387 };
2388
2389 + idle-states {
2390 + /*
2391 + * PSCI node is not added default, U-boot will add missing
2392 + * parts if it determines to use PSCI.
2393 + */
2394 + entry-method = "arm,psci";
2395 +
2396 + CPU_PH20: cpu-ph20 {
2397 + compatible = "arm,idle-state";
2398 + idle-state-name = "PH20";
2399 + arm,psci-suspend-param = <0x0>;
2400 + entry-latency-us = <1000>;
2401 + exit-latency-us = <1000>;
2402 + min-residency-us = <3000>;
2403 + };
2404 + };
2405 +
2406 memory@80000000 {
2407 device_type = "memory";
2408 reg = <0x0 0x80000000 0 0x80000000>;
2409 /* DRAM space 1, size: 2GiB DRAM */
2410 };
2411
2412 + reserved-memory {
2413 + #address-cells = <2>;
2414 + #size-cells = <2>;
2415 + ranges;
2416 +
2417 + bman_fbpr: bman-fbpr {
2418 + compatible = "shared-dma-pool";
2419 + size = <0 0x1000000>;
2420 + alignment = <0 0x1000000>;
2421 + no-map;
2422 + };
2423 +
2424 + qman_fqd: qman-fqd {
2425 + compatible = "shared-dma-pool";
2426 + size = <0 0x400000>;
2427 + alignment = <0 0x400000>;
2428 + no-map;
2429 + };
2430 +
2431 + qman_pfdr: qman-pfdr {
2432 + compatible = "shared-dma-pool";
2433 + size = <0 0x2000000>;
2434 + alignment = <0 0x2000000>;
2435 + no-map;
2436 + };
2437 + };
2438 +
2439 sysclk: sysclk {
2440 compatible = "fixed-clock";
2441 #clock-cells = <0>;
2442 @@ -149,7 +211,7 @@
2443 interrupts = <1 9 0xf08>;
2444 };
2445
2446 - soc {
2447 + soc: soc {
2448 compatible = "simple-bus";
2449 #address-cells = <2>;
2450 #size-cells = <2>;
2451 @@ -213,13 +275,14 @@
2452
2453 dcfg: dcfg@1ee0000 {
2454 compatible = "fsl,ls1043a-dcfg", "syscon";
2455 - reg = <0x0 0x1ee0000 0x0 0x10000>;
2456 + reg = <0x0 0x1ee0000 0x0 0x1000>;
2457 big-endian;
2458 };
2459
2460 ifc: ifc@1530000 {
2461 compatible = "fsl,ifc", "simple-bus";
2462 reg = <0x0 0x1530000 0x0 0x10000>;
2463 + big-endian;
2464 interrupts = <0 43 0x4>;
2465 };
2466
2467 @@ -255,6 +318,103 @@
2468 big-endian;
2469 };
2470
2471 + tmu: tmu@1f00000 {
2472 + compatible = "fsl,qoriq-tmu";
2473 + reg = <0x0 0x1f00000 0x0 0x10000>;
2474 + interrupts = <0 33 0x4>;
2475 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
2476 + fsl,tmu-calibration = <0x00000000 0x00000026
2477 + 0x00000001 0x0000002d
2478 + 0x00000002 0x00000032
2479 + 0x00000003 0x00000039
2480 + 0x00000004 0x0000003f
2481 + 0x00000005 0x00000046
2482 + 0x00000006 0x0000004d
2483 + 0x00000007 0x00000054
2484 + 0x00000008 0x0000005a
2485 + 0x00000009 0x00000061
2486 + 0x0000000a 0x0000006a
2487 + 0x0000000b 0x00000071
2488 +
2489 + 0x00010000 0x00000025
2490 + 0x00010001 0x0000002c
2491 + 0x00010002 0x00000035
2492 + 0x00010003 0x0000003d
2493 + 0x00010004 0x00000045
2494 + 0x00010005 0x0000004e
2495 + 0x00010006 0x00000057
2496 + 0x00010007 0x00000061
2497 + 0x00010008 0x0000006b
2498 + 0x00010009 0x00000076
2499 +
2500 + 0x00020000 0x00000029
2501 + 0x00020001 0x00000033
2502 + 0x00020002 0x0000003d
2503 + 0x00020003 0x00000049
2504 + 0x00020004 0x00000056
2505 + 0x00020005 0x00000061
2506 + 0x00020006 0x0000006d
2507 +
2508 + 0x00030000 0x00000021
2509 + 0x00030001 0x0000002a
2510 + 0x00030002 0x0000003c
2511 + 0x00030003 0x0000004e>;
2512 + #thermal-sensor-cells = <1>;
2513 + };
2514 +
2515 + thermal-zones {
2516 + cpu_thermal: cpu-thermal {
2517 + polling-delay-passive = <1000>;
2518 + polling-delay = <5000>;
2519 +
2520 + thermal-sensors = <&tmu 3>;
2521 +
2522 + trips {
2523 + cpu_alert: cpu-alert {
2524 + temperature = <85000>;
2525 + hysteresis = <2000>;
2526 + type = "passive";
2527 + };
2528 + cpu_crit: cpu-crit {
2529 + temperature = <95000>;
2530 + hysteresis = <2000>;
2531 + type = "critical";
2532 + };
2533 + };
2534 +
2535 + cooling-maps {
2536 + map0 {
2537 + trip = <&cpu_alert>;
2538 + cooling-device =
2539 + <&cpu0 THERMAL_NO_LIMIT
2540 + THERMAL_NO_LIMIT>;
2541 + };
2542 + };
2543 + };
2544 + };
2545 +
2546 + qman: qman@1880000 {
2547 + compatible = "fsl,qman";
2548 + reg = <0x00 0x1880000 0x0 0x10000>;
2549 + interrupts = <0 45 0x4>;
2550 + memory-region = <&qman_fqd &qman_pfdr>;
2551 + };
2552 +
2553 + bman: bman@1890000 {
2554 + compatible = "fsl,bman";
2555 + reg = <0x00 0x1890000 0x0 0x10000>;
2556 + interrupts = <0 45 0x4>;
2557 + memory-region = <&bman_fbpr>;
2558 + };
2559 +
2560 + bportals: bman-portals@508000000 {
2561 + ranges = <0x0 0x5 0x08000000 0x8000000>;
2562 + };
2563 +
2564 + qportals: qman-portals@500000000 {
2565 + ranges = <0x0 0x5 0x00000000 0x8000000>;
2566 + };
2567 +
2568 dspi0: dspi@2100000 {
2569 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
2570 #address-cells = <1>;
2571 @@ -396,6 +556,72 @@
2572 #interrupt-cells = <2>;
2573 };
2574
2575 + uqe: uqe@2400000 {
2576 + #address-cells = <1>;
2577 + #size-cells = <1>;
2578 + device_type = "qe";
2579 + compatible = "fsl,qe", "simple-bus";
2580 + ranges = <0x0 0x0 0x2400000 0x40000>;
2581 + reg = <0x0 0x2400000 0x0 0x480>;
2582 + brg-frequency = <100000000>;
2583 + bus-frequency = <200000000>;
2584 +
2585 + fsl,qe-num-riscs = <1>;
2586 + fsl,qe-num-snums = <28>;
2587 +
2588 + qeic: qeic@80 {
2589 + compatible = "fsl,qe-ic";
2590 + reg = <0x80 0x80>;
2591 + #address-cells = <0>;
2592 + interrupt-controller;
2593 + #interrupt-cells = <1>;
2594 + interrupts = <0 77 0x04 0 77 0x04>;
2595 + };
2596 +
2597 + si1: si@700 {
2598 + #address-cells = <1>;
2599 + #size-cells = <0>;
2600 + compatible = "fsl,ls1043-qe-si",
2601 + "fsl,t1040-qe-si";
2602 + reg = <0x700 0x80>;
2603 + };
2604 +
2605 + siram1: siram@1000 {
2606 + #address-cells = <1>;
2607 + #size-cells = <1>;
2608 + compatible = "fsl,ls1043-qe-siram",
2609 + "fsl,t1040-qe-siram";
2610 + reg = <0x1000 0x800>;
2611 + };
2612 +
2613 + ucc@2000 {
2614 + cell-index = <1>;
2615 + reg = <0x2000 0x200>;
2616 + interrupts = <32>;
2617 + interrupt-parent = <&qeic>;
2618 + };
2619 +
2620 + ucc@2200 {
2621 + cell-index = <3>;
2622 + reg = <0x2200 0x200>;
2623 + interrupts = <34>;
2624 + interrupt-parent = <&qeic>;
2625 + };
2626 +
2627 + muram@10000 {
2628 + #address-cells = <1>;
2629 + #size-cells = <1>;
2630 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
2631 + ranges = <0x0 0x10000 0x6000>;
2632 +
2633 + data-only@0 {
2634 + compatible = "fsl,qe-muram-data",
2635 + "fsl,cpm-muram-data";
2636 + reg = <0x0 0x6000>;
2637 + };
2638 + };
2639 + };
2640 +
2641 lpuart0: serial@2950000 {
2642 compatible = "fsl,ls1021a-lpuart";
2643 reg = <0x0 0x2950000 0x0 0x1000>;
2644 @@ -450,6 +676,16 @@
2645 status = "disabled";
2646 };
2647
2648 + ftm0: ftm0@29d0000 {
2649 + compatible = "fsl,ftm-alarm";
2650 + reg = <0x0 0x29d0000 0x0 0x10000>,
2651 + <0x0 0x1ee2140 0x0 0x4>;
2652 + reg-names = "ftm", "FlexTimer1";
2653 + interrupts = <0 86 0x4>;
2654 + big-endian;
2655 + status = "okay";
2656 + };
2657 +
2658 wdog0: wdog@2ad0000 {
2659 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
2660 reg = <0x0 0x2ad0000 0x0 0x10000>;
2661 @@ -482,6 +718,8 @@
2662 dr_mode = "host";
2663 snps,quirk-frame-length-adjustment = <0x20>;
2664 snps,dis_rxdet_inp3_quirk;
2665 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2666 + snps,dma-snooping;
2667 };
2668
2669 usb1: usb3@3000000 {
2670 @@ -491,6 +729,9 @@
2671 dr_mode = "host";
2672 snps,quirk-frame-length-adjustment = <0x20>;
2673 snps,dis_rxdet_inp3_quirk;
2674 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2675 + snps,dma-snooping;
2676 + configure-gfladj;
2677 };
2678
2679 usb2: usb3@3100000 {
2680 @@ -500,32 +741,52 @@
2681 dr_mode = "host";
2682 snps,quirk-frame-length-adjustment = <0x20>;
2683 snps,dis_rxdet_inp3_quirk;
2684 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2685 + snps,dma-snooping;
2686 + configure-gfladj;
2687 };
2688
2689 sata: sata@3200000 {
2690 compatible = "fsl,ls1043a-ahci";
2691 - reg = <0x0 0x3200000 0x0 0x10000>;
2692 + reg = <0x0 0x3200000 0x0 0x10000>,
2693 + <0x0 0x20140520 0x0 0x4>;
2694 + reg-names = "ahci", "sata-ecc";
2695 interrupts = <0 69 0x4>;
2696 clocks = <&clockgen 4 0>;
2697 dma-coherent;
2698 };
2699
2700 + qdma: qdma@8380000 {
2701 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
2702 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
2703 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
2704 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
2705 + interrupts = <0 152 0x4>,
2706 + <0 39 0x4>;
2707 + interrupt-names = "qdma-error", "qdma-queue";
2708 + channels = <8>;
2709 + queues = <2>;
2710 + status-sizes = <64>;
2711 + queue-sizes = <64 64>;
2712 + big-endian;
2713 + };
2714 +
2715 msi1: msi-controller1@1571000 {
2716 - compatible = "fsl,1s1043a-msi";
2717 + compatible = "fsl,ls1043a-msi";
2718 reg = <0x0 0x1571000 0x0 0x8>;
2719 msi-controller;
2720 interrupts = <0 116 0x4>;
2721 };
2722
2723 msi2: msi-controller2@1572000 {
2724 - compatible = "fsl,1s1043a-msi";
2725 + compatible = "fsl,ls1043a-msi";
2726 reg = <0x0 0x1572000 0x0 0x8>;
2727 msi-controller;
2728 interrupts = <0 126 0x4>;
2729 };
2730
2731 msi3: msi-controller3@1573000 {
2732 - compatible = "fsl,1s1043a-msi";
2733 + compatible = "fsl,ls1043a-msi";
2734 reg = <0x0 0x1573000 0x0 0x8>;
2735 msi-controller;
2736 interrupts = <0 160 0x4>;
2737 @@ -536,9 +797,9 @@
2738 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
2739 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
2740 reg-names = "regs", "config";
2741 - interrupts = <0 118 0x4>, /* controller interrupt */
2742 - <0 117 0x4>; /* PME interrupt */
2743 - interrupt-names = "intr", "pme";
2744 + interrupts = <0 117 0x4>, /* PME interrupt */
2745 + <0 118 0x4>; /* aer interrupt */
2746 + interrupt-names = "pme", "aer";
2747 #address-cells = <3>;
2748 #size-cells = <2>;
2749 device_type = "pci";
2750 @@ -547,7 +808,7 @@
2751 bus-range = <0x0 0xff>;
2752 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
2753 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2754 - msi-parent = <&msi1>;
2755 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2756 #interrupt-cells = <1>;
2757 interrupt-map-mask = <0 0 0 7>;
2758 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
2759 @@ -561,9 +822,9 @@
2760 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
2761 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
2762 reg-names = "regs", "config";
2763 - interrupts = <0 128 0x4>,
2764 - <0 127 0x4>;
2765 - interrupt-names = "intr", "pme";
2766 + interrupts = <0 127 0x4>,
2767 + <0 128 0x4>;
2768 + interrupt-names = "pme", "aer";
2769 #address-cells = <3>;
2770 #size-cells = <2>;
2771 device_type = "pci";
2772 @@ -572,7 +833,7 @@
2773 bus-range = <0x0 0xff>;
2774 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
2775 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2776 - msi-parent = <&msi2>;
2777 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2778 #interrupt-cells = <1>;
2779 interrupt-map-mask = <0 0 0 7>;
2780 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
2781 @@ -586,9 +847,9 @@
2782 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
2783 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
2784 reg-names = "regs", "config";
2785 - interrupts = <0 162 0x4>,
2786 - <0 161 0x4>;
2787 - interrupt-names = "intr", "pme";
2788 + interrupts = <0 161 0x4>,
2789 + <0 162 0x4>;
2790 + interrupt-names = "pme", "aer";
2791 #address-cells = <3>;
2792 #size-cells = <2>;
2793 device_type = "pci";
2794 @@ -597,7 +858,7 @@
2795 bus-range = <0x0 0xff>;
2796 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
2797 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2798 - msi-parent = <&msi3>;
2799 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2800 #interrupt-cells = <1>;
2801 interrupt-map-mask = <0 0 0 7>;
2802 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
2803 @@ -608,3 +869,6 @@
2804 };
2805
2806 };
2807 +
2808 +#include "qoriq-qman1-portals.dtsi"
2809 +#include "qoriq-bman1-portals.dtsi"
2810 --- /dev/null
2811 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
2812 @@ -0,0 +1,48 @@
2813 +/*
2814 + * QorIQ FMan v3 device tree nodes for ls1046
2815 + *
2816 + * Copyright 2015-2016 Freescale Semiconductor Inc.
2817 + *
2818 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2819 + */
2820 +
2821 +&soc {
2822 +
2823 +/* include used FMan blocks */
2824 +#include "qoriq-fman3-0.dtsi"
2825 +#include "qoriq-fman3-0-1g-0.dtsi"
2826 +#include "qoriq-fman3-0-1g-1.dtsi"
2827 +#include "qoriq-fman3-0-1g-2.dtsi"
2828 +#include "qoriq-fman3-0-1g-3.dtsi"
2829 +#include "qoriq-fman3-0-1g-4.dtsi"
2830 +#include "qoriq-fman3-0-1g-5.dtsi"
2831 +#include "qoriq-fman3-0-10g-0.dtsi"
2832 +#include "qoriq-fman3-0-10g-1.dtsi"
2833 +};
2834 +
2835 +&fman0 {
2836 + /* these aliases provide the FMan ports mapping */
2837 + enet0: ethernet@e0000 {
2838 + };
2839 +
2840 + enet1: ethernet@e2000 {
2841 + };
2842 +
2843 + enet2: ethernet@e4000 {
2844 + };
2845 +
2846 + enet3: ethernet@e6000 {
2847 + };
2848 +
2849 + enet4: ethernet@e8000 {
2850 + };
2851 +
2852 + enet5: ethernet@ea000 {
2853 + };
2854 +
2855 + enet6: ethernet@f0000 {
2856 + };
2857 +
2858 + enet7: ethernet@f2000 {
2859 + };
2860 +};
2861 --- /dev/null
2862 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
2863 @@ -0,0 +1,109 @@
2864 +/*
2865 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
2866 + *
2867 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2868 + *
2869 + * Mingkai Hu <Mingkai.hu@freescale.com>
2870 + *
2871 + * This file is dual-licensed: you can use it either under the terms
2872 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2873 + * licensing only applies to this file, and not this project as a
2874 + * whole.
2875 + *
2876 + * a) This library is free software; you can redistribute it and/or
2877 + * modify it under the terms of the GNU General Public License as
2878 + * published by the Free Software Foundation; either version 2 of the
2879 + * License, or (at your option) any later version.
2880 + *
2881 + * This library is distributed in the hope that it will be useful,
2882 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2883 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2884 + * GNU General Public License for more details.
2885 + *
2886 + * Or, alternatively,
2887 + *
2888 + * b) Permission is hereby granted, free of charge, to any person
2889 + * obtaining a copy of this software and associated documentation
2890 + * files (the "Software"), to deal in the Software without
2891 + * restriction, including without limitation the rights to use,
2892 + * copy, modify, merge, publish, distribute, sublicense, and/or
2893 + * sell copies of the Software, and to permit persons to whom the
2894 + * Software is furnished to do so, subject to the following
2895 + * conditions:
2896 + *
2897 + * The above copyright notice and this permission notice shall be
2898 + * included in all copies or substantial portions of the Software.
2899 + *
2900 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2901 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2902 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2903 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2904 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2905 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2906 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2907 + * OTHER DEALINGS IN THE SOFTWARE.
2908 + */
2909 +
2910 +#include "fsl-ls1046a-qds.dts"
2911 +
2912 +&bman_fbpr {
2913 + compatible = "fsl,bman-fbpr";
2914 + alloc-ranges = <0 0 0x10000 0>;
2915 +};
2916 +&qman_fqd {
2917 + compatible = "fsl,qman-fqd";
2918 + alloc-ranges = <0 0 0x10000 0>;
2919 +};
2920 +&qman_pfdr {
2921 + compatible = "fsl,qman-pfdr";
2922 + alloc-ranges = <0 0 0x10000 0>;
2923 +};
2924 +
2925 +&soc {
2926 +#include "qoriq-dpaa-eth.dtsi"
2927 +#include "qoriq-fman3-0-6oh.dtsi"
2928 +};
2929 +
2930 +&fsldpaa {
2931 + ethernet@9 {
2932 + compatible = "fsl,dpa-ethernet";
2933 + fsl,fman-mac = <&enet7>;
2934 + };
2935 +};
2936 +
2937 +&fman0 {
2938 + compatible = "fsl,fman", "simple-bus";
2939 +};
2940 +
2941 +&dspi {
2942 + bus-num = <0>;
2943 + status = "okay";
2944 +
2945 + flash@0 {
2946 + #address-cells = <1>;
2947 + #size-cells = <1>;
2948 + compatible = "n25q128a11", "jedec,spi-nor";
2949 + reg = <0>;
2950 + spi-max-frequency = <10000000>;
2951 + };
2952 +
2953 + flash@1 {
2954 + #address-cells = <1>;
2955 + #size-cells = <1>;
2956 + compatible = "sst25wf040b", "jedec,spi-nor";
2957 + spi-cpol;
2958 + spi-cpha;
2959 + reg = <1>;
2960 + spi-max-frequency = <10000000>;
2961 + };
2962 +
2963 + flash@2 {
2964 + #address-cells = <1>;
2965 + #size-cells = <1>;
2966 + compatible = "en25s64", "jedec,spi-nor";
2967 + spi-cpol;
2968 + spi-cpha;
2969 + reg = <2>;
2970 + spi-max-frequency = <10000000>;
2971 + };
2972 +};
2973 --- /dev/null
2974 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
2975 @@ -0,0 +1,363 @@
2976 +/*
2977 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
2978 + *
2979 + * Copyright 2016 Freescale Semiconductor, Inc.
2980 + *
2981 + * Shaohui Xie <Shaohui.Xie@nxp.com>
2982 + *
2983 + * This file is dual-licensed: you can use it either under the terms
2984 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2985 + * licensing only applies to this file, and not this project as a
2986 + * whole.
2987 + *
2988 + * a) This library is free software; you can redistribute it and/or
2989 + * modify it under the terms of the GNU General Public License as
2990 + * published by the Free Software Foundation; either version 2 of the
2991 + * License, or (at your option) any later version.
2992 + *
2993 + * This library is distributed in the hope that it will be useful,
2994 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2995 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2996 + * GNU General Public License for more details.
2997 + *
2998 + * Or, alternatively,
2999 + *
3000 + * b) Permission is hereby granted, free of charge, to any person
3001 + * obtaining a copy of this software and associated documentation
3002 + * files (the "Software"), to deal in the Software without
3003 + * restriction, including without limitation the rights to use,
3004 + * copy, modify, merge, publish, distribute, sublicense, and/or
3005 + * sell copies of the Software, and to permit persons to whom the
3006 + * Software is furnished to do so, subject to the following
3007 + * conditions:
3008 + *
3009 + * The above copyright notice and this permission notice shall be
3010 + * included in all copies or substantial portions of the Software.
3011 + *
3012 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3013 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3014 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3015 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3016 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3017 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3018 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3019 + * OTHER DEALINGS IN THE SOFTWARE.
3020 + */
3021 +
3022 +/dts-v1/;
3023 +
3024 +#include "fsl-ls1046a.dtsi"
3025 +
3026 +/ {
3027 + model = "LS1046A QDS Board";
3028 + compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
3029 +
3030 + aliases {
3031 + gpio0 = &gpio0;
3032 + gpio1 = &gpio1;
3033 + gpio2 = &gpio2;
3034 + gpio3 = &gpio3;
3035 + serial0 = &duart0;
3036 + serial1 = &duart1;
3037 + serial2 = &duart2;
3038 + serial3 = &duart3;
3039 +
3040 + emi1_slot1 = &ls1046mdio_s1;
3041 + emi1_slot2 = &ls1046mdio_s2;
3042 + emi1_slot4 = &ls1046mdio_s4;
3043 +
3044 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
3045 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
3046 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
3047 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
3048 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
3049 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
3050 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
3051 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
3052 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
3053 + };
3054 +
3055 + chosen {
3056 + stdout-path = "serial0:115200n8";
3057 + };
3058 +};
3059 +
3060 +&dspi {
3061 + bus-num = <0>;
3062 + status = "okay";
3063 +
3064 + flash@0 {
3065 + #address-cells = <1>;
3066 + #size-cells = <1>;
3067 + compatible = "n25q128a11", "jedec,spi-nor";
3068 + reg = <0>;
3069 + spi-max-frequency = <10000000>;
3070 + };
3071 +
3072 + flash@1 {
3073 + #address-cells = <1>;
3074 + #size-cells = <1>;
3075 + compatible = "sst25wf040b", "jedec,spi-nor";
3076 + spi-cpol;
3077 + spi-cpha;
3078 + reg = <1>;
3079 + spi-max-frequency = <10000000>;
3080 + };
3081 +
3082 + flash@2 {
3083 + #address-cells = <1>;
3084 + #size-cells = <1>;
3085 + compatible = "en25s64", "jedec,spi-nor";
3086 + spi-cpol;
3087 + spi-cpha;
3088 + reg = <2>;
3089 + spi-max-frequency = <10000000>;
3090 + };
3091 +};
3092 +
3093 +&duart0 {
3094 + status = "okay";
3095 +};
3096 +
3097 +&duart1 {
3098 + status = "okay";
3099 +};
3100 +
3101 +&i2c0 {
3102 + status = "okay";
3103 +
3104 + pca9547@77 {
3105 + compatible = "nxp,pca9547";
3106 + reg = <0x77>;
3107 + #address-cells = <1>;
3108 + #size-cells = <0>;
3109 +
3110 + i2c@2 {
3111 + #address-cells = <1>;
3112 + #size-cells = <0>;
3113 + reg = <0x2>;
3114 +
3115 + ina220@40 {
3116 + compatible = "ti,ina220";
3117 + reg = <0x40>;
3118 + shunt-resistor = <1000>;
3119 + };
3120 +
3121 + ina220@41 {
3122 + compatible = "ti,ina220";
3123 + reg = <0x41>;
3124 + shunt-resistor = <1000>;
3125 + };
3126 + };
3127 +
3128 + i2c@3 {
3129 + #address-cells = <1>;
3130 + #size-cells = <0>;
3131 + reg = <0x3>;
3132 +
3133 + rtc@51 {
3134 + compatible = "nxp,pcf2129";
3135 + reg = <0x51>;
3136 + /* IRQ10_B */
3137 + interrupts = <0 150 0x4>;
3138 + };
3139 +
3140 + eeprom@56 {
3141 + compatible = "atmel,24c512";
3142 + reg = <0x56>;
3143 + };
3144 +
3145 + eeprom@57 {
3146 + compatible = "atmel,24c512";
3147 + reg = <0x57>;
3148 + };
3149 +
3150 + temp-sensor@4c {
3151 + compatible = "adi,adt7461a";
3152 + reg = <0x4c>;
3153 + };
3154 + };
3155 + };
3156 +};
3157 +
3158 +&ifc {
3159 + #address-cells = <2>;
3160 + #size-cells = <1>;
3161 + /* NOR, NAND Flashes and FPGA on board */
3162 + ranges = <0x0 0x0 0x0 0x60000000 0x08000000
3163 + 0x1 0x0 0x0 0x7e800000 0x00010000
3164 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3165 + status = "okay";
3166 +
3167 + nor@0,0 {
3168 + compatible = "cfi-flash";
3169 + reg = <0x0 0x0 0x8000000>;
3170 + bank-width = <2>;
3171 + device-width = <1>;
3172 + };
3173 +
3174 + nand@1,0 {
3175 + compatible = "fsl,ifc-nand";
3176 + reg = <0x1 0x0 0x10000>;
3177 + };
3178 +
3179 + fpga: board-control@2,0 {
3180 + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
3181 + reg = <0x2 0x0 0x0000100>;
3182 + ranges = <0 2 0 0x100>;
3183 + };
3184 +};
3185 +
3186 +&lpuart0 {
3187 + status = "okay";
3188 +};
3189 +
3190 +&qspi {
3191 + num-cs = <2>;
3192 + bus-num = <0>;
3193 + status = "okay";
3194 +
3195 + qflash0: s25fl128s@0 {
3196 + compatible = "spansion,m25p80";
3197 + #address-cells = <1>;
3198 + #size-cells = <1>;
3199 + spi-max-frequency = <20000000>;
3200 + reg = <0>;
3201 + };
3202 +};
3203 +
3204 +#include "fsl-ls1046-post.dtsi"
3205 +
3206 +&fman0 {
3207 + ethernet@e0000 {
3208 + phy-handle = <&qsgmii_phy_s2_p1>;
3209 + phy-connection-type = "sgmii";
3210 + };
3211 +
3212 + ethernet@e2000 {
3213 + phy-handle = <&sgmii_phy_s4_p1>;
3214 + phy-connection-type = "sgmii";
3215 + };
3216 +
3217 + ethernet@e4000 {
3218 + phy-handle = <&rgmii_phy1>;
3219 + phy-connection-type = "rgmii";
3220 + };
3221 +
3222 + ethernet@e6000 {
3223 + phy-handle = <&rgmii_phy2>;
3224 + phy-connection-type = "rgmii";
3225 + };
3226 +
3227 + ethernet@e8000 {
3228 + phy-handle = <&sgmii_phy_s1_p3>;
3229 + phy-connection-type = "sgmii";
3230 + };
3231 +
3232 + ethernet@ea000 {
3233 + phy-handle = <&sgmii_phy_s1_p4>;
3234 + phy-connection-type = "sgmii";
3235 + };
3236 +
3237 + ethernet@f0000 { /* DTSEC9/10GEC1 */
3238 + phy-handle = <&sgmii_phy_s1_p1>;
3239 + phy-connection-type = "xgmii";
3240 + };
3241 +
3242 + ethernet@f2000 { /* DTSEC10/10GEC2 */
3243 + phy-handle = <&sgmii_phy_s1_p2>;
3244 + phy-connection-type = "xgmii";
3245 + };
3246 +};
3247 +
3248 +&fpga {
3249 + #address-cells = <1>;
3250 + #size-cells = <1>;
3251 + mdio-mux-emi1 {
3252 + compatible = "mdio-mux-mmioreg", "mdio-mux";
3253 + mdio-parent-bus = <&mdio0>;
3254 + #address-cells = <1>;
3255 + #size-cells = <0>;
3256 + reg = <0x54 1>; /* BRDCFG4 */
3257 + mux-mask = <0xe0>; /* EMI1 */
3258 +
3259 + /* On-board RGMII1 PHY */
3260 + ls1046mdio0: mdio@0 {
3261 + reg = <0>;
3262 + #address-cells = <1>;
3263 + #size-cells = <0>;
3264 +
3265 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
3266 + reg = <0x1>;
3267 + };
3268 + };
3269 +
3270 + /* On-board RGMII2 PHY */
3271 + ls1046mdio1: mdio@1 {
3272 + reg = <0x20>;
3273 + #address-cells = <1>;
3274 + #size-cells = <0>;
3275 +
3276 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
3277 + reg = <0x2>;
3278 + };
3279 + };
3280 +
3281 + /* Slot 1 */
3282 + ls1046mdio_s1: mdio@2 {
3283 + reg = <0x40>;
3284 + #address-cells = <1>;
3285 + #size-cells = <0>;
3286 + status = "disabled";
3287 +
3288 + sgmii_phy_s1_p1: ethernet-phy@1c {
3289 + reg = <0x1c>;
3290 + };
3291 +
3292 + sgmii_phy_s1_p2: ethernet-phy@1d {
3293 + reg = <0x1d>;
3294 + };
3295 +
3296 + sgmii_phy_s1_p3: ethernet-phy@1e {
3297 + reg = <0x1e>;
3298 + };
3299 +
3300 + sgmii_phy_s1_p4: ethernet-phy@1f {
3301 + reg = <0x1f>;
3302 + };
3303 + };
3304 +
3305 + /* Slot 2 */
3306 + ls1046mdio_s2: mdio@3 {
3307 + reg = <0x60>;
3308 + #address-cells = <1>;
3309 + #size-cells = <0>;
3310 + status = "disabled";
3311 +
3312 + qsgmii_phy_s2_p1: ethernet-phy@8 {
3313 + reg = <0x8>;
3314 + };
3315 + qsgmii_phy_s2_p2: ethernet-phy@9 {
3316 + reg = <0x9>;
3317 + };
3318 + qsgmii_phy_s2_p3: ethernet-phy@a {
3319 + reg = <0xa>;
3320 + };
3321 + qsgmii_phy_s2_p4: ethernet-phy@b {
3322 + reg = <0xb>;
3323 + };
3324 + };
3325 +
3326 + /* Slot 4 */
3327 + ls1046mdio_s4: mdio@5 {
3328 + reg = <0x80>;
3329 + #address-cells = <1>;
3330 + #size-cells = <0>;
3331 + status = "disabled";
3332 +
3333 + sgmii_phy_s4_p1: ethernet-phy@1c {
3334 + reg = <0x1c>;
3335 + };
3336 + };
3337 + };
3338 +};
3339 --- /dev/null
3340 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3341 @@ -0,0 +1,76 @@
3342 +/*
3343 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3344 + *
3345 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3346 + *
3347 + * Mingkai Hu <Mingkai.hu@freescale.com>
3348 + *
3349 + * This file is dual-licensed: you can use it either under the terms
3350 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3351 + * licensing only applies to this file, and not this project as a
3352 + * whole.
3353 + *
3354 + * a) This library is free software; you can redistribute it and/or
3355 + * modify it under the terms of the GNU General Public License as
3356 + * published by the Free Software Foundation; either version 2 of the
3357 + * License, or (at your option) any later version.
3358 + *
3359 + * This library is distributed in the hope that it will be useful,
3360 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3361 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3362 + * GNU General Public License for more details.
3363 + *
3364 + * Or, alternatively,
3365 + *
3366 + * b) Permission is hereby granted, free of charge, to any person
3367 + * obtaining a copy of this software and associated documentation
3368 + * files (the "Software"), to deal in the Software without
3369 + * restriction, including without limitation the rights to use,
3370 + * copy, modify, merge, publish, distribute, sublicense, and/or
3371 + * sell copies of the Software, and to permit persons to whom the
3372 + * Software is furnished to do so, subject to the following
3373 + * conditions:
3374 + *
3375 + * The above copyright notice and this permission notice shall be
3376 + * included in all copies or substantial portions of the Software.
3377 + *
3378 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3379 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3380 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3381 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3382 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3383 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3384 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3385 + * OTHER DEALINGS IN THE SOFTWARE.
3386 + */
3387 +
3388 +#include "fsl-ls1046a-rdb.dts"
3389 +
3390 +&bman_fbpr {
3391 + compatible = "fsl,bman-fbpr";
3392 + alloc-ranges = <0 0 0x10000 0>;
3393 +};
3394 +&qman_fqd {
3395 + compatible = "fsl,qman-fqd";
3396 + alloc-ranges = <0 0 0x10000 0>;
3397 +};
3398 +&qman_pfdr {
3399 + compatible = "fsl,qman-pfdr";
3400 + alloc-ranges = <0 0 0x10000 0>;
3401 +};
3402 +
3403 +&soc {
3404 +#include "qoriq-dpaa-eth.dtsi"
3405 +#include "qoriq-fman3-0-6oh.dtsi"
3406 +};
3407 +
3408 +&fsldpaa {
3409 + ethernet@9 {
3410 + compatible = "fsl,dpa-ethernet";
3411 + fsl,fman-mac = <&enet7>;
3412 + };
3413 +};
3414 +
3415 +&fman0 {
3416 + compatible = "fsl,fman", "simple-bus";
3417 +};
3418 --- /dev/null
3419 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3420 @@ -0,0 +1,110 @@
3421 +/*
3422 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3423 + *
3424 + * Copyright 2016 Freescale Semiconductor, Inc.
3425 + *
3426 + * This file is licensed under the terms of the GNU General Public
3427 + * License version 2. This program is licensed "as is" without any
3428 + * warranty of any kind, whether express or implied.
3429 + */
3430 +
3431 +#include "fsl-ls1046a-rdb-sdk.dts"
3432 +
3433 +&soc {
3434 + bp7: buffer-pool@7 {
3435 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3436 + fsl,bpid = <7>;
3437 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
3438 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
3439 + };
3440 +
3441 + bp8: buffer-pool@8 {
3442 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3443 + fsl,bpid = <8>;
3444 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
3445 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3446 + };
3447 +
3448 + bp9: buffer-pool@9 {
3449 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3450 + fsl,bpid = <9>;
3451 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
3452 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3453 + };
3454 +
3455 + fsl,dpaa {
3456 + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
3457 +
3458 + ethernet@2 {
3459 + compatible = "fsl,dpa-ethernet-init";
3460 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3461 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
3462 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
3463 + };
3464 +
3465 + ethernet@3 {
3466 + compatible = "fsl,dpa-ethernet-init";
3467 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3468 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
3469 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
3470 + };
3471 +
3472 + ethernet@4 {
3473 + compatible = "fsl,dpa-ethernet-init";
3474 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3475 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
3476 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
3477 + };
3478 +
3479 + ethernet@5 {
3480 + compatible = "fsl,dpa-ethernet-init";
3481 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3482 + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
3483 + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
3484 + };
3485 +
3486 + ethernet@8 {
3487 + compatible = "fsl,dpa-ethernet-init";
3488 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3489 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
3490 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
3491 + };
3492 +
3493 + ethernet@9 {
3494 + compatible = "fsl,dpa-ethernet-init";
3495 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3496 + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
3497 + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
3498 + };
3499 +
3500 + dpa-fman0-oh@2 {
3501 + compatible = "fsl,dpa-oh";
3502 + /* Define frame queues for the OH port*/
3503 + /* <OH Rx error, OH Rx default> */
3504 + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
3505 + fsl,fman-oh-port = <&fman0_oh2>;
3506 + };
3507 + };
3508 +};
3509 +/ {
3510 + reserved-memory {
3511 + #address-cells = <2>;
3512 + #size-cells = <2>;
3513 + ranges;
3514 +
3515 + usdpaa_mem: usdpaa_mem {
3516 + compatible = "fsl,usdpaa-mem";
3517 + alloc-ranges = <0 0 0x10000 0>;
3518 + size = <0 0x10000000>;
3519 + alignment = <0 0x10000000>;
3520 + };
3521 + };
3522 +};
3523 +
3524 +&fman0 {
3525 + fman0_oh2: port@83000 {
3526 + cell-index = <1>;
3527 + compatible = "fsl,fman-port-oh";
3528 + reg = <0x83000 0x1000>;
3529 + };
3530 +};
3531 --- /dev/null
3532 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3533 @@ -0,0 +1,218 @@
3534 +/*
3535 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3536 + *
3537 + * Copyright 2016 Freescale Semiconductor, Inc.
3538 + *
3539 + * Mingkai Hu <mingkai.hu@nxp.com>
3540 + *
3541 + * This file is dual-licensed: you can use it either under the terms
3542 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3543 + * licensing only applies to this file, and not this project as a
3544 + * whole.
3545 + *
3546 + * a) This library is free software; you can redistribute it and/or
3547 + * modify it under the terms of the GNU General Public License as
3548 + * published by the Free Software Foundation; either version 2 of the
3549 + * License, or (at your option) any later version.
3550 + *
3551 + * This library is distributed in the hope that it will be useful,
3552 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3553 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3554 + * GNU General Public License for more details.
3555 + *
3556 + * Or, alternatively,
3557 + *
3558 + * b) Permission is hereby granted, free of charge, to any person
3559 + * obtaining a copy of this software and associated documentation
3560 + * files (the "Software"), to deal in the Software without
3561 + * restriction, including without limitation the rights to use,
3562 + * copy, modify, merge, publish, distribute, sublicense, and/or
3563 + * sell copies of the Software, and to permit persons to whom the
3564 + * Software is furnished to do so, subject to the following
3565 + * conditions:
3566 + *
3567 + * The above copyright notice and this permission notice shall be
3568 + * included in all copies or substantial portions of the Software.
3569 + *
3570 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3571 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3572 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3573 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3574 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3575 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3576 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3577 + * OTHER DEALINGS IN THE SOFTWARE.
3578 + */
3579 +
3580 +/dts-v1/;
3581 +
3582 +#include "fsl-ls1046a.dtsi"
3583 +
3584 +/ {
3585 + model = "LS1046A RDB Board";
3586 + compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
3587 +
3588 + aliases {
3589 + serial0 = &duart0;
3590 + serial1 = &duart1;
3591 + serial2 = &duart2;
3592 + serial3 = &duart3;
3593 + };
3594 +
3595 + chosen {
3596 + stdout-path = "serial0:115200n8";
3597 + };
3598 +};
3599 +
3600 +&esdhc {
3601 + mmc-hs200-1_8v;
3602 + sd-uhs-sdr104;
3603 + sd-uhs-sdr50;
3604 + sd-uhs-sdr25;
3605 + sd-uhs-sdr12;
3606 +};
3607 +
3608 +&duart0 {
3609 + status = "okay";
3610 +};
3611 +
3612 +&duart1 {
3613 + status = "okay";
3614 +};
3615 +
3616 +&i2c0 {
3617 + status = "okay";
3618 +
3619 + ina220@40 {
3620 + compatible = "ti,ina220";
3621 + reg = <0x40>;
3622 + shunt-resistor = <1000>;
3623 + };
3624 +
3625 + temp-sensor@4c {
3626 + compatible = "adi,adt7461";
3627 + reg = <0x4c>;
3628 + };
3629 +
3630 + eeprom@56 {
3631 + compatible = "atmel,24c512";
3632 + reg = <0x52>;
3633 + };
3634 +
3635 + eeprom@57 {
3636 + compatible = "atmel,24c512";
3637 + reg = <0x53>;
3638 + };
3639 +};
3640 +
3641 +&i2c3 {
3642 + status = "okay";
3643 +
3644 + rtc@51 {
3645 + compatible = "nxp,pcf2129";
3646 + reg = <0x51>;
3647 + };
3648 +};
3649 +
3650 +&ifc {
3651 + #address-cells = <2>;
3652 + #size-cells = <1>;
3653 + /* NAND Flashe and CPLD on board */
3654 + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
3655 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3656 + status = "okay";
3657 +
3658 + nand@0,0 {
3659 + compatible = "fsl,ifc-nand";
3660 + #address-cells = <1>;
3661 + #size-cells = <1>;
3662 + reg = <0x0 0x0 0x10000>;
3663 + };
3664 +
3665 + cpld: board-control@2,0 {
3666 + compatible = "fsl,ls1046ardb-cpld";
3667 + reg = <0x2 0x0 0x0000100>;
3668 + };
3669 +};
3670 +
3671 +&qspi {
3672 + num-cs = <2>;
3673 + bus-num = <0>;
3674 + status = "okay";
3675 +
3676 + qflash0: s25fs512s@0 {
3677 + compatible = "spansion,m25p80";
3678 + #address-cells = <1>;
3679 + #size-cells = <1>;
3680 + spi-max-frequency = <20000000>;
3681 + reg = <0>;
3682 + };
3683 +
3684 + qflash1: s25fs512s@1 {
3685 + compatible = "spansion,m25p80";
3686 + #address-cells = <1>;
3687 + #size-cells = <1>;
3688 + spi-max-frequency = <20000000>;
3689 + reg = <1>;
3690 + };
3691 +};
3692 +
3693 +#include "fsl-ls1046-post.dtsi"
3694 +
3695 +&fman0 {
3696 + ethernet@e4000 {
3697 + phy-handle = <&rgmii_phy1>;
3698 + phy-connection-type = "rgmii";
3699 + };
3700 +
3701 + ethernet@e6000 {
3702 + phy-handle = <&rgmii_phy2>;
3703 + phy-connection-type = "rgmii";
3704 + };
3705 +
3706 + ethernet@e8000 {
3707 + phy-handle = <&sgmii_phy1>;
3708 + phy-connection-type = "sgmii";
3709 + };
3710 +
3711 + ethernet@ea000 {
3712 + phy-handle = <&sgmii_phy2>;
3713 + phy-connection-type = "sgmii";
3714 + };
3715 +
3716 + ethernet@f0000 { /* 10GEC1 */
3717 + phy-handle = <&aqr106_phy>;
3718 + phy-connection-type = "xgmii";
3719 + };
3720 +
3721 + ethernet@f2000 { /* 10GEC2 */
3722 + fixed-link = <0 1 1000 0 0>;
3723 + phy-connection-type = "xgmii";
3724 + };
3725 +
3726 + mdio@fc000 {
3727 + rgmii_phy1: ethernet-phy@1 {
3728 + reg = <0x1>;
3729 + };
3730 +
3731 + rgmii_phy2: ethernet-phy@2 {
3732 + reg = <0x2>;
3733 + };
3734 +
3735 + sgmii_phy1: ethernet-phy@3 {
3736 + reg = <0x3>;
3737 + };
3738 +
3739 + sgmii_phy2: ethernet-phy@4 {
3740 + reg = <0x4>;
3741 + };
3742 + };
3743 +
3744 + mdio@fd000 {
3745 + aqr106_phy: ethernet-phy@0 {
3746 + compatible = "ethernet-phy-ieee802.3-c45";
3747 + interrupts = <0 131 4>;
3748 + reg = <0x0>;
3749 + };
3750 + };
3751 +};
3752 --- /dev/null
3753 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
3754 @@ -0,0 +1,793 @@
3755 +/*
3756 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3757 + *
3758 + * Copyright 2016 Freescale Semiconductor, Inc.
3759 + *
3760 + * Mingkai Hu <mingkai.hu@nxp.com>
3761 + *
3762 + * This file is dual-licensed: you can use it either under the terms
3763 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3764 + * licensing only applies to this file, and not this project as a
3765 + * whole.
3766 + *
3767 + * a) This library is free software; you can redistribute it and/or
3768 + * modify it under the terms of the GNU General Public License as
3769 + * published by the Free Software Foundation; either version 2 of the
3770 + * License, or (at your option) any later version.
3771 + *
3772 + * This library is distributed in the hope that it will be useful,
3773 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3774 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3775 + * GNU General Public License for more details.
3776 + *
3777 + * Or, alternatively,
3778 + *
3779 + * b) Permission is hereby granted, free of charge, to any person
3780 + * obtaining a copy of this software and associated documentation
3781 + * files (the "Software"), to deal in the Software without
3782 + * restriction, including without limitation the rights to use,
3783 + * copy, modify, merge, publish, distribute, sublicense, and/or
3784 + * sell copies of the Software, and to permit persons to whom the
3785 + * Software is furnished to do so, subject to the following
3786 + * conditions:
3787 + *
3788 + * The above copyright notice and this permission notice shall be
3789 + * included in all copies or substantial portions of the Software.
3790 + *
3791 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3792 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3793 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3794 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3795 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3796 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3797 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3798 + * OTHER DEALINGS IN THE SOFTWARE.
3799 + */
3800 +
3801 +#include <dt-bindings/interrupt-controller/arm-gic.h>
3802 +#include <dt-bindings/thermal/thermal.h>
3803 +
3804 +/ {
3805 + compatible = "fsl,ls1046a";
3806 + interrupt-parent = <&gic>;
3807 + #address-cells = <2>;
3808 + #size-cells = <2>;
3809 +
3810 + aliases {
3811 + crypto = &crypto;
3812 + fman0 = &fman0;
3813 + ethernet0 = &enet0;
3814 + ethernet1 = &enet1;
3815 + ethernet2 = &enet2;
3816 + ethernet3 = &enet3;
3817 + ethernet4 = &enet4;
3818 + ethernet5 = &enet5;
3819 + ethernet6 = &enet6;
3820 + ethernet7 = &enet7;
3821 + };
3822 +
3823 + cpus {
3824 + #address-cells = <1>;
3825 + #size-cells = <0>;
3826 +
3827 + cpu0: cpu@0 {
3828 + device_type = "cpu";
3829 + compatible = "arm,cortex-a72";
3830 + reg = <0x0>;
3831 + clocks = <&clockgen 1 0>;
3832 + next-level-cache = <&l2>;
3833 + cpu-idle-states = <&CPU_PH20>;
3834 + #cooling-cells = <2>;
3835 + };
3836 +
3837 + cpu1: cpu@1 {
3838 + device_type = "cpu";
3839 + compatible = "arm,cortex-a72";
3840 + reg = <0x1>;
3841 + clocks = <&clockgen 1 0>;
3842 + next-level-cache = <&l2>;
3843 + cpu-idle-states = <&CPU_PH20>;
3844 + };
3845 +
3846 + cpu2: cpu@2 {
3847 + device_type = "cpu";
3848 + compatible = "arm,cortex-a72";
3849 + reg = <0x2>;
3850 + clocks = <&clockgen 1 0>;
3851 + next-level-cache = <&l2>;
3852 + cpu-idle-states = <&CPU_PH20>;
3853 + };
3854 +
3855 + cpu3: cpu@3 {
3856 + device_type = "cpu";
3857 + compatible = "arm,cortex-a72";
3858 + reg = <0x3>;
3859 + clocks = <&clockgen 1 0>;
3860 + next-level-cache = <&l2>;
3861 + cpu-idle-states = <&CPU_PH20>;
3862 + };
3863 +
3864 + l2: l2-cache {
3865 + compatible = "cache";
3866 + };
3867 + };
3868 +
3869 + idle-states {
3870 + /*
3871 + * PSCI node is not added default, U-boot will add missing
3872 + * parts if it determines to use PSCI.
3873 + */
3874 + entry-method = "arm,psci";
3875 +
3876 + CPU_PH20: cpu-ph20 {
3877 + compatible = "arm,idle-state";
3878 + idle-state-name = "PH20";
3879 + arm,psci-suspend-param = <0x0>;
3880 + entry-latency-us = <1000>;
3881 + exit-latency-us = <1000>;
3882 + min-residency-us = <3000>;
3883 + };
3884 + };
3885 +
3886 + memory@80000000 {
3887 + device_type = "memory";
3888 + };
3889 +
3890 + sysclk: sysclk {
3891 + compatible = "fixed-clock";
3892 + #clock-cells = <0>;
3893 + clock-frequency = <100000000>;
3894 + clock-output-names = "sysclk";
3895 + };
3896 +
3897 + reboot {
3898 + compatible ="syscon-reboot";
3899 + regmap = <&dcfg>;
3900 + offset = <0xb0>;
3901 + mask = <0x02>;
3902 + };
3903 +
3904 + timer {
3905 + compatible = "arm,armv8-timer";
3906 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
3907 + IRQ_TYPE_LEVEL_LOW)>,
3908 + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
3909 + IRQ_TYPE_LEVEL_LOW)>,
3910 + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
3911 + IRQ_TYPE_LEVEL_LOW)>,
3912 + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
3913 + IRQ_TYPE_LEVEL_LOW)>;
3914 + };
3915 +
3916 + pmu {
3917 + compatible = "arm,cortex-a72-pmu";
3918 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3919 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3920 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3921 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3922 + interrupt-affinity = <&cpu0>,
3923 + <&cpu1>,
3924 + <&cpu2>,
3925 + <&cpu3>;
3926 + };
3927 +
3928 + gic: interrupt-controller@1400000 {
3929 + compatible = "arm,gic-400";
3930 + #interrupt-cells = <3>;
3931 + interrupt-controller;
3932 + reg = <0x0 0x1410000 0 0x10000>, /* GICD */
3933 + <0x0 0x1420000 0 0x20000>, /* GICC */
3934 + <0x0 0x1440000 0 0x20000>, /* GICH */
3935 + <0x0 0x1460000 0 0x20000>; /* GICV */
3936 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
3937 + IRQ_TYPE_LEVEL_LOW)>;
3938 + };
3939 +
3940 + soc: soc {
3941 + compatible = "simple-bus";
3942 + #address-cells = <2>;
3943 + #size-cells = <2>;
3944 + ranges;
3945 +
3946 + ddr: memory-controller@1080000 {
3947 + compatible = "fsl,qoriq-memory-controller";
3948 + reg = <0x0 0x1080000 0x0 0x1000>;
3949 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
3950 + big-endian;
3951 + };
3952 +
3953 + ifc: ifc@1530000 {
3954 + compatible = "fsl,ifc", "simple-bus";
3955 + reg = <0x0 0x1530000 0x0 0x10000>;
3956 + big-endian;
3957 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
3958 + };
3959 +
3960 + qspi: quadspi@1550000 {
3961 + compatible = "fsl,ls1021a-qspi";
3962 + #address-cells = <1>;
3963 + #size-cells = <0>;
3964 + reg = <0x0 0x1550000 0x0 0x10000>,
3965 + <0x0 0x40000000 0x0 0x10000000>;
3966 + reg-names = "QuadSPI", "QuadSPI-memory";
3967 + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
3968 + clock-names = "qspi_en", "qspi";
3969 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
3970 + big-endian;
3971 + fsl,qspi-has-second-chip;
3972 + status = "disabled";
3973 + };
3974 +
3975 + esdhc: esdhc@1560000 {
3976 + compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
3977 + reg = <0x0 0x1560000 0x0 0x10000>;
3978 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
3979 + clocks = <&clockgen 2 1>;
3980 + voltage-ranges = <1800 1800 3300 3300>;
3981 + sdhci,auto-cmd12;
3982 + big-endian;
3983 + bus-width = <4>;
3984 + };
3985 +
3986 + scfg: scfg@1570000 {
3987 + compatible = "fsl,ls1046a-scfg", "syscon";
3988 + reg = <0x0 0x1570000 0x0 0x10000>;
3989 + big-endian;
3990 + };
3991 +
3992 + crypto: crypto@1700000 {
3993 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
3994 + "fsl,sec-v4.0";
3995 + fsl,sec-era = <8>;
3996 + #address-cells = <1>;
3997 + #size-cells = <1>;
3998 + ranges = <0x0 0x00 0x1700000 0x100000>;
3999 + reg = <0x00 0x1700000 0x0 0x100000>;
4000 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4001 +
4002 + sec_jr0: jr@10000 {
4003 + compatible = "fsl,sec-v5.4-job-ring",
4004 + "fsl,sec-v5.0-job-ring",
4005 + "fsl,sec-v4.0-job-ring";
4006 + reg = <0x10000 0x10000>;
4007 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
4008 + };
4009 +
4010 + sec_jr1: jr@20000 {
4011 + compatible = "fsl,sec-v5.4-job-ring",
4012 + "fsl,sec-v5.0-job-ring",
4013 + "fsl,sec-v4.0-job-ring";
4014 + reg = <0x20000 0x10000>;
4015 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4016 + };
4017 +
4018 + sec_jr2: jr@30000 {
4019 + compatible = "fsl,sec-v5.4-job-ring",
4020 + "fsl,sec-v5.0-job-ring",
4021 + "fsl,sec-v4.0-job-ring";
4022 + reg = <0x30000 0x10000>;
4023 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
4024 + };
4025 +
4026 + sec_jr3: jr@40000 {
4027 + compatible = "fsl,sec-v5.4-job-ring",
4028 + "fsl,sec-v5.0-job-ring",
4029 + "fsl,sec-v4.0-job-ring";
4030 + reg = <0x40000 0x10000>;
4031 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
4032 + };
4033 + };
4034 +
4035 + qman: qman@1880000 {
4036 + compatible = "fsl,qman";
4037 + reg = <0x00 0x1880000 0x0 0x10000>;
4038 + interrupts = <0 45 0x4>;
4039 + memory-region = <&qman_fqd &qman_pfdr>;
4040 +
4041 + };
4042 +
4043 + bman: bman@1890000 {
4044 + compatible = "fsl,bman";
4045 + reg = <0x00 0x1890000 0x0 0x10000>;
4046 + interrupts = <0 45 0x4>;
4047 + memory-region = <&bman_fbpr>;
4048 +
4049 + };
4050 +
4051 + qportals: qman-portals@500000000 {
4052 + ranges = <0x0 0x5 0x00000000 0x8000000>;
4053 + };
4054 +
4055 + bportals: bman-portals@508000000 {
4056 + ranges = <0x0 0x5 0x08000000 0x8000000>;
4057 + };
4058 +
4059 + dcfg: dcfg@1ee0000 {
4060 + compatible = "fsl,ls1046a-dcfg", "syscon";
4061 + reg = <0x0 0x1ee0000 0x0 0x1000>;
4062 + big-endian;
4063 + };
4064 +
4065 + clockgen: clocking@1ee1000 {
4066 + compatible = "fsl,ls1046a-clockgen";
4067 + reg = <0x0 0x1ee1000 0x0 0x1000>;
4068 + #clock-cells = <2>;
4069 + clocks = <&sysclk>;
4070 + };
4071 +
4072 + tmu: tmu@1f00000 {
4073 + compatible = "fsl,qoriq-tmu";
4074 + reg = <0x0 0x1f00000 0x0 0x10000>;
4075 + interrupts = <0 33 0x4>;
4076 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
4077 + fsl,tmu-calibration =
4078 + /* Calibration data group 1 */
4079 + <0x00000000 0x00000026
4080 + 0x00000001 0x0000002d
4081 + 0x00000002 0x00000032
4082 + 0x00000003 0x00000039
4083 + 0x00000004 0x0000003f
4084 + 0x00000005 0x00000046
4085 + 0x00000006 0x0000004d
4086 + 0x00000007 0x00000054
4087 + 0x00000008 0x0000005a
4088 + 0x00000009 0x00000061
4089 + 0x0000000a 0x0000006a
4090 + 0x0000000b 0x00000071
4091 + /* Calibration data group 2 */
4092 + 0x00010000 0x00000025
4093 + 0x00010001 0x0000002c
4094 + 0x00010002 0x00000035
4095 + 0x00010003 0x0000003d
4096 + 0x00010004 0x00000045
4097 + 0x00010005 0x0000004e
4098 + 0x00010006 0x00000057
4099 + 0x00010007 0x00000061
4100 + 0x00010008 0x0000006b
4101 + 0x00010009 0x00000076
4102 + /* Calibration data group 3 */
4103 + 0x00020000 0x00000029
4104 + 0x00020001 0x00000033
4105 + 0x00020002 0x0000003d
4106 + 0x00020003 0x00000049
4107 + 0x00020004 0x00000056
4108 + 0x00020005 0x00000061
4109 + 0x00020006 0x0000006d
4110 + /* Calibration data group 4 */
4111 + 0x00030000 0x00000021
4112 + 0x00030001 0x0000002a
4113 + 0x00030002 0x0000003c
4114 + 0x00030003 0x0000004e>;
4115 + big-endian;
4116 + #thermal-sensor-cells = <1>;
4117 + };
4118 +
4119 + thermal-zones {
4120 + cpu_thermal: cpu-thermal {
4121 + polling-delay-passive = <1000>;
4122 + polling-delay = <5000>;
4123 + thermal-sensors = <&tmu 3>;
4124 +
4125 + trips {
4126 + cpu_alert: cpu-alert {
4127 + temperature = <85000>;
4128 + hysteresis = <2000>;
4129 + type = "passive";
4130 + };
4131 +
4132 + cpu_crit: cpu-crit {
4133 + temperature = <95000>;
4134 + hysteresis = <2000>;
4135 + type = "critical";
4136 + };
4137 + };
4138 +
4139 + cooling-maps {
4140 + map0 {
4141 + trip = <&cpu_alert>;
4142 + cooling-device =
4143 + <&cpu0 THERMAL_NO_LIMIT
4144 + THERMAL_NO_LIMIT>;
4145 + };
4146 + };
4147 + };
4148 + };
4149 +
4150 + dspi: dspi@2100000 {
4151 + compatible = "fsl,ls1021a-v1.0-dspi";
4152 + #address-cells = <1>;
4153 + #size-cells = <0>;
4154 + reg = <0x0 0x2100000 0x0 0x10000>;
4155 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
4156 + clock-names = "dspi";
4157 + clocks = <&clockgen 4 1>;
4158 + spi-num-chipselects = <5>;
4159 + big-endian;
4160 + status = "disabled";
4161 + };
4162 +
4163 + i2c0: i2c@2180000 {
4164 + compatible = "fsl,vf610-i2c";
4165 + #address-cells = <1>;
4166 + #size-cells = <0>;
4167 + reg = <0x0 0x2180000 0x0 0x10000>;
4168 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4169 + clocks = <&clockgen 4 1>;
4170 + dmas = <&edma0 1 39>,
4171 + <&edma0 1 38>;
4172 + dma-names = "tx", "rx";
4173 + status = "disabled";
4174 + };
4175 +
4176 + i2c1: i2c@2190000 {
4177 + compatible = "fsl,vf610-i2c";
4178 + #address-cells = <1>;
4179 + #size-cells = <0>;
4180 + reg = <0x0 0x2190000 0x0 0x10000>;
4181 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
4182 + clocks = <&clockgen 4 1>;
4183 + status = "disabled";
4184 + };
4185 +
4186 + i2c2: i2c@21a0000 {
4187 + compatible = "fsl,vf610-i2c";
4188 + #address-cells = <1>;
4189 + #size-cells = <0>;
4190 + reg = <0x0 0x21a0000 0x0 0x10000>;
4191 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
4192 + clocks = <&clockgen 4 1>;
4193 + status = "disabled";
4194 + };
4195 +
4196 + i2c3: i2c@21b0000 {
4197 + compatible = "fsl,vf610-i2c";
4198 + #address-cells = <1>;
4199 + #size-cells = <0>;
4200 + reg = <0x0 0x21b0000 0x0 0x10000>;
4201 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
4202 + clocks = <&clockgen 4 1>;
4203 + status = "disabled";
4204 + };
4205 +
4206 + duart0: serial@21c0500 {
4207 + compatible = "fsl,ns16550", "ns16550a";
4208 + reg = <0x00 0x21c0500 0x0 0x100>;
4209 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4210 + clocks = <&clockgen 4 1>;
4211 + };
4212 +
4213 + duart1: serial@21c0600 {
4214 + compatible = "fsl,ns16550", "ns16550a";
4215 + reg = <0x00 0x21c0600 0x0 0x100>;
4216 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4217 + clocks = <&clockgen 4 1>;
4218 + };
4219 +
4220 + duart2: serial@21d0500 {
4221 + compatible = "fsl,ns16550", "ns16550a";
4222 + reg = <0x0 0x21d0500 0x0 0x100>;
4223 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4224 + clocks = <&clockgen 4 1>;
4225 + };
4226 +
4227 + duart3: serial@21d0600 {
4228 + compatible = "fsl,ns16550", "ns16550a";
4229 + reg = <0x0 0x21d0600 0x0 0x100>;
4230 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4231 + clocks = <&clockgen 4 1>;
4232 + };
4233 +
4234 + gpio0: gpio@2300000 {
4235 + compatible = "fsl,qoriq-gpio";
4236 + reg = <0x0 0x2300000 0x0 0x10000>;
4237 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4238 + gpio-controller;
4239 + #gpio-cells = <2>;
4240 + interrupt-controller;
4241 + #interrupt-cells = <2>;
4242 + };
4243 +
4244 + gpio1: gpio@2310000 {
4245 + compatible = "fsl,qoriq-gpio";
4246 + reg = <0x0 0x2310000 0x0 0x10000>;
4247 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
4248 + gpio-controller;
4249 + #gpio-cells = <2>;
4250 + interrupt-controller;
4251 + #interrupt-cells = <2>;
4252 + };
4253 +
4254 + gpio2: gpio@2320000 {
4255 + compatible = "fsl,qoriq-gpio";
4256 + reg = <0x0 0x2320000 0x0 0x10000>;
4257 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
4258 + gpio-controller;
4259 + #gpio-cells = <2>;
4260 + interrupt-controller;
4261 + #interrupt-cells = <2>;
4262 + };
4263 +
4264 + gpio3: gpio@2330000 {
4265 + compatible = "fsl,qoriq-gpio";
4266 + reg = <0x0 0x2330000 0x0 0x10000>;
4267 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
4268 + gpio-controller;
4269 + #gpio-cells = <2>;
4270 + interrupt-controller;
4271 + #interrupt-cells = <2>;
4272 + };
4273 +
4274 + lpuart0: serial@2950000 {
4275 + compatible = "fsl,ls1021a-lpuart";
4276 + reg = <0x0 0x2950000 0x0 0x1000>;
4277 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
4278 + clocks = <&clockgen 4 0>;
4279 + clock-names = "ipg";
4280 + status = "disabled";
4281 + };
4282 +
4283 + lpuart1: serial@2960000 {
4284 + compatible = "fsl,ls1021a-lpuart";
4285 + reg = <0x0 0x2960000 0x0 0x1000>;
4286 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4287 + clocks = <&clockgen 4 1>;
4288 + clock-names = "ipg";
4289 + status = "disabled";
4290 + };
4291 +
4292 + lpuart2: serial@2970000 {
4293 + compatible = "fsl,ls1021a-lpuart";
4294 + reg = <0x0 0x2970000 0x0 0x1000>;
4295 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
4296 + clocks = <&clockgen 4 1>;
4297 + clock-names = "ipg";
4298 + status = "disabled";
4299 + };
4300 +
4301 + lpuart3: serial@2980000 {
4302 + compatible = "fsl,ls1021a-lpuart";
4303 + reg = <0x0 0x2980000 0x0 0x1000>;
4304 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4305 + clocks = <&clockgen 4 1>;
4306 + clock-names = "ipg";
4307 + status = "disabled";
4308 + };
4309 +
4310 + lpuart4: serial@2990000 {
4311 + compatible = "fsl,ls1021a-lpuart";
4312 + reg = <0x0 0x2990000 0x0 0x1000>;
4313 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
4314 + clocks = <&clockgen 4 1>;
4315 + clock-names = "ipg";
4316 + status = "disabled";
4317 + };
4318 +
4319 + lpuart5: serial@29a0000 {
4320 + compatible = "fsl,ls1021a-lpuart";
4321 + reg = <0x0 0x29a0000 0x0 0x1000>;
4322 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4323 + clocks = <&clockgen 4 1>;
4324 + clock-names = "ipg";
4325 + status = "disabled";
4326 + };
4327 +
4328 + ftm0: ftm0@29d0000 {
4329 + compatible = "fsl,ftm-alarm";
4330 + reg = <0x0 0x29d0000 0x0 0x10000>,
4331 + <0x0 0x1ee2140 0x0 0x4>;
4332 + reg-names = "ftm", "FlexTimer1";
4333 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
4334 + big-endian;
4335 + };
4336 +
4337 + wdog0: watchdog@2ad0000 {
4338 + compatible = "fsl,imx21-wdt";
4339 + reg = <0x0 0x2ad0000 0x0 0x10000>;
4340 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4341 + clocks = <&clockgen 4 1>;
4342 + big-endian;
4343 + };
4344 +
4345 + edma0: edma@2c00000 {
4346 + #dma-cells = <2>;
4347 + compatible = "fsl,vf610-edma";
4348 + reg = <0x0 0x2c00000 0x0 0x10000>,
4349 + <0x0 0x2c10000 0x0 0x10000>,
4350 + <0x0 0x2c20000 0x0 0x10000>;
4351 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4352 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
4353 + interrupt-names = "edma-tx", "edma-err";
4354 + dma-channels = <32>;
4355 + big-endian;
4356 + clock-names = "dmamux0", "dmamux1";
4357 + clocks = <&clockgen 4 1>,
4358 + <&clockgen 4 1>;
4359 + };
4360 +
4361 + usb0: usb@2f00000 {
4362 + compatible = "snps,dwc3";
4363 + reg = <0x0 0x2f00000 0x0 0x10000>;
4364 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
4365 + dr_mode = "host";
4366 + snps,quirk-frame-length-adjustment = <0x20>;
4367 + snps,dis_rxdet_inp3_quirk;
4368 + };
4369 +
4370 + usb1: usb@3000000 {
4371 + compatible = "snps,dwc3";
4372 + reg = <0x0 0x3000000 0x0 0x10000>;
4373 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
4374 + dr_mode = "host";
4375 + snps,quirk-frame-length-adjustment = <0x20>;
4376 + snps,dis_rxdet_inp3_quirk;
4377 + };
4378 +
4379 + usb2: usb@3100000 {
4380 + compatible = "snps,dwc3";
4381 + reg = <0x0 0x3100000 0x0 0x10000>;
4382 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
4383 + dr_mode = "host";
4384 + snps,quirk-frame-length-adjustment = <0x20>;
4385 + snps,dis_rxdet_inp3_quirk;
4386 + };
4387 +
4388 + sata: sata@3200000 {
4389 + compatible = "fsl,ls1046a-ahci";
4390 + reg = <0x0 0x3200000 0x0 0x10000>,
4391 + <0x0 0x20140520 0x0 0x4>;
4392 + reg-names = "ahci", "sata-ecc";
4393 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
4394 + clocks = <&clockgen 4 1>;
4395 + dma-coherent;
4396 + };
4397 +
4398 + qdma: qdma@8380000 {
4399 + compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
4400 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
4401 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
4402 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
4403 + interrupts = <0 153 0x4>,
4404 + <0 39 0x4>;
4405 + interrupt-names = "qdma-error", "qdma-queue";
4406 + channels = <8>;
4407 + queues = <2>;
4408 + status-sizes = <64>;
4409 + queue-sizes = <64 64>;
4410 + big-endian;
4411 + };
4412 +
4413 + msi1: msi-controller@1580000 {
4414 + compatible = "fsl,ls1046a-msi";
4415 + msi-controller;
4416 + reg = <0x0 0x1580000 0x0 0x10000>;
4417 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4418 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4419 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4420 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
4421 + };
4422 +
4423 + msi2: msi-controller@1590000 {
4424 + compatible = "fsl,ls1046a-msi";
4425 + msi-controller;
4426 + reg = <0x0 0x1590000 0x0 0x10000>;
4427 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
4428 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
4429 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
4430 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
4431 + };
4432 +
4433 + msi3: msi-controller@15a0000 {
4434 + compatible = "fsl,ls1046a-msi";
4435 + msi-controller;
4436 + reg = <0x0 0x15a0000 0x0 0x10000>;
4437 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4438 + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
4439 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
4440 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
4441 + };
4442 +
4443 + pcie@3400000 {
4444 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4445 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
4446 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
4447 + reg-names = "regs", "config";
4448 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
4449 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
4450 + interrupt-names = "pme", "aer";
4451 + #address-cells = <3>;
4452 + #size-cells = <2>;
4453 + device_type = "pci";
4454 + dma-coherent;
4455 + num-lanes = <4>;
4456 + bus-range = <0x0 0xff>;
4457 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
4458 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4459 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4460 + #interrupt-cells = <1>;
4461 + interrupt-map-mask = <0 0 0 7>;
4462 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4463 + <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4464 + <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4465 + <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
4466 + };
4467 +
4468 + pcie@3500000 {
4469 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4470 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
4471 + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
4472 + reg-names = "regs", "config";
4473 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
4474 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
4475 + interrupt-names = "pme", "aer";
4476 + #address-cells = <3>;
4477 + #size-cells = <2>;
4478 + device_type = "pci";
4479 + dma-coherent;
4480 + num-lanes = <2>;
4481 + bus-range = <0x0 0xff>;
4482 + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
4483 + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4484 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4485 + #interrupt-cells = <1>;
4486 + interrupt-map-mask = <0 0 0 7>;
4487 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4488 + <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4489 + <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4490 + <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
4491 + };
4492 +
4493 + pcie@3600000 {
4494 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4495 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
4496 + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
4497 + reg-names = "regs", "config";
4498 + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
4499 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
4500 + interrupt-names = "pme", "aer";
4501 + #address-cells = <3>;
4502 + #size-cells = <2>;
4503 + device_type = "pci";
4504 + dma-coherent;
4505 + num-lanes = <2>;
4506 + bus-range = <0x0 0xff>;
4507 + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
4508 + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4509 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4510 + #interrupt-cells = <1>;
4511 + interrupt-map-mask = <0 0 0 7>;
4512 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4513 + <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4514 + <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4515 + <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
4516 + };
4517 +
4518 + };
4519 +
4520 + reserved-memory {
4521 + #address-cells = <2>;
4522 + #size-cells = <2>;
4523 + ranges;
4524 +
4525 + bman_fbpr: bman-fbpr {
4526 + compatible = "shared-dma-pool";
4527 + size = <0 0x1000000>;
4528 + alignment = <0 0x1000000>;
4529 + no-map;
4530 + };
4531 + qman_fqd: qman-fqd {
4532 + compatible = "shared-dma-pool";
4533 + size = <0 0x800000>;
4534 + alignment = <0 0x800000>;
4535 + no-map;
4536 + };
4537 + qman_pfdr: qman-pfdr {
4538 + compatible = "shared-dma-pool";
4539 + size = <0 0x2000000>;
4540 + alignment = <0 0x2000000>;
4541 + no-map;
4542 + };
4543 + };
4544 +};
4545 +
4546 +#include "qoriq-qman1-portals.dtsi"
4547 +#include "qoriq-bman1-portals.dtsi"
4548 --- /dev/null
4549 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
4550 @@ -0,0 +1,173 @@
4551 +/*
4552 + * Device Tree file for NXP LS1088A QDS Board.
4553 + *
4554 + * Copyright 2017 NXP
4555 + *
4556 + * Harninder Rai <harninder.rai@nxp.com>
4557 + *
4558 + * This file is dual-licensed: you can use it either under the terms
4559 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4560 + * licensing only applies to this file, and not this project as a
4561 + * whole.
4562 + *
4563 + * a) This library is free software; you can redistribute it and/or
4564 + * modify it under the terms of the GNU General Public License as
4565 + * published by the Free Software Foundation; either version 2 of the
4566 + * License, or (at your option) any later version.
4567 + *
4568 + * This library is distributed in the hope that it will be useful,
4569 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4570 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4571 + * GNU General Public License for more details.
4572 + *
4573 + * Or, alternatively,
4574 + *
4575 + * b) Permission is hereby granted, free of charge, to any person
4576 + * obtaining a copy of this software and associated documentation
4577 + * files (the "Software"), to deal in the Software without
4578 + * restriction, including without limitation the rights to use,
4579 + * copy, modify, merge, publish, distribute, sublicense, and/or
4580 + * sell copies of the Software, and to permit persons to whom the
4581 + * Software is furnished to do so, subject to the following
4582 + * conditions:
4583 + *
4584 + * The above copyright notice and this permission notice shall be
4585 + * included in all copies or substantial portions of the Software.
4586 + *
4587 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4588 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4589 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4590 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4591 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4592 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4593 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4594 + * OTHER DEALINGS IN THE SOFTWARE.
4595 + */
4596 +
4597 +/dts-v1/;
4598 +
4599 +#include "fsl-ls1088a.dtsi"
4600 +
4601 +/ {
4602 + model = "LS1088A QDS Board";
4603 + compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
4604 +};
4605 +
4606 +&i2c0 {
4607 + status = "okay";
4608 +
4609 + i2c-switch@77 {
4610 + compatible = "nxp,pca9547";
4611 + reg = <0x77>;
4612 + #address-cells = <1>;
4613 + #size-cells = <0>;
4614 +
4615 + i2c@2 {
4616 + #address-cells = <1>;
4617 + #size-cells = <0>;
4618 + reg = <0x2>;
4619 +
4620 + ina220@40 {
4621 + compatible = "ti,ina220";
4622 + reg = <0x40>;
4623 + shunt-resistor = <1000>;
4624 + };
4625 +
4626 + ina220@41 {
4627 + compatible = "ti,ina220";
4628 + reg = <0x41>;
4629 + shunt-resistor = <1000>;
4630 + };
4631 + };
4632 +
4633 + i2c@3 {
4634 + #address-cells = <1>;
4635 + #size-cells = <0>;
4636 + reg = <0x3>;
4637 +
4638 + temp-sensor@4c {
4639 + compatible = "adi,adt7461a";
4640 + reg = <0x4c>;
4641 + };
4642 +
4643 + rtc@51 {
4644 + compatible = "nxp,pcf2129";
4645 + reg = <0x51>;
4646 + /* IRQ10_B */
4647 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
4648 + };
4649 +
4650 + eeprom@56 {
4651 + compatible = "atmel,24c512";
4652 + reg = <0x56>;
4653 + };
4654 +
4655 + eeprom@57 {
4656 + compatible = "atmel,24c512";
4657 + reg = <0x57>;
4658 + };
4659 + };
4660 + };
4661 +};
4662 +
4663 +&qspi {
4664 + status = "okay";
4665 + qflash0: s25fs512s@0 {
4666 + compatible = "spansion,m25p80";
4667 + #address-cells = <1>;
4668 + #size-cells = <1>;
4669 + spi-max-frequency = <20000000>;
4670 + m25p,fast-read;
4671 + reg = <0>;
4672 + };
4673 +
4674 + qflash1: s25fs512s@1 {
4675 + compatible = "spansion,m25p80";
4676 + #address-cells = <1>;
4677 + #size-cells = <1>;
4678 + spi-max-frequency = <20000000>;
4679 + m25p,fast-read;
4680 + reg = <1>;
4681 + };
4682 +};
4683 +
4684 +&ifc {
4685 + status = "okay";
4686 +
4687 + ranges = <0 0 0x5 0x80000000 0x08000000
4688 + 2 0 0x5 0x30000000 0x00010000
4689 + 3 0 0x5 0x20000000 0x00010000>;
4690 +
4691 + nor@0,0 {
4692 + compatible = "cfi-flash";
4693 + reg = <0x0 0x0 0x8000000>;
4694 + bank-width = <2>;
4695 + device-width = <1>;
4696 + };
4697 +
4698 + nand@2,0 {
4699 + compatible = "fsl,ifc-nand";
4700 + reg = <0x2 0x0 0x10000>;
4701 + };
4702 +
4703 + fpga: board-control@3,0 {
4704 + compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
4705 + reg = <0x3 0x0 0x0000100>;
4706 + };
4707 +};
4708 +
4709 +&duart0 {
4710 + status = "okay";
4711 +};
4712 +
4713 +&duart1 {
4714 + status = "okay";
4715 +};
4716 +
4717 +&esdhc {
4718 + status = "okay";
4719 +};
4720 +
4721 +&sata {
4722 + status = "okay";
4723 +};
4724 --- /dev/null
4725 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
4726 @@ -0,0 +1,236 @@
4727 +/*
4728 + * Device Tree file for NXP LS1088A RDB Board.
4729 + *
4730 + * Copyright 2017 NXP
4731 + *
4732 + * Harninder Rai <harninder.rai@nxp.com>
4733 + *
4734 + * This file is dual-licensed: you can use it either under the terms
4735 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4736 + * licensing only applies to this file, and not this project as a
4737 + * whole.
4738 + *
4739 + * a) This library is free software; you can redistribute it and/or
4740 + * modify it under the terms of the GNU General Public License as
4741 + * published by the Free Software Foundation; either version 2 of the
4742 + * License, or (at your option) any later version.
4743 + *
4744 + * This library is distributed in the hope that it will be useful,
4745 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4746 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4747 + * GNU General Public License for more details.
4748 + *
4749 + * Or, alternatively,
4750 + *
4751 + * b) Permission is hereby granted, free of charge, to any person
4752 + * obtaining a copy of this software and associated documentation
4753 + * files (the "Software"), to deal in the Software without
4754 + * restriction, including without limitation the rights to use,
4755 + * copy, modify, merge, publish, distribute, sublicense, and/or
4756 + * sell copies of the Software, and to permit persons to whom the
4757 + * Software is furnished to do so, subject to the following
4758 + * conditions:
4759 + *
4760 + * The above copyright notice and this permission notice shall be
4761 + * included in all copies or substantial portions of the Software.
4762 + *
4763 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4764 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4765 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4766 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4767 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4768 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4769 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4770 + * OTHER DEALINGS IN THE SOFTWARE.
4771 + */
4772 +
4773 +/dts-v1/;
4774 +
4775 +#include "fsl-ls1088a.dtsi"
4776 +
4777 +/ {
4778 + model = "L1088A RDB Board";
4779 + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
4780 +};
4781 +
4782 +&i2c0 {
4783 + status = "okay";
4784 +
4785 + i2c-switch@77 {
4786 + compatible = "nxp,pca9547";
4787 + reg = <0x77>;
4788 + #address-cells = <1>;
4789 + #size-cells = <0>;
4790 +
4791 + i2c@2 {
4792 + #address-cells = <1>;
4793 + #size-cells = <0>;
4794 + reg = <0x2>;
4795 +
4796 + ina220@40 {
4797 + compatible = "ti,ina220";
4798 + reg = <0x40>;
4799 + shunt-resistor = <1000>;
4800 + };
4801 + };
4802 +
4803 + i2c@3 {
4804 + #address-cells = <1>;
4805 + #size-cells = <0>;
4806 + reg = <0x3>;
4807 +
4808 + temp-sensor@4c {
4809 + compatible = "adi,adt7461a";
4810 + reg = <0x4c>;
4811 + };
4812 +
4813 + rtc@51 {
4814 + compatible = "nxp,pcf2129";
4815 + reg = <0x51>;
4816 + /* IRQ10_B */
4817 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
4818 + };
4819 + };
4820 + };
4821 +};
4822 +
4823 +&qspi {
4824 + status = "okay";
4825 + qflash0: s25fs512s@0 {
4826 + compatible = "spansion,m25p80";
4827 + #address-cells = <1>;
4828 + #size-cells = <1>;
4829 + m25p,fast-read;
4830 + spi-max-frequency = <20000000>;
4831 + reg = <0>;
4832 + };
4833 +
4834 + qflash1: s25fs512s@1 {
4835 + compatible = "spansion,m25p80";
4836 + #address-cells = <1>;
4837 + #size-cells = <1>;
4838 + m25p,fast-read;
4839 + spi-max-frequency = <20000000>;
4840 + reg = <1>;
4841 + };
4842 +};
4843 +
4844 +&ifc {
4845 + status = "okay";
4846 +
4847 + ranges = <0 0 0x5 0x30000000 0x00010000
4848 + 2 0 0x5 0x20000000 0x00010000>;
4849 +
4850 + nand@0,0 {
4851 + compatible = "fsl,ifc-nand";
4852 + reg = <0x0 0x0 0x10000>;
4853 + };
4854 +
4855 + fpga: board-control@2,0 {
4856 + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
4857 + reg = <0x2 0x0 0x0000100>;
4858 + };
4859 +};
4860 +
4861 +&duart0 {
4862 + status = "okay";
4863 +};
4864 +
4865 +&duart1 {
4866 + status = "okay";
4867 +};
4868 +
4869 +&usb0 {
4870 + status = "okay";
4871 +};
4872 +
4873 +&usb1 {
4874 + status = "okay";
4875 +};
4876 +
4877 +&esdhc {
4878 + status = "okay";
4879 +};
4880 +
4881 +&sata {
4882 + status = "okay";
4883 +};
4884 +
4885 +&emdio1 {
4886 + /* Freescale F104 PHY1 */
4887 + mdio1_phy1: emdio1_phy@1 {
4888 + reg = <0x1c>;
4889 + phy-connection-type = "qsgmii";
4890 + };
4891 + mdio1_phy2: emdio1_phy@2 {
4892 + reg = <0x1d>;
4893 + phy-connection-type = "qsgmii";
4894 + };
4895 + mdio1_phy3: emdio1_phy@3 {
4896 + reg = <0x1e>;
4897 + phy-connection-type = "qsgmii";
4898 + };
4899 + mdio1_phy4: emdio1_phy@4 {
4900 + reg = <0x1f>;
4901 + phy-connection-type = "qsgmii";
4902 + };
4903 + /* F104 PHY2 */
4904 + mdio1_phy5: emdio1_phy@5 {
4905 + reg = <0x0c>;
4906 + phy-connection-type = "qsgmii";
4907 + };
4908 + mdio1_phy6: emdio1_phy@6 {
4909 + reg = <0x0d>;
4910 + phy-connection-type = "qsgmii";
4911 + };
4912 + mdio1_phy7: emdio1_phy@7 {
4913 + reg = <0x0e>;
4914 + phy-connection-type = "qsgmii";
4915 + };
4916 + mdio1_phy8: emdio1_phy@8 {
4917 + reg = <0x0f>;
4918 + phy-connection-type = "qsgmii";
4919 + };
4920 +};
4921 +
4922 +&emdio2 {
4923 + /* Aquantia AQR105 10G PHY */
4924 + mdio2_phy1: emdio2_phy@1 {
4925 + compatible = "ethernet-phy-ieee802.3-c45";
4926 + interrupts = <0 2 0x4>;
4927 + reg = <0x0>;
4928 + phy-connection-type = "xfi";
4929 + };
4930 +};
4931 +
4932 +/* DPMAC connections to external PHYs
4933 + * based on LS1088A RM RevC - $24.1.2 SerDes Options
4934 + */
4935 +/* DPMAC1 is 10G SFP+, fixed link */
4936 +&dpmac2 {
4937 + phy-handle = <&mdio2_phy1>;
4938 +};
4939 +&dpmac3 {
4940 + phy-handle = <&mdio1_phy5>;
4941 +};
4942 +&dpmac4 {
4943 + phy-handle = <&mdio1_phy6>;
4944 +};
4945 +&dpmac5 {
4946 + phy-handle = <&mdio1_phy7>;
4947 +};
4948 +&dpmac6 {
4949 + phy-handle = <&mdio1_phy8>;
4950 +};
4951 +&dpmac7 {
4952 + phy-handle = <&mdio1_phy1>;
4953 +};
4954 +&dpmac8 {
4955 + phy-handle = <&mdio1_phy2>;
4956 +};
4957 +&dpmac9 {
4958 + phy-handle = <&mdio1_phy3>;
4959 +};
4960 +&dpmac10 {
4961 + phy-handle = <&mdio1_phy4>;
4962 +};
4963 --- /dev/null
4964 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
4965 @@ -0,0 +1,816 @@
4966 +/*
4967 + * Device Tree Include file for NXP Layerscape-1088A family SoC.
4968 + *
4969 + * Copyright 2017 NXP
4970 + *
4971 + * Harninder Rai <harninder.rai@nxp.com>
4972 + *
4973 + * This file is dual-licensed: you can use it either under the terms
4974 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4975 + * licensing only applies to this file, and not this project as a
4976 + * whole.
4977 + *
4978 + * a) This library is free software; you can redistribute it and/or
4979 + * modify it under the terms of the GNU General Public License as
4980 + * published by the Free Software Foundation; either version 2 of the
4981 + * License, or (at your option) any later version.
4982 + *
4983 + * This library is distributed in the hope that it will be useful,
4984 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4985 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4986 + * GNU General Public License for more details.
4987 + *
4988 + * Or, alternatively,
4989 + *
4990 + * b) Permission is hereby granted, free of charge, to any person
4991 + * obtaining a copy of this software and associated documentation
4992 + * files (the "Software"), to deal in the Software without
4993 + * restriction, including without limitation the rights to use,
4994 + * copy, modify, merge, publish, distribute, sublicense, and/or
4995 + * sell copies of the Software, and to permit persons to whom the
4996 + * Software is furnished to do so, subject to the following
4997 + * conditions:
4998 + *
4999 + * The above copyright notice and this permission notice shall be
5000 + * included in all copies or substantial portions of the Software.
5001 + *
5002 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5003 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5004 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5005 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5006 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5007 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5008 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5009 + * OTHER DEALINGS IN THE SOFTWARE.
5010 + */
5011 +#include <dt-bindings/interrupt-controller/arm-gic.h>
5012 +#include <dt-bindings/thermal/thermal.h>
5013 +
5014 +/ {
5015 + compatible = "fsl,ls1088a";
5016 + interrupt-parent = <&gic>;
5017 + #address-cells = <2>;
5018 + #size-cells = <2>;
5019 +
5020 + aliases {
5021 + crypto = &crypto;
5022 + };
5023 +
5024 + cpus {
5025 + #address-cells = <1>;
5026 + #size-cells = <0>;
5027 +
5028 + /* We have 2 clusters having 4 Cortex-A53 cores each */
5029 + cpu0: cpu@0 {
5030 + device_type = "cpu";
5031 + compatible = "arm,cortex-a53";
5032 + reg = <0x0>;
5033 + clocks = <&clockgen 1 0>;
5034 + #cooling-cells = <2>;
5035 + cpu-idle-states = <&CPU_PH20>;
5036 + };
5037 +
5038 + cpu1: cpu@1 {
5039 + device_type = "cpu";
5040 + compatible = "arm,cortex-a53";
5041 + reg = <0x1>;
5042 + clocks = <&clockgen 1 0>;
5043 + cpu-idle-states = <&CPU_PH20>;
5044 + };
5045 +
5046 + cpu2: cpu@2 {
5047 + device_type = "cpu";
5048 + compatible = "arm,cortex-a53";
5049 + reg = <0x2>;
5050 + clocks = <&clockgen 1 0>;
5051 + cpu-idle-states = <&CPU_PH20>;
5052 + };
5053 +
5054 + cpu3: cpu@3 {
5055 + device_type = "cpu";
5056 + compatible = "arm,cortex-a53";
5057 + reg = <0x3>;
5058 + clocks = <&clockgen 1 0>;
5059 + cpu-idle-states = <&CPU_PH20>;
5060 + };
5061 +
5062 + cpu4: cpu@100 {
5063 + device_type = "cpu";
5064 + compatible = "arm,cortex-a53";
5065 + reg = <0x100>;
5066 + clocks = <&clockgen 1 1>;
5067 + #cooling-cells = <2>;
5068 + cpu-idle-states = <&CPU_PH20>;
5069 + };
5070 +
5071 + cpu5: cpu@101 {
5072 + device_type = "cpu";
5073 + compatible = "arm,cortex-a53";
5074 + reg = <0x101>;
5075 + clocks = <&clockgen 1 1>;
5076 + cpu-idle-states = <&CPU_PH20>;
5077 + };
5078 +
5079 + cpu6: cpu@102 {
5080 + device_type = "cpu";
5081 + compatible = "arm,cortex-a53";
5082 + reg = <0x102>;
5083 + clocks = <&clockgen 1 1>;
5084 + cpu-idle-states = <&CPU_PH20>;
5085 + };
5086 +
5087 + cpu7: cpu@103 {
5088 + device_type = "cpu";
5089 + compatible = "arm,cortex-a53";
5090 + reg = <0x103>;
5091 + clocks = <&clockgen 1 1>;
5092 + cpu-idle-states = <&CPU_PH20>;
5093 + };
5094 + };
5095 +
5096 + idle-states {
5097 + /*
5098 + * PSCI node is not added default, U-boot will add missing
5099 + * parts if it determines to use PSCI.
5100 + */
5101 + entry-method = "arm,psci";
5102 +
5103 + CPU_PH20: cpu-ph20 {
5104 + compatible = "arm,idle-state";
5105 + idle-state-name = "PH20";
5106 + arm,psci-suspend-param = <0x0>;
5107 + entry-latency-us = <1000>;
5108 + exit-latency-us = <1000>;
5109 + min-residency-us = <3000>;
5110 + };
5111 + };
5112 +
5113 + gic: interrupt-controller@6000000 {
5114 + compatible = "arm,gic-v3";
5115 + #interrupt-cells = <3>;
5116 + #address-cells = <2>;
5117 + #size-cells = <2>;
5118 + ranges;
5119 + interrupt-controller;
5120 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
5121 + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
5122 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
5123 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
5124 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
5125 + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
5126 +
5127 + its: gic-its@6020000 {
5128 + compatible = "arm,gic-v3-its";
5129 + msi-controller;
5130 + reg = <0x0 0x6020000 0 0x20000>;
5131 + };
5132 + };
5133 +
5134 + timer {
5135 + compatible = "arm,armv8-timer";
5136 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
5137 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
5138 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
5139 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
5140 + };
5141 +
5142 + fsl_mc: fsl-mc@80c000000 {
5143 + compatible = "fsl,qoriq-mc";
5144 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
5145 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
5146 + msi-parent = <&its>;
5147 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
5148 + #address-cells = <3>;
5149 + #size-cells = <1>;
5150 +
5151 + /*
5152 + * Region type 0x0 - MC portals
5153 + * Region type 0x1 - QBMAN portals
5154 + */
5155 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
5156 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
5157 +
5158 + dpmacs {
5159 + #address-cells = <1>;
5160 + #size-cells = <0>;
5161 +
5162 + dpmac1: dpmac@1 {
5163 + compatible = "fsl,qoriq-mc-dpmac";
5164 + reg = <1>;
5165 + };
5166 + dpmac2: dpmac@2 {
5167 + compatible = "fsl,qoriq-mc-dpmac";
5168 + reg = <2>;
5169 + };
5170 + dpmac3: dpmac@3 {
5171 + compatible = "fsl,qoriq-mc-dpmac";
5172 + reg = <3>;
5173 + };
5174 + dpmac4: dpmac@4 {
5175 + compatible = "fsl,qoriq-mc-dpmac";
5176 + reg = <4>;
5177 + };
5178 + dpmac5: dpmac@5 {
5179 + compatible = "fsl,qoriq-mc-dpmac";
5180 + reg = <5>;
5181 + };
5182 + dpmac6: dpmac@6 {
5183 + compatible = "fsl,qoriq-mc-dpmac";
5184 + reg = <6>;
5185 + };
5186 + dpmac7: dpmac@7 {
5187 + compatible = "fsl,qoriq-mc-dpmac";
5188 + reg = <7>;
5189 + };
5190 + dpmac8: dpmac@8 {
5191 + compatible = "fsl,qoriq-mc-dpmac";
5192 + reg = <8>;
5193 + };
5194 + dpmac9: dpmac@9 {
5195 + compatible = "fsl,qoriq-mc-dpmac";
5196 + reg = <9>;
5197 + };
5198 + dpmac10: dpmac@10 {
5199 + compatible = "fsl,qoriq-mc-dpmac";
5200 + reg = <0xa>;
5201 + };
5202 + };
5203 +
5204 + };
5205 +
5206 + sysclk: sysclk {
5207 + compatible = "fixed-clock";
5208 + #clock-cells = <0>;
5209 + clock-frequency = <100000000>;
5210 + clock-output-names = "sysclk";
5211 + };
5212 +
5213 + dcfg: dcfg@1e00000 {
5214 + compatible = "fsl,ls1088a-dcfg", "syscon";
5215 + reg = <0x0 0x1e00000 0x0 0x10000>;
5216 + little-endian;
5217 + };
5218 +
5219 + rstcr: syscon@1e60000 {
5220 + compatible = "fsl,ls1088a-rstcr", "syscon";
5221 + reg = <0x0 0x1e60000 0x0 0x4>;
5222 + };
5223 +
5224 + reboot {
5225 + compatible = "syscon-reboot";
5226 + regmap = <&rstcr>;
5227 + offset = <0x0>;
5228 + mask = <0x02>;
5229 + };
5230 +
5231 +
5232 + soc {
5233 + compatible = "simple-bus";
5234 + #address-cells = <2>;
5235 + #size-cells = <2>;
5236 + ranges;
5237 +
5238 + clockgen: clocking@1300000 {
5239 + compatible = "fsl,ls1088a-clockgen";
5240 + reg = <0 0x1300000 0 0xa0000>;
5241 + #clock-cells = <2>;
5242 + clocks = <&sysclk>;
5243 + };
5244 +
5245 + tmu: tmu@1f80000 {
5246 + compatible = "fsl,qoriq-tmu";
5247 + reg = <0x0 0x1f80000 0x0 0x10000>;
5248 + interrupts = <0 23 0x4>;
5249 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
5250 + fsl,tmu-calibration =
5251 + /* Calibration data group 1 */
5252 + <0x00000000 0x00000026
5253 + 0x00000001 0x0000002d
5254 + 0x00000002 0x00000032
5255 + 0x00000003 0x00000039
5256 + 0x00000004 0x0000003f
5257 + 0x00000005 0x00000046
5258 + 0x00000006 0x0000004d
5259 + 0x00000007 0x00000054
5260 + 0x00000008 0x0000005a
5261 + 0x00000009 0x00000061
5262 + 0x0000000a 0x0000006a
5263 + 0x0000000b 0x00000071
5264 + /* Calibration data group 2 */
5265 + 0x00010000 0x00000025
5266 + 0x00010001 0x0000002c
5267 + 0x00010002 0x00000035
5268 + 0x00010003 0x0000003d
5269 + 0x00010004 0x00000045
5270 + 0x00010005 0x0000004e
5271 + 0x00010006 0x00000057
5272 + 0x00010007 0x00000061
5273 + 0x00010008 0x0000006b
5274 + 0x00010009 0x00000076
5275 + /* Calibration data group 3 */
5276 + 0x00020000 0x00000029
5277 + 0x00020001 0x00000033
5278 + 0x00020002 0x0000003d
5279 + 0x00020003 0x00000049
5280 + 0x00020004 0x00000056
5281 + 0x00020005 0x00000061
5282 + 0x00020006 0x0000006d
5283 + /* Calibration data group 4 */
5284 + 0x00030000 0x00000021
5285 + 0x00030001 0x0000002a
5286 + 0x00030002 0x0000003c
5287 + 0x00030003 0x0000004e>;
5288 + little-endian;
5289 + #thermal-sensor-cells = <1>;
5290 + };
5291 +
5292 + thermal-zones {
5293 + cpu_thermal: cpu-thermal {
5294 + polling-delay-passive = <1000>;
5295 + polling-delay = <5000>;
5296 + thermal-sensors = <&tmu 0>;
5297 +
5298 + trips {
5299 + cpu_alert: cpu-alert {
5300 + temperature = <85000>;
5301 + hysteresis = <2000>;
5302 + type = "passive";
5303 + };
5304 +
5305 + cpu_crit: cpu-crit {
5306 + temperature = <95000>;
5307 + hysteresis = <2000>;
5308 + type = "critical";
5309 + };
5310 + };
5311 +
5312 + cooling-maps {
5313 + map0 {
5314 + trip = <&cpu_alert>;
5315 + cooling-device =
5316 + <&cpu0 THERMAL_NO_LIMIT
5317 + THERMAL_NO_LIMIT>;
5318 + };
5319 + map1 {
5320 + trip = <&cpu_alert>;
5321 + cooling-device =
5322 + <&cpu4 THERMAL_NO_LIMIT
5323 + THERMAL_NO_LIMIT>;
5324 + };
5325 + };
5326 + };
5327 + };
5328 +
5329 + duart0: serial@21c0500 {
5330 + compatible = "fsl,ns16550", "ns16550a";
5331 + reg = <0x0 0x21c0500 0x0 0x100>;
5332 + clocks = <&clockgen 4 3>;
5333 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5334 + status = "disabled";
5335 + };
5336 +
5337 + duart1: serial@21c0600 {
5338 + compatible = "fsl,ns16550", "ns16550a";
5339 + reg = <0x0 0x21c0600 0x0 0x100>;
5340 + clocks = <&clockgen 4 3>;
5341 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5342 + status = "disabled";
5343 + };
5344 +
5345 + cluster1_core0_watchdog: wdt@c000000 {
5346 + compatible = "arm,sp805-wdt", "arm,primecell";
5347 + reg = <0x0 0xc000000 0x0 0x1000>;
5348 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5349 + clock-names = "apb_pclk", "wdog_clk";
5350 + };
5351 +
5352 + cluster1_core1_watchdog: wdt@c010000 {
5353 + compatible = "arm,sp805-wdt", "arm,primecell";
5354 + reg = <0x0 0xc010000 0x0 0x1000>;
5355 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5356 + clock-names = "apb_pclk", "wdog_clk";
5357 + };
5358 +
5359 + cluster1_core2_watchdog: wdt@c020000 {
5360 + compatible = "arm,sp805-wdt", "arm,primecell";
5361 + reg = <0x0 0xc020000 0x0 0x1000>;
5362 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5363 + clock-names = "apb_pclk", "wdog_clk";
5364 + };
5365 +
5366 + cluster1_core3_watchdog: wdt@c030000 {
5367 + compatible = "arm,sp805-wdt", "arm,primecell";
5368 + reg = <0x0 0xc030000 0x0 0x1000>;
5369 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5370 + clock-names = "apb_pclk", "wdog_clk";
5371 + };
5372 +
5373 + cluster2_core0_watchdog: wdt@c100000 {
5374 + compatible = "arm,sp805-wdt", "arm,primecell";
5375 + reg = <0x0 0xc100000 0x0 0x1000>;
5376 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5377 + clock-names = "apb_pclk", "wdog_clk";
5378 + };
5379 +
5380 + cluster2_core1_watchdog: wdt@c110000 {
5381 + compatible = "arm,sp805-wdt", "arm,primecell";
5382 + reg = <0x0 0xc110000 0x0 0x1000>;
5383 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5384 + clock-names = "apb_pclk", "wdog_clk";
5385 + };
5386 +
5387 + cluster2_core2_watchdog: wdt@c120000 {
5388 + compatible = "arm,sp805-wdt", "arm,primecell";
5389 + reg = <0x0 0xc120000 0x0 0x1000>;
5390 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5391 + clock-names = "apb_pclk", "wdog_clk";
5392 + };
5393 +
5394 + cluster2_core3_watchdog: wdt@c130000 {
5395 + compatible = "arm,sp805-wdt", "arm,primecell";
5396 + reg = <0x0 0xc130000 0x0 0x1000>;
5397 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5398 + clock-names = "apb_pclk", "wdog_clk";
5399 + };
5400 +
5401 + gpio0: gpio@2300000 {
5402 + compatible = "fsl,qoriq-gpio";
5403 + reg = <0x0 0x2300000 0x0 0x10000>;
5404 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5405 + gpio-controller;
5406 + #gpio-cells = <2>;
5407 + interrupt-controller;
5408 + #interrupt-cells = <2>;
5409 + };
5410 +
5411 + gpio1: gpio@2310000 {
5412 + compatible = "fsl,qoriq-gpio";
5413 + reg = <0x0 0x2310000 0x0 0x10000>;
5414 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5415 + gpio-controller;
5416 + #gpio-cells = <2>;
5417 + interrupt-controller;
5418 + #interrupt-cells = <2>;
5419 + };
5420 +
5421 + gpio2: gpio@2320000 {
5422 + compatible = "fsl,qoriq-gpio";
5423 + reg = <0x0 0x2320000 0x0 0x10000>;
5424 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5425 + gpio-controller;
5426 + #gpio-cells = <2>;
5427 + interrupt-controller;
5428 + #interrupt-cells = <2>;
5429 + };
5430 +
5431 + gpio3: gpio@2330000 {
5432 + compatible = "fsl,qoriq-gpio";
5433 + reg = <0x0 0x2330000 0x0 0x10000>;
5434 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5435 + gpio-controller;
5436 + #gpio-cells = <2>;
5437 + interrupt-controller;
5438 + #interrupt-cells = <2>;
5439 + };
5440 +
5441 + /* TODO: WRIOP (CCSR?) */
5442 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
5443 + * E-MDIO1: 0x1_6000
5444 + */
5445 + compatible = "fsl,fman-memac-mdio";
5446 + reg = <0x0 0x8B96000 0x0 0x1000>;
5447 + device_type = "mdio";
5448 + little-endian; /* force the driver in LE mode */
5449 +
5450 + /* Not necessary on the QDS, but needed on the RDB */
5451 + #address-cells = <1>;
5452 + #size-cells = <0>;
5453 + };
5454 +
5455 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
5456 + * E-MDIO2: 0x1_7000
5457 + */
5458 + compatible = "fsl,fman-memac-mdio";
5459 + reg = <0x0 0x8B97000 0x0 0x1000>;
5460 + device_type = "mdio";
5461 + little-endian; /* force the driver in LE mode */
5462 +
5463 + #address-cells = <1>;
5464 + #size-cells = <0>;
5465 + };
5466 +
5467 + ifc: ifc@2240000 {
5468 + compatible = "fsl,ifc", "simple-bus";
5469 + reg = <0x0 0x2240000 0x0 0x20000>;
5470 + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
5471 + little-endian;
5472 + #address-cells = <2>;
5473 + #size-cells = <1>;
5474 +
5475 + };
5476 +
5477 + ftm0: ftm0@2800000 {
5478 + compatible = "fsl,ftm-alarm";
5479 + reg = <0x0 0x2800000 0x0 0x10000>;
5480 + interrupts = <0 44 4>;
5481 + };
5482 +
5483 + i2c0: i2c@2000000 {
5484 + compatible = "fsl,vf610-i2c";
5485 + #address-cells = <1>;
5486 + #size-cells = <0>;
5487 + reg = <0x0 0x2000000 0x0 0x10000>;
5488 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5489 + clocks = <&clockgen 4 3>;
5490 + status = "disabled";
5491 + };
5492 +
5493 + i2c1: i2c@2010000 {
5494 + compatible = "fsl,vf610-i2c";
5495 + #address-cells = <1>;
5496 + #size-cells = <0>;
5497 + reg = <0x0 0x2010000 0x0 0x10000>;
5498 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5499 + clocks = <&clockgen 4 3>;
5500 + status = "disabled";
5501 + };
5502 +
5503 + i2c2: i2c@2020000 {
5504 + compatible = "fsl,vf610-i2c";
5505 + #address-cells = <1>;
5506 + #size-cells = <0>;
5507 + reg = <0x0 0x2020000 0x0 0x10000>;
5508 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5509 + clocks = <&clockgen 4 3>;
5510 + status = "disabled";
5511 + };
5512 +
5513 + i2c3: i2c@2030000 {
5514 + compatible = "fsl,vf610-i2c";
5515 + #address-cells = <1>;
5516 + #size-cells = <0>;
5517 + reg = <0x0 0x2030000 0x0 0x10000>;
5518 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5519 + clocks = <&clockgen 4 3>;
5520 + status = "disabled";
5521 + };
5522 +
5523 + qspi: quadspi@20c0000 {
5524 + compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
5525 + #address-cells = <1>;
5526 + #size-cells = <0>;
5527 + reg = <0x0 0x20c0000 0x0 0x10000>,
5528 + <0x0 0x20000000 0x0 0x10000000>;
5529 + reg-names = "QuadSPI", "QuadSPI-memory";
5530 + interrupts = <0 25 0x4>; /* Level high type */
5531 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5532 + clock-names = "qspi_en", "qspi";
5533 + fsl,qspi-has-second-chip;
5534 + };
5535 +
5536 + esdhc: esdhc@2140000 {
5537 + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
5538 + reg = <0x0 0x2140000 0x0 0x10000>;
5539 + interrupts = <0 28 0x4>; /* Level high type */
5540 + clock-frequency = <0>;
5541 + voltage-ranges = <1800 1800 3300 3300>;
5542 + sdhci,auto-cmd12;
5543 + little-endian;
5544 + bus-width = <4>;
5545 + status = "disabled";
5546 + };
5547 +
5548 + usb0: usb3@3100000 {
5549 + compatible = "snps,dwc3";
5550 + reg = <0x0 0x3100000 0x0 0x10000>;
5551 + interrupts = <0 80 0x4>; /* Level high type */
5552 + dr_mode = "host";
5553 + configure-gfladj;
5554 + snps,dis_rxdet_inp3_quirk;
5555 + };
5556 +
5557 + usb1: usb3@3110000 {
5558 + compatible = "snps,dwc3";
5559 + reg = <0x0 0x3110000 0x0 0x10000>;
5560 + interrupts = <0 81 0x4>; /* Level high type */
5561 + dr_mode = "host";
5562 + configure-gfladj;
5563 + snps,dis_rxdet_inp3_quirk;
5564 + };
5565 +
5566 + sata: sata@3200000 {
5567 + compatible = "fsl,ls1088a-ahci";
5568 + reg = <0x0 0x3200000 0x0 0x10000>,
5569 + <0x7 0x100520 0x0 0x4>;
5570 + reg-names = "ahci", "sata-ecc";
5571 + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
5572 + clocks = <&clockgen 4 3>;
5573 + dma-coherent;
5574 + status = "disabled";
5575 + };
5576 +
5577 + pcie@3400000 {
5578 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5579 + "snps,dw-pcie";
5580 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
5581 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
5582 + reg-names = "regs", "config";
5583 + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5584 + interrupt-names = "aer";
5585 + #address-cells = <3>;
5586 + #size-cells = <2>;
5587 + device_type = "pci";
5588 + dma-coherent;
5589 + num-lanes = <4>;
5590 + bus-range = <0x0 0xff>;
5591 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
5592 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5593 + msi-parent = <&its>;
5594 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5595 + #interrupt-cells = <1>;
5596 + interrupt-map-mask = <0 0 0 7>;
5597 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
5598 + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
5599 + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
5600 + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
5601 + };
5602 +
5603 + pcie@3500000 {
5604 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5605 + "snps,dw-pcie";
5606 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
5607 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
5608 + reg-names = "regs", "config";
5609 + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5610 + interrupt-names = "aer";
5611 + #address-cells = <3>;
5612 + #size-cells = <2>;
5613 + device_type = "pci";
5614 + dma-coherent;
5615 + num-lanes = <4>;
5616 + bus-range = <0x0 0xff>;
5617 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
5618 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5619 + msi-parent = <&its>;
5620 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5621 + #interrupt-cells = <1>;
5622 + interrupt-map-mask = <0 0 0 7>;
5623 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
5624 + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
5625 + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
5626 + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
5627 + };
5628 +
5629 + pcie@3600000 {
5630 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5631 + "snps,dw-pcie";
5632 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
5633 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
5634 + reg-names = "regs", "config";
5635 + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5636 + interrupt-names = "aer";
5637 + #address-cells = <3>;
5638 + #size-cells = <2>;
5639 + device_type = "pci";
5640 + dma-coherent;
5641 + num-lanes = <8>;
5642 + bus-range = <0x0 0xff>;
5643 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
5644 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5645 + msi-parent = <&its>;
5646 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5647 + #interrupt-cells = <1>;
5648 + interrupt-map-mask = <0 0 0 7>;
5649 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
5650 + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
5651 + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
5652 + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
5653 + };
5654 +
5655 + smmu: iommu@5000000 {
5656 + compatible = "arm,mmu-500";
5657 + reg = <0 0x5000000 0 0x800000>;
5658 + #global-interrupts = <12>;
5659 + #iommu-cells = <1>;
5660 + stream-match-mask = <0x7C00>;
5661 + interrupts = <0 13 4>, /* global secure fault */
5662 + <0 14 4>, /* combined secure interrupt */
5663 + <0 15 4>, /* global non-secure fault */
5664 + <0 16 4>, /* combined non-secure interrupt */
5665 + /* performance counter interrupts 0-7 */
5666 + <0 211 4>,
5667 + <0 212 4>,
5668 + <0 213 4>,
5669 + <0 214 4>,
5670 + <0 215 4>,
5671 + <0 216 4>,
5672 + <0 217 4>,
5673 + <0 218 4>,
5674 + /* per context interrupt, 64 interrupts */
5675 + <0 146 4>,
5676 + <0 147 4>,
5677 + <0 148 4>,
5678 + <0 149 4>,
5679 + <0 150 4>,
5680 + <0 151 4>,
5681 + <0 152 4>,
5682 + <0 153 4>,
5683 + <0 154 4>,
5684 + <0 155 4>,
5685 + <0 156 4>,
5686 + <0 157 4>,
5687 + <0 158 4>,
5688 + <0 159 4>,
5689 + <0 160 4>,
5690 + <0 161 4>,
5691 + <0 162 4>,
5692 + <0 163 4>,
5693 + <0 164 4>,
5694 + <0 165 4>,
5695 + <0 166 4>,
5696 + <0 167 4>,
5697 + <0 168 4>,
5698 + <0 169 4>,
5699 + <0 170 4>,
5700 + <0 171 4>,
5701 + <0 172 4>,
5702 + <0 173 4>,
5703 + <0 174 4>,
5704 + <0 175 4>,
5705 + <0 176 4>,
5706 + <0 177 4>,
5707 + <0 178 4>,
5708 + <0 179 4>,
5709 + <0 180 4>,
5710 + <0 181 4>,
5711 + <0 182 4>,
5712 + <0 183 4>,
5713 + <0 184 4>,
5714 + <0 185 4>,
5715 + <0 186 4>,
5716 + <0 187 4>,
5717 + <0 188 4>,
5718 + <0 189 4>,
5719 + <0 190 4>,
5720 + <0 191 4>,
5721 + <0 192 4>,
5722 + <0 193 4>,
5723 + <0 194 4>,
5724 + <0 195 4>,
5725 + <0 196 4>,
5726 + <0 197 4>,
5727 + <0 198 4>,
5728 + <0 199 4>,
5729 + <0 200 4>,
5730 + <0 201 4>,
5731 + <0 202 4>,
5732 + <0 203 4>,
5733 + <0 204 4>,
5734 + <0 205 4>,
5735 + <0 206 4>,
5736 + <0 207 4>,
5737 + <0 208 4>,
5738 + <0 209 4>;
5739 + };
5740 +
5741 + crypto: crypto@8000000 {
5742 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
5743 + fsl,sec-era = <8>;
5744 + #address-cells = <1>;
5745 + #size-cells = <1>;
5746 + ranges = <0x0 0x00 0x8000000 0x100000>;
5747 + reg = <0x00 0x8000000 0x0 0x100000>;
5748 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
5749 + dma-coherent;
5750 +
5751 + sec_jr0: jr@10000 {
5752 + compatible = "fsl,sec-v5.0-job-ring",
5753 + "fsl,sec-v4.0-job-ring";
5754 + reg = <0x10000 0x10000>;
5755 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
5756 + };
5757 +
5758 + sec_jr1: jr@20000 {
5759 + compatible = "fsl,sec-v5.0-job-ring",
5760 + "fsl,sec-v4.0-job-ring";
5761 + reg = <0x20000 0x10000>;
5762 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
5763 + };
5764 +
5765 + sec_jr2: jr@30000 {
5766 + compatible = "fsl,sec-v5.0-job-ring",
5767 + "fsl,sec-v4.0-job-ring";
5768 + reg = <0x30000 0x10000>;
5769 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
5770 + };
5771 +
5772 + sec_jr3: jr@40000 {
5773 + compatible = "fsl,sec-v5.0-job-ring",
5774 + "fsl,sec-v4.0-job-ring";
5775 + reg = <0x40000 0x10000>;
5776 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
5777 + };
5778 + };
5779 + };
5780 +
5781 +};
5782 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
5783 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
5784 @@ -1,8 +1,10 @@
5785 /*
5786 * Device Tree file for Freescale LS2080a QDS Board.
5787 *
5788 - * Copyright (C) 2015, Freescale Semiconductor
5789 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
5790 + * Copyright 2017 NXP
5791 *
5792 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
5793 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
5794 *
5795 * This file is dual-licensed: you can use it either under the terms
5796 @@ -46,169 +48,76 @@
5797
5798 /dts-v1/;
5799
5800 -/include/ "fsl-ls2080a.dtsi"
5801 +#include "fsl-ls2080a.dtsi"
5802 +#include "fsl-ls208xa-qds.dtsi"
5803
5804 / {
5805 model = "Freescale Layerscape 2080a QDS Board";
5806 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
5807
5808 - aliases {
5809 - serial0 = &serial0;
5810 - serial1 = &serial1;
5811 - };
5812 -
5813 chosen {
5814 stdout-path = "serial0:115200n8";
5815 };
5816 };
5817
5818 -&esdhc {
5819 - status = "okay";
5820 -};
5821 -
5822 &ifc {
5823 - status = "okay";
5824 - #address-cells = <2>;
5825 - #size-cells = <1>;
5826 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
5827 - 0x2 0x0 0x5 0x30000000 0x00010000
5828 - 0x3 0x0 0x5 0x20000000 0x00010000>;
5829 -
5830 - nor@0,0 {
5831 + boardctrl: board-control@3,0 {
5832 #address-cells = <1>;
5833 #size-cells = <1>;
5834 - compatible = "cfi-flash";
5835 - reg = <0x0 0x0 0x8000000>;
5836 - bank-width = <2>;
5837 - device-width = <1>;
5838 - };
5839 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
5840 + reg = <3 0 0x300>; /* TODO check address */
5841 + ranges = <0 3 0 0x300>;
5842
5843 - nand@2,0 {
5844 - compatible = "fsl,ifc-nand";
5845 - reg = <0x2 0x0 0x10000>;
5846 - };
5847 + mdio_mux_emi1 {
5848 + compatible = "mdio-mux-mmioreg", "mdio-mux";
5849 + mdio-parent-bus = <&emdio1>;
5850 + reg = <0x54 1>; /* BRDCFG4 */
5851 + mux-mask = <0xe0>; /* EMI1_MDIO */
5852
5853 - cpld@3,0 {
5854 - reg = <0x3 0x0 0x10000>;
5855 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
5856 - };
5857 -};
5858 -
5859 -&i2c0 {
5860 - status = "okay";
5861 - pca9547@77 {
5862 - compatible = "nxp,pca9547";
5863 - reg = <0x77>;
5864 - #address-cells = <1>;
5865 - #size-cells = <0>;
5866 - i2c@0 {
5867 - #address-cells = <1>;
5868 + #address-cells=<1>;
5869 #size-cells = <0>;
5870 - reg = <0x00>;
5871 - rtc@68 {
5872 - compatible = "dallas,ds3232";
5873 - reg = <0x68>;
5874 - };
5875 - };
5876
5877 - i2c@2 {
5878 - #address-cells = <1>;
5879 - #size-cells = <0>;
5880 - reg = <0x02>;
5881 -
5882 - ina220@40 {
5883 - compatible = "ti,ina220";
5884 - reg = <0x40>;
5885 - shunt-resistor = <500>;
5886 - };
5887 -
5888 - ina220@41 {
5889 - compatible = "ti,ina220";
5890 - reg = <0x41>;
5891 - shunt-resistor = <1000>;
5892 - };
5893 - };
5894 -
5895 - i2c@3 {
5896 - #address-cells = <1>;
5897 - #size-cells = <0>;
5898 - reg = <0x3>;
5899 -
5900 - adt7481@4c {
5901 - compatible = "adi,adt7461";
5902 - reg = <0x4c>;
5903 + /* Child MDIO buses, one for each riser card:
5904 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
5905 + * VSC8234 PHYs on the riser cards.
5906 + */
5907 +
5908 + mdio_mux3: mdio@60 {
5909 + reg = <0x60>;
5910 + #address-cells = <1>;
5911 + #size-cells = <0>;
5912 +
5913 + mdio0_phy12: mdio_phy0@1c {
5914 + reg = <0x1c>;
5915 + phy-connection-type = "sgmii";
5916 + };
5917 + mdio0_phy13: mdio_phy1@1d {
5918 + reg = <0x1d>;
5919 + phy-connection-type = "sgmii";
5920 + };
5921 + mdio0_phy14: mdio_phy2@1e {
5922 + reg = <0x1e>;
5923 + phy-connection-type = "sgmii";
5924 + };
5925 + mdio0_phy15: mdio_phy3@1f {
5926 + reg = <0x1f>;
5927 + phy-connection-type = "sgmii";
5928 + };
5929 };
5930 };
5931 };
5932 };
5933
5934 -&i2c1 {
5935 - status = "disabled";
5936 -};
5937 -
5938 -&i2c2 {
5939 - status = "disabled";
5940 -};
5941 -
5942 -&i2c3 {
5943 - status = "disabled";
5944 -};
5945 -
5946 -&dspi {
5947 - status = "okay";
5948 - dflash0: n25q128a {
5949 - #address-cells = <1>;
5950 - #size-cells = <1>;
5951 - compatible = "st,m25p80";
5952 - spi-max-frequency = <3000000>;
5953 - reg = <0>;
5954 - };
5955 - dflash1: sst25wf040b {
5956 - #address-cells = <1>;
5957 - #size-cells = <1>;
5958 - compatible = "st,m25p80";
5959 - spi-max-frequency = <3000000>;
5960 - reg = <1>;
5961 - };
5962 - dflash2: en25s64 {
5963 - #address-cells = <1>;
5964 - #size-cells = <1>;
5965 - compatible = "st,m25p80";
5966 - spi-max-frequency = <3000000>;
5967 - reg = <2>;
5968 - };
5969 -};
5970 -
5971 -&qspi {
5972 - status = "okay";
5973 - flash0: s25fl256s1@0 {
5974 - #address-cells = <1>;
5975 - #size-cells = <1>;
5976 - compatible = "st,m25p80";
5977 - spi-max-frequency = <20000000>;
5978 - reg = <0>;
5979 - };
5980 - flash2: s25fl256s1@2 {
5981 - #address-cells = <1>;
5982 - #size-cells = <1>;
5983 - compatible = "st,m25p80";
5984 - spi-max-frequency = <20000000>;
5985 - reg = <0>;
5986 - };
5987 -};
5988 -
5989 -&sata0 {
5990 - status = "okay";
5991 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
5992 +&dpmac9 {
5993 + phy-handle = <&mdio0_phy12>;
5994 };
5995 -
5996 -&sata1 {
5997 - status = "okay";
5998 +&dpmac10 {
5999 + phy-handle = <&mdio0_phy13>;
6000 };
6001 -
6002 -&usb0 {
6003 - status = "okay";
6004 +&dpmac11 {
6005 + phy-handle = <&mdio0_phy14>;
6006 };
6007 -
6008 -&usb1 {
6009 - status = "okay";
6010 +&dpmac12 {
6011 + phy-handle = <&mdio0_phy15>;
6012 };
6013 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6014 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6015 @@ -1,8 +1,10 @@
6016 /*
6017 * Device Tree file for Freescale LS2080a RDB Board.
6018 *
6019 - * Copyright (C) 2015, Freescale Semiconductor
6020 + * Copyright 2016 Freescale Semiconductor, Inc.
6021 + * Copyright 2017 NXP
6022 *
6023 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6024 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6025 *
6026 * This file is dual-licensed: you can use it either under the terms
6027 @@ -46,125 +48,94 @@
6028
6029 /dts-v1/;
6030
6031 -/include/ "fsl-ls2080a.dtsi"
6032 +#include "fsl-ls2080a.dtsi"
6033 +#include "fsl-ls208xa-rdb.dtsi"
6034
6035 / {
6036 model = "Freescale Layerscape 2080a RDB Board";
6037 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
6038
6039 - aliases {
6040 - serial0 = &serial0;
6041 - serial1 = &serial1;
6042 - };
6043 -
6044 chosen {
6045 stdout-path = "serial1:115200n8";
6046 };
6047 };
6048
6049 -&esdhc {
6050 - status = "okay";
6051 -};
6052 -
6053 -&ifc {
6054 - status = "okay";
6055 - #address-cells = <2>;
6056 - #size-cells = <1>;
6057 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6058 - 0x2 0x0 0x5 0x30000000 0x00010000
6059 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6060 -
6061 - nor@0,0 {
6062 - #address-cells = <1>;
6063 - #size-cells = <1>;
6064 - compatible = "cfi-flash";
6065 - reg = <0x0 0x0 0x8000000>;
6066 - bank-width = <2>;
6067 - device-width = <1>;
6068 - };
6069 -
6070 - nand@2,0 {
6071 - compatible = "fsl,ifc-nand";
6072 - reg = <0x2 0x0 0x10000>;
6073 - };
6074 -
6075 - cpld@3,0 {
6076 - reg = <0x3 0x0 0x10000>;
6077 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6078 - };
6079 -
6080 -};
6081 -
6082 -&i2c0 {
6083 - status = "okay";
6084 - pca9547@75 {
6085 - compatible = "nxp,pca9547";
6086 - reg = <0x75>;
6087 - #address-cells = <1>;
6088 - #size-cells = <0>;
6089 - status = "disabled";
6090 - i2c@1 {
6091 - #address-cells = <1>;
6092 - #size-cells = <0>;
6093 - reg = <0x01>;
6094 - rtc@68 {
6095 - compatible = "dallas,ds3232";
6096 - reg = <0x68>;
6097 - };
6098 - };
6099 -
6100 - i2c@3 {
6101 - #address-cells = <1>;
6102 - #size-cells = <0>;
6103 - reg = <0x3>;
6104 -
6105 - adt7481@4c {
6106 - compatible = "adi,adt7461";
6107 - reg = <0x4c>;
6108 - };
6109 - };
6110 - };
6111 -};
6112 -
6113 -&i2c1 {
6114 - status = "disabled";
6115 -};
6116 -
6117 -&i2c2 {
6118 - status = "disabled";
6119 -};
6120 -
6121 -&i2c3 {
6122 +&emdio1 {
6123 status = "disabled";
6124 + /* CS4340 PHYs */
6125 + mdio1_phy1: emdio1_phy@1 {
6126 + reg = <0x10>;
6127 + phy-connection-type = "xfi";
6128 + };
6129 + mdio1_phy2: emdio1_phy@2 {
6130 + reg = <0x11>;
6131 + phy-connection-type = "xfi";
6132 + };
6133 + mdio1_phy3: emdio1_phy@3 {
6134 + reg = <0x12>;
6135 + phy-connection-type = "xfi";
6136 + };
6137 + mdio1_phy4: emdio1_phy@4 {
6138 + reg = <0x13>;
6139 + phy-connection-type = "xfi";
6140 + };
6141 };
6142
6143 -&dspi {
6144 - status = "okay";
6145 - dflash0: n25q512a {
6146 - #address-cells = <1>;
6147 - #size-cells = <1>;
6148 - compatible = "st,m25p80";
6149 - spi-max-frequency = <3000000>;
6150 - reg = <0>;
6151 +&emdio2 {
6152 + /* AQR405 PHYs */
6153 + mdio2_phy1: emdio2_phy@1 {
6154 + compatible = "ethernet-phy-ieee802.3-c45";
6155 + interrupts = <0 1 0x4>; /* Level high type */
6156 + reg = <0x0>;
6157 + phy-connection-type = "xfi";
6158 + };
6159 + mdio2_phy2: emdio2_phy@2 {
6160 + compatible = "ethernet-phy-ieee802.3-c45";
6161 + interrupts = <0 2 0x4>; /* Level high type */
6162 + reg = <0x1>;
6163 + phy-connection-type = "xfi";
6164 + };
6165 + mdio2_phy3: emdio2_phy@3 {
6166 + compatible = "ethernet-phy-ieee802.3-c45";
6167 + interrupts = <0 4 0x4>; /* Level high type */
6168 + reg = <0x2>;
6169 + phy-connection-type = "xfi";
6170 + };
6171 + mdio2_phy4: emdio2_phy@4 {
6172 + compatible = "ethernet-phy-ieee802.3-c45";
6173 + interrupts = <0 5 0x4>; /* Level high type */
6174 + reg = <0x3>;
6175 + phy-connection-type = "xfi";
6176 };
6177 };
6178
6179 -&qspi {
6180 - status = "disabled";
6181 -};
6182 +/* Update DPMAC connections to external PHYs, under the assumption of
6183 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
6184 + */
6185 +/* Leave Cortina nodes commented out until driver is integrated
6186 + *&dpmac1 {
6187 + * phy-handle = <&mdio1_phy1>;
6188 + *};
6189 + *&dpmac2 {
6190 + * phy-handle = <&mdio1_phy2>;
6191 + *};
6192 + *&dpmac3 {
6193 + * phy-handle = <&mdio1_phy3>;
6194 + *};
6195 + *&dpmac4 {
6196 + * phy-handle = <&mdio1_phy4>;
6197 + *};
6198 + */
6199
6200 -&sata0 {
6201 - status = "okay";
6202 +&dpmac5 {
6203 + phy-handle = <&mdio2_phy1>;
6204 };
6205 -
6206 -&sata1 {
6207 - status = "okay";
6208 +&dpmac6 {
6209 + phy-handle = <&mdio2_phy2>;
6210 };
6211 -
6212 -&usb0 {
6213 - status = "okay";
6214 +&dpmac7 {
6215 + phy-handle = <&mdio2_phy3>;
6216 };
6217 -
6218 -&usb1 {
6219 - status = "okay";
6220 +&dpmac8 {
6221 + phy-handle = <&mdio2_phy4>;
6222 };
6223 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6224 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6225 @@ -1,7 +1,7 @@
6226 /*
6227 * Device Tree file for Freescale LS2080a software Simulator model
6228 *
6229 - * Copyright (C) 2014-2015, Freescale Semiconductor
6230 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
6231 *
6232 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6233 *
6234 @@ -46,17 +46,12 @@
6235
6236 /dts-v1/;
6237
6238 -/include/ "fsl-ls2080a.dtsi"
6239 +#include "fsl-ls2080a.dtsi"
6240
6241 / {
6242 model = "Freescale Layerscape 2080a software Simulator model";
6243 compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
6244
6245 - aliases {
6246 - serial0 = &serial0;
6247 - serial1 = &serial1;
6248 - };
6249 -
6250 ethernet@2210000 {
6251 compatible = "smsc,lan91c111";
6252 reg = <0x0 0x2210000 0x0 0x100>;
6253 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6254 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6255 @@ -1,8 +1,9 @@
6256 /*
6257 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6258 *
6259 - * Copyright (C) 2014-2015, Freescale Semiconductor
6260 + * Copyright 2014-2016 Freescale Semiconductor, Inc.
6261 *
6262 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6263 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6264 *
6265 * This file is dual-licensed: you can use it either under the terms
6266 @@ -44,696 +45,132 @@
6267 * OTHER DEALINGS IN THE SOFTWARE.
6268 */
6269
6270 -/ {
6271 - compatible = "fsl,ls2080a";
6272 - interrupt-parent = <&gic>;
6273 - #address-cells = <2>;
6274 - #size-cells = <2>;
6275 -
6276 - cpus {
6277 - #address-cells = <1>;
6278 - #size-cells = <0>;
6279 -
6280 - /*
6281 - * We expect the enable-method for cpu's to be "psci", but this
6282 - * is dependent on the SoC FW, which will fill this in.
6283 - *
6284 - * Currently supported enable-method is psci v0.2
6285 - */
6286 -
6287 - /* We have 4 clusters having 2 Cortex-A57 cores each */
6288 - cpu@0 {
6289 - device_type = "cpu";
6290 - compatible = "arm,cortex-a57";
6291 - reg = <0x0>;
6292 - clocks = <&clockgen 1 0>;
6293 - next-level-cache = <&cluster0_l2>;
6294 - };
6295 -
6296 - cpu@1 {
6297 - device_type = "cpu";
6298 - compatible = "arm,cortex-a57";
6299 - reg = <0x1>;
6300 - clocks = <&clockgen 1 0>;
6301 - next-level-cache = <&cluster0_l2>;
6302 - };
6303 -
6304 - cpu@100 {
6305 - device_type = "cpu";
6306 - compatible = "arm,cortex-a57";
6307 - reg = <0x100>;
6308 - clocks = <&clockgen 1 1>;
6309 - next-level-cache = <&cluster1_l2>;
6310 - };
6311 -
6312 - cpu@101 {
6313 - device_type = "cpu";
6314 - compatible = "arm,cortex-a57";
6315 - reg = <0x101>;
6316 - clocks = <&clockgen 1 1>;
6317 - next-level-cache = <&cluster1_l2>;
6318 - };
6319 -
6320 - cpu@200 {
6321 - device_type = "cpu";
6322 - compatible = "arm,cortex-a57";
6323 - reg = <0x200>;
6324 - clocks = <&clockgen 1 2>;
6325 - next-level-cache = <&cluster2_l2>;
6326 - };
6327 -
6328 - cpu@201 {
6329 - device_type = "cpu";
6330 - compatible = "arm,cortex-a57";
6331 - reg = <0x201>;
6332 - clocks = <&clockgen 1 2>;
6333 - next-level-cache = <&cluster2_l2>;
6334 - };
6335 -
6336 - cpu@300 {
6337 - device_type = "cpu";
6338 - compatible = "arm,cortex-a57";
6339 - reg = <0x300>;
6340 - clocks = <&clockgen 1 3>;
6341 - next-level-cache = <&cluster3_l2>;
6342 - };
6343 -
6344 - cpu@301 {
6345 - device_type = "cpu";
6346 - compatible = "arm,cortex-a57";
6347 - reg = <0x301>;
6348 - clocks = <&clockgen 1 3>;
6349 - next-level-cache = <&cluster3_l2>;
6350 - };
6351 -
6352 - cluster0_l2: l2-cache0 {
6353 - compatible = "cache";
6354 - };
6355 -
6356 - cluster1_l2: l2-cache1 {
6357 - compatible = "cache";
6358 - };
6359 -
6360 - cluster2_l2: l2-cache2 {
6361 - compatible = "cache";
6362 - };
6363 -
6364 - cluster3_l2: l2-cache3 {
6365 - compatible = "cache";
6366 - };
6367 - };
6368 -
6369 - memory@80000000 {
6370 - device_type = "memory";
6371 - reg = <0x00000000 0x80000000 0 0x80000000>;
6372 - /* DRAM space - 1, size : 2 GB DRAM */
6373 - };
6374 -
6375 - sysclk: sysclk {
6376 - compatible = "fixed-clock";
6377 - #clock-cells = <0>;
6378 - clock-frequency = <100000000>;
6379 - clock-output-names = "sysclk";
6380 - };
6381 -
6382 - gic: interrupt-controller@6000000 {
6383 - compatible = "arm,gic-v3";
6384 - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
6385 - <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
6386 - <0x0 0x0c0c0000 0 0x2000>, /* GICC */
6387 - <0x0 0x0c0d0000 0 0x1000>, /* GICH */
6388 - <0x0 0x0c0e0000 0 0x20000>; /* GICV */
6389 - #interrupt-cells = <3>;
6390 - #address-cells = <2>;
6391 - #size-cells = <2>;
6392 - ranges;
6393 - interrupt-controller;
6394 - interrupts = <1 9 0x4>;
6395 -
6396 - its: gic-its@6020000 {
6397 - compatible = "arm,gic-v3-its";
6398 - msi-controller;
6399 - reg = <0x0 0x6020000 0 0x20000>;
6400 - };
6401 - };
6402 -
6403 - rstcr: syscon@1e60000 {
6404 - compatible = "fsl,ls2080a-rstcr", "syscon";
6405 - reg = <0x0 0x1e60000 0x0 0x4>;
6406 - };
6407 -
6408 - reboot {
6409 - compatible ="syscon-reboot";
6410 - regmap = <&rstcr>;
6411 - offset = <0x0>;
6412 - mask = <0x2>;
6413 - };
6414 -
6415 - timer {
6416 - compatible = "arm,armv8-timer";
6417 - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
6418 - <1 14 4>, /* Physical Non-Secure PPI, active-low */
6419 - <1 11 4>, /* Virtual PPI, active-low */
6420 - <1 10 4>; /* Hypervisor PPI, active-low */
6421 - fsl,erratum-a008585;
6422 - };
6423 -
6424 - pmu {
6425 - compatible = "arm,armv8-pmuv3";
6426 - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
6427 - };
6428 -
6429 - soc {
6430 - compatible = "simple-bus";
6431 - #address-cells = <2>;
6432 - #size-cells = <2>;
6433 - ranges;
6434 -
6435 - clockgen: clocking@1300000 {
6436 - compatible = "fsl,ls2080a-clockgen";
6437 - reg = <0 0x1300000 0 0xa0000>;
6438 - #clock-cells = <2>;
6439 - clocks = <&sysclk>;
6440 - };
6441 -
6442 - serial0: serial@21c0500 {
6443 - compatible = "fsl,ns16550", "ns16550a";
6444 - reg = <0x0 0x21c0500 0x0 0x100>;
6445 - clocks = <&clockgen 4 3>;
6446 - interrupts = <0 32 0x4>; /* Level high type */
6447 - };
6448 -
6449 - serial1: serial@21c0600 {
6450 - compatible = "fsl,ns16550", "ns16550a";
6451 - reg = <0x0 0x21c0600 0x0 0x100>;
6452 - clocks = <&clockgen 4 3>;
6453 - interrupts = <0 32 0x4>; /* Level high type */
6454 - };
6455 -
6456 - cluster1_core0_watchdog: wdt@c000000 {
6457 - compatible = "arm,sp805-wdt", "arm,primecell";
6458 - reg = <0x0 0xc000000 0x0 0x1000>;
6459 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6460 - clock-names = "apb_pclk", "wdog_clk";
6461 - };
6462 -
6463 - cluster1_core1_watchdog: wdt@c010000 {
6464 - compatible = "arm,sp805-wdt", "arm,primecell";
6465 - reg = <0x0 0xc010000 0x0 0x1000>;
6466 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6467 - clock-names = "apb_pclk", "wdog_clk";
6468 - };
6469 -
6470 - cluster2_core0_watchdog: wdt@c100000 {
6471 - compatible = "arm,sp805-wdt", "arm,primecell";
6472 - reg = <0x0 0xc100000 0x0 0x1000>;
6473 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6474 - clock-names = "apb_pclk", "wdog_clk";
6475 - };
6476 -
6477 - cluster2_core1_watchdog: wdt@c110000 {
6478 - compatible = "arm,sp805-wdt", "arm,primecell";
6479 - reg = <0x0 0xc110000 0x0 0x1000>;
6480 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6481 - clock-names = "apb_pclk", "wdog_clk";
6482 - };
6483 -
6484 - cluster3_core0_watchdog: wdt@c200000 {
6485 - compatible = "arm,sp805-wdt", "arm,primecell";
6486 - reg = <0x0 0xc200000 0x0 0x1000>;
6487 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6488 - clock-names = "apb_pclk", "wdog_clk";
6489 - };
6490 -
6491 - cluster3_core1_watchdog: wdt@c210000 {
6492 - compatible = "arm,sp805-wdt", "arm,primecell";
6493 - reg = <0x0 0xc210000 0x0 0x1000>;
6494 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6495 - clock-names = "apb_pclk", "wdog_clk";
6496 - };
6497 -
6498 - cluster4_core0_watchdog: wdt@c300000 {
6499 - compatible = "arm,sp805-wdt", "arm,primecell";
6500 - reg = <0x0 0xc300000 0x0 0x1000>;
6501 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6502 - clock-names = "apb_pclk", "wdog_clk";
6503 - };
6504 -
6505 - cluster4_core1_watchdog: wdt@c310000 {
6506 - compatible = "arm,sp805-wdt", "arm,primecell";
6507 - reg = <0x0 0xc310000 0x0 0x1000>;
6508 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6509 - clock-names = "apb_pclk", "wdog_clk";
6510 - };
6511 -
6512 - fsl_mc: fsl-mc@80c000000 {
6513 - compatible = "fsl,qoriq-mc";
6514 - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
6515 - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
6516 - msi-parent = <&its>;
6517 - #address-cells = <3>;
6518 - #size-cells = <1>;
6519 -
6520 - /*
6521 - * Region type 0x0 - MC portals
6522 - * Region type 0x1 - QBMAN portals
6523 - */
6524 - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
6525 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
6526 -
6527 - /*
6528 - * Define the maximum number of MACs present on the SoC.
6529 - */
6530 - dpmacs {
6531 - #address-cells = <1>;
6532 - #size-cells = <0>;
6533 -
6534 - dpmac1: dpmac@1 {
6535 - compatible = "fsl,qoriq-mc-dpmac";
6536 - reg = <0x1>;
6537 - };
6538 -
6539 - dpmac2: dpmac@2 {
6540 - compatible = "fsl,qoriq-mc-dpmac";
6541 - reg = <0x2>;
6542 - };
6543 -
6544 - dpmac3: dpmac@3 {
6545 - compatible = "fsl,qoriq-mc-dpmac";
6546 - reg = <0x3>;
6547 - };
6548 -
6549 - dpmac4: dpmac@4 {
6550 - compatible = "fsl,qoriq-mc-dpmac";
6551 - reg = <0x4>;
6552 - };
6553 -
6554 - dpmac5: dpmac@5 {
6555 - compatible = "fsl,qoriq-mc-dpmac";
6556 - reg = <0x5>;
6557 - };
6558 -
6559 - dpmac6: dpmac@6 {
6560 - compatible = "fsl,qoriq-mc-dpmac";
6561 - reg = <0x6>;
6562 - };
6563 -
6564 - dpmac7: dpmac@7 {
6565 - compatible = "fsl,qoriq-mc-dpmac";
6566 - reg = <0x7>;
6567 - };
6568 -
6569 - dpmac8: dpmac@8 {
6570 - compatible = "fsl,qoriq-mc-dpmac";
6571 - reg = <0x8>;
6572 - };
6573 -
6574 - dpmac9: dpmac@9 {
6575 - compatible = "fsl,qoriq-mc-dpmac";
6576 - reg = <0x9>;
6577 - };
6578 -
6579 - dpmac10: dpmac@a {
6580 - compatible = "fsl,qoriq-mc-dpmac";
6581 - reg = <0xa>;
6582 - };
6583 -
6584 - dpmac11: dpmac@b {
6585 - compatible = "fsl,qoriq-mc-dpmac";
6586 - reg = <0xb>;
6587 - };
6588 -
6589 - dpmac12: dpmac@c {
6590 - compatible = "fsl,qoriq-mc-dpmac";
6591 - reg = <0xc>;
6592 - };
6593 -
6594 - dpmac13: dpmac@d {
6595 - compatible = "fsl,qoriq-mc-dpmac";
6596 - reg = <0xd>;
6597 - };
6598 -
6599 - dpmac14: dpmac@e {
6600 - compatible = "fsl,qoriq-mc-dpmac";
6601 - reg = <0xe>;
6602 - };
6603 -
6604 - dpmac15: dpmac@f {
6605 - compatible = "fsl,qoriq-mc-dpmac";
6606 - reg = <0xf>;
6607 - };
6608 -
6609 - dpmac16: dpmac@10 {
6610 - compatible = "fsl,qoriq-mc-dpmac";
6611 - reg = <0x10>;
6612 - };
6613 - };
6614 - };
6615 -
6616 - smmu: iommu@5000000 {
6617 - compatible = "arm,mmu-500";
6618 - reg = <0 0x5000000 0 0x800000>;
6619 - #global-interrupts = <12>;
6620 - interrupts = <0 13 4>, /* global secure fault */
6621 - <0 14 4>, /* combined secure interrupt */
6622 - <0 15 4>, /* global non-secure fault */
6623 - <0 16 4>, /* combined non-secure interrupt */
6624 - /* performance counter interrupts 0-7 */
6625 - <0 211 4>, <0 212 4>,
6626 - <0 213 4>, <0 214 4>,
6627 - <0 215 4>, <0 216 4>,
6628 - <0 217 4>, <0 218 4>,
6629 - /* per context interrupt, 64 interrupts */
6630 - <0 146 4>, <0 147 4>,
6631 - <0 148 4>, <0 149 4>,
6632 - <0 150 4>, <0 151 4>,
6633 - <0 152 4>, <0 153 4>,
6634 - <0 154 4>, <0 155 4>,
6635 - <0 156 4>, <0 157 4>,
6636 - <0 158 4>, <0 159 4>,
6637 - <0 160 4>, <0 161 4>,
6638 - <0 162 4>, <0 163 4>,
6639 - <0 164 4>, <0 165 4>,
6640 - <0 166 4>, <0 167 4>,
6641 - <0 168 4>, <0 169 4>,
6642 - <0 170 4>, <0 171 4>,
6643 - <0 172 4>, <0 173 4>,
6644 - <0 174 4>, <0 175 4>,
6645 - <0 176 4>, <0 177 4>,
6646 - <0 178 4>, <0 179 4>,
6647 - <0 180 4>, <0 181 4>,
6648 - <0 182 4>, <0 183 4>,
6649 - <0 184 4>, <0 185 4>,
6650 - <0 186 4>, <0 187 4>,
6651 - <0 188 4>, <0 189 4>,
6652 - <0 190 4>, <0 191 4>,
6653 - <0 192 4>, <0 193 4>,
6654 - <0 194 4>, <0 195 4>,
6655 - <0 196 4>, <0 197 4>,
6656 - <0 198 4>, <0 199 4>,
6657 - <0 200 4>, <0 201 4>,
6658 - <0 202 4>, <0 203 4>,
6659 - <0 204 4>, <0 205 4>,
6660 - <0 206 4>, <0 207 4>,
6661 - <0 208 4>, <0 209 4>;
6662 - mmu-masters = <&fsl_mc 0x300 0>;
6663 - };
6664 -
6665 - dspi: dspi@2100000 {
6666 - status = "disabled";
6667 - compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
6668 - #address-cells = <1>;
6669 - #size-cells = <0>;
6670 - reg = <0x0 0x2100000 0x0 0x10000>;
6671 - interrupts = <0 26 0x4>; /* Level high type */
6672 - clocks = <&clockgen 4 3>;
6673 - clock-names = "dspi";
6674 - spi-num-chipselects = <5>;
6675 - bus-num = <0>;
6676 - };
6677 -
6678 - esdhc: esdhc@2140000 {
6679 - status = "disabled";
6680 - compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
6681 - reg = <0x0 0x2140000 0x0 0x10000>;
6682 - interrupts = <0 28 0x4>; /* Level high type */
6683 - clock-frequency = <0>; /* Updated by bootloader */
6684 - voltage-ranges = <1800 1800 3300 3300>;
6685 - sdhci,auto-cmd12;
6686 - little-endian;
6687 - bus-width = <4>;
6688 - };
6689 -
6690 - gpio0: gpio@2300000 {
6691 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6692 - reg = <0x0 0x2300000 0x0 0x10000>;
6693 - interrupts = <0 36 0x4>; /* Level high type */
6694 - gpio-controller;
6695 - little-endian;
6696 - #gpio-cells = <2>;
6697 - interrupt-controller;
6698 - #interrupt-cells = <2>;
6699 - };
6700 -
6701 - gpio1: gpio@2310000 {
6702 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6703 - reg = <0x0 0x2310000 0x0 0x10000>;
6704 - interrupts = <0 36 0x4>; /* Level high type */
6705 - gpio-controller;
6706 - little-endian;
6707 - #gpio-cells = <2>;
6708 - interrupt-controller;
6709 - #interrupt-cells = <2>;
6710 - };
6711 -
6712 - gpio2: gpio@2320000 {
6713 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6714 - reg = <0x0 0x2320000 0x0 0x10000>;
6715 - interrupts = <0 37 0x4>; /* Level high type */
6716 - gpio-controller;
6717 - little-endian;
6718 - #gpio-cells = <2>;
6719 - interrupt-controller;
6720 - #interrupt-cells = <2>;
6721 - };
6722 -
6723 - gpio3: gpio@2330000 {
6724 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6725 - reg = <0x0 0x2330000 0x0 0x10000>;
6726 - interrupts = <0 37 0x4>; /* Level high type */
6727 - gpio-controller;
6728 - little-endian;
6729 - #gpio-cells = <2>;
6730 - interrupt-controller;
6731 - #interrupt-cells = <2>;
6732 - };
6733 -
6734 - i2c0: i2c@2000000 {
6735 - status = "disabled";
6736 - compatible = "fsl,vf610-i2c";
6737 - #address-cells = <1>;
6738 - #size-cells = <0>;
6739 - reg = <0x0 0x2000000 0x0 0x10000>;
6740 - interrupts = <0 34 0x4>; /* Level high type */
6741 - clock-names = "i2c";
6742 - clocks = <&clockgen 4 3>;
6743 - };
6744 -
6745 - i2c1: i2c@2010000 {
6746 - status = "disabled";
6747 - compatible = "fsl,vf610-i2c";
6748 - #address-cells = <1>;
6749 - #size-cells = <0>;
6750 - reg = <0x0 0x2010000 0x0 0x10000>;
6751 - interrupts = <0 34 0x4>; /* Level high type */
6752 - clock-names = "i2c";
6753 - clocks = <&clockgen 4 3>;
6754 - };
6755 -
6756 - i2c2: i2c@2020000 {
6757 - status = "disabled";
6758 - compatible = "fsl,vf610-i2c";
6759 - #address-cells = <1>;
6760 - #size-cells = <0>;
6761 - reg = <0x0 0x2020000 0x0 0x10000>;
6762 - interrupts = <0 35 0x4>; /* Level high type */
6763 - clock-names = "i2c";
6764 - clocks = <&clockgen 4 3>;
6765 - };
6766 -
6767 - i2c3: i2c@2030000 {
6768 - status = "disabled";
6769 - compatible = "fsl,vf610-i2c";
6770 - #address-cells = <1>;
6771 - #size-cells = <0>;
6772 - reg = <0x0 0x2030000 0x0 0x10000>;
6773 - interrupts = <0 35 0x4>; /* Level high type */
6774 - clock-names = "i2c";
6775 - clocks = <&clockgen 4 3>;
6776 - };
6777 -
6778 - ifc: ifc@2240000 {
6779 - compatible = "fsl,ifc", "simple-bus";
6780 - reg = <0x0 0x2240000 0x0 0x20000>;
6781 - interrupts = <0 21 0x4>; /* Level high type */
6782 - little-endian;
6783 - #address-cells = <2>;
6784 - #size-cells = <1>;
6785 -
6786 - ranges = <0 0 0x5 0x80000000 0x08000000
6787 - 2 0 0x5 0x30000000 0x00010000
6788 - 3 0 0x5 0x20000000 0x00010000>;
6789 - };
6790 -
6791 - qspi: quadspi@20c0000 {
6792 - status = "disabled";
6793 - compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
6794 - #address-cells = <1>;
6795 - #size-cells = <0>;
6796 - reg = <0x0 0x20c0000 0x0 0x10000>,
6797 - <0x0 0x20000000 0x0 0x10000000>;
6798 - reg-names = "QuadSPI", "QuadSPI-memory";
6799 - interrupts = <0 25 0x4>; /* Level high type */
6800 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6801 - clock-names = "qspi_en", "qspi";
6802 - };
6803 -
6804 - pcie@3400000 {
6805 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
6806 - "snps,dw-pcie";
6807 - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
6808 - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
6809 - reg-names = "regs", "config";
6810 - interrupts = <0 108 0x4>; /* Level high type */
6811 - interrupt-names = "intr";
6812 - #address-cells = <3>;
6813 - #size-cells = <2>;
6814 - device_type = "pci";
6815 - dma-coherent;
6816 - num-lanes = <4>;
6817 - bus-range = <0x0 0xff>;
6818 - ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
6819 - 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6820 - msi-parent = <&its>;
6821 - #interrupt-cells = <1>;
6822 - interrupt-map-mask = <0 0 0 7>;
6823 - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
6824 - <0000 0 0 2 &gic 0 0 0 110 4>,
6825 - <0000 0 0 3 &gic 0 0 0 111 4>,
6826 - <0000 0 0 4 &gic 0 0 0 112 4>;
6827 - };
6828 -
6829 - pcie@3500000 {
6830 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
6831 - "snps,dw-pcie";
6832 - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
6833 - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
6834 - reg-names = "regs", "config";
6835 - interrupts = <0 113 0x4>; /* Level high type */
6836 - interrupt-names = "intr";
6837 - #address-cells = <3>;
6838 - #size-cells = <2>;
6839 - device_type = "pci";
6840 - dma-coherent;
6841 - num-lanes = <4>;
6842 - bus-range = <0x0 0xff>;
6843 - ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
6844 - 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6845 - msi-parent = <&its>;
6846 - #interrupt-cells = <1>;
6847 - interrupt-map-mask = <0 0 0 7>;
6848 - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
6849 - <0000 0 0 2 &gic 0 0 0 115 4>,
6850 - <0000 0 0 3 &gic 0 0 0 116 4>,
6851 - <0000 0 0 4 &gic 0 0 0 117 4>;
6852 - };
6853 -
6854 - pcie@3600000 {
6855 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
6856 - "snps,dw-pcie";
6857 - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
6858 - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
6859 - reg-names = "regs", "config";
6860 - interrupts = <0 118 0x4>; /* Level high type */
6861 - interrupt-names = "intr";
6862 - #address-cells = <3>;
6863 - #size-cells = <2>;
6864 - device_type = "pci";
6865 - dma-coherent;
6866 - num-lanes = <8>;
6867 - bus-range = <0x0 0xff>;
6868 - ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
6869 - 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6870 - msi-parent = <&its>;
6871 - #interrupt-cells = <1>;
6872 - interrupt-map-mask = <0 0 0 7>;
6873 - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
6874 - <0000 0 0 2 &gic 0 0 0 120 4>,
6875 - <0000 0 0 3 &gic 0 0 0 121 4>,
6876 - <0000 0 0 4 &gic 0 0 0 122 4>;
6877 - };
6878 -
6879 - pcie@3700000 {
6880 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
6881 - "snps,dw-pcie";
6882 - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
6883 - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
6884 - reg-names = "regs", "config";
6885 - interrupts = <0 123 0x4>; /* Level high type */
6886 - interrupt-names = "intr";
6887 - #address-cells = <3>;
6888 - #size-cells = <2>;
6889 - device_type = "pci";
6890 - dma-coherent;
6891 - num-lanes = <4>;
6892 - bus-range = <0x0 0xff>;
6893 - ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
6894 - 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6895 - msi-parent = <&its>;
6896 - #interrupt-cells = <1>;
6897 - interrupt-map-mask = <0 0 0 7>;
6898 - interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
6899 - <0000 0 0 2 &gic 0 0 0 125 4>,
6900 - <0000 0 0 3 &gic 0 0 0 126 4>,
6901 - <0000 0 0 4 &gic 0 0 0 127 4>;
6902 - };
6903 -
6904 - sata0: sata@3200000 {
6905 - status = "disabled";
6906 - compatible = "fsl,ls2080a-ahci";
6907 - reg = <0x0 0x3200000 0x0 0x10000>;
6908 - interrupts = <0 133 0x4>; /* Level high type */
6909 - clocks = <&clockgen 4 3>;
6910 - dma-coherent;
6911 - };
6912 -
6913 - sata1: sata@3210000 {
6914 - status = "disabled";
6915 - compatible = "fsl,ls2080a-ahci";
6916 - reg = <0x0 0x3210000 0x0 0x10000>;
6917 - interrupts = <0 136 0x4>; /* Level high type */
6918 - clocks = <&clockgen 4 3>;
6919 - dma-coherent;
6920 - };
6921 -
6922 - usb0: usb3@3100000 {
6923 - status = "disabled";
6924 - compatible = "snps,dwc3";
6925 - reg = <0x0 0x3100000 0x0 0x10000>;
6926 - interrupts = <0 80 0x4>; /* Level high type */
6927 - dr_mode = "host";
6928 - snps,quirk-frame-length-adjustment = <0x20>;
6929 - snps,dis_rxdet_inp3_quirk;
6930 - };
6931 -
6932 - usb1: usb3@3110000 {
6933 - status = "disabled";
6934 - compatible = "snps,dwc3";
6935 - reg = <0x0 0x3110000 0x0 0x10000>;
6936 - interrupts = <0 81 0x4>; /* Level high type */
6937 - dr_mode = "host";
6938 - snps,quirk-frame-length-adjustment = <0x20>;
6939 - snps,dis_rxdet_inp3_quirk;
6940 - };
6941 -
6942 - ccn@4000000 {
6943 - compatible = "arm,ccn-504";
6944 - reg = <0x0 0x04000000 0x0 0x01000000>;
6945 - interrupts = <0 12 4>;
6946 - };
6947 - };
6948 -
6949 - ddr1: memory-controller@1080000 {
6950 - compatible = "fsl,qoriq-memory-controller";
6951 - reg = <0x0 0x1080000 0x0 0x1000>;
6952 - interrupts = <0 17 0x4>;
6953 - little-endian;
6954 - };
6955 -
6956 - ddr2: memory-controller@1090000 {
6957 - compatible = "fsl,qoriq-memory-controller";
6958 - reg = <0x0 0x1090000 0x0 0x1000>;
6959 - interrupts = <0 18 0x4>;
6960 - little-endian;
6961 +#include "fsl-ls208xa.dtsi"
6962 +
6963 +&cpu {
6964 + cpu0: cpu@0 {
6965 + device_type = "cpu";
6966 + compatible = "arm,cortex-a57";
6967 + reg = <0x0>;
6968 + clocks = <&clockgen 1 0>;
6969 + next-level-cache = <&cluster0_l2>;
6970 + #cooling-cells = <2>;
6971 + };
6972 +
6973 + cpu1: cpu@1 {
6974 + device_type = "cpu";
6975 + compatible = "arm,cortex-a57";
6976 + reg = <0x1>;
6977 + clocks = <&clockgen 1 0>;
6978 + next-level-cache = <&cluster0_l2>;
6979 + };
6980 +
6981 + cpu2: cpu@100 {
6982 + device_type = "cpu";
6983 + compatible = "arm,cortex-a57";
6984 + reg = <0x100>;
6985 + clocks = <&clockgen 1 1>;
6986 + next-level-cache = <&cluster1_l2>;
6987 + #cooling-cells = <2>;
6988 + };
6989 +
6990 + cpu3: cpu@101 {
6991 + device_type = "cpu";
6992 + compatible = "arm,cortex-a57";
6993 + reg = <0x101>;
6994 + clocks = <&clockgen 1 1>;
6995 + next-level-cache = <&cluster1_l2>;
6996 + };
6997 +
6998 + cpu4: cpu@200 {
6999 + device_type = "cpu";
7000 + compatible = "arm,cortex-a57";
7001 + reg = <0x200>;
7002 + clocks = <&clockgen 1 2>;
7003 + next-level-cache = <&cluster2_l2>;
7004 + #cooling-cells = <2>;
7005 + };
7006 +
7007 + cpu5: cpu@201 {
7008 + device_type = "cpu";
7009 + compatible = "arm,cortex-a57";
7010 + reg = <0x201>;
7011 + clocks = <&clockgen 1 2>;
7012 + next-level-cache = <&cluster2_l2>;
7013 + };
7014 +
7015 + cpu6: cpu@300 {
7016 + device_type = "cpu";
7017 + compatible = "arm,cortex-a57";
7018 + reg = <0x300>;
7019 + clocks = <&clockgen 1 3>;
7020 + next-level-cache = <&cluster3_l2>;
7021 + #cooling-cells = <2>;
7022 + };
7023 +
7024 + cpu7: cpu@301 {
7025 + device_type = "cpu";
7026 + compatible = "arm,cortex-a57";
7027 + reg = <0x301>;
7028 + clocks = <&clockgen 1 3>;
7029 + next-level-cache = <&cluster3_l2>;
7030 };
7031 +
7032 + cluster0_l2: l2-cache0 {
7033 + compatible = "cache";
7034 + };
7035 +
7036 + cluster1_l2: l2-cache1 {
7037 + compatible = "cache";
7038 + };
7039 +
7040 + cluster2_l2: l2-cache2 {
7041 + compatible = "cache";
7042 + };
7043 +
7044 + cluster3_l2: l2-cache3 {
7045 + compatible = "cache";
7046 + };
7047 +};
7048 +
7049 +&usb0 {
7050 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7051 + snps,dma-snooping;
7052 +};
7053 +
7054 +&usb1 {
7055 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7056 + snps,dma-snooping;
7057 +};
7058 +
7059 +&pcie1 {
7060 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7061 + 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7062 +
7063 + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7064 + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7065 +};
7066 +
7067 +&pcie2 {
7068 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7069 + 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7070 +
7071 + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7072 + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7073 +};
7074 +
7075 +&pcie3 {
7076 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7077 + 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7078 +
7079 + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7080 + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7081 +};
7082 +
7083 +&pcie4 {
7084 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7085 + 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7086 +
7087 + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7088 + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7089 };
7090 --- /dev/null
7091 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
7092 @@ -0,0 +1,161 @@
7093 +/*
7094 + * Device Tree file for NXP LS2081A RDB Board.
7095 + *
7096 + * Copyright 2017 NXP
7097 + *
7098 + * Priyanka Jain <priyanka.jain@nxp.com>
7099 + *
7100 + * This file is dual-licensed: you can use it either under the terms
7101 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7102 + * licensing only applies to this file, and not this project as a
7103 + * whole.
7104 + *
7105 + * a) This library is free software; you can redistribute it and/or
7106 + * modify it under the terms of the GNU General Public License as
7107 + * published by the Free Software Foundation; either version 2 of the
7108 + * License, or (at your option) any later version.
7109 + *
7110 + * This library is distributed in the hope that it will be useful,
7111 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7112 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7113 + * GNU General Public License for more details.
7114 + *
7115 + * Or, alternatively,
7116 + *
7117 + * b) Permission is hereby granted, free of charge, to any person
7118 + * obtaining a copy of this software and associated documentation
7119 + * files (the "Software"), to deal in the Software without
7120 + * restriction, including without limitation the rights to use,
7121 + * copy, modify, merge, publish, distribute, sublicense, and/or
7122 + * sell copies of the Software, and to permit persons to whom the
7123 + * Software is furnished to do so, subject to the following
7124 + * conditions:
7125 + *
7126 + * The above copyright notice and this permission notice shall be
7127 + * included in all copies or substantial portions of the Software.
7128 + *
7129 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7130 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7131 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7132 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7133 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7134 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7135 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7136 + * OTHER DEALINGS IN THE SOFTWARE.
7137 + */
7138 +
7139 +/dts-v1/;
7140 +
7141 +#include "fsl-ls2088a.dtsi"
7142 +
7143 +/ {
7144 + model = "NXP Layerscape 2081A RDB Board";
7145 + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
7146 +
7147 + aliases {
7148 + serial0 = &serial0;
7149 + serial1 = &serial1;
7150 + };
7151 +
7152 + chosen {
7153 + stdout-path = "serial1:115200n8";
7154 + };
7155 +};
7156 +
7157 +&esdhc {
7158 + status = "okay";
7159 +};
7160 +
7161 +&ifc {
7162 + status = "disabled";
7163 +};
7164 +
7165 +&i2c0 {
7166 + status = "okay";
7167 + pca9547@75 {
7168 + compatible = "nxp,pca9547";
7169 + reg = <0x75>;
7170 + #address-cells = <1>;
7171 + #size-cells = <0>;
7172 + i2c@1 {
7173 + #address-cells = <1>;
7174 + #size-cells = <0>;
7175 + reg = <0x01>;
7176 + rtc@51 {
7177 + compatible = "nxp,pcf2129";
7178 + reg = <0x51>;
7179 + };
7180 + };
7181 +
7182 + i2c@2 {
7183 + #address-cells = <1>;
7184 + #size-cells = <0>;
7185 + reg = <0x02>;
7186 +
7187 + ina220@40 {
7188 + compatible = "ti,ina220";
7189 + reg = <0x40>;
7190 + shunt-resistor = <500>;
7191 + };
7192 + };
7193 +
7194 + i2c@3 {
7195 + #address-cells = <1>;
7196 + #size-cells = <0>;
7197 + reg = <0x3>;
7198 +
7199 + adt7481@4c {
7200 + compatible = "adi,adt7461";
7201 + reg = <0x4c>;
7202 + };
7203 + };
7204 + };
7205 +};
7206 +
7207 +&dspi {
7208 + status = "okay";
7209 + dflash0: n25q512a {
7210 + #address-cells = <1>;
7211 + #size-cells = <1>;
7212 + compatible = "st,m25p80";
7213 + spi-max-frequency = <3000000>;
7214 + reg = <0>;
7215 + };
7216 +};
7217 +
7218 +&qspi {
7219 + status = "okay";
7220 + fsl,qspi-has-second-chip;
7221 + flash0: s25fs512s@0 {
7222 + #address-cells = <1>;
7223 + #size-cells = <1>;
7224 + compatible = "spansion,m25p80";
7225 + m25p,fast-read;
7226 + spi-max-frequency = <20000000>;
7227 + reg = <0>;
7228 + };
7229 + flash1: s25fs512s@1 {
7230 + #address-cells = <1>;
7231 + #size-cells = <1>;
7232 + compatible = "spansion,m25p80";
7233 + m25p,fast-read;
7234 + spi-max-frequency = <20000000>;
7235 + reg = <1>;
7236 + };
7237 +};
7238 +
7239 +&sata0 {
7240 + status = "okay";
7241 +};
7242 +
7243 +&sata1 {
7244 + status = "okay";
7245 +};
7246 +
7247 +&usb0 {
7248 + status = "okay";
7249 +};
7250 +
7251 +&usb1 {
7252 + status = "okay";
7253 +};
7254 --- /dev/null
7255 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
7256 @@ -0,0 +1,162 @@
7257 +/*
7258 + * Device Tree file for Freescale LS2088A QDS Board.
7259 + *
7260 + * Copyright 2016 Freescale Semiconductor, Inc.
7261 + * Copyright 2017 NXP
7262 + *
7263 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7264 + *
7265 + * This file is dual-licensed: you can use it either under the terms
7266 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7267 + * licensing only applies to this file, and not this project as a
7268 + * whole.
7269 + *
7270 + * a) This library is free software; you can redistribute it and/or
7271 + * modify it under the terms of the GNU General Public License as
7272 + * published by the Free Software Foundation; either version 2 of the
7273 + * License, or (at your option) any later version.
7274 + *
7275 + * This library is distributed in the hope that it will be useful,
7276 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7277 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7278 + * GNU General Public License for more details.
7279 + *
7280 + * Or, alternatively,
7281 + *
7282 + * b) Permission is hereby granted, free of charge, to any person
7283 + * obtaining a copy of this software and associated documentation
7284 + * files (the "Software"), to deal in the Software without
7285 + * restriction, including without limitation the rights to use,
7286 + * copy, modify, merge, publish, distribute, sublicense, and/or
7287 + * sell copies of the Software, and to permit persons to whom the
7288 + * Software is furnished to do so, subject to the following
7289 + * conditions:
7290 + *
7291 + * The above copyright notice and this permission notice shall be
7292 + * included in all copies or substantial portions of the Software.
7293 + *
7294 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7295 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7296 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7297 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7298 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7299 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7300 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7301 + * OTHER DEALINGS IN THE SOFTWARE.
7302 + */
7303 +
7304 +/dts-v1/;
7305 +
7306 +#include "fsl-ls2088a.dtsi"
7307 +#include "fsl-ls208xa-qds.dtsi"
7308 +
7309 +/ {
7310 + model = "Freescale Layerscape 2088A QDS Board";
7311 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
7312 +
7313 + chosen {
7314 + stdout-path = "serial0:115200n8";
7315 + };
7316 +};
7317 +
7318 +&ifc {
7319 + boardctrl: board-control@3,0 {
7320 + #address-cells = <1>;
7321 + #size-cells = <1>;
7322 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
7323 + reg = <3 0 0x300>; /* TODO check address */
7324 + ranges = <0 3 0 0x300>;
7325 +
7326 + mdio_mux_emi1 {
7327 + compatible = "mdio-mux-mmioreg", "mdio-mux";
7328 + mdio-parent-bus = <&emdio1>;
7329 + reg = <0x54 1>; /* BRDCFG4 */
7330 + mux-mask = <0xe0>; /* EMI1_MDIO */
7331 +
7332 + #address-cells=<1>;
7333 + #size-cells = <0>;
7334 +
7335 + /* Child MDIO buses, one for each riser card:
7336 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
7337 + * VSC8234 PHYs on the riser cards.
7338 + */
7339 +
7340 + mdio_mux3: mdio@60 {
7341 + reg = <0x60>;
7342 + #address-cells = <1>;
7343 + #size-cells = <0>;
7344 +
7345 + mdio0_phy12: mdio_phy0@1c {
7346 + reg = <0x1c>;
7347 + phy-connection-type = "sgmii";
7348 + };
7349 + mdio0_phy13: mdio_phy1@1d {
7350 + reg = <0x1d>;
7351 + phy-connection-type = "sgmii";
7352 + };
7353 + mdio0_phy14: mdio_phy2@1e {
7354 + reg = <0x1e>;
7355 + phy-connection-type = "sgmii";
7356 + };
7357 + mdio0_phy15: mdio_phy3@1f {
7358 + reg = <0x1f>;
7359 + phy-connection-type = "sgmii";
7360 + };
7361 + };
7362 + };
7363 + };
7364 +};
7365 +
7366 +&pcs_mdio1 {
7367 + pcs_phy1: ethernet-phy@0 {
7368 + backplane-mode = "10gbase-kr";
7369 + compatible = "ethernet-phy-ieee802.3-c45";
7370 + reg = <0x0>;
7371 + fsl,lane-handle = <&serdes1>;
7372 + fsl,lane-reg = <0x9C0 0x40>;/* lane H */
7373 + };
7374 +};
7375 +
7376 +&pcs_mdio2 {
7377 + pcs_phy2: ethernet-phy@0 {
7378 + backplane-mode = "10gbase-kr";
7379 + compatible = "ethernet-phy-ieee802.3-c45";
7380 + reg = <0x0>;
7381 + fsl,lane-handle = <&serdes1>;
7382 + fsl,lane-reg = <0x980 0x40>;/* lane G */
7383 + };
7384 +};
7385 +
7386 +&pcs_mdio3 {
7387 + pcs_phy3: ethernet-phy@0 {
7388 + backplane-mode = "10gbase-kr";
7389 + compatible = "ethernet-phy-ieee802.3-c45";
7390 + reg = <0x0>;
7391 + fsl,lane-handle = <&serdes1>;
7392 + fsl,lane-reg = <0x940 0x40>;/* lane F */
7393 + };
7394 +};
7395 +
7396 +&pcs_mdio4 {
7397 + pcs_phy4: ethernet-phy@0 {
7398 + backplane-mode = "10gbase-kr";
7399 + compatible = "ethernet-phy-ieee802.3-c45";
7400 + reg = <0x0>;
7401 + fsl,lane-handle = <&serdes1>;
7402 + fsl,lane-reg = <0x900 0x40>;/* lane E */
7403 + };
7404 +};
7405 +
7406 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
7407 +&dpmac9 {
7408 + phy-handle = <&mdio0_phy12>;
7409 +};
7410 +&dpmac10 {
7411 + phy-handle = <&mdio0_phy13>;
7412 +};
7413 +&dpmac11 {
7414 + phy-handle = <&mdio0_phy14>;
7415 +};
7416 +&dpmac12 {
7417 + phy-handle = <&mdio0_phy15>;
7418 +};
7419 --- /dev/null
7420 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
7421 @@ -0,0 +1,140 @@
7422 +/*
7423 + * Device Tree file for Freescale LS2088A RDB Board.
7424 + *
7425 + * Copyright 2016 Freescale Semiconductor, Inc.
7426 + * Copyright 2017 NXP
7427 + *
7428 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7429 + *
7430 + * This file is dual-licensed: you can use it either under the terms
7431 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7432 + * licensing only applies to this file, and not this project as a
7433 + * whole.
7434 + *
7435 + * a) This library is free software; you can redistribute it and/or
7436 + * modify it under the terms of the GNU General Public License as
7437 + * published by the Free Software Foundation; either version 2 of the
7438 + * License, or (at your option) any later version.
7439 + *
7440 + * This library is distributed in the hope that it will be useful,
7441 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7442 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7443 + * GNU General Public License for more details.
7444 + *
7445 + * Or, alternatively,
7446 + *
7447 + * b) Permission is hereby granted, free of charge, to any person
7448 + * obtaining a copy of this software and associated documentation
7449 + * files (the "Software"), to deal in the Software without
7450 + * restriction, including without limitation the rights to use,
7451 + * copy, modify, merge, publish, distribute, sublicense, and/or
7452 + * sell copies of the Software, and to permit persons to whom the
7453 + * Software is furnished to do so, subject to the following
7454 + * conditions:
7455 + *
7456 + * The above copyright notice and this permission notice shall be
7457 + * included in all copies or substantial portions of the Software.
7458 + *
7459 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7460 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7461 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7462 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7463 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7464 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7465 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7466 + * OTHER DEALINGS IN THE SOFTWARE.
7467 + */
7468 +
7469 +/dts-v1/;
7470 +
7471 +#include "fsl-ls2088a.dtsi"
7472 +#include "fsl-ls208xa-rdb.dtsi"
7473 +
7474 +/ {
7475 + model = "Freescale Layerscape 2088A RDB Board";
7476 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
7477 +
7478 + chosen {
7479 + stdout-path = "serial1:115200n8";
7480 + };
7481 +};
7482 +
7483 +&emdio1 {
7484 + status = "disabled";
7485 + /* CS4340 PHYs */
7486 + mdio1_phy1: emdio1_phy@1 {
7487 + reg = <0x10>;
7488 + phy-connection-type = "xfi";
7489 + };
7490 + mdio1_phy2: emdio1_phy@2 {
7491 + reg = <0x11>;
7492 + phy-connection-type = "xfi";
7493 + };
7494 + mdio1_phy3: emdio1_phy@3 {
7495 + reg = <0x12>;
7496 + phy-connection-type = "xfi";
7497 + };
7498 + mdio1_phy4: emdio1_phy@4 {
7499 + reg = <0x13>;
7500 + phy-connection-type = "xfi";
7501 + };
7502 +};
7503 +
7504 +&emdio2 {
7505 + /* AQR405 PHYs */
7506 + mdio2_phy1: emdio2_phy@1 {
7507 + compatible = "ethernet-phy-ieee802.3-c45";
7508 + interrupts = <0 1 0x4>; /* Level high type */
7509 + reg = <0x0>;
7510 + phy-connection-type = "xfi";
7511 + };
7512 + mdio2_phy2: emdio2_phy@2 {
7513 + compatible = "ethernet-phy-ieee802.3-c45";
7514 + interrupts = <0 2 0x4>; /* Level high type */
7515 + reg = <0x1>;
7516 + phy-connection-type = "xfi";
7517 + };
7518 + mdio2_phy3: emdio2_phy@3 {
7519 + compatible = "ethernet-phy-ieee802.3-c45";
7520 + interrupts = <0 4 0x4>; /* Level high type */
7521 + reg = <0x2>;
7522 + phy-connection-type = "xfi";
7523 + };
7524 + mdio2_phy4: emdio2_phy@4 {
7525 + compatible = "ethernet-phy-ieee802.3-c45";
7526 + interrupts = <0 5 0x4>; /* Level high type */
7527 + reg = <0x3>;
7528 + phy-connection-type = "xfi";
7529 + };
7530 +};
7531 +
7532 +/* Update DPMAC connections to external PHYs, under the assumption of
7533 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
7534 + */
7535 +/* Leave Cortina PHYs commented out until proper driver is integrated
7536 + *&dpmac1 {
7537 + * phy-handle = <&mdio1_phy1>;
7538 + *};
7539 + *&dpmac2 {
7540 + * phy-handle = <&mdio1_phy2>;
7541 + *};
7542 + *&dpmac3 {
7543 + * phy-handle = <&mdio1_phy3>;
7544 + *};
7545 + *&dpmac4 {
7546 + * phy-handle = <&mdio1_phy4>;
7547 + *};
7548 + */
7549 +
7550 +&dpmac5 {
7551 + phy-handle = <&mdio2_phy1>;
7552 +};
7553 +&dpmac6 {
7554 + phy-handle = <&mdio2_phy2>;
7555 +};
7556 +&dpmac7 {
7557 + phy-handle = <&mdio2_phy3>;
7558 +};
7559 +&dpmac8 {
7560 + phy-handle = <&mdio2_phy4>;
7561 +};
7562 --- /dev/null
7563 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
7564 @@ -0,0 +1,195 @@
7565 +/*
7566 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
7567 + *
7568 + * Copyright 2016 Freescale Semiconductor, Inc.
7569 + * Copyright 2017 NXP
7570 + *
7571 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7572 + *
7573 + * This file is dual-licensed: you can use it either under the terms
7574 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7575 + * licensing only applies to this file, and not this project as a
7576 + * whole.
7577 + *
7578 + * a) This library is free software; you can redistribute it and/or
7579 + * modify it under the terms of the GNU General Public License as
7580 + * published by the Free Software Foundation; either version 2 of the
7581 + * License, or (at your option) any later version.
7582 + *
7583 + * This library is distributed in the hope that it will be useful,
7584 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7585 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7586 + * GNU General Public License for more details.
7587 + *
7588 + * Or, alternatively,
7589 + *
7590 + * b) Permission is hereby granted, free of charge, to any person
7591 + * obtaining a copy of this software and associated documentation
7592 + * files (the "Software"), to deal in the Software without
7593 + * restriction, including without limitation the rights to use,
7594 + * copy, modify, merge, publish, distribute, sublicense, and/or
7595 + * sell copies of the Software, and to permit persons to whom the
7596 + * Software is furnished to do so, subject to the following
7597 + * conditions:
7598 + *
7599 + * The above copyright notice and this permission notice shall be
7600 + * included in all copies or substantial portions of the Software.
7601 + *
7602 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7603 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7604 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7605 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7606 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7607 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7608 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7609 + * OTHER DEALINGS IN THE SOFTWARE.
7610 + */
7611 +
7612 +#include "fsl-ls208xa.dtsi"
7613 +
7614 +&cpu {
7615 + cpu0: cpu@0 {
7616 + device_type = "cpu";
7617 + compatible = "arm,cortex-a72";
7618 + reg = <0x0>;
7619 + clocks = <&clockgen 1 0>;
7620 + next-level-cache = <&cluster0_l2>;
7621 + #cooling-cells = <2>;
7622 + cpu-idle-states = <&CPU_PH20>;
7623 + };
7624 +
7625 + cpu1: cpu@1 {
7626 + device_type = "cpu";
7627 + compatible = "arm,cortex-a72";
7628 + reg = <0x1>;
7629 + clocks = <&clockgen 1 0>;
7630 + next-level-cache = <&cluster0_l2>;
7631 + cpu-idle-states = <&CPU_PH20>;
7632 + };
7633 +
7634 + cpu2: cpu@100 {
7635 + device_type = "cpu";
7636 + compatible = "arm,cortex-a72";
7637 + reg = <0x100>;
7638 + clocks = <&clockgen 1 1>;
7639 + next-level-cache = <&cluster1_l2>;
7640 + #cooling-cells = <2>;
7641 + cpu-idle-states = <&CPU_PH20>;
7642 + };
7643 +
7644 + cpu3: cpu@101 {
7645 + device_type = "cpu";
7646 + compatible = "arm,cortex-a72";
7647 + reg = <0x101>;
7648 + clocks = <&clockgen 1 1>;
7649 + next-level-cache = <&cluster1_l2>;
7650 + cpu-idle-states = <&CPU_PH20>;
7651 + };
7652 +
7653 + cpu4: cpu@200 {
7654 + device_type = "cpu";
7655 + compatible = "arm,cortex-a72";
7656 + reg = <0x200>;
7657 + clocks = <&clockgen 1 2>;
7658 + next-level-cache = <&cluster2_l2>;
7659 + #cooling-cells = <2>;
7660 + cpu-idle-states = <&CPU_PH20>;
7661 + };
7662 +
7663 + cpu5: cpu@201 {
7664 + device_type = "cpu";
7665 + compatible = "arm,cortex-a72";
7666 + reg = <0x201>;
7667 + clocks = <&clockgen 1 2>;
7668 + next-level-cache = <&cluster2_l2>;
7669 + cpu-idle-states = <&CPU_PH20>;
7670 + };
7671 +
7672 + cpu6: cpu@300 {
7673 + device_type = "cpu";
7674 + compatible = "arm,cortex-a72";
7675 + reg = <0x300>;
7676 + clocks = <&clockgen 1 3>;
7677 + next-level-cache = <&cluster3_l2>;
7678 + #cooling-cells = <2>;
7679 + cpu-idle-states = <&CPU_PH20>;
7680 + };
7681 +
7682 + cpu7: cpu@301 {
7683 + device_type = "cpu";
7684 + compatible = "arm,cortex-a72";
7685 + reg = <0x301>;
7686 + clocks = <&clockgen 1 3>;
7687 + next-level-cache = <&cluster3_l2>;
7688 + cpu-idle-states = <&CPU_PH20>;
7689 + };
7690 +
7691 + idle-states {
7692 + /*
7693 + * PSCI node is not added default, U-boot will add missing
7694 + * parts if it determines to use PSCI.
7695 + */
7696 + entry-method = "arm,psci";
7697 +
7698 + CPU_PH20: cpu-ph20 {
7699 + compatible = "arm,idle-state";
7700 + idle-state-name = "PH20";
7701 + arm,psci-suspend-param = <0x0>;
7702 + entry-latency-us = <1000>;
7703 + exit-latency-us = <1000>;
7704 + min-residency-us = <3000>;
7705 + };
7706 + };
7707 +
7708 + cluster0_l2: l2-cache0 {
7709 + compatible = "cache";
7710 + };
7711 +
7712 + cluster1_l2: l2-cache1 {
7713 + compatible = "cache";
7714 + };
7715 +
7716 + cluster2_l2: l2-cache2 {
7717 + compatible = "cache";
7718 + };
7719 +
7720 + cluster3_l2: l2-cache3 {
7721 + compatible = "cache";
7722 + };
7723 +};
7724 +
7725 +&pcie1 {
7726 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7727 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7728 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
7729 +
7730 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
7731 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
7732 +};
7733 +
7734 +&pcie2 {
7735 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7736 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7737 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
7738 +
7739 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
7740 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
7741 +};
7742 +
7743 +&pcie3 {
7744 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7745 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7746 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
7747 +
7748 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
7749 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
7750 +};
7751 +
7752 +&pcie4 {
7753 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7754 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7755 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
7756 +
7757 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
7758 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
7759 +};
7760 --- /dev/null
7761 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
7762 @@ -0,0 +1,198 @@
7763 +/*
7764 + * Device Tree file for Freescale LS2080A QDS Board.
7765 + *
7766 + * Copyright 2016 Freescale Semiconductor, Inc.
7767 + * Copyright 2017 NXP
7768 + *
7769 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7770 + *
7771 + * This file is dual-licensed: you can use it either under the terms
7772 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7773 + * licensing only applies to this file, and not this project as a
7774 + * whole.
7775 + *
7776 + * a) This library is free software; you can redistribute it and/or
7777 + * modify it under the terms of the GNU General Public License as
7778 + * published by the Free Software Foundation; either version 2 of the
7779 + * License, or (at your option) any later version.
7780 + *
7781 + * This library is distributed in the hope that it will be useful,
7782 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7783 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7784 + * GNU General Public License for more details.
7785 + *
7786 + * Or, alternatively,
7787 + *
7788 + * b) Permission is hereby granted, free of charge, to any person
7789 + * obtaining a copy of this software and associated documentation
7790 + * files (the "Software"), to deal in the Software without
7791 + * restriction, including without limitation the rights to use,
7792 + * copy, modify, merge, publish, distribute, sublicense, and/or
7793 + * sell copies of the Software, and to permit persons to whom the
7794 + * Software is furnished to do so, subject to the following
7795 + * conditions:
7796 + *
7797 + * The above copyright notice and this permission notice shall be
7798 + * included in all copies or substantial portions of the Software.
7799 + *
7800 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7801 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7802 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7803 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7804 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7805 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7806 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7807 + * OTHER DEALINGS IN THE SOFTWARE.
7808 + */
7809 +
7810 +&esdhc {
7811 + mmc-hs200-1_8v;
7812 + status = "okay";
7813 +};
7814 +
7815 +&ifc {
7816 + status = "okay";
7817 + #address-cells = <2>;
7818 + #size-cells = <1>;
7819 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
7820 + 0x2 0x0 0x5 0x30000000 0x00010000
7821 + 0x3 0x0 0x5 0x20000000 0x00010000>;
7822 +
7823 + nor@0,0 {
7824 + #address-cells = <1>;
7825 + #size-cells = <1>;
7826 + compatible = "cfi-flash";
7827 + reg = <0x0 0x0 0x8000000>;
7828 + bank-width = <2>;
7829 + device-width = <1>;
7830 + };
7831 +
7832 + nand@2,0 {
7833 + compatible = "fsl,ifc-nand";
7834 + reg = <0x2 0x0 0x10000>;
7835 + };
7836 +
7837 + cpld@3,0 {
7838 + reg = <0x3 0x0 0x10000>;
7839 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
7840 + };
7841 +};
7842 +
7843 +&i2c0 {
7844 + status = "okay";
7845 + pca9547@77 {
7846 + compatible = "nxp,pca9547";
7847 + reg = <0x77>;
7848 + #address-cells = <1>;
7849 + #size-cells = <0>;
7850 + i2c@0 {
7851 + #address-cells = <1>;
7852 + #size-cells = <0>;
7853 + reg = <0x00>;
7854 + rtc@68 {
7855 + compatible = "dallas,ds3232";
7856 + reg = <0x68>;
7857 + };
7858 + };
7859 +
7860 + i2c@2 {
7861 + #address-cells = <1>;
7862 + #size-cells = <0>;
7863 + reg = <0x02>;
7864 +
7865 + ina220@40 {
7866 + compatible = "ti,ina220";
7867 + reg = <0x40>;
7868 + shunt-resistor = <500>;
7869 + };
7870 +
7871 + ina220@41 {
7872 + compatible = "ti,ina220";
7873 + reg = <0x41>;
7874 + shunt-resistor = <1000>;
7875 + };
7876 + };
7877 +
7878 + i2c@3 {
7879 + #address-cells = <1>;
7880 + #size-cells = <0>;
7881 + reg = <0x3>;
7882 +
7883 + adt7481@4c {
7884 + compatible = "adi,adt7461";
7885 + reg = <0x4c>;
7886 + };
7887 + };
7888 + };
7889 +};
7890 +
7891 +&i2c1 {
7892 + status = "disabled";
7893 +};
7894 +
7895 +&i2c2 {
7896 + status = "disabled";
7897 +};
7898 +
7899 +&i2c3 {
7900 + status = "disabled";
7901 +};
7902 +
7903 +&dspi {
7904 + status = "okay";
7905 + dflash0: n25q128a {
7906 + #address-cells = <1>;
7907 + #size-cells = <1>;
7908 + compatible = "st,m25p80";
7909 + spi-max-frequency = <3000000>;
7910 + reg = <0>;
7911 + };
7912 + dflash1: sst25wf040b {
7913 + #address-cells = <1>;
7914 + #size-cells = <1>;
7915 + compatible = "st,m25p80";
7916 + spi-max-frequency = <3000000>;
7917 + reg = <1>;
7918 + };
7919 + dflash2: en25s64 {
7920 + #address-cells = <1>;
7921 + #size-cells = <1>;
7922 + compatible = "st,m25p80";
7923 + spi-max-frequency = <3000000>;
7924 + reg = <2>;
7925 + };
7926 +};
7927 +
7928 +&qspi {
7929 + status = "okay";
7930 + flash0: s25fl256s1@0 {
7931 + #address-cells = <1>;
7932 + #size-cells = <1>;
7933 + compatible = "st,m25p80";
7934 + spi-max-frequency = <20000000>;
7935 + reg = <0>;
7936 + };
7937 + flash2: s25fl256s1@2 {
7938 + #address-cells = <1>;
7939 + #size-cells = <1>;
7940 + compatible = "st,m25p80";
7941 + spi-max-frequency = <20000000>;
7942 + reg = <0>;
7943 + };
7944 +};
7945 +
7946 +&sata0 {
7947 + status = "okay";
7948 +};
7949 +
7950 +&sata1 {
7951 + status = "okay";
7952 +};
7953 +
7954 +&usb0 {
7955 + status = "okay";
7956 +};
7957 +
7958 +&usb1 {
7959 + status = "okay";
7960 +};
7961 --- /dev/null
7962 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
7963 @@ -0,0 +1,161 @@
7964 +/*
7965 + * Device Tree file for Freescale LS2080A RDB Board.
7966 + *
7967 + * Copyright 2016 Freescale Semiconductor, Inc.
7968 + * Copyright 2017 NXP
7969 + *
7970 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7971 + *
7972 + * This file is dual-licensed: you can use it either under the terms
7973 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7974 + * licensing only applies to this file, and not this project as a
7975 + * whole.
7976 + *
7977 + * a) This library is free software; you can redistribute it and/or
7978 + * modify it under the terms of the GNU General Public License as
7979 + * published by the Free Software Foundation; either version 2 of the
7980 + * License, or (at your option) any later version.
7981 + *
7982 + * This library is distributed in the hope that it will be useful,
7983 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7984 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7985 + * GNU General Public License for more details.
7986 + *
7987 + * Or, alternatively,
7988 + *
7989 + * b) Permission is hereby granted, free of charge, to any person
7990 + * obtaining a copy of this software and associated documentation
7991 + * files (the "Software"), to deal in the Software without
7992 + * restriction, including without limitation the rights to use,
7993 + * copy, modify, merge, publish, distribute, sublicense, and/or
7994 + * sell copies of the Software, and to permit persons to whom the
7995 + * Software is furnished to do so, subject to the following
7996 + * conditions:
7997 + *
7998 + * The above copyright notice and this permission notice shall be
7999 + * included in all copies or substantial portions of the Software.
8000 + *
8001 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8002 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8003 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8004 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8005 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8006 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8007 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8008 + * OTHER DEALINGS IN THE SOFTWARE.
8009 + */
8010 +
8011 +&esdhc {
8012 + status = "okay";
8013 +};
8014 +
8015 +&ifc {
8016 + status = "okay";
8017 + #address-cells = <2>;
8018 + #size-cells = <1>;
8019 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8020 + 0x2 0x0 0x5 0x30000000 0x00010000
8021 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8022 +
8023 + nor@0,0 {
8024 + #address-cells = <1>;
8025 + #size-cells = <1>;
8026 + compatible = "cfi-flash";
8027 + reg = <0x0 0x0 0x8000000>;
8028 + bank-width = <2>;
8029 + device-width = <1>;
8030 + };
8031 +
8032 + nand@2,0 {
8033 + compatible = "fsl,ifc-nand";
8034 + reg = <0x2 0x0 0x10000>;
8035 + };
8036 +
8037 + cpld@3,0 {
8038 + reg = <0x3 0x0 0x10000>;
8039 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8040 + };
8041 +
8042 +};
8043 +
8044 +&i2c0 {
8045 + status = "okay";
8046 + pca9547@75 {
8047 + compatible = "nxp,pca9547";
8048 + reg = <0x75>;
8049 + #address-cells = <1>;
8050 + #size-cells = <0>;
8051 + i2c-mux-never-disable;
8052 + i2c@1 {
8053 + #address-cells = <1>;
8054 + #size-cells = <0>;
8055 + reg = <0x01>;
8056 + rtc@68 {
8057 + compatible = "dallas,ds3232";
8058 + reg = <0x68>;
8059 + };
8060 + };
8061 +
8062 + i2c@3 {
8063 + #address-cells = <1>;
8064 + #size-cells = <0>;
8065 + reg = <0x3>;
8066 +
8067 + adt7481@4c {
8068 + compatible = "adi,adt7461";
8069 + reg = <0x4c>;
8070 + };
8071 + };
8072 + };
8073 +};
8074 +
8075 +&i2c1 {
8076 + status = "disabled";
8077 +};
8078 +
8079 +&i2c2 {
8080 + status = "disabled";
8081 +};
8082 +
8083 +&i2c3 {
8084 + status = "disabled";
8085 +};
8086 +
8087 +&dspi {
8088 + status = "okay";
8089 + dflash0: n25q512a {
8090 + #address-cells = <1>;
8091 + #size-cells = <1>;
8092 + compatible = "st,m25p80";
8093 + spi-max-frequency = <3000000>;
8094 + reg = <0>;
8095 + };
8096 +};
8097 +
8098 +&qspi {
8099 + status = "okay";
8100 + flash0: s25fs512s@0 {
8101 + #address-cells = <1>;
8102 + #size-cells = <1>;
8103 + compatible = "spansion,m25p80";
8104 + m25p,fast-read;
8105 + spi-max-frequency = <20000000>;
8106 + reg = <0>;
8107 + };
8108 +};
8109 +
8110 +&sata0 {
8111 + status = "okay";
8112 +};
8113 +
8114 +&sata1 {
8115 + status = "okay";
8116 +};
8117 +
8118 +&usb0 {
8119 + status = "okay";
8120 +};
8121 +
8122 +&usb1 {
8123 + status = "okay";
8124 +};
8125 --- /dev/null
8126 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
8127 @@ -0,0 +1,910 @@
8128 +/*
8129 + * Device Tree Include file for Freescale Layerscape-2080A family SoC.
8130 + *
8131 + * Copyright 2016 Freescale Semiconductor, Inc.
8132 + * Copyright 2017 NXP
8133 + *
8134 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8135 + *
8136 + * This file is dual-licensed: you can use it either under the terms
8137 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8138 + * licensing only applies to this file, and not this project as a
8139 + * whole.
8140 + *
8141 + * a) This library is free software; you can redistribute it and/or
8142 + * modify it under the terms of the GNU General Public License as
8143 + * published by the Free Software Foundation; either version 2 of the
8144 + * License, or (at your option) any later version.
8145 + *
8146 + * This library is distributed in the hope that it will be useful,
8147 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8148 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8149 + * GNU General Public License for more details.
8150 + *
8151 + * Or, alternatively,
8152 + *
8153 + * b) Permission is hereby granted, free of charge, to any person
8154 + * obtaining a copy of this software and associated documentation
8155 + * files (the "Software"), to deal in the Software without
8156 + * restriction, including without limitation the rights to use,
8157 + * copy, modify, merge, publish, distribute, sublicense, and/or
8158 + * sell copies of the Software, and to permit persons to whom the
8159 + * Software is furnished to do so, subject to the following
8160 + * conditions:
8161 + *
8162 + * The above copyright notice and this permission notice shall be
8163 + * included in all copies or substantial portions of the Software.
8164 + *
8165 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8166 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8167 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8168 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8169 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8170 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8171 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8172 + * OTHER DEALINGS IN THE SOFTWARE.
8173 + */
8174 +
8175 +#include <dt-bindings/thermal/thermal.h>
8176 +#include <dt-bindings/interrupt-controller/arm-gic.h>
8177 +
8178 +/ {
8179 + compatible = "fsl,ls2080a";
8180 + interrupt-parent = <&gic>;
8181 + #address-cells = <2>;
8182 + #size-cells = <2>;
8183 +
8184 + aliases {
8185 + crypto = &crypto;
8186 + serial0 = &serial0;
8187 + serial1 = &serial1;
8188 + };
8189 +
8190 + cpu: cpus {
8191 + #address-cells = <1>;
8192 + #size-cells = <0>;
8193 + };
8194 +
8195 + memory@80000000 {
8196 + device_type = "memory";
8197 + reg = <0x00000000 0x80000000 0 0x80000000>;
8198 + /* DRAM space - 1, size : 2 GB DRAM */
8199 + };
8200 +
8201 + sysclk: sysclk {
8202 + compatible = "fixed-clock";
8203 + #clock-cells = <0>;
8204 + clock-frequency = <100000000>;
8205 + clock-output-names = "sysclk";
8206 + };
8207 +
8208 + gic: interrupt-controller@6000000 {
8209 + compatible = "arm,gic-v3";
8210 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
8211 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
8212 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
8213 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
8214 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
8215 + #interrupt-cells = <3>;
8216 + #address-cells = <2>;
8217 + #size-cells = <2>;
8218 + ranges;
8219 + interrupt-controller;
8220 + interrupts = <1 9 0x4>;
8221 +
8222 + its: gic-its@6020000 {
8223 + compatible = "arm,gic-v3-its";
8224 + msi-controller;
8225 + reg = <0x0 0x6020000 0 0x20000>;
8226 + };
8227 + };
8228 +
8229 + rstcr: syscon@1e60000 {
8230 + compatible = "fsl,ls2080a-rstcr", "syscon";
8231 + reg = <0x0 0x1e60000 0x0 0x4>;
8232 + };
8233 +
8234 + reboot {
8235 + compatible ="syscon-reboot";
8236 + regmap = <&rstcr>;
8237 + offset = <0x0>;
8238 + mask = <0x2>;
8239 + };
8240 +
8241 + timer {
8242 + compatible = "arm,armv8-timer";
8243 + interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
8244 + <1 14 4>, /* Physical Non-Secure PPI, active-low */
8245 + <1 11 4>, /* Virtual PPI, active-low */
8246 + <1 10 4>; /* Hypervisor PPI, active-low */
8247 + fsl,erratum-a008585;
8248 + };
8249 +
8250 + pmu {
8251 + compatible = "arm,armv8-pmuv3";
8252 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
8253 + };
8254 +
8255 + soc {
8256 + compatible = "simple-bus";
8257 + #address-cells = <2>;
8258 + #size-cells = <2>;
8259 + ranges;
8260 +
8261 + clockgen: clocking@1300000 {
8262 + compatible = "fsl,ls2080a-clockgen";
8263 + reg = <0 0x1300000 0 0xa0000>;
8264 + #clock-cells = <2>;
8265 + clocks = <&sysclk>;
8266 + };
8267 +
8268 + dcfg: dcfg@1e00000 {
8269 + compatible = "fsl,ls2080a-dcfg", "syscon";
8270 + reg = <0x0 0x1e00000 0x0 0x10000>;
8271 + little-endian;
8272 + };
8273 +
8274 + tmu: tmu@1f80000 {
8275 + compatible = "fsl,qoriq-tmu";
8276 + reg = <0x0 0x1f80000 0x0 0x10000>;
8277 + interrupts = <0 23 0x4>;
8278 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
8279 + fsl,tmu-calibration = <0x00000000 0x00000026
8280 + 0x00000001 0x0000002d
8281 + 0x00000002 0x00000032
8282 + 0x00000003 0x00000039
8283 + 0x00000004 0x0000003f
8284 + 0x00000005 0x00000046
8285 + 0x00000006 0x0000004d
8286 + 0x00000007 0x00000054
8287 + 0x00000008 0x0000005a
8288 + 0x00000009 0x00000061
8289 + 0x0000000a 0x0000006a
8290 + 0x0000000b 0x00000071
8291 +
8292 + 0x00010000 0x00000025
8293 + 0x00010001 0x0000002c
8294 + 0x00010002 0x00000035
8295 + 0x00010003 0x0000003d
8296 + 0x00010004 0x00000045
8297 + 0x00010005 0x0000004e
8298 + 0x00010006 0x00000057
8299 + 0x00010007 0x00000061
8300 + 0x00010008 0x0000006b
8301 + 0x00010009 0x00000076
8302 +
8303 + 0x00020000 0x00000029
8304 + 0x00020001 0x00000033
8305 + 0x00020002 0x0000003d
8306 + 0x00020003 0x00000049
8307 + 0x00020004 0x00000056
8308 + 0x00020005 0x00000061
8309 + 0x00020006 0x0000006d
8310 +
8311 + 0x00030000 0x00000021
8312 + 0x00030001 0x0000002a
8313 + 0x00030002 0x0000003c
8314 + 0x00030003 0x0000004e>;
8315 + little-endian;
8316 + #thermal-sensor-cells = <1>;
8317 + };
8318 +
8319 + thermal-zones {
8320 + cpu_thermal: cpu-thermal {
8321 + polling-delay-passive = <1000>;
8322 + polling-delay = <5000>;
8323 +
8324 + thermal-sensors = <&tmu 4>;
8325 +
8326 + trips {
8327 + cpu_alert: cpu-alert {
8328 + temperature = <75000>;
8329 + hysteresis = <2000>;
8330 + type = "passive";
8331 + };
8332 + cpu_crit: cpu-crit {
8333 + temperature = <85000>;
8334 + hysteresis = <2000>;
8335 + type = "critical";
8336 + };
8337 + };
8338 +
8339 + cooling-maps {
8340 + map0 {
8341 + trip = <&cpu_alert>;
8342 + cooling-device =
8343 + <&cpu0 THERMAL_NO_LIMIT
8344 + THERMAL_NO_LIMIT>;
8345 + };
8346 + map1 {
8347 + trip = <&cpu_alert>;
8348 + cooling-device =
8349 + <&cpu2 THERMAL_NO_LIMIT
8350 + THERMAL_NO_LIMIT>;
8351 + };
8352 + map2 {
8353 + trip = <&cpu_alert>;
8354 + cooling-device =
8355 + <&cpu4 THERMAL_NO_LIMIT
8356 + THERMAL_NO_LIMIT>;
8357 + };
8358 + map3 {
8359 + trip = <&cpu_alert>;
8360 + cooling-device =
8361 + <&cpu6 THERMAL_NO_LIMIT
8362 + THERMAL_NO_LIMIT>;
8363 + };
8364 + };
8365 + };
8366 + };
8367 +
8368 + serial0: serial@21c0500 {
8369 + compatible = "fsl,ns16550", "ns16550a";
8370 + reg = <0x0 0x21c0500 0x0 0x100>;
8371 + clocks = <&clockgen 4 3>;
8372 + interrupts = <0 32 0x4>; /* Level high type */
8373 + };
8374 +
8375 + serial1: serial@21c0600 {
8376 + compatible = "fsl,ns16550", "ns16550a";
8377 + reg = <0x0 0x21c0600 0x0 0x100>;
8378 + clocks = <&clockgen 4 3>;
8379 + interrupts = <0 32 0x4>; /* Level high type */
8380 + };
8381 +
8382 + cluster1_core0_watchdog: wdt@c000000 {
8383 + compatible = "arm,sp805-wdt", "arm,primecell";
8384 + reg = <0x0 0xc000000 0x0 0x1000>;
8385 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8386 + clock-names = "apb_pclk", "wdog_clk";
8387 + };
8388 +
8389 + cluster1_core1_watchdog: wdt@c010000 {
8390 + compatible = "arm,sp805-wdt", "arm,primecell";
8391 + reg = <0x0 0xc010000 0x0 0x1000>;
8392 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8393 + clock-names = "apb_pclk", "wdog_clk";
8394 + };
8395 +
8396 + cluster2_core0_watchdog: wdt@c100000 {
8397 + compatible = "arm,sp805-wdt", "arm,primecell";
8398 + reg = <0x0 0xc100000 0x0 0x1000>;
8399 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8400 + clock-names = "apb_pclk", "wdog_clk";
8401 + };
8402 +
8403 + cluster2_core1_watchdog: wdt@c110000 {
8404 + compatible = "arm,sp805-wdt", "arm,primecell";
8405 + reg = <0x0 0xc110000 0x0 0x1000>;
8406 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8407 + clock-names = "apb_pclk", "wdog_clk";
8408 + };
8409 +
8410 + cluster3_core0_watchdog: wdt@c200000 {
8411 + compatible = "arm,sp805-wdt", "arm,primecell";
8412 + reg = <0x0 0xc200000 0x0 0x1000>;
8413 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8414 + clock-names = "apb_pclk", "wdog_clk";
8415 + };
8416 +
8417 + cluster3_core1_watchdog: wdt@c210000 {
8418 + compatible = "arm,sp805-wdt", "arm,primecell";
8419 + reg = <0x0 0xc210000 0x0 0x1000>;
8420 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8421 + clock-names = "apb_pclk", "wdog_clk";
8422 + };
8423 +
8424 + cluster4_core0_watchdog: wdt@c300000 {
8425 + compatible = "arm,sp805-wdt", "arm,primecell";
8426 + reg = <0x0 0xc300000 0x0 0x1000>;
8427 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8428 + clock-names = "apb_pclk", "wdog_clk";
8429 + };
8430 +
8431 + cluster4_core1_watchdog: wdt@c310000 {
8432 + compatible = "arm,sp805-wdt", "arm,primecell";
8433 + reg = <0x0 0xc310000 0x0 0x1000>;
8434 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8435 + clock-names = "apb_pclk", "wdog_clk";
8436 + };
8437 +
8438 + crypto: crypto@8000000 {
8439 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
8440 + fsl,sec-era = <8>;
8441 + #address-cells = <1>;
8442 + #size-cells = <1>;
8443 + ranges = <0x0 0x00 0x8000000 0x100000>;
8444 + reg = <0x00 0x8000000 0x0 0x100000>;
8445 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
8446 + dma-coherent;
8447 +
8448 + sec_jr0: jr@10000 {
8449 + compatible = "fsl,sec-v5.0-job-ring",
8450 + "fsl,sec-v4.0-job-ring";
8451 + reg = <0x10000 0x10000>;
8452 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
8453 + };
8454 +
8455 + sec_jr1: jr@20000 {
8456 + compatible = "fsl,sec-v5.0-job-ring",
8457 + "fsl,sec-v4.0-job-ring";
8458 + reg = <0x20000 0x10000>;
8459 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
8460 + };
8461 +
8462 + sec_jr2: jr@30000 {
8463 + compatible = "fsl,sec-v5.0-job-ring",
8464 + "fsl,sec-v4.0-job-ring";
8465 + reg = <0x30000 0x10000>;
8466 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
8467 + };
8468 +
8469 + sec_jr3: jr@40000 {
8470 + compatible = "fsl,sec-v5.0-job-ring",
8471 + "fsl,sec-v4.0-job-ring";
8472 + reg = <0x40000 0x10000>;
8473 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
8474 + };
8475 + };
8476 +
8477 + fsl_mc: fsl-mc@80c000000 {
8478 + compatible = "fsl,qoriq-mc";
8479 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
8480 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
8481 + msi-parent = <&its>;
8482 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
8483 + #address-cells = <3>;
8484 + #size-cells = <1>;
8485 +
8486 + /*
8487 + * Region type 0x0 - MC portals
8488 + * Region type 0x1 - QBMAN portals
8489 + */
8490 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
8491 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
8492 +
8493 + /*
8494 + * Define the maximum number of MACs present on the SoC.
8495 + */
8496 + dpmacs {
8497 + #address-cells = <1>;
8498 + #size-cells = <0>;
8499 +
8500 + dpmac1: dpmac@1 {
8501 + compatible = "fsl,qoriq-mc-dpmac";
8502 + reg = <0x1>;
8503 + };
8504 +
8505 + dpmac2: dpmac@2 {
8506 + compatible = "fsl,qoriq-mc-dpmac";
8507 + reg = <0x2>;
8508 + };
8509 +
8510 + dpmac3: dpmac@3 {
8511 + compatible = "fsl,qoriq-mc-dpmac";
8512 + reg = <0x3>;
8513 + };
8514 +
8515 + dpmac4: dpmac@4 {
8516 + compatible = "fsl,qoriq-mc-dpmac";
8517 + reg = <0x4>;
8518 + };
8519 +
8520 + dpmac5: dpmac@5 {
8521 + compatible = "fsl,qoriq-mc-dpmac";
8522 + reg = <0x5>;
8523 + };
8524 +
8525 + dpmac6: dpmac@6 {
8526 + compatible = "fsl,qoriq-mc-dpmac";
8527 + reg = <0x6>;
8528 + };
8529 +
8530 + dpmac7: dpmac@7 {
8531 + compatible = "fsl,qoriq-mc-dpmac";
8532 + reg = <0x7>;
8533 + };
8534 +
8535 + dpmac8: dpmac@8 {
8536 + compatible = "fsl,qoriq-mc-dpmac";
8537 + reg = <0x8>;
8538 + };
8539 +
8540 + dpmac9: dpmac@9 {
8541 + compatible = "fsl,qoriq-mc-dpmac";
8542 + reg = <0x9>;
8543 + };
8544 +
8545 + dpmac10: dpmac@a {
8546 + compatible = "fsl,qoriq-mc-dpmac";
8547 + reg = <0xa>;
8548 + };
8549 +
8550 + dpmac11: dpmac@b {
8551 + compatible = "fsl,qoriq-mc-dpmac";
8552 + reg = <0xb>;
8553 + };
8554 +
8555 + dpmac12: dpmac@c {
8556 + compatible = "fsl,qoriq-mc-dpmac";
8557 + reg = <0xc>;
8558 + };
8559 +
8560 + dpmac13: dpmac@d {
8561 + compatible = "fsl,qoriq-mc-dpmac";
8562 + reg = <0xd>;
8563 + };
8564 +
8565 + dpmac14: dpmac@e {
8566 + compatible = "fsl,qoriq-mc-dpmac";
8567 + reg = <0xe>;
8568 + };
8569 +
8570 + dpmac15: dpmac@f {
8571 + compatible = "fsl,qoriq-mc-dpmac";
8572 + reg = <0xf>;
8573 + };
8574 +
8575 + dpmac16: dpmac@10 {
8576 + compatible = "fsl,qoriq-mc-dpmac";
8577 + reg = <0x10>;
8578 + };
8579 + };
8580 + };
8581 +
8582 + smmu: iommu@5000000 {
8583 + compatible = "arm,mmu-500";
8584 + reg = <0 0x5000000 0 0x800000>;
8585 + #global-interrupts = <12>;
8586 + #iommu-cells = <1>;
8587 + stream-match-mask = <0x7C00>;
8588 + interrupts = <0 13 4>, /* global secure fault */
8589 + <0 14 4>, /* combined secure interrupt */
8590 + <0 15 4>, /* global non-secure fault */
8591 + <0 16 4>, /* combined non-secure interrupt */
8592 + /* performance counter interrupts 0-7 */
8593 + <0 211 4>, <0 212 4>,
8594 + <0 213 4>, <0 214 4>,
8595 + <0 215 4>, <0 216 4>,
8596 + <0 217 4>, <0 218 4>,
8597 + /* per context interrupt, 64 interrupts */
8598 + <0 146 4>, <0 147 4>,
8599 + <0 148 4>, <0 149 4>,
8600 + <0 150 4>, <0 151 4>,
8601 + <0 152 4>, <0 153 4>,
8602 + <0 154 4>, <0 155 4>,
8603 + <0 156 4>, <0 157 4>,
8604 + <0 158 4>, <0 159 4>,
8605 + <0 160 4>, <0 161 4>,
8606 + <0 162 4>, <0 163 4>,
8607 + <0 164 4>, <0 165 4>,
8608 + <0 166 4>, <0 167 4>,
8609 + <0 168 4>, <0 169 4>,
8610 + <0 170 4>, <0 171 4>,
8611 + <0 172 4>, <0 173 4>,
8612 + <0 174 4>, <0 175 4>,
8613 + <0 176 4>, <0 177 4>,
8614 + <0 178 4>, <0 179 4>,
8615 + <0 180 4>, <0 181 4>,
8616 + <0 182 4>, <0 183 4>,
8617 + <0 184 4>, <0 185 4>,
8618 + <0 186 4>, <0 187 4>,
8619 + <0 188 4>, <0 189 4>,
8620 + <0 190 4>, <0 191 4>,
8621 + <0 192 4>, <0 193 4>,
8622 + <0 194 4>, <0 195 4>,
8623 + <0 196 4>, <0 197 4>,
8624 + <0 198 4>, <0 199 4>,
8625 + <0 200 4>, <0 201 4>,
8626 + <0 202 4>, <0 203 4>,
8627 + <0 204 4>, <0 205 4>,
8628 + <0 206 4>, <0 207 4>,
8629 + <0 208 4>, <0 209 4>;
8630 + };
8631 +
8632 + dspi: dspi@2100000 {
8633 + status = "disabled";
8634 + compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
8635 + #address-cells = <1>;
8636 + #size-cells = <0>;
8637 + reg = <0x0 0x2100000 0x0 0x10000>;
8638 + interrupts = <0 26 0x4>; /* Level high type */
8639 + clocks = <&clockgen 4 3>;
8640 + clock-names = "dspi";
8641 + spi-num-chipselects = <5>;
8642 + bus-num = <0>;
8643 + };
8644 +
8645 + esdhc: esdhc@2140000 {
8646 + status = "disabled";
8647 + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
8648 + reg = <0x0 0x2140000 0x0 0x10000>;
8649 + interrupts = <0 28 0x4>; /* Level high type */
8650 + clocks = <&clockgen 4 1>;
8651 + voltage-ranges = <1800 1800 3300 3300>;
8652 + sdhci,auto-cmd12;
8653 + little-endian;
8654 + bus-width = <4>;
8655 + };
8656 +
8657 + gpio0: gpio@2300000 {
8658 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8659 + reg = <0x0 0x2300000 0x0 0x10000>;
8660 + interrupts = <0 36 0x4>; /* Level high type */
8661 + gpio-controller;
8662 + little-endian;
8663 + #gpio-cells = <2>;
8664 + interrupt-controller;
8665 + #interrupt-cells = <2>;
8666 + };
8667 +
8668 + gpio1: gpio@2310000 {
8669 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8670 + reg = <0x0 0x2310000 0x0 0x10000>;
8671 + interrupts = <0 36 0x4>; /* Level high type */
8672 + gpio-controller;
8673 + little-endian;
8674 + #gpio-cells = <2>;
8675 + interrupt-controller;
8676 + #interrupt-cells = <2>;
8677 + };
8678 +
8679 + gpio2: gpio@2320000 {
8680 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8681 + reg = <0x0 0x2320000 0x0 0x10000>;
8682 + interrupts = <0 37 0x4>; /* Level high type */
8683 + gpio-controller;
8684 + little-endian;
8685 + #gpio-cells = <2>;
8686 + interrupt-controller;
8687 + #interrupt-cells = <2>;
8688 + };
8689 +
8690 + gpio3: gpio@2330000 {
8691 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8692 + reg = <0x0 0x2330000 0x0 0x10000>;
8693 + interrupts = <0 37 0x4>; /* Level high type */
8694 + gpio-controller;
8695 + little-endian;
8696 + #gpio-cells = <2>;
8697 + interrupt-controller;
8698 + #interrupt-cells = <2>;
8699 + };
8700 +
8701 + /* TODO: WRIOP (CCSR?) */
8702 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
8703 + * E-MDIO1: 0x1_6000
8704 + */
8705 + compatible = "fsl,fman-memac-mdio";
8706 + reg = <0x0 0x8B96000 0x0 0x1000>;
8707 + device_type = "mdio"; /* TODO: is this necessary? */
8708 + little-endian; /* force the driver in LE mode */
8709 +
8710 + /* Not necessary on the QDS, but needed on the RDB */
8711 + #address-cells = <1>;
8712 + #size-cells = <0>;
8713 + };
8714 +
8715 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
8716 + * E-MDIO2: 0x1_7000
8717 + */
8718 + compatible = "fsl,fman-memac-mdio";
8719 + reg = <0x0 0x8B97000 0x0 0x1000>;
8720 + device_type = "mdio"; /* TODO: is this necessary? */
8721 + little-endian; /* force the driver in LE mode */
8722 +
8723 + #address-cells = <1>;
8724 + #size-cells = <0>;
8725 + };
8726 +
8727 + pcs_mdio1: mdio@0x8c07000 {
8728 + compatible = "fsl,fman-memac-mdio";
8729 + reg = <0x0 0x8c07000 0x0 0x1000>;
8730 + device_type = "mdio";
8731 + little-endian;
8732 +
8733 + #address-cells = <1>;
8734 + #size-cells = <0>;
8735 + };
8736 +
8737 + pcs_mdio2: mdio@0x8c0b000 {
8738 + compatible = "fsl,fman-memac-mdio";
8739 + reg = <0x0 0x8c0b000 0x0 0x1000>;
8740 + device_type = "mdio";
8741 + little-endian;
8742 +
8743 + #address-cells = <1>;
8744 + #size-cells = <0>;
8745 + };
8746 +
8747 + pcs_mdio3: mdio@0x8c0f000 {
8748 + compatible = "fsl,fman-memac-mdio";
8749 + reg = <0x0 0x8c0f000 0x0 0x1000>;
8750 + device_type = "mdio";
8751 + little-endian;
8752 +
8753 + #address-cells = <1>;
8754 + #size-cells = <0>;
8755 + };
8756 +
8757 + pcs_mdio4: mdio@0x8c13000 {
8758 + compatible = "fsl,fman-memac-mdio";
8759 + reg = <0x0 0x8c13000 0x0 0x1000>;
8760 + device_type = "mdio";
8761 + little-endian;
8762 +
8763 + #address-cells = <1>;
8764 + #size-cells = <0>;
8765 + };
8766 +
8767 + pcs_mdio5: mdio@0x8c17000 {
8768 + status = "disabled";
8769 + compatible = "fsl,fman-memac-mdio";
8770 + reg = <0x0 0x8c17000 0x0 0x1000>;
8771 + device_type = "mdio";
8772 + little-endian;
8773 +
8774 + #address-cells = <1>;
8775 + #size-cells = <0>;
8776 + };
8777 +
8778 + pcs_mdio6: mdio@0x8c1b000 {
8779 + status = "disabled";
8780 + compatible = "fsl,fman-memac-mdio";
8781 + reg = <0x0 0x8c1b000 0x0 0x1000>;
8782 + device_type = "mdio";
8783 + little-endian;
8784 +
8785 + #address-cells = <1>;
8786 + #size-cells = <0>;
8787 + };
8788 +
8789 + pcs_mdio7: mdio@0x8c1f000 {
8790 + status = "disabled";
8791 + compatible = "fsl,fman-memac-mdio";
8792 + reg = <0x0 0x8c1f000 0x0 0x1000>;
8793 + device_type = "mdio";
8794 + little-endian;
8795 +
8796 + #address-cells = <1>;
8797 + #size-cells = <0>;
8798 + };
8799 +
8800 + pcs_mdio8: mdio@0x8c23000 {
8801 + status = "disabled";
8802 + compatible = "fsl,fman-memac-mdio";
8803 + reg = <0x0 0x8c23000 0x0 0x1000>;
8804 + device_type = "mdio";
8805 + little-endian;
8806 +
8807 + #address-cells = <1>;
8808 + #size-cells = <0>;
8809 + };
8810 +
8811 + i2c0: i2c@2000000 {
8812 + status = "disabled";
8813 + compatible = "fsl,vf610-i2c";
8814 + #address-cells = <1>;
8815 + #size-cells = <0>;
8816 + reg = <0x0 0x2000000 0x0 0x10000>;
8817 + interrupts = <0 34 0x4>; /* Level high type */
8818 + clock-names = "i2c";
8819 + clocks = <&clockgen 4 3>;
8820 + };
8821 +
8822 + i2c1: i2c@2010000 {
8823 + status = "disabled";
8824 + compatible = "fsl,vf610-i2c";
8825 + #address-cells = <1>;
8826 + #size-cells = <0>;
8827 + reg = <0x0 0x2010000 0x0 0x10000>;
8828 + interrupts = <0 34 0x4>; /* Level high type */
8829 + clock-names = "i2c";
8830 + clocks = <&clockgen 4 3>;
8831 + };
8832 +
8833 + i2c2: i2c@2020000 {
8834 + status = "disabled";
8835 + compatible = "fsl,vf610-i2c";
8836 + #address-cells = <1>;
8837 + #size-cells = <0>;
8838 + reg = <0x0 0x2020000 0x0 0x10000>;
8839 + interrupts = <0 35 0x4>; /* Level high type */
8840 + clock-names = "i2c";
8841 + clocks = <&clockgen 4 3>;
8842 + };
8843 +
8844 + i2c3: i2c@2030000 {
8845 + status = "disabled";
8846 + compatible = "fsl,vf610-i2c";
8847 + #address-cells = <1>;
8848 + #size-cells = <0>;
8849 + reg = <0x0 0x2030000 0x0 0x10000>;
8850 + interrupts = <0 35 0x4>; /* Level high type */
8851 + clock-names = "i2c";
8852 + clocks = <&clockgen 4 3>;
8853 + };
8854 +
8855 + ifc: ifc@2240000 {
8856 + compatible = "fsl,ifc", "simple-bus";
8857 + reg = <0x0 0x2240000 0x0 0x20000>;
8858 + interrupts = <0 21 0x4>; /* Level high type */
8859 + little-endian;
8860 + #address-cells = <2>;
8861 + #size-cells = <1>;
8862 +
8863 + ranges = <0 0 0x5 0x80000000 0x08000000
8864 + 2 0 0x5 0x30000000 0x00010000
8865 + 3 0 0x5 0x20000000 0x00010000>;
8866 + };
8867 +
8868 + qspi: quadspi@20c0000 {
8869 + status = "disabled";
8870 + compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
8871 + #address-cells = <1>;
8872 + #size-cells = <0>;
8873 + reg = <0x0 0x20c0000 0x0 0x10000>,
8874 + <0x0 0x20000000 0x0 0x10000000>;
8875 + reg-names = "QuadSPI", "QuadSPI-memory";
8876 + interrupts = <0 25 0x4>; /* Level high type */
8877 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8878 + clock-names = "qspi_en", "qspi";
8879 + };
8880 +
8881 + pcie1: pcie@3400000 {
8882 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
8883 + "snps,dw-pcie";
8884 + reg-names = "regs", "config";
8885 + interrupts = <0 108 0x4>; /* aer interrupt */
8886 + interrupt-names = "aer";
8887 + #address-cells = <3>;
8888 + #size-cells = <2>;
8889 + device_type = "pci";
8890 + dma-coherent;
8891 + num-lanes = <4>;
8892 + bus-range = <0x0 0xff>;
8893 + msi-parent = <&its>;
8894 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
8895 + #interrupt-cells = <1>;
8896 + interrupt-map-mask = <0 0 0 7>;
8897 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
8898 + <0000 0 0 2 &gic 0 0 0 110 4>,
8899 + <0000 0 0 3 &gic 0 0 0 111 4>,
8900 + <0000 0 0 4 &gic 0 0 0 112 4>;
8901 + };
8902 +
8903 + pcie2: pcie@3500000 {
8904 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
8905 + "snps,dw-pcie";
8906 + reg-names = "regs", "config";
8907 + interrupts = <0 113 0x4>; /* aer interrupt */
8908 + interrupt-names = "aer";
8909 + #address-cells = <3>;
8910 + #size-cells = <2>;
8911 + device_type = "pci";
8912 + dma-coherent;
8913 + num-lanes = <4>;
8914 + bus-range = <0x0 0xff>;
8915 + msi-parent = <&its>;
8916 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
8917 + #interrupt-cells = <1>;
8918 + interrupt-map-mask = <0 0 0 7>;
8919 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
8920 + <0000 0 0 2 &gic 0 0 0 115 4>,
8921 + <0000 0 0 3 &gic 0 0 0 116 4>,
8922 + <0000 0 0 4 &gic 0 0 0 117 4>;
8923 + };
8924 +
8925 + pcie3: pcie@3600000 {
8926 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
8927 + "snps,dw-pcie";
8928 + reg-names = "regs", "config";
8929 + interrupts = <0 118 0x4>; /* aer interrupt */
8930 + interrupt-names = "aer";
8931 + #address-cells = <3>;
8932 + #size-cells = <2>;
8933 + device_type = "pci";
8934 + dma-coherent;
8935 + num-lanes = <8>;
8936 + bus-range = <0x0 0xff>;
8937 + msi-parent = <&its>;
8938 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
8939 + #interrupt-cells = <1>;
8940 + interrupt-map-mask = <0 0 0 7>;
8941 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
8942 + <0000 0 0 2 &gic 0 0 0 120 4>,
8943 + <0000 0 0 3 &gic 0 0 0 121 4>,
8944 + <0000 0 0 4 &gic 0 0 0 122 4>;
8945 + };
8946 +
8947 + pcie4: pcie@3700000 {
8948 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
8949 + "snps,dw-pcie";
8950 + reg-names = "regs", "config";
8951 + interrupts = <0 123 0x4>; /* aer interrupt */
8952 + interrupt-names = "aer";
8953 + #address-cells = <3>;
8954 + #size-cells = <2>;
8955 + device_type = "pci";
8956 + dma-coherent;
8957 + num-lanes = <4>;
8958 + bus-range = <0x0 0xff>;
8959 + msi-parent = <&its>;
8960 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
8961 + #interrupt-cells = <1>;
8962 + interrupt-map-mask = <0 0 0 7>;
8963 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
8964 + <0000 0 0 2 &gic 0 0 0 125 4>,
8965 + <0000 0 0 3 &gic 0 0 0 126 4>,
8966 + <0000 0 0 4 &gic 0 0 0 127 4>;
8967 + };
8968 +
8969 + sata0: sata@3200000 {
8970 + status = "disabled";
8971 + compatible = "fsl,ls2080a-ahci";
8972 + reg = <0x0 0x3200000 0x0 0x10000>;
8973 + interrupts = <0 133 0x4>; /* Level high type */
8974 + clocks = <&clockgen 4 3>;
8975 + dma-coherent;
8976 + };
8977 +
8978 + sata1: sata@3210000 {
8979 + status = "disabled";
8980 + compatible = "fsl,ls2080a-ahci";
8981 + reg = <0x0 0x3210000 0x0 0x10000>;
8982 + interrupts = <0 136 0x4>; /* Level high type */
8983 + clocks = <&clockgen 4 3>;
8984 + dma-coherent;
8985 + };
8986 +
8987 + usb0: usb3@3100000 {
8988 + status = "disabled";
8989 + compatible = "snps,dwc3";
8990 + reg = <0x0 0x3100000 0x0 0x10000>;
8991 + interrupts = <0 80 0x4>; /* Level high type */
8992 + dr_mode = "host";
8993 + snps,quirk-frame-length-adjustment = <0x20>;
8994 + snps,dis_rxdet_inp3_quirk;
8995 + };
8996 +
8997 + usb1: usb3@3110000 {
8998 + status = "disabled";
8999 + compatible = "snps,dwc3";
9000 + reg = <0x0 0x3110000 0x0 0x10000>;
9001 + interrupts = <0 81 0x4>; /* Level high type */
9002 + dr_mode = "host";
9003 + snps,quirk-frame-length-adjustment = <0x20>;
9004 + snps,dis_rxdet_inp3_quirk;
9005 + };
9006 +
9007 + serdes1: serdes@1ea0000 {
9008 + reg = <0x0 0x1ea0000 0 0x00002000>;
9009 + };
9010 +
9011 + ccn@4000000 {
9012 + compatible = "arm,ccn-504";
9013 + reg = <0x0 0x04000000 0x0 0x01000000>;
9014 + interrupts = <0 12 4>;
9015 + };
9016 +
9017 + ftm0: ftm0@2800000 {
9018 + compatible = "fsl,ftm-alarm";
9019 + reg = <0x0 0x2800000 0x0 0x10000>;
9020 + interrupts = <0 44 4>;
9021 + };
9022 + };
9023 +
9024 + ddr1: memory-controller@1080000 {
9025 + compatible = "fsl,qoriq-memory-controller";
9026 + reg = <0x0 0x1080000 0x0 0x1000>;
9027 + interrupts = <0 17 0x4>;
9028 + little-endian;
9029 + };
9030 +
9031 + ddr2: memory-controller@1090000 {
9032 + compatible = "fsl,qoriq-memory-controller";
9033 + reg = <0x0 0x1090000 0x0 0x1000>;
9034 + interrupts = <0 18 0x4>;
9035 + little-endian;
9036 + };
9037 +};
9038 --- /dev/null
9039 +++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
9040 @@ -0,0 +1,81 @@
9041 +/*
9042 + * QorIQ BMan Portals device tree
9043 + *
9044 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9045 + *
9046 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9047 + */
9048 +
9049 +&bportals {
9050 + #address-cells = <1>;
9051 + #size-cells = <1>;
9052 + compatible = "simple-bus";
9053 +
9054 + bman-portal@0 {
9055 + cell-index = <0>;
9056 + compatible = "fsl,bman-portal";
9057 + reg = <0x0 0x4000 0x4000000 0x4000>;
9058 + interrupts = <0 173 0x4>;
9059 + };
9060 +
9061 + bman-portal@10000 {
9062 + cell-index = <1>;
9063 + compatible = "fsl,bman-portal";
9064 + reg = <0x10000 0x4000 0x4010000 0x4000>;
9065 + interrupts = <0 175 0x4>;
9066 + };
9067 +
9068 + bman-portal@20000 {
9069 + cell-index = <2>;
9070 + compatible = "fsl,bman-portal";
9071 + reg = <0x20000 0x4000 0x4020000 0x4000>;
9072 + interrupts = <0 177 0x4>;
9073 + };
9074 +
9075 + bman-portal@30000 {
9076 + cell-index = <3>;
9077 + compatible = "fsl,bman-portal";
9078 + reg = <0x30000 0x4000 0x4030000 0x4000>;
9079 + interrupts = <0 179 0x4>;
9080 + };
9081 +
9082 + bman-portal@40000 {
9083 + cell-index = <4>;
9084 + compatible = "fsl,bman-portal";
9085 + reg = <0x40000 0x4000 0x4040000 0x4000>;
9086 + interrupts = <0 181 0x4>;
9087 + };
9088 +
9089 + bman-portal@50000 {
9090 + cell-index = <5>;
9091 + compatible = "fsl,bman-portal";
9092 + reg = <0x50000 0x4000 0x4050000 0x4000>;
9093 + interrupts = <0 183 0x4>;
9094 + };
9095 +
9096 + bman-portal@60000 {
9097 + cell-index = <6>;
9098 + compatible = "fsl,bman-portal";
9099 + reg = <0x60000 0x4000 0x4060000 0x4000>;
9100 + interrupts = <0 185 0x4>;
9101 + };
9102 +
9103 + bman-portal@70000 {
9104 + cell-index = <7>;
9105 + compatible = "fsl,bman-portal";
9106 + reg = <0x70000 0x4000 0x4070000 0x4000>;
9107 + interrupts = <0 187 0x4>;
9108 + };
9109 +
9110 + bman-portal@80000 {
9111 + cell-index = <8>;
9112 + compatible = "fsl,bman-portal";
9113 + reg = <0x80000 0x4000 0x4080000 0x4000>;
9114 + interrupts = <0 189 0x4>;
9115 + };
9116 +
9117 + bman-bpids@0 {
9118 + compatible = "fsl,bpid-range";
9119 + fsl,bpid-range = <32 32>;
9120 + };
9121 +};
9122 --- /dev/null
9123 +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
9124 @@ -0,0 +1,66 @@
9125 +/*
9126 + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
9127 + *
9128 + * Copyright 2012 - 2015 Freescale Semiconductor Inc.
9129 + *
9130 + * Redistribution and use in source and binary forms, with or without
9131 + * modification, are permitted provided that the following conditions are met:
9132 + * * Redistributions of source code must retain the above copyright
9133 + * notice, this list of conditions and the following disclaimer.
9134 + * * Redistributions in binary form must reproduce the above copyright
9135 + * notice, this list of conditions and the following disclaimer in the
9136 + * documentation and/or other materials provided with the distribution.
9137 + * * Neither the name of Freescale Semiconductor nor the
9138 + * names of its contributors may be used to endorse or promote products
9139 + * derived from this software without specific prior written permission.
9140 + *
9141 + *
9142 + * ALTERNATIVELY, this software may be distributed under the terms of the
9143 + * GNU General Public License ("GPL") as published by the Free Software
9144 + * Foundation, either version 2 of that License or (at your option) any
9145 + * later version.
9146 + *
9147 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9148 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9149 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9150 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9151 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9152 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9153 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9154 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9155 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9156 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9157 + */
9158 +
9159 +fsldpaa: fsl,dpaa {
9160 + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
9161 + ethernet@0 {
9162 + compatible = "fsl,dpa-ethernet";
9163 + fsl,fman-mac = <&enet0>;
9164 + };
9165 + ethernet@1 {
9166 + compatible = "fsl,dpa-ethernet";
9167 + fsl,fman-mac = <&enet1>;
9168 + };
9169 + ethernet@2 {
9170 + compatible = "fsl,dpa-ethernet";
9171 + fsl,fman-mac = <&enet2>;
9172 + };
9173 + ethernet@3 {
9174 + compatible = "fsl,dpa-ethernet";
9175 + fsl,fman-mac = <&enet3>;
9176 + };
9177 + ethernet@4 {
9178 + compatible = "fsl,dpa-ethernet";
9179 + fsl,fman-mac = <&enet4>;
9180 + };
9181 + ethernet@5 {
9182 + compatible = "fsl,dpa-ethernet";
9183 + fsl,fman-mac = <&enet5>;
9184 + };
9185 + ethernet@8 {
9186 + compatible = "fsl,dpa-ethernet";
9187 + fsl,fman-mac = <&enet6>;
9188 + };
9189 +};
9190 +
9191 --- /dev/null
9192 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
9193 @@ -0,0 +1,43 @@
9194 +/*
9195 + * QorIQ FMan v3 10g port #0 device tree
9196 + *
9197 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9198 + *
9199 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9200 + */
9201 +
9202 +fman@1a00000 {
9203 + fman0_rx_0x10: port@90000 {
9204 + cell-index = <0x10>;
9205 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9206 + reg = <0x90000 0x1000>;
9207 + fsl,fman-10g-port;
9208 + };
9209 +
9210 + fman0_tx_0x30: port@b0000 {
9211 + cell-index = <0x30>;
9212 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9213 + reg = <0xb0000 0x1000>;
9214 + fsl,fman-10g-port;
9215 + fsl,qman-channel-id = <0x800>;
9216 + };
9217 +
9218 + ethernet@f0000 {
9219 + cell-index = <0x8>;
9220 + compatible = "fsl,fman-memac";
9221 + reg = <0xf0000 0x1000>;
9222 + fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
9223 + pcsphy-handle = <&pcsphy6>;
9224 + };
9225 +
9226 + mdio@f1000 {
9227 + #address-cells = <1>;
9228 + #size-cells = <0>;
9229 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9230 + reg = <0xf1000 0x1000>;
9231 +
9232 + pcsphy6: ethernet-phy@0 {
9233 + reg = <0x0>;
9234 + };
9235 + };
9236 +};
9237 --- /dev/null
9238 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
9239 @@ -0,0 +1,43 @@
9240 +/*
9241 + * QorIQ FMan v3 10g port #1 device tree
9242 + *
9243 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9244 + *
9245 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9246 + */
9247 +
9248 +fman@1a00000 {
9249 + fman0_rx_0x11: port@91000 {
9250 + cell-index = <0x11>;
9251 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9252 + reg = <0x91000 0x1000>;
9253 + fsl,fman-10g-port;
9254 + };
9255 +
9256 + fman0_tx_0x31: port@b1000 {
9257 + cell-index = <0x31>;
9258 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9259 + reg = <0xb1000 0x1000>;
9260 + fsl,fman-10g-port;
9261 + fsl,qman-channel-id = <0x801>;
9262 + };
9263 +
9264 + ethernet@f2000 {
9265 + cell-index = <0x9>;
9266 + compatible = "fsl,fman-memac";
9267 + reg = <0xf2000 0x1000>;
9268 + fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
9269 + pcsphy-handle = <&pcsphy7>;
9270 + };
9271 +
9272 + mdio@f3000 {
9273 + #address-cells = <1>;
9274 + #size-cells = <0>;
9275 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9276 + reg = <0xf3000 0x1000>;
9277 +
9278 + pcsphy7: ethernet-phy@0 {
9279 + reg = <0x0>;
9280 + };
9281 + };
9282 +};
9283 --- /dev/null
9284 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
9285 @@ -0,0 +1,42 @@
9286 +/*
9287 + * QorIQ FMan v3 1g port #0 device tree
9288 + *
9289 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9290 + *
9291 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9292 + */
9293 +
9294 +fman@1a00000 {
9295 + fman0_rx_0x08: port@88000 {
9296 + cell-index = <0x8>;
9297 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9298 + reg = <0x88000 0x1000>;
9299 + };
9300 +
9301 + fman0_tx_0x28: port@a8000 {
9302 + cell-index = <0x28>;
9303 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9304 + reg = <0xa8000 0x1000>;
9305 + fsl,qman-channel-id = <0x802>;
9306 + };
9307 +
9308 + ethernet@e0000 {
9309 + cell-index = <0>;
9310 + compatible = "fsl,fman-memac";
9311 + reg = <0xe0000 0x1000>;
9312 + fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
9313 + ptp-timer = <&ptp_timer0>;
9314 + pcsphy-handle = <&pcsphy0>;
9315 + };
9316 +
9317 + mdio@e1000 {
9318 + #address-cells = <1>;
9319 + #size-cells = <0>;
9320 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9321 + reg = <0xe1000 0x1000>;
9322 +
9323 + pcsphy0: ethernet-phy@0 {
9324 + reg = <0x0>;
9325 + };
9326 + };
9327 +};
9328 --- /dev/null
9329 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
9330 @@ -0,0 +1,42 @@
9331 +/*
9332 + * QorIQ FMan v3 1g port #1 device tree
9333 + *
9334 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9335 + *
9336 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9337 + */
9338 +
9339 +fman@1a00000 {
9340 + fman0_rx_0x09: port@89000 {
9341 + cell-index = <0x9>;
9342 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9343 + reg = <0x89000 0x1000>;
9344 + };
9345 +
9346 + fman0_tx_0x29: port@a9000 {
9347 + cell-index = <0x29>;
9348 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9349 + reg = <0xa9000 0x1000>;
9350 + fsl,qman-channel-id = <0x803>;
9351 + };
9352 +
9353 + ethernet@e2000 {
9354 + cell-index = <1>;
9355 + compatible = "fsl,fman-memac";
9356 + reg = <0xe2000 0x1000>;
9357 + fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
9358 + ptp-timer = <&ptp_timer0>;
9359 + pcsphy-handle = <&pcsphy1>;
9360 + };
9361 +
9362 + mdio@e3000 {
9363 + #address-cells = <1>;
9364 + #size-cells = <0>;
9365 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9366 + reg = <0xe3000 0x1000>;
9367 +
9368 + pcsphy1: ethernet-phy@0 {
9369 + reg = <0x0>;
9370 + };
9371 + };
9372 +};
9373 --- /dev/null
9374 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
9375 @@ -0,0 +1,42 @@
9376 +/*
9377 + * QorIQ FMan v3 1g port #2 device tree
9378 + *
9379 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9380 + *
9381 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9382 + */
9383 +
9384 +fman@1a00000 {
9385 + fman0_rx_0x0a: port@8a000 {
9386 + cell-index = <0xa>;
9387 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9388 + reg = <0x8a000 0x1000>;
9389 + };
9390 +
9391 + fman0_tx_0x2a: port@aa000 {
9392 + cell-index = <0x2a>;
9393 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9394 + reg = <0xaa000 0x1000>;
9395 + fsl,qman-channel-id = <0x804>;
9396 + };
9397 +
9398 + ethernet@e4000 {
9399 + cell-index = <2>;
9400 + compatible = "fsl,fman-memac";
9401 + reg = <0xe4000 0x1000>;
9402 + fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
9403 + ptp-timer = <&ptp_timer0>;
9404 + pcsphy-handle = <&pcsphy2>;
9405 + };
9406 +
9407 + mdio@e5000 {
9408 + #address-cells = <1>;
9409 + #size-cells = <0>;
9410 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9411 + reg = <0xe5000 0x1000>;
9412 +
9413 + pcsphy2: ethernet-phy@0 {
9414 + reg = <0x0>;
9415 + };
9416 + };
9417 +};
9418 --- /dev/null
9419 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
9420 @@ -0,0 +1,42 @@
9421 +/*
9422 + * QorIQ FMan v3 1g port #3 device tree
9423 + *
9424 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9425 + *
9426 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9427 + */
9428 +
9429 +fman@1a00000 {
9430 + fman0_rx_0x0b: port@8b000 {
9431 + cell-index = <0xb>;
9432 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9433 + reg = <0x8b000 0x1000>;
9434 + };
9435 +
9436 + fman0_tx_0x2b: port@ab000 {
9437 + cell-index = <0x2b>;
9438 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9439 + reg = <0xab000 0x1000>;
9440 + fsl,qman-channel-id = <0x805>;
9441 + };
9442 +
9443 + ethernet@e6000 {
9444 + cell-index = <3>;
9445 + compatible = "fsl,fman-memac";
9446 + reg = <0xe6000 0x1000>;
9447 + fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
9448 + ptp-timer = <&ptp_timer0>;
9449 + pcsphy-handle = <&pcsphy3>;
9450 + };
9451 +
9452 + mdio@e7000 {
9453 + #address-cells = <1>;
9454 + #size-cells = <0>;
9455 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9456 + reg = <0xe7000 0x1000>;
9457 +
9458 + pcsphy3: ethernet-phy@0 {
9459 + reg = <0x0>;
9460 + };
9461 + };
9462 +};
9463 --- /dev/null
9464 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
9465 @@ -0,0 +1,42 @@
9466 +/*
9467 + * QorIQ FMan v3 1g port #4 device tree
9468 + *
9469 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9470 + *
9471 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9472 + */
9473 +
9474 +fman@1a00000 {
9475 + fman0_rx_0x0c: port@8c000 {
9476 + cell-index = <0xc>;
9477 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9478 + reg = <0x8c000 0x1000>;
9479 + };
9480 +
9481 + fman0_tx_0x2c: port@ac000 {
9482 + cell-index = <0x2c>;
9483 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9484 + reg = <0xac000 0x1000>;
9485 + fsl,qman-channel-id = <0x806>;
9486 + };
9487 +
9488 + ethernet@e8000 {
9489 + cell-index = <4>;
9490 + compatible = "fsl,fman-memac";
9491 + reg = <0xe8000 0x1000>;
9492 + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
9493 + ptp-timer = <&ptp_timer0>;
9494 + pcsphy-handle = <&pcsphy4>;
9495 + };
9496 +
9497 + mdio@e9000 {
9498 + #address-cells = <1>;
9499 + #size-cells = <0>;
9500 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9501 + reg = <0xe9000 0x1000>;
9502 +
9503 + pcsphy4: ethernet-phy@0 {
9504 + reg = <0x0>;
9505 + };
9506 + };
9507 +};
9508 --- /dev/null
9509 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
9510 @@ -0,0 +1,42 @@
9511 +/*
9512 + * QorIQ FMan v3 1g port #5 device tree
9513 + *
9514 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9515 + *
9516 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9517 + */
9518 +
9519 +fman@1a00000 {
9520 + fman0_rx_0x0d: port@8d000 {
9521 + cell-index = <0xd>;
9522 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9523 + reg = <0x8d000 0x1000>;
9524 + };
9525 +
9526 + fman0_tx_0x2d: port@ad000 {
9527 + cell-index = <0x2d>;
9528 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9529 + reg = <0xad000 0x1000>;
9530 + fsl,qman-channel-id = <0x807>;
9531 + };
9532 +
9533 + ethernet@ea000 {
9534 + cell-index = <5>;
9535 + compatible = "fsl,fman-memac";
9536 + reg = <0xea000 0x1000>;
9537 + fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
9538 + ptp-timer = <&ptp_timer0>;
9539 + pcsphy-handle = <&pcsphy5>;
9540 + };
9541 +
9542 + mdio@eb000 {
9543 + #address-cells = <1>;
9544 + #size-cells = <0>;
9545 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9546 + reg = <0xeb000 0x1000>;
9547 +
9548 + pcsphy5: ethernet-phy@0 {
9549 + reg = <0x0>;
9550 + };
9551 + };
9552 +};
9553 --- /dev/null
9554 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
9555 @@ -0,0 +1,47 @@
9556 +/*
9557 + * QorIQ FMan v3 OH ports device tree
9558 + *
9559 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9560 + *
9561 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9562 + */
9563 +
9564 +fman@1a00000 {
9565 +
9566 + fman0_oh1: port@82000 {
9567 + cell-index = <0>;
9568 + compatible = "fsl,fman-port-oh";
9569 + reg = <0x82000 0x1000>;
9570 + };
9571 +
9572 + fman0_oh2: port@83000 {
9573 + cell-index = <1>;
9574 + compatible = "fsl,fman-port-oh";
9575 + reg = <0x83000 0x1000>;
9576 + };
9577 +
9578 + fman0_oh3: port@84000 {
9579 + cell-index = <2>;
9580 + compatible = "fsl,fman-port-oh";
9581 + reg = <0x84000 0x1000>;
9582 + };
9583 +
9584 + fman0_oh4: port@85000 {
9585 + cell-index = <3>;
9586 + compatible = "fsl,fman-port-oh";
9587 + reg = <0x85000 0x1000>;
9588 + };
9589 +
9590 + fman0_oh5: port@86000 {
9591 + cell-index = <4>;
9592 + compatible = "fsl,fman-port-oh";
9593 + reg = <0x86000 0x1000>;
9594 + };
9595 +
9596 + fman0_oh6: port@87000 {
9597 + cell-index = <5>;
9598 + compatible = "fsl,fman-port-oh";
9599 + reg = <0x87000 0x1000>;
9600 + };
9601 +
9602 +};
9603 --- /dev/null
9604 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
9605 @@ -0,0 +1,130 @@
9606 +/*
9607 + * QorIQ FMan v3 device tree
9608 + *
9609 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9610 + *
9611 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9612 + */
9613 +
9614 +fman0: fman@1a00000 {
9615 + #address-cells = <1>;
9616 + #size-cells = <1>;
9617 + cell-index = <0>;
9618 + compatible = "fsl,fman";
9619 + ranges = <0x0 0x00 0x1a00000 0x100000>;
9620 + reg = <0x0 0x1a00000 0x0 0x100000>;
9621 + interrupts = <0 44 0x4>, <0 45 0x4>;
9622 + clocks = <&clockgen 3 0>;
9623 + clock-names = "fmanclk";
9624 + fsl,qman-channel-range = <0x800 0x10>;
9625 +
9626 + cc {
9627 + compatible = "fsl,fman-cc";
9628 + };
9629 +
9630 + muram@0 {
9631 + compatible = "fsl,fman-muram";
9632 + reg = <0x0 0x60000>;
9633 + };
9634 +
9635 + bmi@80000 {
9636 + compatible = "fsl,fman-bmi";
9637 + reg = <0x80000 0x400>;
9638 + };
9639 +
9640 + qmi@80400 {
9641 + compatible = "fsl,fman-qmi";
9642 + reg = <0x80400 0x400>;
9643 + };
9644 +
9645 + fman0_oh_0x2: port@82000 {
9646 + cell-index = <0x2>;
9647 + compatible = "fsl,fman-v3-port-oh";
9648 + reg = <0x82000 0x1000>;
9649 + fsl,qman-channel-id = <0x809>;
9650 + };
9651 +
9652 + fman0_oh_0x3: port@83000 {
9653 + cell-index = <0x3>;
9654 + compatible = "fsl,fman-v3-port-oh";
9655 + reg = <0x83000 0x1000>;
9656 + fsl,qman-channel-id = <0x80a>;
9657 + };
9658 +
9659 + fman0_oh_0x4: port@84000 {
9660 + cell-index = <0x4>;
9661 + compatible = "fsl,fman-v3-port-oh";
9662 + reg = <0x84000 0x1000>;
9663 + fsl,qman-channel-id = <0x80b>;
9664 + };
9665 +
9666 + fman0_oh_0x5: port@85000 {
9667 + cell-index = <0x5>;
9668 + compatible = "fsl,fman-v3-port-oh";
9669 + reg = <0x85000 0x1000>;
9670 + fsl,qman-channel-id = <0x80c>;
9671 + };
9672 +
9673 + fman0_oh_0x6: port@86000 {
9674 + cell-index = <0x6>;
9675 + compatible = "fsl,fman-v3-port-oh";
9676 + reg = <0x86000 0x1000>;
9677 + fsl,qman-channel-id = <0x80d>;
9678 + };
9679 +
9680 + fman0_oh_0x7: port@87000 {
9681 + cell-index = <0x7>;
9682 + compatible = "fsl,fman-v3-port-oh";
9683 + reg = <0x87000 0x1000>;
9684 + fsl,qman-channel-id = <0x80e>;
9685 + };
9686 +
9687 + policer@c0000 {
9688 + compatible = "fsl,fman-policer";
9689 + reg = <0xc0000 0x1000>;
9690 + };
9691 +
9692 + keygen@c1000 {
9693 + compatible = "fsl,fman-keygen";
9694 + reg = <0xc1000 0x1000>;
9695 + };
9696 +
9697 + dma@c2000 {
9698 + compatible = "fsl,fman-dma";
9699 + reg = <0xc2000 0x1000>;
9700 + };
9701 +
9702 + fpm@c3000 {
9703 + compatible = "fsl,fman-fpm";
9704 + reg = <0xc3000 0x1000>;
9705 + };
9706 +
9707 + parser@c7000 {
9708 + compatible = "fsl,fman-parser";
9709 + reg = <0xc7000 0x1000>;
9710 + };
9711 +
9712 + vsps@dc000 {
9713 + compatible = "fsl,fman-vsps";
9714 + reg = <0xdc000 0x1000>;
9715 + };
9716 +
9717 + mdio0: mdio@fc000 {
9718 + #address-cells = <1>;
9719 + #size-cells = <0>;
9720 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9721 + reg = <0xfc000 0x1000>;
9722 + };
9723 +
9724 + xmdio0: mdio@fd000 {
9725 + #address-cells = <1>;
9726 + #size-cells = <0>;
9727 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9728 + reg = <0xfd000 0x1000>;
9729 + };
9730 +
9731 + ptp_timer0: ptp-timer@fe000 {
9732 + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
9733 + reg = <0xfe000 0x1000>;
9734 + };
9735 +};
9736 --- /dev/null
9737 +++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
9738 @@ -0,0 +1,104 @@
9739 +/*
9740 + * QorIQ QMan Portals device tree
9741 + *
9742 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9743 + *
9744 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9745 + */
9746 +
9747 +&qportals {
9748 + #address-cells = <1>;
9749 + #size-cells = <1>;
9750 + compatible = "simple-bus";
9751 +
9752 + qportal0: qman-portal@0 {
9753 + compatible = "fsl,qman-portal";
9754 + reg = <0x0 0x4000 0x4000000 0x4000>;
9755 + interrupts = <0 172 0x4>;
9756 + cell-index = <0>;
9757 + };
9758 +
9759 + qportal1: qman-portal@10000 {
9760 + compatible = "fsl,qman-portal";
9761 + reg = <0x10000 0x4000 0x4010000 0x4000>;
9762 + interrupts = <0 174 0x4>;
9763 + cell-index = <1>;
9764 + };
9765 +
9766 + qportal2: qman-portal@20000 {
9767 + compatible = "fsl,qman-portal";
9768 + reg = <0x20000 0x4000 0x4020000 0x4000>;
9769 + interrupts = <0 176 0x4>;
9770 + cell-index = <2>;
9771 + };
9772 +
9773 + qportal3: qman-portal@30000 {
9774 + compatible = "fsl,qman-portal";
9775 + reg = <0x30000 0x4000 0x4030000 0x4000>;
9776 + interrupts = <0 178 0x4>;
9777 + cell-index = <3>;
9778 + };
9779 +
9780 + qportal4: qman-portal@40000 {
9781 + compatible = "fsl,qman-portal";
9782 + reg = <0x40000 0x4000 0x4040000 0x4000>;
9783 + interrupts = <0 180 0x4>;
9784 + cell-index = <4>;
9785 + };
9786 +
9787 + qportal5: qman-portal@50000 {
9788 + compatible = "fsl,qman-portal";
9789 + reg = <0x50000 0x4000 0x4050000 0x4000>;
9790 + interrupts = <0 182 0x4>;
9791 + cell-index = <5>;
9792 + };
9793 +
9794 + qportal6: qman-portal@60000 {
9795 + compatible = "fsl,qman-portal";
9796 + reg = <0x60000 0x4000 0x4060000 0x4000>;
9797 + interrupts = <0 184 0x4>;
9798 + cell-index = <6>;
9799 + };
9800 +
9801 + qportal7: qman-portal@70000 {
9802 + compatible = "fsl,qman-portal";
9803 + reg = <0x70000 0x4000 0x4070000 0x4000>;
9804 + interrupts = <0 186 0x4>;
9805 + cell-index = <7>;
9806 + };
9807 +
9808 + qportal8: qman-portal@80000 {
9809 + compatible = "fsl,qman-portal";
9810 + reg = <0x80000 0x4000 0x4080000 0x4000>;
9811 + interrupts = <0 188 0x4>;
9812 + cell-index = <8>;
9813 + };
9814 +
9815 + qman-fqids@0 {
9816 + compatible = "fsl,fqid-range";
9817 + fsl,fqid-range = <256 256>;
9818 + };
9819 +
9820 + qman-fqids@1 {
9821 + compatible = "fsl,fqid-range";
9822 + fsl,fqid-range = <32768 32768>;
9823 + };
9824 +
9825 + qman-pools@0 {
9826 + compatible = "fsl,pool-channel-range";
9827 + fsl,pool-channel-range = <0x401 0xf>;
9828 + };
9829 +
9830 + qman-cgrids@0 {
9831 + compatible = "fsl,cgrid-range";
9832 + fsl,cgrid-range = <0 256>;
9833 + };
9834 +
9835 + qman-ceetm@0 {
9836 + compatible = "fsl,qman-ceetm";
9837 + fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
9838 + fsl,ceetm-sp-range = <0 12>;
9839 + fsl,ceetm-lni-range = <0 8>;
9840 + fsl,ceetm-channel-range = <0 32>;
9841 + };
9842 +};
9843 --- a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
9844 +++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
9845 @@ -38,51 +38,61 @@
9846 compatible = "simple-bus";
9847
9848 bman-portal@0 {
9849 + cell-index = <0>;
9850 compatible = "fsl,bman-portal";
9851 reg = <0x0 0x4000>, <0x100000 0x1000>;
9852 interrupts = <105 2 0 0>;
9853 };
9854 bman-portal@4000 {
9855 + cell-index = <1>;
9856 compatible = "fsl,bman-portal";
9857 reg = <0x4000 0x4000>, <0x101000 0x1000>;
9858 interrupts = <107 2 0 0>;
9859 };
9860 bman-portal@8000 {
9861 + cell-index = <2>;
9862 compatible = "fsl,bman-portal";
9863 reg = <0x8000 0x4000>, <0x102000 0x1000>;
9864 interrupts = <109 2 0 0>;
9865 };
9866 bman-portal@c000 {
9867 + cell-index = <3>;
9868 compatible = "fsl,bman-portal";
9869 reg = <0xc000 0x4000>, <0x103000 0x1000>;
9870 interrupts = <111 2 0 0>;
9871 };
9872 bman-portal@10000 {
9873 + cell-index = <4>;
9874 compatible = "fsl,bman-portal";
9875 reg = <0x10000 0x4000>, <0x104000 0x1000>;
9876 interrupts = <113 2 0 0>;
9877 };
9878 bman-portal@14000 {
9879 + cell-index = <5>;
9880 compatible = "fsl,bman-portal";
9881 reg = <0x14000 0x4000>, <0x105000 0x1000>;
9882 interrupts = <115 2 0 0>;
9883 };
9884 bman-portal@18000 {
9885 + cell-index = <6>;
9886 compatible = "fsl,bman-portal";
9887 reg = <0x18000 0x4000>, <0x106000 0x1000>;
9888 interrupts = <117 2 0 0>;
9889 };
9890 bman-portal@1c000 {
9891 + cell-index = <7>;
9892 compatible = "fsl,bman-portal";
9893 reg = <0x1c000 0x4000>, <0x107000 0x1000>;
9894 interrupts = <119 2 0 0>;
9895 };
9896 bman-portal@20000 {
9897 + cell-index = <8>;
9898 compatible = "fsl,bman-portal";
9899 reg = <0x20000 0x4000>, <0x108000 0x1000>;
9900 interrupts = <121 2 0 0>;
9901 };
9902 bman-portal@24000 {
9903 + cell-index = <9>;
9904 compatible = "fsl,bman-portal";
9905 reg = <0x24000 0x4000>, <0x109000 0x1000>;
9906 interrupts = <123 2 0 0>;
9907 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
9908 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
9909 @@ -35,14 +35,14 @@
9910 fman@400000 {
9911 fman0_rx_0x10: port@90000 {
9912 cell-index = <0x10>;
9913 - compatible = "fsl,fman-v3-port-rx";
9914 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9915 reg = <0x90000 0x1000>;
9916 fsl,fman-10g-port;
9917 };
9918
9919 fman0_tx_0x30: port@b0000 {
9920 cell-index = <0x30>;
9921 - compatible = "fsl,fman-v3-port-tx";
9922 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9923 reg = <0xb0000 0x1000>;
9924 fsl,fman-10g-port;
9925 };
9926 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
9927 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
9928 @@ -35,14 +35,14 @@
9929 fman@400000 {
9930 fman0_rx_0x11: port@91000 {
9931 cell-index = <0x11>;
9932 - compatible = "fsl,fman-v3-port-rx";
9933 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9934 reg = <0x91000 0x1000>;
9935 fsl,fman-10g-port;
9936 };
9937
9938 fman0_tx_0x31: port@b1000 {
9939 cell-index = <0x31>;
9940 - compatible = "fsl,fman-v3-port-tx";
9941 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9942 reg = <0xb1000 0x1000>;
9943 fsl,fman-10g-port;
9944 };
OpenWrt Source Repository