daca6141933f21ebcdb93c7b846bb826e4c6bef2
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 302-dts-support-layercape.patch
1 From bfa4a794f91162cfeccfa4d59121cde9a84e32a3 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 10:02:10 +0800
4 Subject: [PATCH] dts: support layercape
5
6 This is a integrated patch for layerscape dts support.
7
8 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 Signed-off-by: Li Yang <leoyang.li@nxp.com>
11 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
12 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
15 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
18 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
19 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
20 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
21 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
22 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
23 Signed-off-by: Meng Yi <meng.yi@nxp.com>
24 Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
25 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
26 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
27 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
28 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
29 ---
30 arch/arm/boot/dts/alpine.dtsi | 2 +-
31 arch/arm/boot/dts/axm55xx.dtsi | 2 +-
32 arch/arm/boot/dts/ecx-2000.dts | 2 +-
33 arch/arm/boot/dts/imx6ul.dtsi | 4 +-
34 arch/arm/boot/dts/keystone.dtsi | 4 +-
35 arch/arm/boot/dts/ls1021a-qds.dts | 13 +
36 arch/arm/boot/dts/ls1021a-twr.dts | 13 +
37 arch/arm/boot/dts/ls1021a.dtsi | 155 ++--
38 arch/arm/boot/dts/mt6580.dtsi | 2 +-
39 arch/arm/boot/dts/mt6589.dtsi | 2 +-
40 arch/arm/boot/dts/mt8127.dtsi | 2 +-
41 arch/arm/boot/dts/mt8135.dtsi | 2 +-
42 arch/arm/boot/dts/rk3288.dtsi | 2 +-
43 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
44 arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
45 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
46 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
47 arch/arm64/boot/dts/freescale/Makefile | 16 +
48 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 177 ++++
49 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 198 +++++
50 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 134 +++
51 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 594 ++++++++++++++
52 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi | 45 +
53 .../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 69 ++
54 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 171 +++-
55 .../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 69 ++
56 .../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
57 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 113 ++-
58 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 302 ++++++-
59 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi | 48 ++
60 .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 109 +++
61 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 363 ++++++++
62 .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 76 ++
63 .../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
64 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 218 +++++
65 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 793 ++++++++++++++++++
66 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 173 ++++
67 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 236 ++++++
68 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 818 ++++++++++++++++++
69 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 191 ++---
70 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 169 ++--
71 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 9 +-
72 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 763 +++--------------
73 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++
74 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 162 ++++
75 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 140 ++++
76 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 195 +++++
77 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
78 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
79 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 912 +++++++++++++++++++++
80 .../boot/dts/freescale/qoriq-bman1-portals.dtsi | 81 ++
81 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 66 ++
82 .../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
83 .../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
84 .../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
85 .../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 +
86 .../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 +
87 .../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 +
88 .../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 +
89 .../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 +
90 .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++
91 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++
92 .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 104 +++
93 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
94 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
95 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
96 66 files changed, 7988 insertions(+), 1021 deletions(-)
97 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
98 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
99 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
100 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
101 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
102 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
103 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
104 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
105 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
106 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
107 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
108 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
109 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
110 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
111 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
112 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
113 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
114 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
115 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
116 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
117 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
118 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
119 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
120 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
121 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
122 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
123 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
124 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
125 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
126 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
127 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
128 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
129 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
130 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
131 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
132 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
133 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
134 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
135
136 diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
137 index db8752fc..d0eefc3b 100644
138 --- a/arch/arm/boot/dts/alpine.dtsi
139 +++ b/arch/arm/boot/dts/alpine.dtsi
140 @@ -93,7 +93,7 @@
141 interrupt-controller;
142 reg = <0x0 0xfb001000 0x0 0x1000>,
143 <0x0 0xfb002000 0x0 0x2000>,
144 - <0x0 0xfb004000 0x0 0x1000>,
145 + <0x0 0xfb004000 0x0 0x2000>,
146 <0x0 0xfb006000 0x0 0x2000>;
147 interrupts =
148 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
150 index a9d6d593..47799f59 100644
151 --- a/arch/arm/boot/dts/axm55xx.dtsi
152 +++ b/arch/arm/boot/dts/axm55xx.dtsi
153 @@ -62,7 +62,7 @@
154 #address-cells = <0>;
155 interrupt-controller;
156 reg = <0x20 0x01001000 0 0x1000>,
157 - <0x20 0x01002000 0 0x1000>,
158 + <0x20 0x01002000 0 0x2000>,
159 <0x20 0x01004000 0 0x2000>,
160 <0x20 0x01006000 0 0x2000>;
161 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
162 diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
163 index 2ccbb57f..c15e7e0c 100644
164 --- a/arch/arm/boot/dts/ecx-2000.dts
165 +++ b/arch/arm/boot/dts/ecx-2000.dts
166 @@ -99,7 +99,7 @@
167 interrupt-controller;
168 interrupts = <1 9 0xf04>;
169 reg = <0xfff11000 0x1000>,
170 - <0xfff12000 0x1000>,
171 + <0xfff12000 0x2000>,
172 <0xfff14000 0x2000>,
173 <0xfff16000 0x2000>;
174 };
175 diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
176 index c5c05fdc..c1396873 100644
177 --- a/arch/arm/boot/dts/imx6ul.dtsi
178 +++ b/arch/arm/boot/dts/imx6ul.dtsi
179 @@ -89,11 +89,11 @@
180 };
181
182 intc: interrupt-controller@00a01000 {
183 - compatible = "arm,cortex-a7-gic";
184 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
185 #interrupt-cells = <3>;
186 interrupt-controller;
187 reg = <0x00a01000 0x1000>,
188 - <0x00a02000 0x1000>,
189 + <0x00a02000 0x2000>,
190 <0x00a04000 0x2000>,
191 <0x00a06000 0x2000>;
192 };
193 diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
194 index 02708ba2..e30c83fc 100644
195 --- a/arch/arm/boot/dts/keystone.dtsi
196 +++ b/arch/arm/boot/dts/keystone.dtsi
197 @@ -30,12 +30,12 @@
198 };
199
200 gic: interrupt-controller {
201 - compatible = "arm,cortex-a15-gic";
202 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
203 #interrupt-cells = <3>;
204 interrupt-controller;
205 reg = <0x0 0x02561000 0x0 0x1000>,
206 <0x0 0x02562000 0x0 0x2000>,
207 - <0x0 0x02564000 0x0 0x1000>,
208 + <0x0 0x02564000 0x0 0x2000>,
209 <0x0 0x02566000 0x0 0x2000>;
210 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
211 IRQ_TYPE_LEVEL_HIGH)>;
212 diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
213 index 94087531..5611a9c9 100644
214 --- a/arch/arm/boot/dts/ls1021a-qds.dts
215 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
216 @@ -124,6 +124,19 @@
217 };
218 };
219
220 +&qspi {
221 + num-cs = <2>;
222 + status = "okay";
223 +
224 + qflash0: s25fl128s@0 {
225 + compatible = "spansion,m25p80";
226 + #address-cells = <1>;
227 + #size-cells = <1>;
228 + spi-max-frequency = <20000000>;
229 + reg = <0>;
230 + };
231 +};
232 +
233 &enet0 {
234 tbi-handle = <&tbi0>;
235 phy-handle = <&sgmii_phy1c>;
236 diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
237 index a8b148ad..907e5392 100644
238 --- a/arch/arm/boot/dts/ls1021a-twr.dts
239 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
240 @@ -142,6 +142,19 @@
241 };
242 };
243
244 +&qspi {
245 + num-cs = <2>;
246 + status = "okay";
247 +
248 + qflash0: n25q128a13@0 {
249 + compatible = "n25q128a13", "jedec,spi-nor";
250 + #address-cells = <1>;
251 + #size-cells = <1>;
252 + spi-max-frequency = <20000000>;
253 + reg = <0>;
254 + };
255 +};
256 +
257 &enet0 {
258 tbi-handle = <&tbi1>;
259 phy-handle = <&sgmii_phy2>;
260 diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
261 index 368e2193..9d8d1fee 100644
262 --- a/arch/arm/boot/dts/ls1021a.dtsi
263 +++ b/arch/arm/boot/dts/ls1021a.dtsi
264 @@ -74,17 +74,24 @@
265 compatible = "arm,cortex-a7";
266 device_type = "cpu";
267 reg = <0xf00>;
268 - clocks = <&cluster1_clk>;
269 + clocks = <&clockgen 1 0>;
270 };
271
272 cpu@f01 {
273 compatible = "arm,cortex-a7";
274 device_type = "cpu";
275 reg = <0xf01>;
276 - clocks = <&cluster1_clk>;
277 + clocks = <&clockgen 1 0>;
278 };
279 };
280
281 + sysclk: sysclk {
282 + compatible = "fixed-clock";
283 + #clock-cells = <0>;
284 + clock-frequency = <100000000>;
285 + clock-output-names = "sysclk";
286 + };
287 +
288 timer {
289 compatible = "arm,armv7-timer";
290 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
291 @@ -108,11 +115,11 @@
292 ranges;
293
294 gic: interrupt-controller@1400000 {
295 - compatible = "arm,cortex-a7-gic";
296 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
297 #interrupt-cells = <3>;
298 interrupt-controller;
299 reg = <0x0 0x1401000 0x0 0x1000>,
300 - <0x0 0x1402000 0x0 0x1000>,
301 + <0x0 0x1402000 0x0 0x2000>,
302 <0x0 0x1404000 0x0 0x2000>,
303 <0x0 0x1406000 0x0 0x2000>;
304 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
305 @@ -120,14 +127,14 @@
306 };
307
308 msi1: msi-controller@1570e00 {
309 - compatible = "fsl,1s1021a-msi";
310 + compatible = "fsl,ls1021a-msi";
311 reg = <0x0 0x1570e00 0x0 0x8>;
312 msi-controller;
313 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
314 };
315
316 msi2: msi-controller@1570e08 {
317 - compatible = "fsl,1s1021a-msi";
318 + compatible = "fsl,ls1021a-msi";
319 reg = <0x0 0x1570e08 0x0 0x8>;
320 msi-controller;
321 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
322 @@ -137,11 +144,12 @@
323 compatible = "fsl,ifc", "simple-bus";
324 reg = <0x0 0x1530000 0x0 0x10000>;
325 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
326 + big-endian;
327 };
328
329 dcfg: dcfg@1ee0000 {
330 compatible = "fsl,ls1021a-dcfg", "syscon";
331 - reg = <0x0 0x1ee0000 0x0 0x10000>;
332 + reg = <0x0 0x1ee0000 0x0 0x1000>;
333 big-endian;
334 };
335
336 @@ -163,7 +171,7 @@
337 <0x0 0x20220520 0x0 0x4>;
338 reg-names = "ahci", "sata-ecc";
339 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
340 - clocks = <&platform_clk 1>;
341 + clocks = <&clockgen 4 1>;
342 dma-coherent;
343 status = "disabled";
344 };
345 @@ -214,41 +222,10 @@
346 };
347
348 clockgen: clocking@1ee1000 {
349 - #address-cells = <1>;
350 - #size-cells = <1>;
351 - ranges = <0x0 0x0 0x1ee1000 0x10000>;
352 -
353 - sysclk: sysclk {
354 - compatible = "fixed-clock";
355 - #clock-cells = <0>;
356 - clock-output-names = "sysclk";
357 - };
358 -
359 - cga_pll1: pll@800 {
360 - compatible = "fsl,qoriq-core-pll-2.0";
361 - #clock-cells = <1>;
362 - reg = <0x800 0x10>;
363 - clocks = <&sysclk>;
364 - clock-output-names = "cga-pll1", "cga-pll1-div2",
365 - "cga-pll1-div4";
366 - };
367 -
368 - platform_clk: pll@c00 {
369 - compatible = "fsl,qoriq-core-pll-2.0";
370 - #clock-cells = <1>;
371 - reg = <0xc00 0x10>;
372 - clocks = <&sysclk>;
373 - clock-output-names = "platform-clk", "platform-clk-div2";
374 - };
375 -
376 - cluster1_clk: clk0c0@0 {
377 - compatible = "fsl,qoriq-core-mux-2.0";
378 - #clock-cells = <0>;
379 - reg = <0x0 0x10>;
380 - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
381 - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
382 - clock-output-names = "cluster1-clk";
383 - };
384 + compatible = "fsl,ls1021a-clockgen";
385 + reg = <0x0 0x1ee1000 0x0 0x1000>;
386 + #clock-cells = <2>;
387 + clocks = <&sysclk>;
388 };
389
390 dspi0: dspi@2100000 {
391 @@ -258,7 +235,7 @@
392 reg = <0x0 0x2100000 0x0 0x10000>;
393 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
394 clock-names = "dspi";
395 - clocks = <&platform_clk 1>;
396 + clocks = <&clockgen 4 1>;
397 spi-num-chipselects = <6>;
398 big-endian;
399 status = "disabled";
400 @@ -271,12 +248,27 @@
401 reg = <0x0 0x2110000 0x0 0x10000>;
402 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
403 clock-names = "dspi";
404 - clocks = <&platform_clk 1>;
405 + clocks = <&clockgen 4 1>;
406 spi-num-chipselects = <6>;
407 big-endian;
408 status = "disabled";
409 };
410
411 + qspi: quadspi@1550000 {
412 + compatible = "fsl,ls1021a-qspi";
413 + #address-cells = <1>;
414 + #size-cells = <0>;
415 + reg = <0x0 0x1550000 0x0 0x10000>,
416 + <0x0 0x40000000 0x0 0x4000000>;
417 + reg-names = "QuadSPI", "QuadSPI-memory";
418 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
419 + clock-names = "qspi_en", "qspi";
420 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
421 + big-endian;
422 + amba-base = <0x40000000>;
423 + status = "disabled";
424 + };
425 +
426 i2c0: i2c@2180000 {
427 compatible = "fsl,vf610-i2c";
428 #address-cells = <1>;
429 @@ -284,7 +276,7 @@
430 reg = <0x0 0x2180000 0x0 0x10000>;
431 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
432 clock-names = "i2c";
433 - clocks = <&platform_clk 1>;
434 + clocks = <&clockgen 4 1>;
435 status = "disabled";
436 };
437
438 @@ -295,7 +287,7 @@
439 reg = <0x0 0x2190000 0x0 0x10000>;
440 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
441 clock-names = "i2c";
442 - clocks = <&platform_clk 1>;
443 + clocks = <&clockgen 4 1>;
444 status = "disabled";
445 };
446
447 @@ -306,7 +298,7 @@
448 reg = <0x0 0x21a0000 0x0 0x10000>;
449 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
450 clock-names = "i2c";
451 - clocks = <&platform_clk 1>;
452 + clocks = <&clockgen 4 1>;
453 status = "disabled";
454 };
455
456 @@ -399,7 +391,7 @@
457 compatible = "fsl,ls1021a-lpuart";
458 reg = <0x0 0x2960000 0x0 0x1000>;
459 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
460 - clocks = <&platform_clk 1>;
461 + clocks = <&clockgen 4 1>;
462 clock-names = "ipg";
463 status = "disabled";
464 };
465 @@ -408,7 +400,7 @@
466 compatible = "fsl,ls1021a-lpuart";
467 reg = <0x0 0x2970000 0x0 0x1000>;
468 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
469 - clocks = <&platform_clk 1>;
470 + clocks = <&clockgen 4 1>;
471 clock-names = "ipg";
472 status = "disabled";
473 };
474 @@ -417,7 +409,7 @@
475 compatible = "fsl,ls1021a-lpuart";
476 reg = <0x0 0x2980000 0x0 0x1000>;
477 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
478 - clocks = <&platform_clk 1>;
479 + clocks = <&clockgen 4 1>;
480 clock-names = "ipg";
481 status = "disabled";
482 };
483 @@ -426,7 +418,7 @@
484 compatible = "fsl,ls1021a-lpuart";
485 reg = <0x0 0x2990000 0x0 0x1000>;
486 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
487 - clocks = <&platform_clk 1>;
488 + clocks = <&clockgen 4 1>;
489 clock-names = "ipg";
490 status = "disabled";
491 };
492 @@ -435,16 +427,26 @@
493 compatible = "fsl,ls1021a-lpuart";
494 reg = <0x0 0x29a0000 0x0 0x1000>;
495 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
496 - clocks = <&platform_clk 1>;
497 + clocks = <&clockgen 4 1>;
498 clock-names = "ipg";
499 status = "disabled";
500 };
501
502 + ftm0: ftm0@29d0000 {
503 + compatible = "fsl,ls1021a-ftm";
504 + reg = <0x0 0x29d0000 0x0 0x10000>,
505 + <0x0 0x1ee2140 0x0 0x4>;
506 + reg-names = "ftm", "FlexTimer1";
507 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
508 + big-endian;
509 + status = "okay";
510 + };
511 +
512 wdog0: watchdog@2ad0000 {
513 compatible = "fsl,imx21-wdt";
514 reg = <0x0 0x2ad0000 0x0 0x10000>;
515 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
516 - clocks = <&platform_clk 1>;
517 + clocks = <&clockgen 4 1>;
518 clock-names = "wdog-en";
519 big-endian;
520 };
521 @@ -454,8 +456,8 @@
522 compatible = "fsl,vf610-sai";
523 reg = <0x0 0x2b50000 0x0 0x10000>;
524 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
525 - clocks = <&platform_clk 1>, <&platform_clk 1>,
526 - <&platform_clk 1>, <&platform_clk 1>;
527 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
528 + <&clockgen 4 1>, <&clockgen 4 1>;
529 clock-names = "bus", "mclk1", "mclk2", "mclk3";
530 dma-names = "tx", "rx";
531 dmas = <&edma0 1 47>,
532 @@ -468,8 +470,8 @@
533 compatible = "fsl,vf610-sai";
534 reg = <0x0 0x2b60000 0x0 0x10000>;
535 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
536 - clocks = <&platform_clk 1>, <&platform_clk 1>,
537 - <&platform_clk 1>, <&platform_clk 1>;
538 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
539 + <&clockgen 4 1>, <&clockgen 4 1>;
540 clock-names = "bus", "mclk1", "mclk2", "mclk3";
541 dma-names = "tx", "rx";
542 dmas = <&edma0 1 45>,
543 @@ -489,16 +491,31 @@
544 dma-channels = <32>;
545 big-endian;
546 clock-names = "dmamux0", "dmamux1";
547 - clocks = <&platform_clk 1>,
548 - <&platform_clk 1>;
549 + clocks = <&clockgen 4 1>,
550 + <&clockgen 4 1>;
551 + };
552 +
553 + qdma: qdma@8390000 {
554 + compatible = "fsl,ls1021a-qdma";
555 + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
556 + <0x0 0x8389000 0x0 0x1000>, /* Status regs */
557 + <0x0 0x838a000 0x0 0x2000>; /* Block regs */
558 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
559 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
560 + interrupt-names = "qdma-error", "qdma-queue";
561 + channels = <8>;
562 + queues = <2>;
563 + status-sizes = <64>;
564 + queue-sizes = <64 64>;
565 + big-endian;
566 };
567
568 dcu: dcu@2ce0000 {
569 compatible = "fsl,ls1021a-dcu";
570 reg = <0x0 0x2ce0000 0x0 0x10000>;
571 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
572 - clocks = <&platform_clk 0>,
573 - <&platform_clk 0>;
574 + clocks = <&clockgen 4 0>,
575 + <&clockgen 4 0>;
576 clock-names = "dcu", "pix";
577 big-endian;
578 status = "disabled";
579 @@ -626,6 +643,8 @@
580 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
581 dr_mode = "host";
582 snps,quirk-frame-length-adjustment = <0x20>;
583 + configure-gfladj;
584 + dma-coherent;
585 snps,dis_rxdet_inp3_quirk;
586 };
587
588 @@ -634,7 +653,9 @@
589 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
590 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
591 reg-names = "regs", "config";
592 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
593 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
594 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
595 + interrupt-names = "pme", "aer";
596 fsl,pcie-scfg = <&scfg 0>;
597 #address-cells = <3>;
598 #size-cells = <2>;
599 @@ -643,7 +664,7 @@
600 bus-range = <0x0 0xff>;
601 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
602 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
603 - msi-parent = <&msi1>;
604 + msi-parent = <&msi1>, <&msi2>;
605 #interrupt-cells = <1>;
606 interrupt-map-mask = <0 0 0 7>;
607 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
608 @@ -657,7 +678,9 @@
609 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
610 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
611 reg-names = "regs", "config";
612 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
613 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
614 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
615 + interrupt-names = "pme", "aer";
616 fsl,pcie-scfg = <&scfg 1>;
617 #address-cells = <3>;
618 #size-cells = <2>;
619 @@ -666,7 +689,7 @@
620 bus-range = <0x0 0xff>;
621 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
622 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
623 - msi-parent = <&msi2>;
624 + msi-parent = <&msi1>, <&msi2>;
625 #interrupt-cells = <1>;
626 interrupt-map-mask = <0 0 0 7>;
627 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
628 diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
629 index 06fdf6c2..a349dba5 100644
630 --- a/arch/arm/boot/dts/mt6580.dtsi
631 +++ b/arch/arm/boot/dts/mt6580.dtsi
632 @@ -91,7 +91,7 @@
633 #interrupt-cells = <3>;
634 interrupt-parent = <&gic>;
635 reg = <0x10211000 0x1000>,
636 - <0x10212000 0x1000>,
637 + <0x10212000 0x2000>,
638 <0x10214000 0x2000>,
639 <0x10216000 0x2000>;
640 };
641 diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
642 index 88b3cb12..0d6f60af 100644
643 --- a/arch/arm/boot/dts/mt6589.dtsi
644 +++ b/arch/arm/boot/dts/mt6589.dtsi
645 @@ -102,7 +102,7 @@
646 #interrupt-cells = <3>;
647 interrupt-parent = <&gic>;
648 reg = <0x10211000 0x1000>,
649 - <0x10212000 0x1000>,
650 + <0x10212000 0x2000>,
651 <0x10214000 0x2000>,
652 <0x10216000 0x2000>;
653 };
654 diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
655 index 52086c80..916c095d 100644
656 --- a/arch/arm/boot/dts/mt8127.dtsi
657 +++ b/arch/arm/boot/dts/mt8127.dtsi
658 @@ -129,7 +129,7 @@
659 #interrupt-cells = <3>;
660 interrupt-parent = <&gic>;
661 reg = <0 0x10211000 0 0x1000>,
662 - <0 0x10212000 0 0x1000>,
663 + <0 0x10212000 0 0x2000>,
664 <0 0x10214000 0 0x2000>,
665 <0 0x10216000 0 0x2000>;
666 };
667 diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
668 index 1d7f92bd..a97b4ee4 100644
669 --- a/arch/arm/boot/dts/mt8135.dtsi
670 +++ b/arch/arm/boot/dts/mt8135.dtsi
671 @@ -221,7 +221,7 @@
672 #interrupt-cells = <3>;
673 interrupt-parent = <&gic>;
674 reg = <0 0x10211000 0 0x1000>,
675 - <0 0x10212000 0 0x1000>,
676 + <0 0x10212000 0 0x2000>,
677 <0 0x10214000 0 0x2000>,
678 <0 0x10216000 0 0x2000>;
679 };
680 diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
681 index 17ec2e2d..559fc549 100644
682 --- a/arch/arm/boot/dts/rk3288.dtsi
683 +++ b/arch/arm/boot/dts/rk3288.dtsi
684 @@ -1109,7 +1109,7 @@
685 #address-cells = <0>;
686
687 reg = <0xffc01000 0x1000>,
688 - <0xffc02000 0x1000>,
689 + <0xffc02000 0x2000>,
690 <0xffc04000 0x2000>,
691 <0xffc06000 0x2000>;
692 interrupts = <GIC_PPI 9 0xf04>;
693 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
694 index ce196045..97f28399 100644
695 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
696 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
697 @@ -791,7 +791,7 @@
698 gic: interrupt-controller@01c81000 {
699 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
700 reg = <0x01c81000 0x1000>,
701 - <0x01c82000 0x1000>,
702 + <0x01c82000 0x2000>,
703 <0x01c84000 0x2000>,
704 <0x01c86000 0x2000>;
705 interrupt-controller;
706 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
707 index 94cf5a1c..81e5a44c 100644
708 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
709 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
710 @@ -1685,9 +1685,9 @@
711 };
712
713 gic: interrupt-controller@01c81000 {
714 - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
715 + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
716 reg = <0x01c81000 0x1000>,
717 - <0x01c82000 0x1000>,
718 + <0x01c82000 0x2000>,
719 <0x01c84000 0x2000>,
720 <0x01c86000 0x2000>;
721 interrupt-controller;
722 diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
723 index 300a1bd5..cdff5888 100644
724 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
725 +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
726 @@ -488,7 +488,7 @@
727 gic: interrupt-controller@01c81000 {
728 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
729 reg = <0x01c81000 0x1000>,
730 - <0x01c82000 0x1000>,
731 + <0x01c82000 0x2000>,
732 <0x01c84000 0x2000>,
733 <0x01c86000 0x2000>;
734 interrupt-controller;
735 diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
736 index 3c5214cb..ba7e7c71 100644
737 --- a/arch/arm/boot/dts/sun9i-a80.dtsi
738 +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
739 @@ -613,7 +613,7 @@
740 gic: interrupt-controller@01c41000 {
741 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
742 reg = <0x01c41000 0x1000>,
743 - <0x01c42000 0x1000>,
744 + <0x01c42000 0x2000>,
745 <0x01c44000 0x2000>,
746 <0x01c46000 0x2000>;
747 interrupt-controller;
748 diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
749 index 1b7783db..2d7986a1 100644
750 --- a/arch/arm64/boot/dts/freescale/Makefile
751 +++ b/arch/arm64/boot/dts/freescale/Makefile
752 @@ -1,8 +1,24 @@
753 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
754 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
755 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
756 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
757 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
758 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
759 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
760 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
761 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
762 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
763 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
764 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
765 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
766 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
767 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
768 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
769 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
770 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
771 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
772 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
773 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
774
775 always := $(dtb-y)
776 subdir-y := $(dts-dirs)
777 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
778 new file mode 100644
779 index 00000000..de8ee499
780 --- /dev/null
781 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
782 @@ -0,0 +1,177 @@
783 +/*
784 + * Device Tree file for Freescale LS1012A Freedom Board.
785 + *
786 + * Copyright 2016 Freescale Semiconductor, Inc.
787 + *
788 + * This file is dual-licensed: you can use it either under the terms
789 + * of the GPLv2 or the X11 license, at your option. Note that this dual
790 + * licensing only applies to this file, and not this project as a
791 + * whole.
792 + *
793 + * a) This library is free software; you can redistribute it and/or
794 + * modify it under the terms of the GNU General Public License as
795 + * published by the Free Software Foundation; either version 2 of the
796 + * License, or (at your option) any later version.
797 + *
798 + * This library is distributed in the hope that it will be useful,
799 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
800 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
801 + * GNU General Public License for more details.
802 + *
803 + * Or, alternatively,
804 + *
805 + * b) Permission is hereby granted, free of charge, to any person
806 + * obtaining a copy of this software and associated documentation
807 + * files (the "Software"), to deal in the Software without
808 + * restriction, including without limitation the rights to use,
809 + * copy, modify, merge, publish, distribute, sublicense, and/or
810 + * sell copies of the Software, and to permit persons to whom the
811 + * Software is furnished to do so, subject to the following
812 + * conditions:
813 + *
814 + * The above copyright notice and this permission notice shall be
815 + * included in all copies or substantial portions of the Software.
816 + *
817 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
818 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
819 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
820 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
821 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
822 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
823 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
824 + * OTHER DEALINGS IN THE SOFTWARE.
825 + */
826 +/dts-v1/;
827 +
828 +#include "fsl-ls1012a.dtsi"
829 +
830 +/ {
831 + model = "LS1012A Freedom Board";
832 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
833 +
834 + aliases {
835 + ethernet0 = &pfe_mac0;
836 + ethernet1 = &pfe_mac1;
837 + };
838 +
839 + sys_mclk: clock-mclk {
840 + compatible = "fixed-clock";
841 + #clock-cells = <0>;
842 + clock-frequency = <25000000>;
843 + };
844 +
845 + reg_1p8v: regulator-1p8v {
846 + compatible = "regulator-fixed";
847 + regulator-name = "1P8V";
848 + regulator-min-microvolt = <1800000>;
849 + regulator-max-microvolt = <1800000>;
850 + regulator-always-on;
851 + };
852 +
853 + sound {
854 + compatible = "simple-audio-card";
855 + simple-audio-card,format = "i2s";
856 + simple-audio-card,widgets =
857 + "Microphone", "Microphone Jack",
858 + "Headphone", "Headphone Jack",
859 + "Speaker", "Speaker Ext",
860 + "Line", "Line In Jack";
861 + simple-audio-card,routing =
862 + "MIC_IN", "Microphone Jack",
863 + "Microphone Jack", "Mic Bias",
864 + "LINE_IN", "Line In Jack",
865 + "Headphone Jack", "HP_OUT",
866 + "Speaker Ext", "LINE_OUT";
867 +
868 + simple-audio-card,cpu {
869 + sound-dai = <&sai2>;
870 + frame-master;
871 + bitclock-master;
872 + };
873 +
874 + simple-audio-card,codec {
875 + sound-dai = <&codec>;
876 + frame-master;
877 + bitclock-master;
878 + system-clock-frequency = <25000000>;
879 + };
880 + };
881 +};
882 +
883 +&duart0 {
884 + status = "okay";
885 +};
886 +
887 +&i2c0 {
888 + status = "okay";
889 +
890 + codec: sgtl5000@a {
891 + #sound-dai-cells = <0>;
892 + compatible = "fsl,sgtl5000";
893 + reg = <0xa>;
894 + VDDA-supply = <&reg_1p8v>;
895 + VDDIO-supply = <&reg_1p8v>;
896 + clocks = <&sys_mclk>;
897 + };
898 +};
899 +
900 +&qspi {
901 + num-cs = <1>;
902 + bus-num = <0>;
903 + status = "okay";
904 +
905 + qflash0: s25fs512s@0 {
906 + compatible = "spansion,m25p80";
907 + #address-cells = <1>;
908 + #size-cells = <1>;
909 + m25p,fast-read;
910 + spi-max-frequency = <20000000>;
911 + reg = <0>;
912 + };
913 +};
914 +
915 +&pfe {
916 + status = "okay";
917 + #address-cells = <1>;
918 + #size-cells = <0>;
919 +
920 + ethernet@0 {
921 + compatible = "fsl,pfe-gemac-port";
922 + #address-cells = <1>;
923 + #size-cells = <0>;
924 + reg = <0x0>; /* GEM_ID */
925 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
926 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
927 + fsl,mdio-mux-val = <0x0>;
928 + phy-mode = "sgmii";
929 + fsl,pfe-phy-if-flags = <0x0>;
930 +
931 + mdio@0 {
932 + reg = <0x1>; /* enabled/disabled */
933 + };
934 + };
935 +
936 + ethernet@1 {
937 + compatible = "fsl,pfe-gemac-port";
938 + #address-cells = <1>;
939 + #size-cells = <0>;
940 + reg = <0x1>; /* GEM_ID */
941 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
942 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
943 + fsl,mdio-mux-val = <0x0>;
944 + phy-mode = "sgmii";
945 + fsl,pfe-phy-if-flags = <0x0>;
946 +
947 + mdio@0 {
948 + reg = <0x0>; /* enabled/disabled */
949 + };
950 + };
951 +};
952 +
953 +&sai2 {
954 + status = "okay";
955 +};
956 +
957 +&sata {
958 + status = "okay";
959 +};
960 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
961 new file mode 100644
962 index 00000000..edd87676
963 --- /dev/null
964 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
965 @@ -0,0 +1,198 @@
966 +/*
967 + * Device Tree file for Freescale LS1012A QDS Board.
968 + *
969 + * Copyright 2016 Freescale Semiconductor, Inc.
970 + *
971 + * This file is dual-licensed: you can use it either under the terms
972 + * of the GPLv2 or the X11 license, at your option. Note that this dual
973 + * licensing only applies to this file, and not this project as a
974 + * whole.
975 + *
976 + * a) This library is free software; you can redistribute it and/or
977 + * modify it under the terms of the GNU General Public License as
978 + * published by the Free Software Foundation; either version 2 of the
979 + * License, or (at your option) any later version.
980 + *
981 + * This library is distributed in the hope that it will be useful,
982 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
983 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
984 + * GNU General Public License for more details.
985 + *
986 + * Or, alternatively,
987 + *
988 + * b) Permission is hereby granted, free of charge, to any person
989 + * obtaining a copy of this software and associated documentation
990 + * files (the "Software"), to deal in the Software without
991 + * restriction, including without limitation the rights to use,
992 + * copy, modify, merge, publish, distribute, sublicense, and/or
993 + * sell copies of the Software, and to permit persons to whom the
994 + * Software is furnished to do so, subject to the following
995 + * conditions:
996 + *
997 + * The above copyright notice and this permission notice shall be
998 + * included in all copies or substantial portions of the Software.
999 + *
1000 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1001 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1002 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1003 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1004 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1005 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1006 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1007 + * OTHER DEALINGS IN THE SOFTWARE.
1008 + */
1009 +/dts-v1/;
1010 +
1011 +#include "fsl-ls1012a.dtsi"
1012 +
1013 +/ {
1014 + model = "LS1012A QDS Board";
1015 + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
1016 +
1017 + aliases {
1018 + ethernet0 = &pfe_mac0;
1019 + ethernet1 = &pfe_mac1;
1020 + };
1021 +
1022 + sys_mclk: clock-mclk {
1023 + compatible = "fixed-clock";
1024 + #clock-cells = <0>;
1025 + clock-frequency = <24576000>;
1026 + };
1027 +
1028 + reg_3p3v: regulator-3p3v {
1029 + compatible = "regulator-fixed";
1030 + regulator-name = "3P3V";
1031 + regulator-min-microvolt = <3300000>;
1032 + regulator-max-microvolt = <3300000>;
1033 + regulator-always-on;
1034 + };
1035 +
1036 + sound {
1037 + compatible = "simple-audio-card";
1038 + simple-audio-card,format = "i2s";
1039 + simple-audio-card,widgets =
1040 + "Microphone", "Microphone Jack",
1041 + "Headphone", "Headphone Jack",
1042 + "Speaker", "Speaker Ext",
1043 + "Line", "Line In Jack";
1044 + simple-audio-card,routing =
1045 + "MIC_IN", "Microphone Jack",
1046 + "Microphone Jack", "Mic Bias",
1047 + "LINE_IN", "Line In Jack",
1048 + "Headphone Jack", "HP_OUT",
1049 + "Speaker Ext", "LINE_OUT";
1050 +
1051 + simple-audio-card,cpu {
1052 + sound-dai = <&sai2>;
1053 + frame-master;
1054 + bitclock-master;
1055 + };
1056 +
1057 + simple-audio-card,codec {
1058 + sound-dai = <&codec>;
1059 + frame-master;
1060 + bitclock-master;
1061 + system-clock-frequency = <24576000>;
1062 + };
1063 + };
1064 +};
1065 +
1066 +&duart0 {
1067 + status = "okay";
1068 +};
1069 +
1070 +&i2c0 {
1071 + status = "okay";
1072 +
1073 + pca9547@77 {
1074 + compatible = "nxp,pca9547";
1075 + reg = <0x77>;
1076 + #address-cells = <1>;
1077 + #size-cells = <0>;
1078 +
1079 + i2c@4 {
1080 + #address-cells = <1>;
1081 + #size-cells = <0>;
1082 + reg = <0x4>;
1083 +
1084 + codec: sgtl5000@a {
1085 + #sound-dai-cells = <0>;
1086 + compatible = "fsl,sgtl5000";
1087 + reg = <0xa>;
1088 + VDDA-supply = <&reg_3p3v>;
1089 + VDDIO-supply = <&reg_3p3v>;
1090 + clocks = <&sys_mclk>;
1091 + };
1092 + };
1093 + };
1094 +};
1095 +
1096 +&qspi {
1097 + num-cs = <2>;
1098 + bus-num = <0>;
1099 + status = "okay";
1100 +
1101 + qflash0: s25fs512s@0 {
1102 + compatible = "spansion,m25p80";
1103 + #address-cells = <1>;
1104 + #size-cells = <1>;
1105 + spi-max-frequency = <20000000>;
1106 + m25p,fast-read;
1107 + reg = <0>;
1108 + };
1109 +};
1110 +
1111 +&pfe {
1112 + status = "okay";
1113 + #address-cells = <1>;
1114 + #size-cells = <0>;
1115 +
1116 + ethernet@0 {
1117 + compatible = "fsl,pfe-gemac-port";
1118 + #address-cells = <1>;
1119 + #size-cells = <0>;
1120 + reg = <0x0>; /* GEM_ID */
1121 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1122 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1123 + fsl,mdio-mux-val = <0x2>;
1124 + phy-mode = "sgmii-2500";
1125 + fsl,pfe-phy-if-flags = <0x0>;
1126 +
1127 + mdio@0 {
1128 + reg = <0x1>; /* enabled/disabled */
1129 + };
1130 + };
1131 +
1132 + ethernet@1 {
1133 + compatible = "fsl,pfe-gemac-port";
1134 + #address-cells = <1>;
1135 + #size-cells = <0>;
1136 + reg = <0x1>; /* GEM_ID */
1137 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1138 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1139 + fsl,mdio-mux-val = <0x3>;
1140 + phy-mode = "sgmii-2500";
1141 + fsl,pfe-phy-if-flags = <0x0>;
1142 +
1143 + mdio@0 {
1144 + reg = <0x0>; /* enabled/disabled */
1145 + };
1146 + };
1147 +};
1148 +
1149 +&sai2 {
1150 + status = "okay";
1151 +};
1152 +
1153 +&sata {
1154 + status = "okay";
1155 +};
1156 +
1157 +&esdhc0 {
1158 + status = "okay";
1159 +};
1160 +
1161 +&esdhc1 {
1162 + status = "okay";
1163 +};
1164 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1165 new file mode 100644
1166 index 00000000..88684eac
1167 --- /dev/null
1168 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1169 @@ -0,0 +1,134 @@
1170 +/*
1171 + * Device Tree file for Freescale LS1012A RDB Board.
1172 + *
1173 + * Copyright 2016 Freescale Semiconductor, Inc.
1174 + *
1175 + * This file is dual-licensed: you can use it either under the terms
1176 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1177 + * licensing only applies to this file, and not this project as a
1178 + * whole.
1179 + *
1180 + * a) This library is free software; you can redistribute it and/or
1181 + * modify it under the terms of the GNU General Public License as
1182 + * published by the Free Software Foundation; either version 2 of the
1183 + * License, or (at your option) any later version.
1184 + *
1185 + * This library is distributed in the hope that it will be useful,
1186 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1187 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1188 + * GNU General Public License for more details.
1189 + *
1190 + * Or, alternatively,
1191 + *
1192 + * b) Permission is hereby granted, free of charge, to any person
1193 + * obtaining a copy of this software and associated documentation
1194 + * files (the "Software"), to deal in the Software without
1195 + * restriction, including without limitation the rights to use,
1196 + * copy, modify, merge, publish, distribute, sublicense, and/or
1197 + * sell copies of the Software, and to permit persons to whom the
1198 + * Software is furnished to do so, subject to the following
1199 + * conditions:
1200 + *
1201 + * The above copyright notice and this permission notice shall be
1202 + * included in all copies or substantial portions of the Software.
1203 + *
1204 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1205 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1206 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1207 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1208 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1209 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1210 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1211 + * OTHER DEALINGS IN THE SOFTWARE.
1212 + */
1213 +/dts-v1/;
1214 +
1215 +#include "fsl-ls1012a.dtsi"
1216 +
1217 +/ {
1218 + model = "LS1012A RDB Board";
1219 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1220 +
1221 + aliases {
1222 + ethernet0 = &pfe_mac0;
1223 + ethernet1 = &pfe_mac1;
1224 + };
1225 +};
1226 +
1227 +&duart0 {
1228 + status = "okay";
1229 +};
1230 +
1231 +&i2c0 {
1232 + status = "okay";
1233 +};
1234 +
1235 +&qspi {
1236 + num-cs = <2>;
1237 + bus-num = <0>;
1238 + status = "okay";
1239 +
1240 + qflash0: s25fs512s@0 {
1241 + compatible = "spansion,m25p80";
1242 + #address-cells = <1>;
1243 + #size-cells = <1>;
1244 + spi-max-frequency = <20000000>;
1245 + m25p,fast-read;
1246 + reg = <0>;
1247 + };
1248 +};
1249 +
1250 +&sata {
1251 + status = "okay";
1252 +};
1253 +
1254 +&esdhc0 {
1255 + sd-uhs-sdr104;
1256 + sd-uhs-sdr50;
1257 + sd-uhs-sdr25;
1258 + sd-uhs-sdr12;
1259 + status = "okay";
1260 +};
1261 +
1262 +&esdhc1 {
1263 + mmc-hs200-1_8v;
1264 + status = "okay";
1265 +};
1266 +
1267 +&pfe {
1268 + status = "okay";
1269 + #address-cells = <1>;
1270 + #size-cells = <0>;
1271 +
1272 + ethernet@0 {
1273 + compatible = "fsl,pfe-gemac-port";
1274 + #address-cells = <1>;
1275 + #size-cells = <0>;
1276 + reg = <0x0>; /* GEM_ID */
1277 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1278 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1279 + fsl,mdio-mux-val = <0x0>;
1280 + phy-mode = "sgmii";
1281 + fsl,pfe-phy-if-flags = <0x0>;
1282 +
1283 + mdio@0 {
1284 + reg = <0x1>; /* enabled/disabled */
1285 + };
1286 + };
1287 +
1288 + ethernet@1 {
1289 + compatible = "fsl,pfe-gemac-port";
1290 + #address-cells = <1>;
1291 + #size-cells = <0>;
1292 + reg = <0x1>; /* GEM_ID */
1293 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
1294 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
1295 + fsl,mdio-mux-val = <0x0>;
1296 + phy-mode = "rgmii-txid";
1297 + fsl,pfe-phy-if-flags = <0x0>;
1298 +
1299 + mdio@0 {
1300 + reg = <0x0>; /* enabled/disabled */
1301 + };
1302 + };
1303 +};
1304 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1305 new file mode 100644
1306 index 00000000..0b11ece1
1307 --- /dev/null
1308 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1309 @@ -0,0 +1,594 @@
1310 +/*
1311 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
1312 + *
1313 + * Copyright 2016 Freescale Semiconductor, Inc.
1314 + *
1315 + * This file is dual-licensed: you can use it either under the terms
1316 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1317 + * licensing only applies to this file, and not this project as a
1318 + * whole.
1319 + *
1320 + * a) This library is free software; you can redistribute it and/or
1321 + * modify it under the terms of the GNU General Public License as
1322 + * published by the Free Software Foundation; either version 2 of the
1323 + * License, or (at your option) any later version.
1324 + *
1325 + * This library is distributed in the hope that it will be useful,
1326 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1327 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1328 + * GNU General Public License for more details.
1329 + *
1330 + * Or, alternatively,
1331 + *
1332 + * b) Permission is hereby granted, free of charge, to any person
1333 + * obtaining a copy of this software and associated documentation
1334 + * files (the "Software"), to deal in the Software without
1335 + * restriction, including without limitation the rights to use,
1336 + * copy, modify, merge, publish, distribute, sublicense, and/or
1337 + * sell copies of the Software, and to permit persons to whom the
1338 + * Software is furnished to do so, subject to the following
1339 + * conditions:
1340 + *
1341 + * The above copyright notice and this permission notice shall be
1342 + * included in all copies or substantial portions of the Software.
1343 + *
1344 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1345 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1346 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1347 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1348 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1349 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1350 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1351 + * OTHER DEALINGS IN THE SOFTWARE.
1352 + */
1353 +
1354 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1355 +#include <dt-bindings/thermal/thermal.h>
1356 +
1357 +/ {
1358 + compatible = "fsl,ls1012a";
1359 + interrupt-parent = <&gic>;
1360 + #address-cells = <2>;
1361 + #size-cells = <2>;
1362 +
1363 + aliases {
1364 + crypto = &crypto;
1365 + rtic_a = &rtic_a;
1366 + rtic_b = &rtic_b;
1367 + rtic_c = &rtic_c;
1368 + rtic_d = &rtic_d;
1369 + sec_mon = &sec_mon;
1370 + };
1371 +
1372 + cpus {
1373 + #address-cells = <1>;
1374 + #size-cells = <0>;
1375 +
1376 + cpu0: cpu@0 {
1377 + device_type = "cpu";
1378 + compatible = "arm,cortex-a53";
1379 + reg = <0x0>;
1380 + clocks = <&clockgen 1 0>;
1381 + #cooling-cells = <2>;
1382 + cpu-idle-states = <&CPU_PH20>;
1383 + };
1384 + };
1385 +
1386 + idle-states {
1387 + /*
1388 + * PSCI node is not added default, U-boot will add missing
1389 + * parts if it determines to use PSCI.
1390 + */
1391 + entry-method = "arm,psci";
1392 +
1393 + CPU_PH20: cpu-ph20 {
1394 + compatible = "arm,idle-state";
1395 + idle-state-name = "PH20";
1396 + arm,psci-suspend-param = <0x0>;
1397 + entry-latency-us = <1000>;
1398 + exit-latency-us = <1000>;
1399 + min-residency-us = <3000>;
1400 + };
1401 + };
1402 +
1403 + sysclk: sysclk {
1404 + compatible = "fixed-clock";
1405 + #clock-cells = <0>;
1406 + clock-frequency = <125000000>;
1407 + clock-output-names = "sysclk";
1408 + };
1409 +
1410 + coreclk: coreclk {
1411 + compatible = "fixed-clock";
1412 + #clock-cells = <0>;
1413 + clock-frequency = <100000000>;
1414 + clock-output-names = "coreclk";
1415 + };
1416 +
1417 + timer {
1418 + compatible = "arm,armv8-timer";
1419 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
1420 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
1421 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
1422 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
1423 + };
1424 +
1425 + pmu {
1426 + compatible = "arm,armv8-pmuv3";
1427 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1428 + };
1429 +
1430 + gic: interrupt-controller@1400000 {
1431 + compatible = "arm,gic-400";
1432 + #interrupt-cells = <3>;
1433 + interrupt-controller;
1434 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
1435 + <0x0 0x1402000 0 0x2000>, /* GICC */
1436 + <0x0 0x1404000 0 0x2000>, /* GICH */
1437 + <0x0 0x1406000 0 0x2000>; /* GICV */
1438 + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
1439 + };
1440 +
1441 + reboot {
1442 + compatible = "syscon-reboot";
1443 + regmap = <&dcfg>;
1444 + offset = <0xb0>;
1445 + mask = <0x02>;
1446 + };
1447 +
1448 + soc {
1449 + compatible = "simple-bus";
1450 + #address-cells = <2>;
1451 + #size-cells = <2>;
1452 + ranges;
1453 +
1454 + scfg: scfg@1570000 {
1455 + compatible = "fsl,ls1012a-scfg", "syscon";
1456 + reg = <0x0 0x1570000 0x0 0x10000>;
1457 + big-endian;
1458 + };
1459 +
1460 + crypto: crypto@1700000 {
1461 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
1462 + "fsl,sec-v4.0";
1463 + fsl,sec-era = <8>;
1464 + #address-cells = <1>;
1465 + #size-cells = <1>;
1466 + ranges = <0x0 0x00 0x1700000 0x100000>;
1467 + reg = <0x00 0x1700000 0x0 0x100000>;
1468 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1469 +
1470 + sec_jr0: jr@10000 {
1471 + compatible = "fsl,sec-v5.4-job-ring",
1472 + "fsl,sec-v5.0-job-ring",
1473 + "fsl,sec-v4.0-job-ring";
1474 + reg = <0x10000 0x10000>;
1475 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1476 + };
1477 +
1478 + sec_jr1: jr@20000 {
1479 + compatible = "fsl,sec-v5.4-job-ring",
1480 + "fsl,sec-v5.0-job-ring",
1481 + "fsl,sec-v4.0-job-ring";
1482 + reg = <0x20000 0x10000>;
1483 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1484 + };
1485 +
1486 + sec_jr2: jr@30000 {
1487 + compatible = "fsl,sec-v5.4-job-ring",
1488 + "fsl,sec-v5.0-job-ring",
1489 + "fsl,sec-v4.0-job-ring";
1490 + reg = <0x30000 0x10000>;
1491 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1492 + };
1493 +
1494 + sec_jr3: jr@40000 {
1495 + compatible = "fsl,sec-v5.4-job-ring",
1496 + "fsl,sec-v5.0-job-ring",
1497 + "fsl,sec-v4.0-job-ring";
1498 + reg = <0x40000 0x10000>;
1499 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1500 + };
1501 +
1502 + caam-dma {
1503 + compatible = "fsl,sec-v5.4-dma",
1504 + "fsl,sec-v5.0-dma",
1505 + "fsl,sec-v4.0-dma";
1506 + };
1507 +
1508 + rtic@60000 {
1509 + compatible = "fsl,sec-v5.4-rtic",
1510 + "fsl,sec-v5.0-rtic",
1511 + "fsl,sec-v4.0-rtic";
1512 + #address-cells = <1>;
1513 + #size-cells = <1>;
1514 + reg = <0x60000 0x100 0x60e00 0x18>;
1515 + ranges = <0x0 0x60100 0x500>;
1516 +
1517 + rtic_a: rtic-a@0 {
1518 + compatible = "fsl,sec-v5.4-rtic-memory",
1519 + "fsl,sec-v5.0-rtic-memory",
1520 + "fsl,sec-v4.0-rtic-memory";
1521 + reg = <0x00 0x20 0x100 0x100>;
1522 + };
1523 +
1524 + rtic_b: rtic-b@20 {
1525 + compatible = "fsl,sec-v5.4-rtic-memory",
1526 + "fsl,sec-v5.0-rtic-memory",
1527 + "fsl,sec-v4.0-rtic-memory";
1528 + reg = <0x20 0x20 0x200 0x100>;
1529 + };
1530 +
1531 + rtic_c: rtic-c@40 {
1532 + compatible = "fsl,sec-v5.4-rtic-memory",
1533 + "fsl,sec-v5.0-rtic-memory",
1534 + "fsl,sec-v4.0-rtic-memory";
1535 + reg = <0x40 0x20 0x300 0x100>;
1536 + };
1537 +
1538 + rtic_d: rtic-d@60 {
1539 + compatible = "fsl,sec-v5.4-rtic-memory",
1540 + "fsl,sec-v5.0-rtic-memory",
1541 + "fsl,sec-v4.0-rtic-memory";
1542 + reg = <0x60 0x20 0x400 0x100>;
1543 + };
1544 + };
1545 + };
1546 +
1547 + sec_mon: sec_mon@1e90000 {
1548 + compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
1549 + "fsl,sec-v4.0-mon";
1550 + reg = <0x0 0x1e90000 0x0 0x10000>;
1551 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
1552 + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1553 + };
1554 +
1555 + dcfg: dcfg@1ee0000 {
1556 + compatible = "fsl,ls1012a-dcfg",
1557 + "syscon";
1558 + reg = <0x0 0x1ee0000 0x0 0x10000>;
1559 + big-endian;
1560 + };
1561 +
1562 + clockgen: clocking@1ee1000 {
1563 + compatible = "fsl,ls1012a-clockgen";
1564 + reg = <0x0 0x1ee1000 0x0 0x1000>;
1565 + #clock-cells = <2>;
1566 + clocks = <&sysclk &coreclk>;
1567 + clock-names = "sysclk", "coreclk";
1568 + };
1569 +
1570 + tmu: tmu@1f00000 {
1571 + compatible = "fsl,qoriq-tmu";
1572 + reg = <0x0 0x1f00000 0x0 0x10000>;
1573 + interrupts = <0 33 0x4>;
1574 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
1575 + fsl,tmu-calibration = <0x00000000 0x00000026
1576 + 0x00000001 0x0000002d
1577 + 0x00000002 0x00000032
1578 + 0x00000003 0x00000039
1579 + 0x00000004 0x0000003f
1580 + 0x00000005 0x00000046
1581 + 0x00000006 0x0000004d
1582 + 0x00000007 0x00000054
1583 + 0x00000008 0x0000005a
1584 + 0x00000009 0x00000061
1585 + 0x0000000a 0x0000006a
1586 + 0x0000000b 0x00000071
1587 +
1588 + 0x00010000 0x00000025
1589 + 0x00010001 0x0000002c
1590 + 0x00010002 0x00000035
1591 + 0x00010003 0x0000003d
1592 + 0x00010004 0x00000045
1593 + 0x00010005 0x0000004e
1594 + 0x00010006 0x00000057
1595 + 0x00010007 0x00000061
1596 + 0x00010008 0x0000006b
1597 + 0x00010009 0x00000076
1598 +
1599 + 0x00020000 0x00000029
1600 + 0x00020001 0x00000033
1601 + 0x00020002 0x0000003d
1602 + 0x00020003 0x00000049
1603 + 0x00020004 0x00000056
1604 + 0x00020005 0x00000061
1605 + 0x00020006 0x0000006d
1606 +
1607 + 0x00030000 0x00000021
1608 + 0x00030001 0x0000002a
1609 + 0x00030002 0x0000003c
1610 + 0x00030003 0x0000004e>;
1611 + big-endian;
1612 + #thermal-sensor-cells = <1>;
1613 + };
1614 +
1615 + thermal-zones {
1616 + cpu_thermal: cpu-thermal {
1617 + polling-delay-passive = <1000>;
1618 + polling-delay = <5000>;
1619 + thermal-sensors = <&tmu 0>;
1620 +
1621 + trips {
1622 + cpu_alert: cpu-alert {
1623 + temperature = <85000>;
1624 + hysteresis = <2000>;
1625 + type = "passive";
1626 + };
1627 +
1628 + cpu_crit: cpu-crit {
1629 + temperature = <95000>;
1630 + hysteresis = <2000>;
1631 + type = "critical";
1632 + };
1633 + };
1634 +
1635 + cooling-maps {
1636 + map0 {
1637 + trip = <&cpu_alert>;
1638 + cooling-device =
1639 + <&cpu0 THERMAL_NO_LIMIT
1640 + THERMAL_NO_LIMIT>;
1641 + };
1642 + };
1643 + };
1644 + };
1645 +
1646 + esdhc0: esdhc@1560000 {
1647 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1648 + reg = <0x0 0x1560000 0x0 0x10000>;
1649 + interrupts = <0 62 0x4>;
1650 + clocks = <&clockgen 4 0>;
1651 + voltage-ranges = <1800 1800 3300 3300>;
1652 + sdhci,auto-cmd12;
1653 + big-endian;
1654 + bus-width = <4>;
1655 + status = "disabled";
1656 + };
1657 +
1658 + esdhc1: esdhc@1580000 {
1659 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1660 + reg = <0x0 0x1580000 0x0 0x10000>;
1661 + interrupts = <0 65 0x4>;
1662 + clocks = <&clockgen 4 0>;
1663 + voltage-ranges = <1800 1800 3300 3300>;
1664 + sdhci,auto-cmd12;
1665 + big-endian;
1666 + broken-cd;
1667 + bus-width = <4>;
1668 + status = "disabled";
1669 + };
1670 +
1671 + rcpm: rcpm@1ee2000 {
1672 + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
1673 + reg = <0x0 0x1ee2000 0x0 0x1000>;
1674 + fsl,#rcpm-wakeup-cells = <1>;
1675 + };
1676 +
1677 + ftm0: ftm0@29d0000 {
1678 + compatible = "fsl,ls1012a-ftm";
1679 + reg = <0x0 0x29d0000 0x0 0x10000>,
1680 + <0x0 0x1ee2140 0x0 0x4>;
1681 + reg-names = "ftm", "FlexTimer1";
1682 + interrupts = <0 86 0x4>;
1683 + big-endian;
1684 + };
1685 +
1686 + i2c0: i2c@2180000 {
1687 + compatible = "fsl,vf610-i2c";
1688 + #address-cells = <1>;
1689 + #size-cells = <0>;
1690 + reg = <0x0 0x2180000 0x0 0x10000>;
1691 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
1692 + clocks = <&clockgen 4 0>;
1693 + status = "disabled";
1694 + };
1695 +
1696 + i2c1: i2c@2190000 {
1697 + compatible = "fsl,vf610-i2c";
1698 + #address-cells = <1>;
1699 + #size-cells = <0>;
1700 + reg = <0x0 0x2190000 0x0 0x10000>;
1701 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
1702 + clocks = <&clockgen 4 0>;
1703 + status = "disabled";
1704 + };
1705 +
1706 + duart0: serial@21c0500 {
1707 + compatible = "fsl,ns16550", "ns16550a";
1708 + reg = <0x00 0x21c0500 0x0 0x100>;
1709 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1710 + clocks = <&clockgen 4 0>;
1711 + status = "disabled";
1712 + };
1713 +
1714 + duart1: serial@21c0600 {
1715 + compatible = "fsl,ns16550", "ns16550a";
1716 + reg = <0x00 0x21c0600 0x0 0x100>;
1717 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1718 + clocks = <&clockgen 4 0>;
1719 + status = "disabled";
1720 + };
1721 +
1722 + gpio0: gpio@2300000 {
1723 + compatible = "fsl,qoriq-gpio";
1724 + reg = <0x0 0x2300000 0x0 0x10000>;
1725 + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
1726 + gpio-controller;
1727 + #gpio-cells = <2>;
1728 + interrupt-controller;
1729 + #interrupt-cells = <2>;
1730 + };
1731 +
1732 + gpio1: gpio@2310000 {
1733 + compatible = "fsl,qoriq-gpio";
1734 + reg = <0x0 0x2310000 0x0 0x10000>;
1735 + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
1736 + gpio-controller;
1737 + #gpio-cells = <2>;
1738 + interrupt-controller;
1739 + #interrupt-cells = <2>;
1740 + };
1741 +
1742 + qspi: quadspi@1550000 {
1743 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
1744 + #address-cells = <1>;
1745 + #size-cells = <0>;
1746 + reg = <0x0 0x1550000 0x0 0x10000>,
1747 + <0x0 0x40000000 0x0 0x10000000>;
1748 + reg-names = "QuadSPI", "QuadSPI-memory";
1749 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1750 + clock-names = "qspi_en", "qspi";
1751 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
1752 + big-endian;
1753 + fsl,qspi-has-second-chip;
1754 + status = "disabled";
1755 + };
1756 +
1757 + wdog0: wdog@2ad0000 {
1758 + compatible = "fsl,ls1012a-wdt",
1759 + "fsl,imx21-wdt";
1760 + reg = <0x0 0x2ad0000 0x0 0x10000>;
1761 + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
1762 + clocks = <&clockgen 4 0>;
1763 + big-endian;
1764 + };
1765 +
1766 + sai1: sai@2b50000 {
1767 + #sound-dai-cells = <0>;
1768 + compatible = "fsl,vf610-sai";
1769 + reg = <0x0 0x2b50000 0x0 0x10000>;
1770 + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
1771 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1772 + <&clockgen 4 3>, <&clockgen 4 3>;
1773 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1774 + dma-names = "tx", "rx";
1775 + dmas = <&edma0 1 47>,
1776 + <&edma0 1 46>;
1777 + status = "disabled";
1778 + };
1779 +
1780 + sai2: sai@2b60000 {
1781 + #sound-dai-cells = <0>;
1782 + compatible = "fsl,vf610-sai";
1783 + reg = <0x0 0x2b60000 0x0 0x10000>;
1784 + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
1785 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1786 + <&clockgen 4 3>, <&clockgen 4 3>;
1787 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1788 + dma-names = "tx", "rx";
1789 + dmas = <&edma0 1 45>,
1790 + <&edma0 1 44>;
1791 + status = "disabled";
1792 + };
1793 +
1794 + edma0: edma@2c00000 {
1795 + #dma-cells = <2>;
1796 + compatible = "fsl,vf610-edma";
1797 + reg = <0x0 0x2c00000 0x0 0x10000>,
1798 + <0x0 0x2c10000 0x0 0x10000>,
1799 + <0x0 0x2c20000 0x0 0x10000>;
1800 + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
1801 + <0 103 IRQ_TYPE_LEVEL_HIGH>;
1802 + interrupt-names = "edma-tx", "edma-err";
1803 + dma-channels = <32>;
1804 + big-endian;
1805 + clock-names = "dmamux0", "dmamux1";
1806 + clocks = <&clockgen 4 3>,
1807 + <&clockgen 4 3>;
1808 + };
1809 +
1810 + usb0: usb3@2f00000 {
1811 + compatible = "snps,dwc3";
1812 + reg = <0x0 0x2f00000 0x0 0x10000>;
1813 + interrupts = <0 60 0x4>;
1814 + dr_mode = "host";
1815 + snps,quirk-frame-length-adjustment = <0x20>;
1816 + snps,dis_rxdet_inp3_quirk;
1817 + };
1818 +
1819 + usb1: usb2@8600000 {
1820 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
1821 + reg = <0x0 0x8600000 0x0 0x1000>;
1822 + interrupts = <0 139 0x4>;
1823 + dr_mode = "host";
1824 + phy_type = "ulpi";
1825 + };
1826 +
1827 + sata: sata@3200000 {
1828 + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
1829 + reg = <0x0 0x3200000 0x0 0x10000>,
1830 + <0x0 0x20140520 0x0 0x4>;
1831 + reg-names = "ahci", "sata-ecc";
1832 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
1833 + clocks = <&clockgen 4 0>;
1834 + dma-coherent;
1835 + status = "disabled";
1836 + };
1837 +
1838 + msi: msi-controller1@1572000 {
1839 + compatible = "fsl,ls1012a-msi";
1840 + reg = <0x0 0x1572000 0x0 0x8>;
1841 + msi-controller;
1842 + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
1843 + };
1844 +
1845 + pcie@3400000 {
1846 + compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
1847 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
1848 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
1849 + reg-names = "regs", "config";
1850 + interrupts = <0 118 0x4>, /* AER interrupt */
1851 + <0 117 0x4>; /* PME interrupt */
1852 + interrupt-names = "aer", "pme";
1853 + #address-cells = <3>;
1854 + #size-cells = <2>;
1855 + device_type = "pci";
1856 + num-lanes = <4>;
1857 + bus-range = <0x0 0xff>;
1858 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
1859 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1860 + msi-parent = <&msi>;
1861 + #interrupt-cells = <1>;
1862 + interrupt-map-mask = <0 0 0 7>;
1863 + interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
1864 + <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
1865 + <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
1866 + <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1867 + };
1868 + };
1869 +
1870 + reserved-memory {
1871 + #address-cells = <2>;
1872 + #size-cells = <2>;
1873 + ranges;
1874 +
1875 + pfe_reserved: packetbuffer@83400000 {
1876 + reg = <0 0x83400000 0 0xc00000>;
1877 + };
1878 + };
1879 +
1880 + pfe: pfe@04000000 {
1881 + compatible = "fsl,pfe";
1882 + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
1883 + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
1884 + reg-names = "pfe", "pfe-ddr";
1885 + fsl,pfe-num-interfaces = <0x2>;
1886 + interrupts = <0 172 0x4>, /* HIF interrupt */
1887 + <0 173 0x4>, /*HIF_NOCPY interrupt */
1888 + <0 174 0x4>; /* WoL interrupt */
1889 + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
1890 + memory-region = <&pfe_reserved>;
1891 + fsl,pfe-scfg = <&scfg 0>;
1892 + fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
1893 + clocks = <&clockgen 4 0>;
1894 + clock-names = "pfe";
1895 +
1896 + status = "okay";
1897 + pfe_mac0: ethernet@0 {
1898 + };
1899 +
1900 + pfe_mac1: ethernet@1 {
1901 + };
1902 + };
1903 +};
1904 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
1905 new file mode 100644
1906 index 00000000..169e1714
1907 --- /dev/null
1908 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
1909 @@ -0,0 +1,45 @@
1910 +/*
1911 + * QorIQ FMan v3 device tree nodes for ls1043
1912 + *
1913 + * Copyright 2015-2016 Freescale Semiconductor Inc.
1914 + *
1915 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
1916 + */
1917 +
1918 +&soc {
1919 +
1920 +/* include used FMan blocks */
1921 +#include "qoriq-fman3-0.dtsi"
1922 +#include "qoriq-fman3-0-1g-0.dtsi"
1923 +#include "qoriq-fman3-0-1g-1.dtsi"
1924 +#include "qoriq-fman3-0-1g-2.dtsi"
1925 +#include "qoriq-fman3-0-1g-3.dtsi"
1926 +#include "qoriq-fman3-0-1g-4.dtsi"
1927 +#include "qoriq-fman3-0-1g-5.dtsi"
1928 +#include "qoriq-fman3-0-10g-0.dtsi"
1929 +
1930 +};
1931 +
1932 +&fman0 {
1933 + /* these aliases provide the FMan ports mapping */
1934 + enet0: ethernet@e0000 {
1935 + };
1936 +
1937 + enet1: ethernet@e2000 {
1938 + };
1939 +
1940 + enet2: ethernet@e4000 {
1941 + };
1942 +
1943 + enet3: ethernet@e6000 {
1944 + };
1945 +
1946 + enet4: ethernet@e8000 {
1947 + };
1948 +
1949 + enet5: ethernet@ea000 {
1950 + };
1951 +
1952 + enet6: ethernet@f0000 {
1953 + };
1954 +};
1955 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
1956 new file mode 100644
1957 index 00000000..6c13b416
1958 --- /dev/null
1959 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
1960 @@ -0,0 +1,69 @@
1961 +/*
1962 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1963 + *
1964 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1965 + *
1966 + * Mingkai Hu <Mingkai.hu@freescale.com>
1967 + *
1968 + * This file is dual-licensed: you can use it either under the terms
1969 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1970 + * licensing only applies to this file, and not this project as a
1971 + * whole.
1972 + *
1973 + * a) This library is free software; you can redistribute it and/or
1974 + * modify it under the terms of the GNU General Public License as
1975 + * published by the Free Software Foundation; either version 2 of the
1976 + * License, or (at your option) any later version.
1977 + *
1978 + * This library is distributed in the hope that it will be useful,
1979 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1980 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1981 + * GNU General Public License for more details.
1982 + *
1983 + * Or, alternatively,
1984 + *
1985 + * b) Permission is hereby granted, free of charge, to any person
1986 + * obtaining a copy of this software and associated documentation
1987 + * files (the "Software"), to deal in the Software without
1988 + * restriction, including without limitation the rights to use,
1989 + * copy, modify, merge, publish, distribute, sublicense, and/or
1990 + * sell copies of the Software, and to permit persons to whom the
1991 + * Software is furnished to do so, subject to the following
1992 + * conditions:
1993 + *
1994 + * The above copyright notice and this permission notice shall be
1995 + * included in all copies or substantial portions of the Software.
1996 + *
1997 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1998 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1999 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2000 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2001 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2002 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2003 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2004 + * OTHER DEALINGS IN THE SOFTWARE.
2005 + */
2006 +
2007 +#include "fsl-ls1043a-qds.dts"
2008 +
2009 +&bman_fbpr {
2010 + compatible = "fsl,bman-fbpr";
2011 + alloc-ranges = <0 0 0x10000 0>;
2012 +};
2013 +&qman_fqd {
2014 + compatible = "fsl,qman-fqd";
2015 + alloc-ranges = <0 0 0x10000 0>;
2016 +};
2017 +&qman_pfdr {
2018 + compatible = "fsl,qman-pfdr";
2019 + alloc-ranges = <0 0 0x10000 0>;
2020 +};
2021 +
2022 +&soc {
2023 +#include "qoriq-dpaa-eth.dtsi"
2024 +#include "qoriq-fman3-0-6oh.dtsi"
2025 +};
2026 +
2027 +&fman0 {
2028 + compatible = "fsl,fman", "simple-bus";
2029 +};
2030 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2031 index dd9e9194..08abff73 100644
2032 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2033 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2034 @@ -1,7 +1,7 @@
2035 /*
2036 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2037 *
2038 - * Copyright 2014-2015, Freescale Semiconductor
2039 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2040 *
2041 * Mingkai Hu <Mingkai.hu@freescale.com>
2042 *
2043 @@ -45,7 +45,7 @@
2044 */
2045
2046 /dts-v1/;
2047 -/include/ "fsl-ls1043a.dtsi"
2048 +#include "fsl-ls1043a.dtsi"
2049
2050 / {
2051 model = "LS1043A QDS Board";
2052 @@ -60,6 +60,22 @@
2053 serial1 = &duart1;
2054 serial2 = &duart2;
2055 serial3 = &duart3;
2056 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
2057 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
2058 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
2059 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
2060 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
2061 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
2062 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
2063 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
2064 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
2065 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
2066 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
2067 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
2068 + emi1_slot1 = &ls1043mdio_s1;
2069 + emi1_slot2 = &ls1043mdio_s2;
2070 + emi1_slot3 = &ls1043mdio_s3;
2071 + emi1_slot4 = &ls1043mdio_s4;
2072 };
2073
2074 chosen {
2075 @@ -97,8 +113,11 @@
2076 };
2077
2078 fpga: board-control@2,0 {
2079 - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
2080 + #address-cells = <1>;
2081 + #size-cells = <1>;
2082 + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
2083 reg = <0x2 0x0 0x0000100>;
2084 + ranges = <0 2 0 0x100>;
2085 };
2086 };
2087
2088 @@ -181,3 +200,149 @@
2089 reg = <0>;
2090 };
2091 };
2092 +
2093 +#include "fsl-ls1043-post.dtsi"
2094 +
2095 +&fman0 {
2096 + ethernet@e0000 {
2097 + phy-handle = <&qsgmii_phy_s2_p1>;
2098 + phy-connection-type = "sgmii";
2099 + };
2100 +
2101 + ethernet@e2000 {
2102 + phy-handle = <&qsgmii_phy_s2_p2>;
2103 + phy-connection-type = "sgmii";
2104 + };
2105 +
2106 + ethernet@e4000 {
2107 + phy-handle = <&rgmii_phy1>;
2108 + phy-connection-type = "rgmii";
2109 + };
2110 +
2111 + ethernet@e6000 {
2112 + phy-handle = <&rgmii_phy2>;
2113 + phy-connection-type = "rgmii";
2114 + };
2115 +
2116 + ethernet@e8000 {
2117 + phy-handle = <&qsgmii_phy_s2_p3>;
2118 + phy-connection-type = "sgmii";
2119 + };
2120 +
2121 + ethernet@ea000 {
2122 + phy-handle = <&qsgmii_phy_s2_p4>;
2123 + phy-connection-type = "sgmii";
2124 + };
2125 +
2126 + ethernet@f0000 { /* DTSEC9/10GEC1 */
2127 + fixed-link = <1 1 10000 0 0>;
2128 + phy-connection-type = "xgmii";
2129 + };
2130 +};
2131 +
2132 +&fpga {
2133 + mdio-mux-emi1 {
2134 + compatible = "mdio-mux-mmioreg", "mdio-mux";
2135 + mdio-parent-bus = <&mdio0>;
2136 + #address-cells = <1>;
2137 + #size-cells = <0>;
2138 + reg = <0x54 1>; /* BRDCFG4 */
2139 + mux-mask = <0xe0>; /* EMI1 */
2140 +
2141 + /* On-board RGMII1 PHY */
2142 + ls1043mdio0: mdio@0 {
2143 + reg = <0>;
2144 + #address-cells = <1>;
2145 + #size-cells = <0>;
2146 +
2147 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
2148 + reg = <0x1>;
2149 + };
2150 + };
2151 +
2152 + /* On-board RGMII2 PHY */
2153 + ls1043mdio1: mdio@1 {
2154 + reg = <0x20>;
2155 + #address-cells = <1>;
2156 + #size-cells = <0>;
2157 +
2158 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
2159 + reg = <0x2>;
2160 + };
2161 + };
2162 +
2163 + /* Slot 1 */
2164 + ls1043mdio_s1: mdio@2 {
2165 + reg = <0x40>;
2166 + #address-cells = <1>;
2167 + #size-cells = <0>;
2168 + status = "disabled";
2169 +
2170 + qsgmii_phy_s1_p1: ethernet-phy@4 {
2171 + reg = <0x4>;
2172 + };
2173 + qsgmii_phy_s1_p2: ethernet-phy@5 {
2174 + reg = <0x5>;
2175 + };
2176 + qsgmii_phy_s1_p3: ethernet-phy@6 {
2177 + reg = <0x6>;
2178 + };
2179 + qsgmii_phy_s1_p4: ethernet-phy@7 {
2180 + reg = <0x7>;
2181 + };
2182 +
2183 + sgmii_phy_s1_p1: ethernet-phy@1c {
2184 + reg = <0x1c>;
2185 + };
2186 + };
2187 +
2188 + /* Slot 2 */
2189 + ls1043mdio_s2: mdio@3 {
2190 + reg = <0x60>;
2191 + #address-cells = <1>;
2192 + #size-cells = <0>;
2193 + status = "disabled";
2194 +
2195 + qsgmii_phy_s2_p1: ethernet-phy@8 {
2196 + reg = <0x8>;
2197 + };
2198 + qsgmii_phy_s2_p2: ethernet-phy@9 {
2199 + reg = <0x9>;
2200 + };
2201 + qsgmii_phy_s2_p3: ethernet-phy@a {
2202 + reg = <0xa>;
2203 + };
2204 + qsgmii_phy_s2_p4: ethernet-phy@b {
2205 + reg = <0xb>;
2206 + };
2207 +
2208 + sgmii_phy_s2_p1: ethernet-phy@1c {
2209 + reg = <0x1c>;
2210 + };
2211 + };
2212 +
2213 + /* Slot 3 */
2214 + ls1043mdio_s3: mdio@4 {
2215 + reg = <0x80>;
2216 + #address-cells = <1>;
2217 + #size-cells = <0>;
2218 + status = "disabled";
2219 +
2220 + sgmii_phy_s3_p1: ethernet-phy@1c {
2221 + reg = <0x1c>;
2222 + };
2223 + };
2224 +
2225 + /* Slot 4 */
2226 + ls1043mdio_s4: mdio@5 {
2227 + reg = <0xa0>;
2228 + #address-cells = <1>;
2229 + #size-cells = <0>;
2230 + status = "disabled";
2231 +
2232 + sgmii_phy_s4_p1: ethernet-phy@1c {
2233 + reg = <0x1c>;
2234 + };
2235 + };
2236 + };
2237 +};
2238 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2239 new file mode 100644
2240 index 00000000..ac4b9a41
2241 --- /dev/null
2242 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2243 @@ -0,0 +1,69 @@
2244 +/*
2245 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2246 + *
2247 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2248 + *
2249 + * Mingkai Hu <Mingkai.hu@freescale.com>
2250 + *
2251 + * This file is dual-licensed: you can use it either under the terms
2252 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2253 + * licensing only applies to this file, and not this project as a
2254 + * whole.
2255 + *
2256 + * a) This library is free software; you can redistribute it and/or
2257 + * modify it under the terms of the GNU General Public License as
2258 + * published by the Free Software Foundation; either version 2 of the
2259 + * License, or (at your option) any later version.
2260 + *
2261 + * This library is distributed in the hope that it will be useful,
2262 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2263 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2264 + * GNU General Public License for more details.
2265 + *
2266 + * Or, alternatively,
2267 + *
2268 + * b) Permission is hereby granted, free of charge, to any person
2269 + * obtaining a copy of this software and associated documentation
2270 + * files (the "Software"), to deal in the Software without
2271 + * restriction, including without limitation the rights to use,
2272 + * copy, modify, merge, publish, distribute, sublicense, and/or
2273 + * sell copies of the Software, and to permit persons to whom the
2274 + * Software is furnished to do so, subject to the following
2275 + * conditions:
2276 + *
2277 + * The above copyright notice and this permission notice shall be
2278 + * included in all copies or substantial portions of the Software.
2279 + *
2280 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2281 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2282 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2283 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2284 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2285 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2286 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2287 + * OTHER DEALINGS IN THE SOFTWARE.
2288 + */
2289 +
2290 +#include "fsl-ls1043a-rdb.dts"
2291 +
2292 +&bman_fbpr {
2293 + compatible = "fsl,bman-fbpr";
2294 + alloc-ranges = <0 0 0x10000 0>;
2295 +};
2296 +&qman_fqd {
2297 + compatible = "fsl,qman-fqd";
2298 + alloc-ranges = <0 0 0x10000 0>;
2299 +};
2300 +&qman_pfdr {
2301 + compatible = "fsl,qman-pfdr";
2302 + alloc-ranges = <0 0 0x10000 0>;
2303 +};
2304 +
2305 +&soc {
2306 +#include "qoriq-dpaa-eth.dtsi"
2307 +#include "qoriq-fman3-0-6oh.dtsi"
2308 +};
2309 +
2310 +&fman0 {
2311 + compatible = "fsl,fman", "simple-bus";
2312 +};
2313 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2314 new file mode 100644
2315 index 00000000..4e46a0a5
2316 --- /dev/null
2317 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2318 @@ -0,0 +1,117 @@
2319 +/*
2320 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2321 + *
2322 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2323 + *
2324 + * This file is licensed under the terms of the GNU General Public
2325 + * License version 2. This program is licensed "as is" without any
2326 + * warranty of any kind, whether express or implied.
2327 + */
2328 +
2329 +#include "fsl-ls1043a-rdb-sdk.dts"
2330 +
2331 +&soc {
2332 + bp7: buffer-pool@7 {
2333 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2334 + fsl,bpid = <7>;
2335 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
2336 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
2337 + };
2338 +
2339 + bp8: buffer-pool@8 {
2340 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2341 + fsl,bpid = <8>;
2342 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
2343 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2344 + };
2345 +
2346 + bp9: buffer-pool@9 {
2347 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2348 + fsl,bpid = <9>;
2349 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
2350 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2351 + };
2352 +
2353 + fsl,dpaa {
2354 + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
2355 +
2356 + ethernet@0 {
2357 + compatible = "fsl,dpa-ethernet-init";
2358 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2359 + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
2360 + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
2361 + };
2362 +
2363 + ethernet@1 {
2364 + compatible = "fsl,dpa-ethernet-init";
2365 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2366 + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
2367 + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
2368 + };
2369 +
2370 + ethernet@2 {
2371 + compatible = "fsl,dpa-ethernet-init";
2372 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2373 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
2374 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
2375 + };
2376 +
2377 + ethernet@3 {
2378 + compatible = "fsl,dpa-ethernet-init";
2379 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2380 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
2381 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
2382 + };
2383 +
2384 + ethernet@4 {
2385 + compatible = "fsl,dpa-ethernet-init";
2386 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2387 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
2388 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
2389 + };
2390 +
2391 + ethernet@5 {
2392 + compatible = "fsl,dpa-ethernet-init";
2393 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2394 + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
2395 + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
2396 + };
2397 +
2398 + ethernet@8 {
2399 + compatible = "fsl,dpa-ethernet-init";
2400 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2401 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
2402 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
2403 +
2404 + };
2405 + dpa-fman0-oh@2 {
2406 + compatible = "fsl,dpa-oh";
2407 + /* Define frame queues for the OH port*/
2408 + /* <OH Rx error, OH Rx default> */
2409 + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
2410 + fsl,fman-oh-port = <&fman0_oh2>;
2411 + };
2412 + };
2413 +};
2414 +/ {
2415 + reserved-memory {
2416 + #address-cells = <2>;
2417 + #size-cells = <2>;
2418 + ranges;
2419 +
2420 + usdpaa_mem: usdpaa_mem {
2421 + compatible = "fsl,usdpaa-mem";
2422 + alloc-ranges = <0 0 0x10000 0>;
2423 + size = <0 0x10000000>;
2424 + alignment = <0 0x10000000>;
2425 + };
2426 + };
2427 +};
2428 +
2429 +&fman0 {
2430 + fman0_oh2: port@83000 {
2431 + cell-index = <1>;
2432 + compatible = "fsl,fman-port-oh";
2433 + reg = <0x83000 0x1000>;
2434 + };
2435 +};
2436 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2437 index d2313e05..f92ae325 100644
2438 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2439 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2440 @@ -1,7 +1,7 @@
2441 /*
2442 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2443 *
2444 - * Copyright 2014-2015, Freescale Semiconductor
2445 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2446 *
2447 * Mingkai Hu <Mingkai.hu@freescale.com>
2448 *
2449 @@ -45,7 +45,7 @@
2450 */
2451
2452 /dts-v1/;
2453 -/include/ "fsl-ls1043a.dtsi"
2454 +#include "fsl-ls1043a.dtsi"
2455
2456 / {
2457 model = "LS1043A RDB Board";
2458 @@ -86,6 +86,10 @@
2459 compatible = "pericom,pt7c4338";
2460 reg = <0x68>;
2461 };
2462 + rtc@51 {
2463 + compatible = "nxp,pcf85263";
2464 + reg = <0x51>;
2465 + };
2466 };
2467
2468 &ifc {
2469 @@ -130,6 +134,38 @@
2470 reg = <0>;
2471 spi-max-frequency = <1000000>; /* input clock */
2472 };
2473 +
2474 + slic@2 {
2475 + compatible = "maxim,ds26522";
2476 + reg = <2>;
2477 + spi-max-frequency = <2000000>;
2478 + fsl,spi-cs-sck-delay = <100>;
2479 + fsl,spi-sck-cs-delay = <50>;
2480 + };
2481 +
2482 + slic@3 {
2483 + compatible = "maxim,ds26522";
2484 + reg = <3>;
2485 + spi-max-frequency = <2000000>;
2486 + fsl,spi-cs-sck-delay = <100>;
2487 + fsl,spi-sck-cs-delay = <50>;
2488 + };
2489 +};
2490 +
2491 +&uqe {
2492 + ucc_hdlc: ucc@2000 {
2493 + compatible = "fsl,ucc-hdlc";
2494 + rx-clock-name = "clk8";
2495 + tx-clock-name = "clk9";
2496 + fsl,rx-sync-clock = "rsync_pin";
2497 + fsl,tx-sync-clock = "tsync_pin";
2498 + fsl,tx-timeslot-mask = <0xfffffffe>;
2499 + fsl,rx-timeslot-mask = <0xfffffffe>;
2500 + fsl,tdm-framer-type = "e1";
2501 + fsl,tdm-id = <0>;
2502 + fsl,siram-entry-id = <0>;
2503 + fsl,tdm-interface;
2504 + };
2505 };
2506
2507 &duart0 {
2508 @@ -139,3 +175,76 @@
2509 &duart1 {
2510 status = "okay";
2511 };
2512 +
2513 +#include "fsl-ls1043-post.dtsi"
2514 +
2515 +&fman0 {
2516 + ethernet@e0000 {
2517 + phy-handle = <&qsgmii_phy1>;
2518 + phy-connection-type = "qsgmii";
2519 + };
2520 +
2521 + ethernet@e2000 {
2522 + phy-handle = <&qsgmii_phy2>;
2523 + phy-connection-type = "qsgmii";
2524 + };
2525 +
2526 + ethernet@e4000 {
2527 + phy-handle = <&rgmii_phy1>;
2528 + phy-connection-type = "rgmii-txid";
2529 + };
2530 +
2531 + ethernet@e6000 {
2532 + phy-handle = <&rgmii_phy2>;
2533 + phy-connection-type = "rgmii-txid";
2534 + };
2535 +
2536 + ethernet@e8000 {
2537 + phy-handle = <&qsgmii_phy3>;
2538 + phy-connection-type = "qsgmii";
2539 + };
2540 +
2541 + ethernet@ea000 {
2542 + phy-handle = <&qsgmii_phy4>;
2543 + phy-connection-type = "qsgmii";
2544 + };
2545 +
2546 + ethernet@f0000 { /* 10GEC1 */
2547 + phy-handle = <&aqr105_phy>;
2548 + phy-connection-type = "xgmii";
2549 + };
2550 +
2551 + mdio@fc000 {
2552 + rgmii_phy1: ethernet-phy@1 {
2553 + reg = <0x1>;
2554 + };
2555 +
2556 + rgmii_phy2: ethernet-phy@2 {
2557 + reg = <0x2>;
2558 + };
2559 +
2560 + qsgmii_phy1: ethernet-phy@4 {
2561 + reg = <0x4>;
2562 + };
2563 +
2564 + qsgmii_phy2: ethernet-phy@5 {
2565 + reg = <0x5>;
2566 + };
2567 +
2568 + qsgmii_phy3: ethernet-phy@6 {
2569 + reg = <0x6>;
2570 + };
2571 +
2572 + qsgmii_phy4: ethernet-phy@7 {
2573 + reg = <0x7>;
2574 + };
2575 + };
2576 +
2577 + mdio@fd000 {
2578 + aqr105_phy: ethernet-phy@1 {
2579 + compatible = "ethernet-phy-ieee802.3-c45";
2580 + interrupts = <0 132 4>;
2581 + reg = <0x1>;
2582 + };
2583 + };
2584 +};
2585 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2586 index 97d331ec..ef7c0a24 100644
2587 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2588 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2589 @@ -1,7 +1,7 @@
2590 /*
2591 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2592 *
2593 - * Copyright 2014-2015, Freescale Semiconductor
2594 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2595 *
2596 * Mingkai Hu <Mingkai.hu@freescale.com>
2597 *
2598 @@ -44,12 +44,25 @@
2599 * OTHER DEALINGS IN THE SOFTWARE.
2600 */
2601
2602 +#include <dt-bindings/thermal/thermal.h>
2603 +
2604 / {
2605 compatible = "fsl,ls1043a";
2606 interrupt-parent = <&gic>;
2607 #address-cells = <2>;
2608 #size-cells = <2>;
2609
2610 + aliases {
2611 + fman0 = &fman0;
2612 + ethernet0 = &enet0;
2613 + ethernet1 = &enet1;
2614 + ethernet2 = &enet2;
2615 + ethernet3 = &enet3;
2616 + ethernet4 = &enet4;
2617 + ethernet5 = &enet5;
2618 + ethernet6 = &enet6;
2619 + };
2620 +
2621 cpus {
2622 #address-cells = <1>;
2623 #size-cells = <0>;
2624 @@ -66,6 +79,8 @@
2625 reg = <0x0>;
2626 clocks = <&clockgen 1 0>;
2627 next-level-cache = <&l2>;
2628 + #cooling-cells = <2>;
2629 + cpu-idle-states = <&CPU_PH20>;
2630 };
2631
2632 cpu1: cpu@1 {
2633 @@ -74,6 +89,7 @@
2634 reg = <0x1>;
2635 clocks = <&clockgen 1 0>;
2636 next-level-cache = <&l2>;
2637 + cpu-idle-states = <&CPU_PH20>;
2638 };
2639
2640 cpu2: cpu@2 {
2641 @@ -82,6 +98,7 @@
2642 reg = <0x2>;
2643 clocks = <&clockgen 1 0>;
2644 next-level-cache = <&l2>;
2645 + cpu-idle-states = <&CPU_PH20>;
2646 };
2647
2648 cpu3: cpu@3 {
2649 @@ -90,6 +107,7 @@
2650 reg = <0x3>;
2651 clocks = <&clockgen 1 0>;
2652 next-level-cache = <&l2>;
2653 + cpu-idle-states = <&CPU_PH20>;
2654 };
2655
2656 l2: l2-cache {
2657 @@ -97,12 +115,56 @@
2658 };
2659 };
2660
2661 + idle-states {
2662 + /*
2663 + * PSCI node is not added default, U-boot will add missing
2664 + * parts if it determines to use PSCI.
2665 + */
2666 + entry-method = "arm,psci";
2667 +
2668 + CPU_PH20: cpu-ph20 {
2669 + compatible = "arm,idle-state";
2670 + idle-state-name = "PH20";
2671 + arm,psci-suspend-param = <0x0>;
2672 + entry-latency-us = <1000>;
2673 + exit-latency-us = <1000>;
2674 + min-residency-us = <3000>;
2675 + };
2676 + };
2677 +
2678 memory@80000000 {
2679 device_type = "memory";
2680 reg = <0x0 0x80000000 0 0x80000000>;
2681 /* DRAM space 1, size: 2GiB DRAM */
2682 };
2683
2684 + reserved-memory {
2685 + #address-cells = <2>;
2686 + #size-cells = <2>;
2687 + ranges;
2688 +
2689 + bman_fbpr: bman-fbpr {
2690 + compatible = "shared-dma-pool";
2691 + size = <0 0x1000000>;
2692 + alignment = <0 0x1000000>;
2693 + no-map;
2694 + };
2695 +
2696 + qman_fqd: qman-fqd {
2697 + compatible = "shared-dma-pool";
2698 + size = <0 0x400000>;
2699 + alignment = <0 0x400000>;
2700 + no-map;
2701 + };
2702 +
2703 + qman_pfdr: qman-pfdr {
2704 + compatible = "shared-dma-pool";
2705 + size = <0 0x2000000>;
2706 + alignment = <0 0x2000000>;
2707 + no-map;
2708 + };
2709 + };
2710 +
2711 sysclk: sysclk {
2712 compatible = "fixed-clock";
2713 #clock-cells = <0>;
2714 @@ -149,7 +211,7 @@
2715 interrupts = <1 9 0xf08>;
2716 };
2717
2718 - soc {
2719 + soc: soc {
2720 compatible = "simple-bus";
2721 #address-cells = <2>;
2722 #size-cells = <2>;
2723 @@ -213,13 +275,14 @@
2724
2725 dcfg: dcfg@1ee0000 {
2726 compatible = "fsl,ls1043a-dcfg", "syscon";
2727 - reg = <0x0 0x1ee0000 0x0 0x10000>;
2728 + reg = <0x0 0x1ee0000 0x0 0x1000>;
2729 big-endian;
2730 };
2731
2732 ifc: ifc@1530000 {
2733 compatible = "fsl,ifc", "simple-bus";
2734 reg = <0x0 0x1530000 0x0 0x10000>;
2735 + big-endian;
2736 interrupts = <0 43 0x4>;
2737 };
2738
2739 @@ -255,6 +318,103 @@
2740 big-endian;
2741 };
2742
2743 + tmu: tmu@1f00000 {
2744 + compatible = "fsl,qoriq-tmu";
2745 + reg = <0x0 0x1f00000 0x0 0x10000>;
2746 + interrupts = <0 33 0x4>;
2747 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
2748 + fsl,tmu-calibration = <0x00000000 0x00000026
2749 + 0x00000001 0x0000002d
2750 + 0x00000002 0x00000032
2751 + 0x00000003 0x00000039
2752 + 0x00000004 0x0000003f
2753 + 0x00000005 0x00000046
2754 + 0x00000006 0x0000004d
2755 + 0x00000007 0x00000054
2756 + 0x00000008 0x0000005a
2757 + 0x00000009 0x00000061
2758 + 0x0000000a 0x0000006a
2759 + 0x0000000b 0x00000071
2760 +
2761 + 0x00010000 0x00000025
2762 + 0x00010001 0x0000002c
2763 + 0x00010002 0x00000035
2764 + 0x00010003 0x0000003d
2765 + 0x00010004 0x00000045
2766 + 0x00010005 0x0000004e
2767 + 0x00010006 0x00000057
2768 + 0x00010007 0x00000061
2769 + 0x00010008 0x0000006b
2770 + 0x00010009 0x00000076
2771 +
2772 + 0x00020000 0x00000029
2773 + 0x00020001 0x00000033
2774 + 0x00020002 0x0000003d
2775 + 0x00020003 0x00000049
2776 + 0x00020004 0x00000056
2777 + 0x00020005 0x00000061
2778 + 0x00020006 0x0000006d
2779 +
2780 + 0x00030000 0x00000021
2781 + 0x00030001 0x0000002a
2782 + 0x00030002 0x0000003c
2783 + 0x00030003 0x0000004e>;
2784 + #thermal-sensor-cells = <1>;
2785 + };
2786 +
2787 + thermal-zones {
2788 + cpu_thermal: cpu-thermal {
2789 + polling-delay-passive = <1000>;
2790 + polling-delay = <5000>;
2791 +
2792 + thermal-sensors = <&tmu 3>;
2793 +
2794 + trips {
2795 + cpu_alert: cpu-alert {
2796 + temperature = <85000>;
2797 + hysteresis = <2000>;
2798 + type = "passive";
2799 + };
2800 + cpu_crit: cpu-crit {
2801 + temperature = <95000>;
2802 + hysteresis = <2000>;
2803 + type = "critical";
2804 + };
2805 + };
2806 +
2807 + cooling-maps {
2808 + map0 {
2809 + trip = <&cpu_alert>;
2810 + cooling-device =
2811 + <&cpu0 THERMAL_NO_LIMIT
2812 + THERMAL_NO_LIMIT>;
2813 + };
2814 + };
2815 + };
2816 + };
2817 +
2818 + qman: qman@1880000 {
2819 + compatible = "fsl,qman";
2820 + reg = <0x00 0x1880000 0x0 0x10000>;
2821 + interrupts = <0 45 0x4>;
2822 + memory-region = <&qman_fqd &qman_pfdr>;
2823 + };
2824 +
2825 + bman: bman@1890000 {
2826 + compatible = "fsl,bman";
2827 + reg = <0x00 0x1890000 0x0 0x10000>;
2828 + interrupts = <0 45 0x4>;
2829 + memory-region = <&bman_fbpr>;
2830 + };
2831 +
2832 + bportals: bman-portals@508000000 {
2833 + ranges = <0x0 0x5 0x08000000 0x8000000>;
2834 + };
2835 +
2836 + qportals: qman-portals@500000000 {
2837 + ranges = <0x0 0x5 0x00000000 0x8000000>;
2838 + };
2839 +
2840 dspi0: dspi@2100000 {
2841 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
2842 #address-cells = <1>;
2843 @@ -396,6 +556,72 @@
2844 #interrupt-cells = <2>;
2845 };
2846
2847 + uqe: uqe@2400000 {
2848 + #address-cells = <1>;
2849 + #size-cells = <1>;
2850 + device_type = "qe";
2851 + compatible = "fsl,qe", "simple-bus";
2852 + ranges = <0x0 0x0 0x2400000 0x40000>;
2853 + reg = <0x0 0x2400000 0x0 0x480>;
2854 + brg-frequency = <100000000>;
2855 + bus-frequency = <200000000>;
2856 +
2857 + fsl,qe-num-riscs = <1>;
2858 + fsl,qe-num-snums = <28>;
2859 +
2860 + qeic: qeic@80 {
2861 + compatible = "fsl,qe-ic";
2862 + reg = <0x80 0x80>;
2863 + #address-cells = <0>;
2864 + interrupt-controller;
2865 + #interrupt-cells = <1>;
2866 + interrupts = <0 77 0x04 0 77 0x04>;
2867 + };
2868 +
2869 + si1: si@700 {
2870 + #address-cells = <1>;
2871 + #size-cells = <0>;
2872 + compatible = "fsl,ls1043-qe-si",
2873 + "fsl,t1040-qe-si";
2874 + reg = <0x700 0x80>;
2875 + };
2876 +
2877 + siram1: siram@1000 {
2878 + #address-cells = <1>;
2879 + #size-cells = <1>;
2880 + compatible = "fsl,ls1043-qe-siram",
2881 + "fsl,t1040-qe-siram";
2882 + reg = <0x1000 0x800>;
2883 + };
2884 +
2885 + ucc@2000 {
2886 + cell-index = <1>;
2887 + reg = <0x2000 0x200>;
2888 + interrupts = <32>;
2889 + interrupt-parent = <&qeic>;
2890 + };
2891 +
2892 + ucc@2200 {
2893 + cell-index = <3>;
2894 + reg = <0x2200 0x200>;
2895 + interrupts = <34>;
2896 + interrupt-parent = <&qeic>;
2897 + };
2898 +
2899 + muram@10000 {
2900 + #address-cells = <1>;
2901 + #size-cells = <1>;
2902 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
2903 + ranges = <0x0 0x10000 0x6000>;
2904 +
2905 + data-only@0 {
2906 + compatible = "fsl,qe-muram-data",
2907 + "fsl,cpm-muram-data";
2908 + reg = <0x0 0x6000>;
2909 + };
2910 + };
2911 + };
2912 +
2913 lpuart0: serial@2950000 {
2914 compatible = "fsl,ls1021a-lpuart";
2915 reg = <0x0 0x2950000 0x0 0x1000>;
2916 @@ -450,6 +676,16 @@
2917 status = "disabled";
2918 };
2919
2920 + ftm0: ftm0@29d0000 {
2921 + compatible = "fsl,ls1043a-ftm";
2922 + reg = <0x0 0x29d0000 0x0 0x10000>,
2923 + <0x0 0x1ee2140 0x0 0x4>;
2924 + reg-names = "ftm", "FlexTimer1";
2925 + interrupts = <0 86 0x4>;
2926 + big-endian;
2927 + status = "okay";
2928 + };
2929 +
2930 wdog0: wdog@2ad0000 {
2931 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
2932 reg = <0x0 0x2ad0000 0x0 0x10000>;
2933 @@ -482,6 +718,8 @@
2934 dr_mode = "host";
2935 snps,quirk-frame-length-adjustment = <0x20>;
2936 snps,dis_rxdet_inp3_quirk;
2937 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2938 + snps,dma-snooping;
2939 };
2940
2941 usb1: usb3@3000000 {
2942 @@ -491,6 +729,9 @@
2943 dr_mode = "host";
2944 snps,quirk-frame-length-adjustment = <0x20>;
2945 snps,dis_rxdet_inp3_quirk;
2946 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2947 + snps,dma-snooping;
2948 + configure-gfladj;
2949 };
2950
2951 usb2: usb3@3100000 {
2952 @@ -500,32 +741,52 @@
2953 dr_mode = "host";
2954 snps,quirk-frame-length-adjustment = <0x20>;
2955 snps,dis_rxdet_inp3_quirk;
2956 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2957 + snps,dma-snooping;
2958 + configure-gfladj;
2959 };
2960
2961 sata: sata@3200000 {
2962 compatible = "fsl,ls1043a-ahci";
2963 - reg = <0x0 0x3200000 0x0 0x10000>;
2964 + reg = <0x0 0x3200000 0x0 0x10000>,
2965 + <0x0 0x20140520 0x0 0x4>;
2966 + reg-names = "ahci", "sata-ecc";
2967 interrupts = <0 69 0x4>;
2968 clocks = <&clockgen 4 0>;
2969 dma-coherent;
2970 };
2971
2972 + qdma: qdma@8380000 {
2973 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
2974 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
2975 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
2976 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
2977 + interrupts = <0 152 0x4>,
2978 + <0 39 0x4>;
2979 + interrupt-names = "qdma-error", "qdma-queue";
2980 + channels = <8>;
2981 + queues = <2>;
2982 + status-sizes = <64>;
2983 + queue-sizes = <64 64>;
2984 + big-endian;
2985 + };
2986 +
2987 msi1: msi-controller1@1571000 {
2988 - compatible = "fsl,1s1043a-msi";
2989 + compatible = "fsl,ls1043a-msi";
2990 reg = <0x0 0x1571000 0x0 0x8>;
2991 msi-controller;
2992 interrupts = <0 116 0x4>;
2993 };
2994
2995 msi2: msi-controller2@1572000 {
2996 - compatible = "fsl,1s1043a-msi";
2997 + compatible = "fsl,ls1043a-msi";
2998 reg = <0x0 0x1572000 0x0 0x8>;
2999 msi-controller;
3000 interrupts = <0 126 0x4>;
3001 };
3002
3003 msi3: msi-controller3@1573000 {
3004 - compatible = "fsl,1s1043a-msi";
3005 + compatible = "fsl,ls1043a-msi";
3006 reg = <0x0 0x1573000 0x0 0x8>;
3007 msi-controller;
3008 interrupts = <0 160 0x4>;
3009 @@ -536,9 +797,9 @@
3010 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
3011 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
3012 reg-names = "regs", "config";
3013 - interrupts = <0 118 0x4>, /* controller interrupt */
3014 - <0 117 0x4>; /* PME interrupt */
3015 - interrupt-names = "intr", "pme";
3016 + interrupts = <0 117 0x4>, /* PME interrupt */
3017 + <0 118 0x4>; /* aer interrupt */
3018 + interrupt-names = "pme", "aer";
3019 #address-cells = <3>;
3020 #size-cells = <2>;
3021 device_type = "pci";
3022 @@ -547,7 +808,7 @@
3023 bus-range = <0x0 0xff>;
3024 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
3025 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3026 - msi-parent = <&msi1>;
3027 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3028 #interrupt-cells = <1>;
3029 interrupt-map-mask = <0 0 0 7>;
3030 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
3031 @@ -561,9 +822,9 @@
3032 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
3033 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
3034 reg-names = "regs", "config";
3035 - interrupts = <0 128 0x4>,
3036 - <0 127 0x4>;
3037 - interrupt-names = "intr", "pme";
3038 + interrupts = <0 127 0x4>,
3039 + <0 128 0x4>;
3040 + interrupt-names = "pme", "aer";
3041 #address-cells = <3>;
3042 #size-cells = <2>;
3043 device_type = "pci";
3044 @@ -572,7 +833,7 @@
3045 bus-range = <0x0 0xff>;
3046 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
3047 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3048 - msi-parent = <&msi2>;
3049 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3050 #interrupt-cells = <1>;
3051 interrupt-map-mask = <0 0 0 7>;
3052 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
3053 @@ -586,9 +847,9 @@
3054 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
3055 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
3056 reg-names = "regs", "config";
3057 - interrupts = <0 162 0x4>,
3058 - <0 161 0x4>;
3059 - interrupt-names = "intr", "pme";
3060 + interrupts = <0 161 0x4>,
3061 + <0 162 0x4>;
3062 + interrupt-names = "pme", "aer";
3063 #address-cells = <3>;
3064 #size-cells = <2>;
3065 device_type = "pci";
3066 @@ -597,7 +858,7 @@
3067 bus-range = <0x0 0xff>;
3068 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
3069 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3070 - msi-parent = <&msi3>;
3071 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3072 #interrupt-cells = <1>;
3073 interrupt-map-mask = <0 0 0 7>;
3074 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
3075 @@ -608,3 +869,6 @@
3076 };
3077
3078 };
3079 +
3080 +#include "qoriq-qman1-portals.dtsi"
3081 +#include "qoriq-bman1-portals.dtsi"
3082 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
3083 new file mode 100644
3084 index 00000000..f5017dba
3085 --- /dev/null
3086 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
3087 @@ -0,0 +1,48 @@
3088 +/*
3089 + * QorIQ FMan v3 device tree nodes for ls1046
3090 + *
3091 + * Copyright 2015-2016 Freescale Semiconductor Inc.
3092 + *
3093 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3094 + */
3095 +
3096 +&soc {
3097 +
3098 +/* include used FMan blocks */
3099 +#include "qoriq-fman3-0.dtsi"
3100 +#include "qoriq-fman3-0-1g-0.dtsi"
3101 +#include "qoriq-fman3-0-1g-1.dtsi"
3102 +#include "qoriq-fman3-0-1g-2.dtsi"
3103 +#include "qoriq-fman3-0-1g-3.dtsi"
3104 +#include "qoriq-fman3-0-1g-4.dtsi"
3105 +#include "qoriq-fman3-0-1g-5.dtsi"
3106 +#include "qoriq-fman3-0-10g-0.dtsi"
3107 +#include "qoriq-fman3-0-10g-1.dtsi"
3108 +};
3109 +
3110 +&fman0 {
3111 + /* these aliases provide the FMan ports mapping */
3112 + enet0: ethernet@e0000 {
3113 + };
3114 +
3115 + enet1: ethernet@e2000 {
3116 + };
3117 +
3118 + enet2: ethernet@e4000 {
3119 + };
3120 +
3121 + enet3: ethernet@e6000 {
3122 + };
3123 +
3124 + enet4: ethernet@e8000 {
3125 + };
3126 +
3127 + enet5: ethernet@ea000 {
3128 + };
3129 +
3130 + enet6: ethernet@f0000 {
3131 + };
3132 +
3133 + enet7: ethernet@f2000 {
3134 + };
3135 +};
3136 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
3137 new file mode 100644
3138 index 00000000..c375af47
3139 --- /dev/null
3140 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
3141 @@ -0,0 +1,109 @@
3142 +/*
3143 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3144 + *
3145 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3146 + *
3147 + * Mingkai Hu <Mingkai.hu@freescale.com>
3148 + *
3149 + * This file is dual-licensed: you can use it either under the terms
3150 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3151 + * licensing only applies to this file, and not this project as a
3152 + * whole.
3153 + *
3154 + * a) This library is free software; you can redistribute it and/or
3155 + * modify it under the terms of the GNU General Public License as
3156 + * published by the Free Software Foundation; either version 2 of the
3157 + * License, or (at your option) any later version.
3158 + *
3159 + * This library is distributed in the hope that it will be useful,
3160 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3161 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3162 + * GNU General Public License for more details.
3163 + *
3164 + * Or, alternatively,
3165 + *
3166 + * b) Permission is hereby granted, free of charge, to any person
3167 + * obtaining a copy of this software and associated documentation
3168 + * files (the "Software"), to deal in the Software without
3169 + * restriction, including without limitation the rights to use,
3170 + * copy, modify, merge, publish, distribute, sublicense, and/or
3171 + * sell copies of the Software, and to permit persons to whom the
3172 + * Software is furnished to do so, subject to the following
3173 + * conditions:
3174 + *
3175 + * The above copyright notice and this permission notice shall be
3176 + * included in all copies or substantial portions of the Software.
3177 + *
3178 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3179 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3180 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3181 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3182 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3183 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3184 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3185 + * OTHER DEALINGS IN THE SOFTWARE.
3186 + */
3187 +
3188 +#include "fsl-ls1046a-qds.dts"
3189 +
3190 +&bman_fbpr {
3191 + compatible = "fsl,bman-fbpr";
3192 + alloc-ranges = <0 0 0x10000 0>;
3193 +};
3194 +&qman_fqd {
3195 + compatible = "fsl,qman-fqd";
3196 + alloc-ranges = <0 0 0x10000 0>;
3197 +};
3198 +&qman_pfdr {
3199 + compatible = "fsl,qman-pfdr";
3200 + alloc-ranges = <0 0 0x10000 0>;
3201 +};
3202 +
3203 +&soc {
3204 +#include "qoriq-dpaa-eth.dtsi"
3205 +#include "qoriq-fman3-0-6oh.dtsi"
3206 +};
3207 +
3208 +&fsldpaa {
3209 + ethernet@9 {
3210 + compatible = "fsl,dpa-ethernet";
3211 + fsl,fman-mac = <&enet7>;
3212 + };
3213 +};
3214 +
3215 +&fman0 {
3216 + compatible = "fsl,fman", "simple-bus";
3217 +};
3218 +
3219 +&dspi {
3220 + bus-num = <0>;
3221 + status = "okay";
3222 +
3223 + flash@0 {
3224 + #address-cells = <1>;
3225 + #size-cells = <1>;
3226 + compatible = "n25q128a11", "jedec,spi-nor";
3227 + reg = <0>;
3228 + spi-max-frequency = <10000000>;
3229 + };
3230 +
3231 + flash@1 {
3232 + #address-cells = <1>;
3233 + #size-cells = <1>;
3234 + compatible = "sst25wf040b", "jedec,spi-nor";
3235 + spi-cpol;
3236 + spi-cpha;
3237 + reg = <1>;
3238 + spi-max-frequency = <10000000>;
3239 + };
3240 +
3241 + flash@2 {
3242 + #address-cells = <1>;
3243 + #size-cells = <1>;
3244 + compatible = "en25s64", "jedec,spi-nor";
3245 + spi-cpol;
3246 + spi-cpha;
3247 + reg = <2>;
3248 + spi-max-frequency = <10000000>;
3249 + };
3250 +};
3251 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3252 new file mode 100644
3253 index 00000000..3b8e9b7e
3254 --- /dev/null
3255 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3256 @@ -0,0 +1,363 @@
3257 +/*
3258 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3259 + *
3260 + * Copyright 2016 Freescale Semiconductor, Inc.
3261 + *
3262 + * Shaohui Xie <Shaohui.Xie@nxp.com>
3263 + *
3264 + * This file is dual-licensed: you can use it either under the terms
3265 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3266 + * licensing only applies to this file, and not this project as a
3267 + * whole.
3268 + *
3269 + * a) This library is free software; you can redistribute it and/or
3270 + * modify it under the terms of the GNU General Public License as
3271 + * published by the Free Software Foundation; either version 2 of the
3272 + * License, or (at your option) any later version.
3273 + *
3274 + * This library is distributed in the hope that it will be useful,
3275 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3276 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3277 + * GNU General Public License for more details.
3278 + *
3279 + * Or, alternatively,
3280 + *
3281 + * b) Permission is hereby granted, free of charge, to any person
3282 + * obtaining a copy of this software and associated documentation
3283 + * files (the "Software"), to deal in the Software without
3284 + * restriction, including without limitation the rights to use,
3285 + * copy, modify, merge, publish, distribute, sublicense, and/or
3286 + * sell copies of the Software, and to permit persons to whom the
3287 + * Software is furnished to do so, subject to the following
3288 + * conditions:
3289 + *
3290 + * The above copyright notice and this permission notice shall be
3291 + * included in all copies or substantial portions of the Software.
3292 + *
3293 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3294 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3295 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3296 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3297 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3298 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3299 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3300 + * OTHER DEALINGS IN THE SOFTWARE.
3301 + */
3302 +
3303 +/dts-v1/;
3304 +
3305 +#include "fsl-ls1046a.dtsi"
3306 +
3307 +/ {
3308 + model = "LS1046A QDS Board";
3309 + compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
3310 +
3311 + aliases {
3312 + gpio0 = &gpio0;
3313 + gpio1 = &gpio1;
3314 + gpio2 = &gpio2;
3315 + gpio3 = &gpio3;
3316 + serial0 = &duart0;
3317 + serial1 = &duart1;
3318 + serial2 = &duart2;
3319 + serial3 = &duart3;
3320 +
3321 + emi1_slot1 = &ls1046mdio_s1;
3322 + emi1_slot2 = &ls1046mdio_s2;
3323 + emi1_slot4 = &ls1046mdio_s4;
3324 +
3325 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
3326 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
3327 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
3328 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
3329 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
3330 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
3331 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
3332 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
3333 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
3334 + };
3335 +
3336 + chosen {
3337 + stdout-path = "serial0:115200n8";
3338 + };
3339 +};
3340 +
3341 +&dspi {
3342 + bus-num = <0>;
3343 + status = "okay";
3344 +
3345 + flash@0 {
3346 + #address-cells = <1>;
3347 + #size-cells = <1>;
3348 + compatible = "n25q128a11", "jedec,spi-nor";
3349 + reg = <0>;
3350 + spi-max-frequency = <10000000>;
3351 + };
3352 +
3353 + flash@1 {
3354 + #address-cells = <1>;
3355 + #size-cells = <1>;
3356 + compatible = "sst25wf040b", "jedec,spi-nor";
3357 + spi-cpol;
3358 + spi-cpha;
3359 + reg = <1>;
3360 + spi-max-frequency = <10000000>;
3361 + };
3362 +
3363 + flash@2 {
3364 + #address-cells = <1>;
3365 + #size-cells = <1>;
3366 + compatible = "en25s64", "jedec,spi-nor";
3367 + spi-cpol;
3368 + spi-cpha;
3369 + reg = <2>;
3370 + spi-max-frequency = <10000000>;
3371 + };
3372 +};
3373 +
3374 +&duart0 {
3375 + status = "okay";
3376 +};
3377 +
3378 +&duart1 {
3379 + status = "okay";
3380 +};
3381 +
3382 +&i2c0 {
3383 + status = "okay";
3384 +
3385 + pca9547@77 {
3386 + compatible = "nxp,pca9547";
3387 + reg = <0x77>;
3388 + #address-cells = <1>;
3389 + #size-cells = <0>;
3390 +
3391 + i2c@2 {
3392 + #address-cells = <1>;
3393 + #size-cells = <0>;
3394 + reg = <0x2>;
3395 +
3396 + ina220@40 {
3397 + compatible = "ti,ina220";
3398 + reg = <0x40>;
3399 + shunt-resistor = <1000>;
3400 + };
3401 +
3402 + ina220@41 {
3403 + compatible = "ti,ina220";
3404 + reg = <0x41>;
3405 + shunt-resistor = <1000>;
3406 + };
3407 + };
3408 +
3409 + i2c@3 {
3410 + #address-cells = <1>;
3411 + #size-cells = <0>;
3412 + reg = <0x3>;
3413 +
3414 + rtc@51 {
3415 + compatible = "nxp,pcf2129";
3416 + reg = <0x51>;
3417 + /* IRQ10_B */
3418 + interrupts = <0 150 0x4>;
3419 + };
3420 +
3421 + eeprom@56 {
3422 + compatible = "atmel,24c512";
3423 + reg = <0x56>;
3424 + };
3425 +
3426 + eeprom@57 {
3427 + compatible = "atmel,24c512";
3428 + reg = <0x57>;
3429 + };
3430 +
3431 + temp-sensor@4c {
3432 + compatible = "adi,adt7461a";
3433 + reg = <0x4c>;
3434 + };
3435 + };
3436 + };
3437 +};
3438 +
3439 +&ifc {
3440 + #address-cells = <2>;
3441 + #size-cells = <1>;
3442 + /* NOR, NAND Flashes and FPGA on board */
3443 + ranges = <0x0 0x0 0x0 0x60000000 0x08000000
3444 + 0x1 0x0 0x0 0x7e800000 0x00010000
3445 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3446 + status = "okay";
3447 +
3448 + nor@0,0 {
3449 + compatible = "cfi-flash";
3450 + reg = <0x0 0x0 0x8000000>;
3451 + bank-width = <2>;
3452 + device-width = <1>;
3453 + };
3454 +
3455 + nand@1,0 {
3456 + compatible = "fsl,ifc-nand";
3457 + reg = <0x1 0x0 0x10000>;
3458 + };
3459 +
3460 + fpga: board-control@2,0 {
3461 + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
3462 + reg = <0x2 0x0 0x0000100>;
3463 + ranges = <0 2 0 0x100>;
3464 + };
3465 +};
3466 +
3467 +&lpuart0 {
3468 + status = "okay";
3469 +};
3470 +
3471 +&qspi {
3472 + num-cs = <2>;
3473 + bus-num = <0>;
3474 + status = "okay";
3475 +
3476 + qflash0: s25fl128s@0 {
3477 + compatible = "spansion,m25p80";
3478 + #address-cells = <1>;
3479 + #size-cells = <1>;
3480 + spi-max-frequency = <20000000>;
3481 + reg = <0>;
3482 + };
3483 +};
3484 +
3485 +#include "fsl-ls1046-post.dtsi"
3486 +
3487 +&fman0 {
3488 + ethernet@e0000 {
3489 + phy-handle = <&qsgmii_phy_s2_p1>;
3490 + phy-connection-type = "sgmii";
3491 + };
3492 +
3493 + ethernet@e2000 {
3494 + phy-handle = <&sgmii_phy_s4_p1>;
3495 + phy-connection-type = "sgmii";
3496 + };
3497 +
3498 + ethernet@e4000 {
3499 + phy-handle = <&rgmii_phy1>;
3500 + phy-connection-type = "rgmii";
3501 + };
3502 +
3503 + ethernet@e6000 {
3504 + phy-handle = <&rgmii_phy2>;
3505 + phy-connection-type = "rgmii";
3506 + };
3507 +
3508 + ethernet@e8000 {
3509 + phy-handle = <&sgmii_phy_s1_p3>;
3510 + phy-connection-type = "sgmii";
3511 + };
3512 +
3513 + ethernet@ea000 {
3514 + phy-handle = <&sgmii_phy_s1_p4>;
3515 + phy-connection-type = "sgmii";
3516 + };
3517 +
3518 + ethernet@f0000 { /* DTSEC9/10GEC1 */
3519 + phy-handle = <&sgmii_phy_s1_p1>;
3520 + phy-connection-type = "xgmii";
3521 + };
3522 +
3523 + ethernet@f2000 { /* DTSEC10/10GEC2 */
3524 + phy-handle = <&sgmii_phy_s1_p2>;
3525 + phy-connection-type = "xgmii";
3526 + };
3527 +};
3528 +
3529 +&fpga {
3530 + #address-cells = <1>;
3531 + #size-cells = <1>;
3532 + mdio-mux-emi1 {
3533 + compatible = "mdio-mux-mmioreg", "mdio-mux";
3534 + mdio-parent-bus = <&mdio0>;
3535 + #address-cells = <1>;
3536 + #size-cells = <0>;
3537 + reg = <0x54 1>; /* BRDCFG4 */
3538 + mux-mask = <0xe0>; /* EMI1 */
3539 +
3540 + /* On-board RGMII1 PHY */
3541 + ls1046mdio0: mdio@0 {
3542 + reg = <0>;
3543 + #address-cells = <1>;
3544 + #size-cells = <0>;
3545 +
3546 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
3547 + reg = <0x1>;
3548 + };
3549 + };
3550 +
3551 + /* On-board RGMII2 PHY */
3552 + ls1046mdio1: mdio@1 {
3553 + reg = <0x20>;
3554 + #address-cells = <1>;
3555 + #size-cells = <0>;
3556 +
3557 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
3558 + reg = <0x2>;
3559 + };
3560 + };
3561 +
3562 + /* Slot 1 */
3563 + ls1046mdio_s1: mdio@2 {
3564 + reg = <0x40>;
3565 + #address-cells = <1>;
3566 + #size-cells = <0>;
3567 + status = "disabled";
3568 +
3569 + sgmii_phy_s1_p1: ethernet-phy@1c {
3570 + reg = <0x1c>;
3571 + };
3572 +
3573 + sgmii_phy_s1_p2: ethernet-phy@1d {
3574 + reg = <0x1d>;
3575 + };
3576 +
3577 + sgmii_phy_s1_p3: ethernet-phy@1e {
3578 + reg = <0x1e>;
3579 + };
3580 +
3581 + sgmii_phy_s1_p4: ethernet-phy@1f {
3582 + reg = <0x1f>;
3583 + };
3584 + };
3585 +
3586 + /* Slot 2 */
3587 + ls1046mdio_s2: mdio@3 {
3588 + reg = <0x60>;
3589 + #address-cells = <1>;
3590 + #size-cells = <0>;
3591 + status = "disabled";
3592 +
3593 + qsgmii_phy_s2_p1: ethernet-phy@8 {
3594 + reg = <0x8>;
3595 + };
3596 + qsgmii_phy_s2_p2: ethernet-phy@9 {
3597 + reg = <0x9>;
3598 + };
3599 + qsgmii_phy_s2_p3: ethernet-phy@a {
3600 + reg = <0xa>;
3601 + };
3602 + qsgmii_phy_s2_p4: ethernet-phy@b {
3603 + reg = <0xb>;
3604 + };
3605 + };
3606 +
3607 + /* Slot 4 */
3608 + ls1046mdio_s4: mdio@5 {
3609 + reg = <0x80>;
3610 + #address-cells = <1>;
3611 + #size-cells = <0>;
3612 + status = "disabled";
3613 +
3614 + sgmii_phy_s4_p1: ethernet-phy@1c {
3615 + reg = <0x1c>;
3616 + };
3617 + };
3618 + };
3619 +};
3620 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3621 new file mode 100644
3622 index 00000000..bfe2f36c
3623 --- /dev/null
3624 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3625 @@ -0,0 +1,76 @@
3626 +/*
3627 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3628 + *
3629 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3630 + *
3631 + * Mingkai Hu <Mingkai.hu@freescale.com>
3632 + *
3633 + * This file is dual-licensed: you can use it either under the terms
3634 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3635 + * licensing only applies to this file, and not this project as a
3636 + * whole.
3637 + *
3638 + * a) This library is free software; you can redistribute it and/or
3639 + * modify it under the terms of the GNU General Public License as
3640 + * published by the Free Software Foundation; either version 2 of the
3641 + * License, or (at your option) any later version.
3642 + *
3643 + * This library is distributed in the hope that it will be useful,
3644 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3645 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3646 + * GNU General Public License for more details.
3647 + *
3648 + * Or, alternatively,
3649 + *
3650 + * b) Permission is hereby granted, free of charge, to any person
3651 + * obtaining a copy of this software and associated documentation
3652 + * files (the "Software"), to deal in the Software without
3653 + * restriction, including without limitation the rights to use,
3654 + * copy, modify, merge, publish, distribute, sublicense, and/or
3655 + * sell copies of the Software, and to permit persons to whom the
3656 + * Software is furnished to do so, subject to the following
3657 + * conditions:
3658 + *
3659 + * The above copyright notice and this permission notice shall be
3660 + * included in all copies or substantial portions of the Software.
3661 + *
3662 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3663 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3664 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3665 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3666 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3667 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3668 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3669 + * OTHER DEALINGS IN THE SOFTWARE.
3670 + */
3671 +
3672 +#include "fsl-ls1046a-rdb.dts"
3673 +
3674 +&bman_fbpr {
3675 + compatible = "fsl,bman-fbpr";
3676 + alloc-ranges = <0 0 0x10000 0>;
3677 +};
3678 +&qman_fqd {
3679 + compatible = "fsl,qman-fqd";
3680 + alloc-ranges = <0 0 0x10000 0>;
3681 +};
3682 +&qman_pfdr {
3683 + compatible = "fsl,qman-pfdr";
3684 + alloc-ranges = <0 0 0x10000 0>;
3685 +};
3686 +
3687 +&soc {
3688 +#include "qoriq-dpaa-eth.dtsi"
3689 +#include "qoriq-fman3-0-6oh.dtsi"
3690 +};
3691 +
3692 +&fsldpaa {
3693 + ethernet@9 {
3694 + compatible = "fsl,dpa-ethernet";
3695 + fsl,fman-mac = <&enet7>;
3696 + };
3697 +};
3698 +
3699 +&fman0 {
3700 + compatible = "fsl,fman", "simple-bus";
3701 +};
3702 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3703 new file mode 100644
3704 index 00000000..54336aa6
3705 --- /dev/null
3706 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3707 @@ -0,0 +1,110 @@
3708 +/*
3709 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3710 + *
3711 + * Copyright 2016 Freescale Semiconductor, Inc.
3712 + *
3713 + * This file is licensed under the terms of the GNU General Public
3714 + * License version 2. This program is licensed "as is" without any
3715 + * warranty of any kind, whether express or implied.
3716 + */
3717 +
3718 +#include "fsl-ls1046a-rdb-sdk.dts"
3719 +
3720 +&soc {
3721 + bp7: buffer-pool@7 {
3722 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3723 + fsl,bpid = <7>;
3724 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
3725 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
3726 + };
3727 +
3728 + bp8: buffer-pool@8 {
3729 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3730 + fsl,bpid = <8>;
3731 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
3732 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3733 + };
3734 +
3735 + bp9: buffer-pool@9 {
3736 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3737 + fsl,bpid = <9>;
3738 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
3739 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3740 + };
3741 +
3742 + fsl,dpaa {
3743 + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
3744 +
3745 + ethernet@2 {
3746 + compatible = "fsl,dpa-ethernet-init";
3747 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3748 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
3749 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
3750 + };
3751 +
3752 + ethernet@3 {
3753 + compatible = "fsl,dpa-ethernet-init";
3754 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3755 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
3756 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
3757 + };
3758 +
3759 + ethernet@4 {
3760 + compatible = "fsl,dpa-ethernet-init";
3761 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3762 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
3763 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
3764 + };
3765 +
3766 + ethernet@5 {
3767 + compatible = "fsl,dpa-ethernet-init";
3768 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3769 + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
3770 + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
3771 + };
3772 +
3773 + ethernet@8 {
3774 + compatible = "fsl,dpa-ethernet-init";
3775 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3776 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
3777 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
3778 + };
3779 +
3780 + ethernet@9 {
3781 + compatible = "fsl,dpa-ethernet-init";
3782 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3783 + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
3784 + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
3785 + };
3786 +
3787 + dpa-fman0-oh@2 {
3788 + compatible = "fsl,dpa-oh";
3789 + /* Define frame queues for the OH port*/
3790 + /* <OH Rx error, OH Rx default> */
3791 + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
3792 + fsl,fman-oh-port = <&fman0_oh2>;
3793 + };
3794 + };
3795 +};
3796 +/ {
3797 + reserved-memory {
3798 + #address-cells = <2>;
3799 + #size-cells = <2>;
3800 + ranges;
3801 +
3802 + usdpaa_mem: usdpaa_mem {
3803 + compatible = "fsl,usdpaa-mem";
3804 + alloc-ranges = <0 0 0x10000 0>;
3805 + size = <0 0x10000000>;
3806 + alignment = <0 0x10000000>;
3807 + };
3808 + };
3809 +};
3810 +
3811 +&fman0 {
3812 + fman0_oh2: port@83000 {
3813 + cell-index = <1>;
3814 + compatible = "fsl,fman-port-oh";
3815 + reg = <0x83000 0x1000>;
3816 + };
3817 +};
3818 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3819 new file mode 100644
3820 index 00000000..be9b62ca
3821 --- /dev/null
3822 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3823 @@ -0,0 +1,218 @@
3824 +/*
3825 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3826 + *
3827 + * Copyright 2016 Freescale Semiconductor, Inc.
3828 + *
3829 + * Mingkai Hu <mingkai.hu@nxp.com>
3830 + *
3831 + * This file is dual-licensed: you can use it either under the terms
3832 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3833 + * licensing only applies to this file, and not this project as a
3834 + * whole.
3835 + *
3836 + * a) This library is free software; you can redistribute it and/or
3837 + * modify it under the terms of the GNU General Public License as
3838 + * published by the Free Software Foundation; either version 2 of the
3839 + * License, or (at your option) any later version.
3840 + *
3841 + * This library is distributed in the hope that it will be useful,
3842 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3843 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3844 + * GNU General Public License for more details.
3845 + *
3846 + * Or, alternatively,
3847 + *
3848 + * b) Permission is hereby granted, free of charge, to any person
3849 + * obtaining a copy of this software and associated documentation
3850 + * files (the "Software"), to deal in the Software without
3851 + * restriction, including without limitation the rights to use,
3852 + * copy, modify, merge, publish, distribute, sublicense, and/or
3853 + * sell copies of the Software, and to permit persons to whom the
3854 + * Software is furnished to do so, subject to the following
3855 + * conditions:
3856 + *
3857 + * The above copyright notice and this permission notice shall be
3858 + * included in all copies or substantial portions of the Software.
3859 + *
3860 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3861 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3862 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3863 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3864 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3865 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3866 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3867 + * OTHER DEALINGS IN THE SOFTWARE.
3868 + */
3869 +
3870 +/dts-v1/;
3871 +
3872 +#include "fsl-ls1046a.dtsi"
3873 +
3874 +/ {
3875 + model = "LS1046A RDB Board";
3876 + compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
3877 +
3878 + aliases {
3879 + serial0 = &duart0;
3880 + serial1 = &duart1;
3881 + serial2 = &duart2;
3882 + serial3 = &duart3;
3883 + };
3884 +
3885 + chosen {
3886 + stdout-path = "serial0:115200n8";
3887 + };
3888 +};
3889 +
3890 +&esdhc {
3891 + mmc-hs200-1_8v;
3892 + sd-uhs-sdr104;
3893 + sd-uhs-sdr50;
3894 + sd-uhs-sdr25;
3895 + sd-uhs-sdr12;
3896 +};
3897 +
3898 +&duart0 {
3899 + status = "okay";
3900 +};
3901 +
3902 +&duart1 {
3903 + status = "okay";
3904 +};
3905 +
3906 +&i2c0 {
3907 + status = "okay";
3908 +
3909 + ina220@40 {
3910 + compatible = "ti,ina220";
3911 + reg = <0x40>;
3912 + shunt-resistor = <1000>;
3913 + };
3914 +
3915 + temp-sensor@4c {
3916 + compatible = "adi,adt7461";
3917 + reg = <0x4c>;
3918 + };
3919 +
3920 + eeprom@56 {
3921 + compatible = "atmel,24c512";
3922 + reg = <0x52>;
3923 + };
3924 +
3925 + eeprom@57 {
3926 + compatible = "atmel,24c512";
3927 + reg = <0x53>;
3928 + };
3929 +};
3930 +
3931 +&i2c3 {
3932 + status = "okay";
3933 +
3934 + rtc@51 {
3935 + compatible = "nxp,pcf2129";
3936 + reg = <0x51>;
3937 + };
3938 +};
3939 +
3940 +&ifc {
3941 + #address-cells = <2>;
3942 + #size-cells = <1>;
3943 + /* NAND Flashe and CPLD on board */
3944 + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
3945 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3946 + status = "okay";
3947 +
3948 + nand@0,0 {
3949 + compatible = "fsl,ifc-nand";
3950 + #address-cells = <1>;
3951 + #size-cells = <1>;
3952 + reg = <0x0 0x0 0x10000>;
3953 + };
3954 +
3955 + cpld: board-control@2,0 {
3956 + compatible = "fsl,ls1046ardb-cpld";
3957 + reg = <0x2 0x0 0x0000100>;
3958 + };
3959 +};
3960 +
3961 +&qspi {
3962 + num-cs = <2>;
3963 + bus-num = <0>;
3964 + status = "okay";
3965 +
3966 + qflash0: s25fs512s@0 {
3967 + compatible = "spansion,m25p80";
3968 + #address-cells = <1>;
3969 + #size-cells = <1>;
3970 + spi-max-frequency = <20000000>;
3971 + reg = <0>;
3972 + };
3973 +
3974 + qflash1: s25fs512s@1 {
3975 + compatible = "spansion,m25p80";
3976 + #address-cells = <1>;
3977 + #size-cells = <1>;
3978 + spi-max-frequency = <20000000>;
3979 + reg = <1>;
3980 + };
3981 +};
3982 +
3983 +#include "fsl-ls1046-post.dtsi"
3984 +
3985 +&fman0 {
3986 + ethernet@e4000 {
3987 + phy-handle = <&rgmii_phy1>;
3988 + phy-connection-type = "rgmii";
3989 + };
3990 +
3991 + ethernet@e6000 {
3992 + phy-handle = <&rgmii_phy2>;
3993 + phy-connection-type = "rgmii";
3994 + };
3995 +
3996 + ethernet@e8000 {
3997 + phy-handle = <&sgmii_phy1>;
3998 + phy-connection-type = "sgmii";
3999 + };
4000 +
4001 + ethernet@ea000 {
4002 + phy-handle = <&sgmii_phy2>;
4003 + phy-connection-type = "sgmii";
4004 + };
4005 +
4006 + ethernet@f0000 { /* 10GEC1 */
4007 + phy-handle = <&aqr106_phy>;
4008 + phy-connection-type = "xgmii";
4009 + };
4010 +
4011 + ethernet@f2000 { /* 10GEC2 */
4012 + fixed-link = <0 1 1000 0 0>;
4013 + phy-connection-type = "xgmii";
4014 + };
4015 +
4016 + mdio@fc000 {
4017 + rgmii_phy1: ethernet-phy@1 {
4018 + reg = <0x1>;
4019 + };
4020 +
4021 + rgmii_phy2: ethernet-phy@2 {
4022 + reg = <0x2>;
4023 + };
4024 +
4025 + sgmii_phy1: ethernet-phy@3 {
4026 + reg = <0x3>;
4027 +