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layerscape: define ls-append function
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 401-mtd-spi-nor-support-layerscape.patch
1 From c03c545e064a81515fe109ddcc4ecb3895528e58 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Fri, 6 Jul 2018 15:32:05 +0800
4 Subject: [PATCH] mtd: spi-nor: support layerscape
5
6 This is an integrated patch for layerscape qspi support.
7
8 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
9 Signed-off-by: Yunhui Cui <B56489@freescale.com>
10 Signed-off-by: mar.krzeminski <mar.krzeminski@gmail.com>
11 Signed-off-by: Alison Wang <b18965@freescale.com>
12 Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
13 Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
14 Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
15 Signed-off-by: Alexander Kurz <akurz@blala.de>
16 Signed-off-by: L. D. Pinney <ldpinney@gmail.com>
17 Signed-off-by: Ash Benz <ash.benz@bk.ru>
18 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
19 ---
20 drivers/mtd/devices/m25p80.c | 3 +-
21 drivers/mtd/mtdchar.c | 2 +-
22 drivers/mtd/spi-nor/fsl-quadspi.c | 327 ++++++++++++++++++++++++------
23 drivers/mtd/spi-nor/spi-nor.c | 141 ++++++++++++-
24 include/linux/mtd/spi-nor.h | 14 +-
25 5 files changed, 416 insertions(+), 71 deletions(-)
26
27 --- a/drivers/mtd/mtdchar.c
28 +++ b/drivers/mtd/mtdchar.c
29 @@ -451,7 +451,7 @@ static int mtdchar_readoob(struct file *
30 * data. For our userspace tools it is important to dump areas
31 * with ECC errors!
32 * For kernel internal usage it also might return -EUCLEAN
33 - * to signal the caller that a bitflip has occured and has
34 + * to signal the caller that a bitflip has occurred and has
35 * been corrected by the ECC algorithm.
36 *
37 * Note: currently the standard NAND function, nand_read_oob_std,
38 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
39 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
40 @@ -41,6 +41,8 @@
41 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
42 /* Controller cannot wake up from wait mode, TKT245618 */
43 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
44 +/* QSPI_AMBA_BASE is internally added by SOC design */
45 +#define QUADSPI_AMBA_BASE_INTERNAL (0x10000)
46
47 /* The registers */
48 #define QUADSPI_MCR 0x00
49 @@ -193,7 +195,7 @@
50 #define QUADSPI_LUT_NUM 64
51
52 /* SEQID -- we can have 16 seqids at most. */
53 -#define SEQID_QUAD_READ 0
54 +#define SEQID_READ 0
55 #define SEQID_WREN 1
56 #define SEQID_WRDI 2
57 #define SEQID_RDSR 3
58 @@ -205,15 +207,22 @@
59 #define SEQID_RDCR 9
60 #define SEQID_EN4B 10
61 #define SEQID_BRWR 11
62 +#define SEQID_RDAR_OR_RD_EVCR 12
63 +#define SEQID_WRAR 13
64 +#define SEQID_WD_EVCR 14
65
66 #define QUADSPI_MIN_IOMAP SZ_4M
67
68 +#define FLASH_VENDOR_SPANSION_FS "s25fs"
69 +#define SPANSION_S25FS_FAMILY (1 << 1)
70 +
71 enum fsl_qspi_devtype {
72 FSL_QUADSPI_VYBRID,
73 FSL_QUADSPI_IMX6SX,
74 FSL_QUADSPI_IMX7D,
75 FSL_QUADSPI_IMX6UL,
76 FSL_QUADSPI_LS1021A,
77 + FSL_QUADSPI_LS2080A,
78 };
79
80 struct fsl_qspi_devtype_data {
81 @@ -224,7 +233,7 @@ struct fsl_qspi_devtype_data {
82 int driver_data;
83 };
84
85 -static struct fsl_qspi_devtype_data vybrid_data = {
86 +static const struct fsl_qspi_devtype_data vybrid_data = {
87 .devtype = FSL_QUADSPI_VYBRID,
88 .rxfifo = 128,
89 .txfifo = 64,
90 @@ -232,7 +241,7 @@ static struct fsl_qspi_devtype_data vybr
91 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
92 };
93
94 -static struct fsl_qspi_devtype_data imx6sx_data = {
95 +static const struct fsl_qspi_devtype_data imx6sx_data = {
96 .devtype = FSL_QUADSPI_IMX6SX,
97 .rxfifo = 128,
98 .txfifo = 512,
99 @@ -241,7 +250,7 @@ static struct fsl_qspi_devtype_data imx6
100 | QUADSPI_QUIRK_TKT245618,
101 };
102
103 -static struct fsl_qspi_devtype_data imx7d_data = {
104 +static const struct fsl_qspi_devtype_data imx7d_data = {
105 .devtype = FSL_QUADSPI_IMX7D,
106 .rxfifo = 512,
107 .txfifo = 512,
108 @@ -250,7 +259,7 @@ static struct fsl_qspi_devtype_data imx7
109 | QUADSPI_QUIRK_4X_INT_CLK,
110 };
111
112 -static struct fsl_qspi_devtype_data imx6ul_data = {
113 +static const struct fsl_qspi_devtype_data imx6ul_data = {
114 .devtype = FSL_QUADSPI_IMX6UL,
115 .rxfifo = 128,
116 .txfifo = 512,
117 @@ -267,6 +276,14 @@ static struct fsl_qspi_devtype_data ls10
118 .driver_data = 0,
119 };
120
121 +static struct fsl_qspi_devtype_data ls2080a_data = {
122 + .devtype = FSL_QUADSPI_LS2080A,
123 + .rxfifo = 128,
124 + .txfifo = 64,
125 + .ahb_buf_size = 1024,
126 + .driver_data = QUADSPI_AMBA_BASE_INTERNAL | QUADSPI_QUIRK_TKT253890,
127 +};
128 +
129 #define FSL_QSPI_MAX_CHIP 4
130 struct fsl_qspi {
131 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
132 @@ -282,6 +299,7 @@ struct fsl_qspi {
133 u32 nor_size;
134 u32 nor_num;
135 u32 clk_rate;
136 + u32 ddr_smp;
137 unsigned int chip_base_addr; /* We may support two chips. */
138 bool has_second_chip;
139 bool big_endian;
140 @@ -309,6 +327,23 @@ static inline int needs_wakeup_wait_mode
141 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
142 }
143
144 +static inline int has_added_amba_base_internal(struct fsl_qspi *q)
145 +{
146 + return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
147 +}
148 +
149 +static u32 fsl_get_nor_vendor(struct spi_nor *nor)
150 +{
151 + u32 vendor_id;
152 +
153 + if (nor->vendor) {
154 + if (memcmp(nor->vendor, FLASH_VENDOR_SPANSION_FS,
155 + sizeof(FLASH_VENDOR_SPANSION_FS) - 1))
156 + vendor_id = SPANSION_S25FS_FAMILY;
157 + }
158 + return vendor_id;
159 +}
160 +
161 /*
162 * R/W functions for big- or little-endian registers:
163 * The qSPI controller's endian is independent of the CPU core's endian.
164 @@ -331,6 +366,31 @@ static u32 qspi_readl(struct fsl_qspi *q
165 return ioread32(addr);
166 }
167
168 +static inline u32 *u8tou32(u32 *dest, const u8 *src, size_t n)
169 +{
170 + size_t i;
171 + *dest = 0;
172 +
173 + n = n > 4 ? 4 : n;
174 + for (i = 0; i < n; i++)
175 + *dest |= *src++ << i * 8;
176 +
177 + return dest;
178 +
179 +}
180 +
181 +static inline u8 *u32tou8(u8 *dest, const u32 *src, size_t n)
182 +{
183 + size_t i;
184 + u8 *xdest = dest;
185 +
186 + n = n > 4 ? 4 : n;
187 + for (i = 0; i < n; i++)
188 + *xdest++ = *src >> i * 8;
189 +
190 + return dest;
191 +}
192 +
193 /*
194 * An IC bug makes us to re-arrange the 32-bit data.
195 * The following chips, such as IMX6SLX, have fixed this bug.
196 @@ -373,8 +433,15 @@ static void fsl_qspi_init_lut(struct fsl
197 void __iomem *base = q->iobase;
198 int rxfifo = q->devtype_data->rxfifo;
199 u32 lut_base;
200 - u8 cmd, addrlen, dummy;
201 int i;
202 + u32 vendor;
203 +
204 + struct spi_nor *nor = &q->nor[0];
205 + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
206 + u8 read_op = nor->read_opcode;
207 + u8 read_dm = nor->read_dummy;
208 +
209 + vendor = fsl_get_nor_vendor(nor);
210
211 fsl_qspi_unlock_lut(q);
212
213 @@ -382,24 +449,50 @@ static void fsl_qspi_init_lut(struct fsl
214 for (i = 0; i < QUADSPI_LUT_NUM; i++)
215 qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
216
217 - /* Quad Read */
218 - lut_base = SEQID_QUAD_READ * 4;
219 + /* Read */
220 + lut_base = SEQID_READ * 4;
221
222 - if (q->nor_size <= SZ_16M) {
223 - cmd = SPINOR_OP_READ_1_1_4;
224 - addrlen = ADDR24BIT;
225 - dummy = 8;
226 - } else {
227 - /* use the 4-byte address */
228 - cmd = SPINOR_OP_READ_1_1_4;
229 - addrlen = ADDR32BIT;
230 - dummy = 8;
231 - }
232 -
233 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
234 + if (nor->flash_read == SPI_NOR_FAST) {
235 + qspi_writel(q, LUT0(CMD, PAD1, read_op) |
236 + LUT1(ADDR, PAD1, addrlen),
237 + base + QUADSPI_LUT(lut_base));
238 + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
239 + LUT1(FSL_READ, PAD1, rxfifo),
240 + base + QUADSPI_LUT(lut_base + 1));
241 + } else if (nor->flash_read == SPI_NOR_QUAD) {
242 + if (q->nor_size == 0x4000000) {
243 + read_op = 0xEC;
244 + qspi_writel(q,
245 + LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD4, addrlen),
246 base + QUADSPI_LUT(lut_base));
247 - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
248 + qspi_writel(q,
249 + LUT0(MODE, PAD4, 0xff) | LUT1(DUMMY, PAD4, read_dm),
250 base + QUADSPI_LUT(lut_base + 1));
251 + qspi_writel(q,
252 + LUT0(FSL_READ, PAD4, rxfifo),
253 + base + QUADSPI_LUT(lut_base + 2));
254 + } else {
255 + qspi_writel(q, LUT0(CMD, PAD1, read_op) |
256 + LUT1(ADDR, PAD1, addrlen),
257 + base + QUADSPI_LUT(lut_base));
258 + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
259 + LUT1(FSL_READ, PAD4, rxfifo),
260 + base + QUADSPI_LUT(lut_base + 1));
261 + }
262 + } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
263 + /* read mode : 1-4-4, such as Spansion s25fl128s. */
264 + qspi_writel(q, LUT0(CMD, PAD1, read_op)
265 + | LUT1(ADDR_DDR, PAD4, addrlen),
266 + base + QUADSPI_LUT(lut_base));
267 +
268 + qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff)
269 + | LUT1(DUMMY, PAD1, read_dm),
270 + base + QUADSPI_LUT(lut_base + 1));
271 +
272 + qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
273 + | LUT1(JMP_ON_CS, PAD1, 0),
274 + base + QUADSPI_LUT(lut_base + 2));
275 + }
276
277 /* Write enable */
278 lut_base = SEQID_WREN * 4;
279 @@ -409,16 +502,8 @@ static void fsl_qspi_init_lut(struct fsl
280 /* Page Program */
281 lut_base = SEQID_PP * 4;
282
283 - if (q->nor_size <= SZ_16M) {
284 - cmd = SPINOR_OP_PP;
285 - addrlen = ADDR24BIT;
286 - } else {
287 - /* use the 4-byte address */
288 - cmd = SPINOR_OP_PP;
289 - addrlen = ADDR32BIT;
290 - }
291 -
292 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
293 + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
294 + LUT1(ADDR, PAD1, addrlen),
295 base + QUADSPI_LUT(lut_base));
296 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
297 base + QUADSPI_LUT(lut_base + 1));
298 @@ -432,10 +517,8 @@ static void fsl_qspi_init_lut(struct fsl
299 /* Erase a sector */
300 lut_base = SEQID_SE * 4;
301
302 - cmd = q->nor[0].erase_opcode;
303 - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
304 -
305 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
306 + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
307 + LUT1(ADDR, PAD1, addrlen),
308 base + QUADSPI_LUT(lut_base));
309
310 /* Erase the whole chip */
311 @@ -476,6 +559,44 @@ static void fsl_qspi_init_lut(struct fsl
312 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
313 base + QUADSPI_LUT(lut_base));
314
315 +
316 + /*
317 + * Flash Micron and Spansion command confilict
318 + * use the same value 0x65. But it indicates different meaning.
319 + */
320 + lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
321 +
322 + if (vendor == SPANSION_S25FS_FAMILY) {
323 + /*
324 + * Read any device register.
325 + * Used for Spansion S25FS-S family flash only.
326 + */
327 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
328 + LUT1(ADDR, PAD1, ADDR24BIT),
329 + base + QUADSPI_LUT(lut_base));
330 + qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
331 + base + QUADSPI_LUT(lut_base + 1));
332 + } else {
333 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
334 + base + QUADSPI_LUT(lut_base));
335 + }
336 +
337 + /*
338 + * Write any device register.
339 + * Used for Spansion S25FS-S family flash only.
340 + */
341 + lut_base = SEQID_WRAR * 4;
342 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
343 + LUT1(ADDR, PAD1, ADDR24BIT),
344 + base + QUADSPI_LUT(lut_base));
345 + qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
346 + base + QUADSPI_LUT(lut_base + 1));
347 +
348 + /* Write EVCR register */
349 + lut_base = SEQID_WD_EVCR * 4;
350 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
351 + base + QUADSPI_LUT(lut_base));
352 +
353 fsl_qspi_lock_lut(q);
354 }
355
356 @@ -483,8 +604,24 @@ static void fsl_qspi_init_lut(struct fsl
357 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
358 {
359 switch (cmd) {
360 + case SPINOR_OP_READ_1_4_4_D:
361 + case SPINOR_OP_READ4_1_4_4_D:
362 + case SPINOR_OP_READ4_1_1_4:
363 case SPINOR_OP_READ_1_1_4:
364 - return SEQID_QUAD_READ;
365 + case SPINOR_OP_READ_FAST:
366 + case SPINOR_OP_READ4_FAST:
367 + return SEQID_READ;
368 + /*
369 + * Spansion & Micron use the same command value 0x65
370 + * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
371 + * Micron: SPINOR_OP_RD_EVCR,
372 + * read enhanced volatile configuration register.
373 + * case SPINOR_OP_RD_EVCR:
374 + */
375 + case SPINOR_OP_SPANSION_RDAR:
376 + return SEQID_RDAR_OR_RD_EVCR;
377 + case SPINOR_OP_SPANSION_WRAR:
378 + return SEQID_WRAR;
379 case SPINOR_OP_WREN:
380 return SEQID_WREN;
381 case SPINOR_OP_WRDI:
382 @@ -496,6 +633,7 @@ static int fsl_qspi_get_seqid(struct fsl
383 case SPINOR_OP_CHIP_ERASE:
384 return SEQID_CHIP_ERASE;
385 case SPINOR_OP_PP:
386 + case SPINOR_OP_PP_4B:
387 return SEQID_PP;
388 case SPINOR_OP_RDID:
389 return SEQID_RDID;
390 @@ -507,6 +645,8 @@ static int fsl_qspi_get_seqid(struct fsl
391 return SEQID_EN4B;
392 case SPINOR_OP_BRWR:
393 return SEQID_BRWR;
394 + case SPINOR_OP_WD_EVCR:
395 + return SEQID_WD_EVCR;
396 default:
397 if (cmd == q->nor[0].erase_opcode)
398 return SEQID_SE;
399 @@ -531,8 +671,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
400 /* save the reg */
401 reg = qspi_readl(q, base + QUADSPI_MCR);
402
403 - qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
404 - base + QUADSPI_SFAR);
405 + if (has_added_amba_base_internal(q))
406 + qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR);
407 + else
408 + qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
409 + base + QUADSPI_SFAR);
410 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
411 base + QUADSPI_RBCT);
412 qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
413 @@ -582,10 +725,10 @@ static void fsl_qspi_read_data(struct fs
414 q->chip_base_addr, tmp);
415
416 if (len >= 4) {
417 - *((u32 *)rxbuf) = tmp;
418 + u32tou8(rxbuf, &tmp, 4);
419 rxbuf += 4;
420 } else {
421 - memcpy(rxbuf, &tmp, len);
422 + u32tou8(rxbuf, &tmp, len);
423 break;
424 }
425
426 @@ -619,11 +762,12 @@ static inline void fsl_qspi_invalid(stru
427 }
428
429 static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
430 - u8 opcode, unsigned int to, u32 *txbuf,
431 + u8 opcode, unsigned int to, u8 *txbuf,
432 unsigned count)
433 {
434 int ret, i, j;
435 u32 tmp;
436 + u8 byts;
437
438 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
439 q->chip_base_addr, to, count);
440 @@ -633,10 +777,13 @@ static ssize_t fsl_qspi_nor_write(struct
441 qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
442
443 /* fill the TX data to the FIFO */
444 + byts = count;
445 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
446 - tmp = fsl_qspi_endian_xchg(q, *txbuf);
447 + u8tou32(&tmp, txbuf, byts);
448 + tmp = fsl_qspi_endian_xchg(q, tmp);
449 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
450 - txbuf++;
451 + txbuf += 4;
452 + byts -= 4;
453 }
454
455 /* fill the TXFIFO upto 16 bytes for i.MX7d */
456 @@ -657,11 +804,43 @@ static void fsl_qspi_set_map_addr(struct
457 {
458 int nor_size = q->nor_size;
459 void __iomem *base = q->iobase;
460 + u32 mem_base;
461 +
462 + if (has_added_amba_base_internal(q))
463 + mem_base = 0x0;
464 + else
465 + mem_base = q->memmap_phy;
466 +
467 + qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
468 + qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
469 + qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
470 + qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD);
471 +}
472 +
473 +/*
474 + * enable controller ddr quad mode to support different
475 + * vender flashes ddr quad mode.
476 + */
477 +static void set_ddr_quad_mode(struct fsl_qspi *q)
478 +{
479 + u32 reg, reg2;
480 +
481 + reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
482 +
483 + /* Firstly, disable the module */
484 + qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
485 +
486 + /* Set the Sampling Register for DDR */
487 + reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR);
488 + reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
489 + reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) &
490 + QUADSPI_SMPR_DDRSMP_MASK);
491 + qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
492 +
493 + /* Enable the module again (enable the DDR too) */
494 + reg |= QUADSPI_MCR_DDR_EN_MASK;
495 + qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
496
497 - qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
498 - qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
499 - qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
500 - qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
501 }
502
503 /*
504 @@ -704,6 +883,11 @@ static void fsl_qspi_init_abh_read(struc
505 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
506 qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
507 q->iobase + QUADSPI_BFGENCR);
508 +
509 + /* enable the DDR quad read */
510 + if (q->nor->flash_read == SPI_NOR_DDR_QUAD)
511 + set_ddr_quad_mode(q);
512 +
513 }
514
515 /* This function was used to prepare and enable QSPI clock */
516 @@ -822,6 +1006,7 @@ static const struct of_device_id fsl_qsp
517 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
518 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
519 { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
520 + { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
521 { /* sentinel */ }
522 };
523 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
524 @@ -835,8 +1020,12 @@ static int fsl_qspi_read_reg(struct spi_
525 {
526 int ret;
527 struct fsl_qspi *q = nor->priv;
528 + u32 to = 0;
529
530 - ret = fsl_qspi_runcmd(q, opcode, 0, len);
531 + if (opcode == SPINOR_OP_SPANSION_RDAR)
532 + u8tou32(&to, nor->cmd_buf, 4);
533 +
534 + ret = fsl_qspi_runcmd(q, opcode, to, len);
535 if (ret)
536 return ret;
537
538 @@ -848,9 +1037,13 @@ static int fsl_qspi_write_reg(struct spi
539 {
540 struct fsl_qspi *q = nor->priv;
541 int ret;
542 + u32 to = 0;
543 +
544 + if (opcode == SPINOR_OP_SPANSION_WRAR)
545 + u8tou32(&to, nor->cmd_buf, 4);
546
547 if (!buf) {
548 - ret = fsl_qspi_runcmd(q, opcode, 0, 1);
549 + ret = fsl_qspi_runcmd(q, opcode, to, 1);
550 if (ret)
551 return ret;
552
553 @@ -859,7 +1052,7 @@ static int fsl_qspi_write_reg(struct spi
554
555 } else if (len > 0) {
556 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
557 - (u32 *)buf, len);
558 + buf, len);
559 if (ret > 0)
560 return 0;
561 } else {
562 @@ -875,7 +1068,7 @@ static ssize_t fsl_qspi_write(struct spi
563 {
564 struct fsl_qspi *q = nor->priv;
565 ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
566 - (u32 *)buf, len);
567 + (u8 *)buf, len);
568
569 /* invalid the data in the AHB buffer. */
570 fsl_qspi_invalid(q);
571 @@ -922,7 +1115,7 @@ static ssize_t fsl_qspi_read(struct spi_
572 len);
573
574 /* Read out the data directly from the AHB buffer.*/
575 - memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
576 + memcpy_toio(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
577 len);
578
579 return len;
580 @@ -980,6 +1173,8 @@ static int fsl_qspi_probe(struct platfor
581 struct spi_nor *nor;
582 struct mtd_info *mtd;
583 int ret, i = 0;
584 + int find_node;
585 + enum read_mode mode = SPI_NOR_QUAD;
586
587 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
588 if (!q)
589 @@ -1027,6 +1222,12 @@ static int fsl_qspi_probe(struct platfor
590 goto clk_failed;
591 }
592
593 + /* find ddrsmp value */
594 + ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point",
595 + &q->ddr_smp);
596 + if (ret)
597 + q->ddr_smp = 0;
598 +
599 /* find the irq */
600 ret = platform_get_irq(pdev, 0);
601 if (ret < 0) {
602 @@ -1050,6 +1251,7 @@ static int fsl_qspi_probe(struct platfor
603
604 mutex_init(&q->lock);
605
606 + find_node = 0;
607 /* iterate the subnodes. */
608 for_each_available_child_of_node(dev->of_node, np) {
609 /* skip the holes */
610 @@ -1076,18 +1278,25 @@ static int fsl_qspi_probe(struct platfor
611 ret = of_property_read_u32(np, "spi-max-frequency",
612 &q->clk_rate);
613 if (ret < 0)
614 - goto mutex_failed;
615 + continue;
616
617 /* set the chip address for READID */
618 fsl_qspi_set_base_addr(q, nor);
619
620 - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
621 + ret = of_property_read_bool(np, "m25p,fast-read");
622 + mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
623 + /* Can we enable the DDR Quad Read? */
624 + ret = of_property_read_bool(np, "ddr-quad-read");
625 if (ret)
626 - goto mutex_failed;
627 + mode = SPI_NOR_DDR_QUAD;
628 +
629 + ret = spi_nor_scan(nor, NULL, mode);
630 + if (ret)
631 + continue;
632
633 ret = mtd_device_register(mtd, NULL, 0);
634 if (ret)
635 - goto mutex_failed;
636 + continue;
637
638 /* Set the correct NOR size now. */
639 if (q->nor_size == 0) {
640 @@ -1110,8 +1319,12 @@ static int fsl_qspi_probe(struct platfor
641 nor->page_size = q->devtype_data->txfifo;
642
643 i++;
644 + find_node++;
645 }
646
647 + if (find_node == 0)
648 + goto mutex_failed;
649 +
650 /* finish the rest init. */
651 ret = fsl_qspi_nor_setup_last(q);
652 if (ret)
653 --- a/drivers/mtd/spi-nor/spi-nor.c
654 +++ b/drivers/mtd/spi-nor/spi-nor.c
655 @@ -40,6 +40,13 @@
656 #define SPI_NOR_MAX_ID_LEN 6
657 #define SPI_NOR_MAX_ADDR_WIDTH 4
658
659 +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
660 +/* Added for S25FS-S family flash */
661 +#define SPINOR_CONFIG_REG3_OFFSET 0x800004
662 +#define CR3V_4KB_ERASE_UNABLE 0x8
663 +#define SPINOR_S25FS_FAMILY_ID 0x81
664 +
665 +
666 struct flash_info {
667 char *name;
668
669 @@ -68,7 +75,8 @@ struct flash_info {
670 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
671 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
672 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
673 -#define USE_FSR BIT(7) /* use flag status register */
674 +#define USE_FSR BIT(13) /* use flag status register */
675 +#define SPI_NOR_DDR_QUAD_READ BIT(7) /* Flash supports DDR Quad Read */
676 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
677 #define SPI_NOR_HAS_TB BIT(9) /*
678 * Flash SR has Top/Bottom (TB) protect
679 @@ -85,9 +93,11 @@ struct flash_info {
680 * Use dedicated 4byte address op codes
681 * to support memory size above 128Mib.
682 */
683 +#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
684 };
685
686 #define JEDEC_MFR(info) ((info)->id[0])
687 +#define EXT_ID(info) ((info)->id[5])
688
689 static const struct flash_info *spi_nor_match_id(const char *name);
690
691 @@ -132,7 +142,7 @@ static int read_fsr(struct spi_nor *nor)
692 /*
693 * Read configuration register, returning its value in the
694 * location. Return the configuration register value.
695 - * Returns negative if error occured.
696 + * Returns negative if error occurred.
697 */
698 static int read_cr(struct spi_nor *nor)
699 {
700 @@ -160,6 +170,8 @@ static inline int spi_nor_read_dummy_cyc
701 case SPI_NOR_DUAL:
702 case SPI_NOR_QUAD:
703 return 8;
704 + case SPI_NOR_DDR_QUAD:
705 + return 6;
706 case SPI_NOR_NORMAL:
707 return 0;
708 }
709 @@ -962,6 +974,8 @@ static const struct flash_info spi_nor_i
710
711 /* ESMT */
712 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
713 + { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
714 + { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
715
716 /* Everspin */
717 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
718 @@ -1015,12 +1029,15 @@ static const struct flash_info spi_nor_i
719 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
720 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
721 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
722 + { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
723 + { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
724 + { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
725 { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64, 0) },
726 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
727 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
728 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
729 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
730 - { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
731 + { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
732 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
733 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
734 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
735 @@ -1034,10 +1051,11 @@ static const struct flash_info spi_nor_i
736 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
737 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
738 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
739 + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
740 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
741 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
742 - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
743 - { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
744 + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
745 + { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
746
747 /* PMC */
748 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
749 @@ -1055,8 +1073,11 @@ static const struct flash_info spi_nor_i
750 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
751 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
752 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
753 - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
754 + { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
755 + { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ
756 + | SPI_NOR_DDR_QUAD_READ) },
757 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
758 + { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)},
759 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
760 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
761 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
762 @@ -1130,7 +1151,15 @@ static const struct flash_info spi_nor_i
763 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
764 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
765 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
766 + {
767 + "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
768 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
769 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
770 + },
771 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
772 + { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
773 + { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
774 + { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
775 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
776 {
777 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
778 @@ -1197,6 +1226,53 @@ static const struct flash_info *spi_nor_
779 id[0], id[1], id[2]);
780 return ERR_PTR(-ENODEV);
781 }
782 +/*
783 + * The S25FS-S family physical sectors may be configured as a
784 + * hybrid combination of eight 4-kB parameter sectors
785 + * at the top or bottom of the address space with all
786 + * but one of the remaining sectors being uniform size.
787 + * The Parameter Sector Erase commands (20h or 21h) must
788 + * be used to erase the 4-kB parameter sectors individually.
789 + * The Sector (uniform sector) Erase commands (D8h or DCh)
790 + * must be used to erase any of the remaining
791 + * sectors, including the portion of highest or lowest address
792 + * sector that is not overlaid by the parameter sectors.
793 + * The uniform sector erase command has no effect on parameter sectors.
794 + */
795 +static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor)
796 +{
797 + struct fsl_qspi *q;
798 + u32 cr3v_addr = SPINOR_CONFIG_REG3_OFFSET;
799 + u8 cr3v = 0x0;
800 + int ret = 0x0;
801 +
802 + q = nor->priv;
803 +
804 + nor->cmd_buf[2] = cr3v_addr >> 16;
805 + nor->cmd_buf[1] = cr3v_addr >> 8;
806 + nor->cmd_buf[0] = cr3v_addr >> 0;
807 +
808 + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
809 + if (ret)
810 + return ret;
811 + if (cr3v & CR3V_4KB_ERASE_UNABLE)
812 + return 0;
813 + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
814 + if (ret)
815 + return ret;
816 + cr3v = CR3V_4KB_ERASE_UNABLE;
817 + nor->program_opcode = SPINOR_OP_SPANSION_WRAR;
818 + nor->write(nor, cr3v_addr, 1, &cr3v);
819 +
820 + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
821 + if (ret)
822 + return ret;
823 + if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
824 + return -EPERM;
825 +
826 + return 0;
827 +}
828 +
829
830 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
831 size_t *retlen, u_char *buf)
832 @@ -1416,7 +1492,7 @@ static int macronix_quad_enable(struct s
833 * Write status Register and configuration register with 2 bytes
834 * The first byte will be written to the status register, while the
835 * second byte will be written to the configuration register.
836 - * Return negative if error occured.
837 + * Return negative if error occurred.
838 */
839 static int write_sr_cr(struct spi_nor *nor, u16 val)
840 {
841 @@ -1464,6 +1540,24 @@ static int spansion_quad_enable(struct s
842 return 0;
843 }
844
845 +static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info)
846 +{
847 + int status;
848 +
849 + switch (JEDEC_MFR(info)) {
850 + case SNOR_MFR_SPANSION:
851 + status = spansion_quad_enable(nor);
852 + if (status) {
853 + dev_err(nor->dev, "Spansion DDR quad-read not enabled\n");
854 + return status;
855 + }
856 + return status;
857 + default:
858 + return -EINVAL;
859 + }
860 +}
861 +
862 +
863 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
864 {
865 int status;
866 @@ -1610,9 +1704,25 @@ int spi_nor_scan(struct spi_nor *nor, co
867 write_sr(nor, 0);
868 spi_nor_wait_till_ready(nor);
869 }
870 + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
871 + ret = read_sr(nor);
872 + ret &= SPI_NOR_MICRON_WRITE_ENABLE;
873 +
874 + write_enable(nor);
875 + write_sr(nor, ret);
876 + }
877 +
878 + if (EXT_ID(info) == SPINOR_S25FS_FAMILY_ID) {
879 + ret = spansion_s25fs_disable_4kb_erase(nor);
880 + if (ret)
881 + return ret;
882 + }
883 +
884
885 if (!mtd->name)
886 mtd->name = dev_name(dev);
887 + if (info->name)
888 + nor->vendor = info->name;
889 mtd->priv = nor;
890 mtd->type = MTD_NORFLASH;
891 mtd->writesize = 1;
892 @@ -1646,6 +1756,8 @@ int spi_nor_scan(struct spi_nor *nor, co
893 nor->flags |= SNOR_F_USE_FSR;
894 if (info->flags & SPI_NOR_HAS_TB)
895 nor->flags |= SNOR_F_HAS_SR_TB;
896 + if (info->flags & NO_CHIP_ERASE)
897 + nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
898
899 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
900 /* prefer "small sector" erase if possible */
901 @@ -1685,9 +1797,15 @@ int spi_nor_scan(struct spi_nor *nor, co
902 /* Some devices cannot do fast-read, no matter what DT tells us */
903 if (info->flags & SPI_NOR_NO_FR)
904 nor->flash_read = SPI_NOR_NORMAL;
905 -
906 - /* Quad/Dual-read mode takes precedence over fast/normal */
907 - if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
908 + /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
909 + if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
910 + ret = set_ddr_quad_mode(nor, info);
911 + if (ret) {
912 + dev_err(dev, "DDR quad mode not supported\n");
913 + return ret;
914 + }
915 + nor->flash_read = SPI_NOR_DDR_QUAD;
916 + } else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
917 ret = set_quad_mode(nor, info);
918 if (ret) {
919 dev_err(dev, "quad mode not supported\n");
920 @@ -1700,6 +1818,9 @@ int spi_nor_scan(struct spi_nor *nor, co
921
922 /* Default commands */
923 switch (nor->flash_read) {
924 + case SPI_NOR_DDR_QUAD:
925 + nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
926 + break;
927 case SPI_NOR_QUAD:
928 nor->read_opcode = SPINOR_OP_READ_1_1_4;
929 break;
930 --- a/include/linux/mtd/spi-nor.h
931 +++ b/include/linux/mtd/spi-nor.h
932 @@ -31,10 +31,10 @@
933
934 /*
935 * Note on opcode nomenclature: some opcodes have a format like
936 - * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
937 + * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y,and z stand for the number
938 * of I/O lines used for the opcode, address, and data (respectively). The
939 * FUNCTION has an optional suffix of '4', to represent an opcode which
940 - * requires a 4-byte (32-bit) address.
941 + * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the
942 */
943
944 /* Flash opcodes. */
945 @@ -46,7 +46,9 @@
946 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
947 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
948 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
949 +#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
950 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
951 +#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
952 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
953 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
954 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
955 @@ -62,9 +64,11 @@
956 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
957 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
958 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
959 +#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
960 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
961 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
962 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
963 +#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
964 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
965 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
966 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
967 @@ -94,6 +98,10 @@
968 /* Used for Spansion flashes only. */
969 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
970
971 +/* Used for Spansion S25FS-S family flash only. */
972 +#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */
973 +#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */
974 +
975 /* Used for Micron flashes only. */
976 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
977 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
978 @@ -124,6 +132,7 @@ enum read_mode {
979 SPI_NOR_FAST,
980 SPI_NOR_DUAL,
981 SPI_NOR_QUAD,
982 + SPI_NOR_DDR_QUAD,
983 };
984
985 #define SPI_NOR_MAX_CMD_SIZE 8
986 @@ -189,6 +198,7 @@ struct spi_nor {
987 bool sst_write_second;
988 u32 flags;
989 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
990 + char *vendor;
991
992 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
993 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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