projects / openwrt / openwrt.git / blob
? search:


14f503f8e5375e65b4323ec6e420ed9d07140db3
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 402-mtd-support-layerscape.patch
1 From d9d0181f74146507026c31cccd52dda27ec3d966 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Wed, 17 Jan 2018 14:57:31 +0800
4 Subject: [PATCH 06/30] mtd: support layerscape
5
6 This is an integrated patch for layerscape ifc-nor-nand support.
7
8 Signed-off-by: Alison Wang <b18965@freescale.com>
9 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
10 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
11 ---
12 drivers/memory/Kconfig | 2 +-
13 drivers/memory/fsl_ifc.c | 263 ++++++++++++++++++++++++++++++++++++++++
14 drivers/mtd/maps/physmap_of.c | 4 +
15 drivers/mtd/nand/Kconfig | 2 +-
16 drivers/mtd/nand/fsl_ifc_nand.c | 5 +-
17 include/linux/fsl_ifc.h | 7 ++
18 6 files changed, 280 insertions(+), 3 deletions(-)
19
20 --- a/drivers/memory/Kconfig
21 +++ b/drivers/memory/Kconfig
22 @@ -115,7 +115,7 @@ config FSL_CORENET_CF
23
24 config FSL_IFC
25 bool
26 - depends on FSL_SOC || ARCH_LAYERSCAPE
27 + depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
28
29 config JZ4780_NEMC
30 bool "Ingenic JZ4780 SoC NEMC driver"
31 --- a/drivers/memory/fsl_ifc.c
32 +++ b/drivers/memory/fsl_ifc.c
33 @@ -24,6 +24,7 @@
34 #include <linux/compiler.h>
35 #include <linux/sched.h>
36 #include <linux/spinlock.h>
37 +#include <linux/delay.h>
38 #include <linux/types.h>
39 #include <linux/slab.h>
40 #include <linux/io.h>
41 @@ -37,6 +38,8 @@
42
43 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
44 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
45 +#define FSL_IFC_V1_3_0 0x01030000
46 +#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */
47
48 /*
49 * convert_ifc_address - convert the base address
50 @@ -311,6 +314,261 @@ err:
51 return ret;
52 }
53
54 +#ifdef CONFIG_PM_SLEEP
55 +/* save ifc registers */
56 +static int fsl_ifc_suspend(struct device *dev)
57 +{
58 + struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
59 + struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
60 + struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
61 + __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
62 + gpcm_evter_intr_en;
63 + uint32_t ifc_bank, i;
64 +
65 + ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_global), GFP_KERNEL);
66 + if (!ctrl->saved_gregs)
67 + return -ENOMEM;
68 + ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
69 + if (!ctrl->saved_rregs)
70 + return -ENOMEM;
71 +
72 + cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
73 + nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
74 + nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
75 + gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
76 +
77 +/* IFC interrupts disabled */
78 +
79 + ifc_out32(0x0, &fcm->cm_evter_intr_en);
80 + ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
81 + ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
82 + ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
83 +
84 + if (ctrl->saved_gregs) {
85 + for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
86 + ctrl->saved_gregs->cspr_cs[ifc_bank].cspr_ext =
87 + ifc_in32(&fcm->cspr_cs[ifc_bank].cspr_ext);
88 + ctrl->saved_gregs->cspr_cs[ifc_bank].cspr =
89 + ifc_in32(&fcm->cspr_cs[ifc_bank].cspr);
90 + ctrl->saved_gregs->amask_cs[ifc_bank].amask =
91 + ifc_in32(&fcm->amask_cs[ifc_bank].amask);
92 + ctrl->saved_gregs->csor_cs[ifc_bank].csor_ext =
93 + ifc_in32(&fcm->csor_cs[ifc_bank].csor_ext);
94 + ctrl->saved_gregs->csor_cs[ifc_bank].csor =
95 + ifc_in32(&fcm->csor_cs[ifc_bank].csor);
96 + for (i = 0; i < 4; i++) {
97 + ctrl->saved_gregs->ftim_cs[ifc_bank].ftim[i] =
98 + ifc_in32(
99 + &fcm->ftim_cs[ifc_bank].ftim[i]);
100 + }
101 + }
102 +
103 + ctrl->saved_gregs->rb_map = ifc_in32(&fcm->rb_map);
104 + ctrl->saved_gregs->wb_map = ifc_in32(&fcm->wb_map);
105 + ctrl->saved_gregs->ifc_gcr = ifc_in32(&fcm->ifc_gcr);
106 + ctrl->saved_gregs->ddr_ccr_low = ifc_in32(&fcm->ddr_ccr_low);
107 + ctrl->saved_gregs->cm_evter_en = ifc_in32(&fcm->cm_evter_en);
108 + }
109 +
110 + if (ctrl->saved_rregs) {
111 + /* IFC controller NAND machine registers */
112 + ctrl->saved_rregs->ifc_nand.ncfgr =
113 + ifc_in32(&runtime->ifc_nand.ncfgr);
114 + ctrl->saved_rregs->ifc_nand.nand_fcr0 =
115 + ifc_in32(&runtime->ifc_nand.nand_fcr0);
116 + ctrl->saved_rregs->ifc_nand.nand_fcr1 =
117 + ifc_in32(&runtime->ifc_nand.nand_fcr1);
118 + ctrl->saved_rregs->ifc_nand.row0 =
119 + ifc_in32(&runtime->ifc_nand.row0);
120 + ctrl->saved_rregs->ifc_nand.row1 =
121 + ifc_in32(&runtime->ifc_nand.row1);
122 + ctrl->saved_rregs->ifc_nand.col0 =
123 + ifc_in32(&runtime->ifc_nand.col0);
124 + ctrl->saved_rregs->ifc_nand.col1 =
125 + ifc_in32(&runtime->ifc_nand.col1);
126 + ctrl->saved_rregs->ifc_nand.row2 =
127 + ifc_in32(&runtime->ifc_nand.row2);
128 + ctrl->saved_rregs->ifc_nand.col2 =
129 + ifc_in32(&runtime->ifc_nand.col2);
130 + ctrl->saved_rregs->ifc_nand.row3 =
131 + ifc_in32(&runtime->ifc_nand.row3);
132 + ctrl->saved_rregs->ifc_nand.col3 =
133 + ifc_in32(&runtime->ifc_nand.col3);
134 +
135 + ctrl->saved_rregs->ifc_nand.nand_fbcr =
136 + ifc_in32(&runtime->ifc_nand.nand_fbcr);
137 + ctrl->saved_rregs->ifc_nand.nand_fir0 =
138 + ifc_in32(&runtime->ifc_nand.nand_fir0);
139 + ctrl->saved_rregs->ifc_nand.nand_fir1 =
140 + ifc_in32(&runtime->ifc_nand.nand_fir1);
141 + ctrl->saved_rregs->ifc_nand.nand_fir2 =
142 + ifc_in32(&runtime->ifc_nand.nand_fir2);
143 + ctrl->saved_rregs->ifc_nand.nand_csel =
144 + ifc_in32(&runtime->ifc_nand.nand_csel);
145 + ctrl->saved_rregs->ifc_nand.nandseq_strt =
146 + ifc_in32(
147 + &runtime->ifc_nand.nandseq_strt);
148 + ctrl->saved_rregs->ifc_nand.nand_evter_en =
149 + ifc_in32(
150 + &runtime->ifc_nand.nand_evter_en);
151 + ctrl->saved_rregs->ifc_nand.nanndcr =
152 + ifc_in32(&runtime->ifc_nand.nanndcr);
153 + ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg0 =
154 + ifc_in32(
155 + &runtime->ifc_nand.nand_dll_lowcfg0);
156 + ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg1 =
157 + ifc_in32(
158 + &runtime->ifc_nand.nand_dll_lowcfg1);
159 +
160 + /* IFC controller NOR machine registers */
161 + ctrl->saved_rregs->ifc_nor.nor_evter_en =
162 + ifc_in32(
163 + &runtime->ifc_nor.nor_evter_en);
164 + ctrl->saved_rregs->ifc_nor.norcr =
165 + ifc_in32(&runtime->ifc_nor.norcr);
166 +
167 + /* IFC controller GPCM Machine registers */
168 + ctrl->saved_rregs->ifc_gpcm.gpcm_evter_en =
169 + ifc_in32(
170 + &runtime->ifc_gpcm.gpcm_evter_en);
171 + }
172 +
173 +/* save the interrupt values */
174 + ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
175 + ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
176 + ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
177 + ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
178 +
179 + return 0;
180 +}
181 +
182 +/* restore ifc registers */
183 +static int fsl_ifc_resume(struct device *dev)
184 +{
185 + struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
186 + struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
187 + struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
188 + struct fsl_ifc_global *savd_gregs = ctrl->saved_gregs;
189 + struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
190 + uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
191 +
192 +/*
193 + * IFC interrupts disabled
194 + */
195 + ifc_out32(0x0, &fcm->cm_evter_intr_en);
196 + ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
197 + ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
198 + ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
199 +
200 +
201 + if (ctrl->saved_gregs) {
202 + for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
203 + ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
204 + &fcm->cspr_cs[ifc_bank].cspr_ext);
205 + ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
206 + &fcm->cspr_cs[ifc_bank].cspr);
207 + ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
208 + &fcm->amask_cs[ifc_bank].amask);
209 + ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
210 + &fcm->csor_cs[ifc_bank].csor_ext);
211 + ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
212 + &fcm->csor_cs[ifc_bank].csor);
213 + for (i = 0; i < 4; i++) {
214 + ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
215 + &fcm->ftim_cs[ifc_bank].ftim[i]);
216 + }
217 + }
218 + ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
219 + ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
220 + ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
221 + ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
222 + ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
223 + }
224 +
225 + if (ctrl->saved_rregs) {
226 + /* IFC controller NAND machine registers */
227 + ifc_out32(savd_rregs->ifc_nand.ncfgr,
228 + &runtime->ifc_nand.ncfgr);
229 + ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
230 + &runtime->ifc_nand.nand_fcr0);
231 + ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
232 + &runtime->ifc_nand.nand_fcr1);
233 + ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
234 + ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
235 + ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
236 + ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
237 + ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
238 + ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
239 + ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
240 + ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
241 + ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
242 + &runtime->ifc_nand.nand_fbcr);
243 + ifc_out32(savd_rregs->ifc_nand.nand_fir0,
244 + &runtime->ifc_nand.nand_fir0);
245 + ifc_out32(savd_rregs->ifc_nand.nand_fir1,
246 + &runtime->ifc_nand.nand_fir1);
247 + ifc_out32(savd_rregs->ifc_nand.nand_fir2,
248 + &runtime->ifc_nand.nand_fir2);
249 + ifc_out32(savd_rregs->ifc_nand.nand_csel,
250 + &runtime->ifc_nand.nand_csel);
251 + ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
252 + &runtime->ifc_nand.nandseq_strt);
253 + ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
254 + &runtime->ifc_nand.nand_evter_en);
255 + ifc_out32(savd_rregs->ifc_nand.nanndcr,
256 + &runtime->ifc_nand.nanndcr);
257 + ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
258 + &runtime->ifc_nand.nand_dll_lowcfg0);
259 + ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
260 + &runtime->ifc_nand.nand_dll_lowcfg1);
261 +
262 + /* IFC controller NOR machine registers */
263 + ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
264 + &runtime->ifc_nor.nor_evter_en);
265 + ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
266 +
267 + /* IFC controller GPCM Machine registers */
268 + ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
269 + &runtime->ifc_gpcm.gpcm_evter_en);
270 +
271 + /* IFC interrupts enabled */
272 + ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
273 + &fcm->cm_evter_intr_en);
274 + ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
275 + &runtime->ifc_nand.nand_evter_intr_en);
276 + ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
277 + &runtime->ifc_nor.nor_evter_intr_en);
278 + ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
279 + &runtime->ifc_gpcm.gpcm_evter_intr_en);
280 +
281 + kfree(ctrl->saved_gregs);
282 + kfree(ctrl->saved_rregs);
283 + ctrl->saved_gregs = NULL;
284 + ctrl->saved_rregs = NULL;
285 + }
286 +
287 + ver = ifc_in32(&fcm->ifc_rev);
288 + ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
289 + if (ver >= FSL_IFC_V1_3_0) {
290 +
291 + ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
292 + &runtime->ifc_nand.ncfgr);
293 + /* wait for SRAM_INIT bit to be clear or timeout */
294 + timeout = 10;
295 + while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
296 + IFC_NAND_SRAM_INIT_EN) && timeout) {
297 + mdelay(IFC_TIMEOUT_MSECS);
298 + timeout--;
299 + }
300 +
301 + if (!timeout)
302 + dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
303 + }
304 +
305 + return 0;
306 +}
307 +#endif /* CONFIG_PM_SLEEP */
308 +
309 static const struct of_device_id fsl_ifc_match[] = {
310 {
311 .compatible = "fsl,ifc",
312 @@ -318,10 +576,15 @@ static const struct of_device_id fsl_ifc
313 {},
314 };
315
316 +static const struct dev_pm_ops ifc_pm_ops = {
317 + SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
318 +};
319 +
320 static struct platform_driver fsl_ifc_ctrl_driver = {
321 .driver = {
322 .name = "fsl-ifc",
323 .of_match_table = fsl_ifc_match,
324 + .pm = &ifc_pm_ops,
325 },
326 .probe = fsl_ifc_ctrl_probe,
327 .remove = fsl_ifc_ctrl_remove,
328 --- a/drivers/mtd/maps/physmap_of.c
329 +++ b/drivers/mtd/maps/physmap_of.c
330 @@ -20,6 +20,7 @@
331 #include <linux/mtd/map.h>
332 #include <linux/mtd/partitions.h>
333 #include <linux/mtd/concat.h>
334 +#include <linux/mtd/cfi_endian.h>
335 #include <linux/of.h>
336 #include <linux/of_address.h>
337 #include <linux/of_platform.h>
338 @@ -209,6 +210,9 @@ static int of_flash_probe(struct platfor
339 return err;
340 }
341
342 + if (of_property_read_bool(dp->parent, "big-endian"))
343 + info->list[i].map.swap = CFI_BIG_ENDIAN;
344 +
345 err = -ENOMEM;
346 info->list[i].map.virt = ioremap(info->list[i].map.phys,
347 info->list[i].map.size);
348 --- a/drivers/mtd/nand/Kconfig
349 +++ b/drivers/mtd/nand/Kconfig
350 @@ -438,7 +438,7 @@ config MTD_NAND_FSL_ELBC
351
352 config MTD_NAND_FSL_IFC
353 tristate "NAND support for Freescale IFC controller"
354 - depends on FSL_SOC || ARCH_LAYERSCAPE
355 + depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
356 select FSL_IFC
357 select MEMORY
358 help
359 --- a/drivers/mtd/nand/fsl_ifc_nand.c
360 +++ b/drivers/mtd/nand/fsl_ifc_nand.c
361 @@ -904,9 +904,12 @@ static int fsl_ifc_chip_init(struct fsl_
362 chip->ecc.algo = NAND_ECC_HAMMING;
363 }
364
365 - if (ctrl->version == FSL_IFC_VERSION_1_1_0)
366 + if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
367 fsl_ifc_sram_init(priv);
368
369 + if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
370 + priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
371 +
372 return 0;
373 }
374
375 --- a/include/linux/fsl_ifc.h
376 +++ b/include/linux/fsl_ifc.h
377 @@ -274,6 +274,8 @@
378 */
379 /* Auto Boot Mode */
380 #define IFC_NAND_NCFGR_BOOT 0x80000000
381 +/* SRAM INIT EN */
382 +#define IFC_NAND_SRAM_INIT_EN 0x20000000
383 /* Addressing Mode-ROW0+n/COL0 */
384 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
385 /* Addressing Mode-ROW0+n/COL0+n */
386 @@ -861,6 +863,11 @@ struct fsl_ifc_ctrl {
387 u32 nand_stat;
388 wait_queue_head_t nand_wait;
389 bool little_endian;
390 +#ifdef CONFIG_PM_SLEEP
391 + /*save regs when system goes to deep sleep*/
392 + struct fsl_ifc_global *saved_gregs;
393 + struct fsl_ifc_runtime *saved_rregs;
394 +#endif
395 };
396
397 extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
OpenWrt Source Repository