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kernel: bump 4.9 to 4.9.63
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 702-pci-support-layerscape.patch
1 From 9e6e0a53b29190dbd86a39304b59c3028f5b36c2 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 11:04:10 +0800
4 Subject: [PATCH] pci: support layerscape
5
6 This is a integrated patch for layerscape pcie support.
7
8 Signed-off-by: Po Liu <po.liu@nxp.com>
9 Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
10 Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
11 Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
12 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
13 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
14 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
15 Signed-off-by: Christoph Hellwig <hch@lst.de>
16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
17 ---
18 drivers/irqchip/irq-ls-scfg-msi.c | 257 +++++++--
19 drivers/pci/host/Makefile | 2 +-
20 drivers/pci/host/pci-layerscape-ep-debugfs.c | 758 +++++++++++++++++++++++++++
21 drivers/pci/host/pci-layerscape-ep.c | 309 +++++++++++
22 drivers/pci/host/pci-layerscape-ep.h | 115 ++++
23 drivers/pci/host/pci-layerscape.c | 38 +-
24 drivers/pci/host/pcie-designware.c | 6 +
25 drivers/pci/host/pcie-designware.h | 1 +
26 drivers/pci/pcie/portdrv_core.c | 181 +++----
27 include/linux/pci.h | 1 +
28 10 files changed, 1520 insertions(+), 148 deletions(-)
29 create mode 100644 drivers/pci/host/pci-layerscape-ep-debugfs.c
30 create mode 100644 drivers/pci/host/pci-layerscape-ep.c
31 create mode 100644 drivers/pci/host/pci-layerscape-ep.h
32
33 --- a/drivers/irqchip/irq-ls-scfg-msi.c
34 +++ b/drivers/irqchip/irq-ls-scfg-msi.c
35 @@ -17,13 +17,32 @@
36 #include <linux/irq.h>
37 #include <linux/irqchip/chained_irq.h>
38 #include <linux/irqdomain.h>
39 +#include <linux/of_irq.h>
40 #include <linux/of_pci.h>
41 #include <linux/of_platform.h>
42 #include <linux/spinlock.h>
43
44 -#define MSI_MAX_IRQS 32
45 -#define MSI_IBS_SHIFT 3
46 -#define MSIR 4
47 +#define MSI_IRQS_PER_MSIR 32
48 +#define MSI_MSIR_OFFSET 4
49 +
50 +#define MSI_LS1043V1_1_IRQS_PER_MSIR 8
51 +#define MSI_LS1043V1_1_MSIR_OFFSET 0x10
52 +
53 +struct ls_scfg_msi_cfg {
54 + u32 ibs_shift; /* Shift of interrupt bit select */
55 + u32 msir_irqs; /* The irq number per MSIR */
56 + u32 msir_base; /* The base address of MSIR */
57 +};
58 +
59 +struct ls_scfg_msir {
60 + struct ls_scfg_msi *msi_data;
61 + unsigned int index;
62 + unsigned int gic_irq;
63 + unsigned int bit_start;
64 + unsigned int bit_end;
65 + unsigned int srs; /* Shared interrupt register select */
66 + void __iomem *reg;
67 +};
68
69 struct ls_scfg_msi {
70 spinlock_t lock;
71 @@ -32,8 +51,11 @@ struct ls_scfg_msi {
72 struct irq_domain *msi_domain;
73 void __iomem *regs;
74 phys_addr_t msiir_addr;
75 - int irq;
76 - DECLARE_BITMAP(used, MSI_MAX_IRQS);
77 + struct ls_scfg_msi_cfg *cfg;
78 + u32 msir_num;
79 + struct ls_scfg_msir *msir;
80 + u32 irqs_num;
81 + unsigned long *used;
82 };
83
84 static struct irq_chip ls_scfg_msi_irq_chip = {
85 @@ -49,19 +71,56 @@ static struct msi_domain_info ls_scfg_ms
86 .chip = &ls_scfg_msi_irq_chip,
87 };
88
89 +static int msi_affinity_flag = 1;
90 +
91 +static int __init early_parse_ls_scfg_msi(char *p)
92 +{
93 + if (p && strncmp(p, "no-affinity", 11) == 0)
94 + msi_affinity_flag = 0;
95 + else
96 + msi_affinity_flag = 1;
97 +
98 + return 0;
99 +}
100 +early_param("lsmsi", early_parse_ls_scfg_msi);
101 +
102 static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
103 {
104 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
105
106 msg->address_hi = upper_32_bits(msi_data->msiir_addr);
107 msg->address_lo = lower_32_bits(msi_data->msiir_addr);
108 - msg->data = data->hwirq << MSI_IBS_SHIFT;
109 + msg->data = data->hwirq;
110 +
111 + if (msi_affinity_flag)
112 + msg->data |= cpumask_first(data->common->affinity);
113 }
114
115 static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
116 const struct cpumask *mask, bool force)
117 {
118 - return -EINVAL;
119 + struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
120 + u32 cpu;
121 +
122 + if (!msi_affinity_flag)
123 + return -EINVAL;
124 +
125 + if (!force)
126 + cpu = cpumask_any_and(mask, cpu_online_mask);
127 + else
128 + cpu = cpumask_first(mask);
129 +
130 + if (cpu >= msi_data->msir_num)
131 + return -EINVAL;
132 +
133 + if (msi_data->msir[cpu].gic_irq <= 0) {
134 + pr_warn("cannot bind the irq to cpu%d\n", cpu);
135 + return -EINVAL;
136 + }
137 +
138 + cpumask_copy(irq_data->common->affinity, mask);
139 +
140 + return IRQ_SET_MASK_OK;
141 }
142
143 static struct irq_chip ls_scfg_msi_parent_chip = {
144 @@ -81,8 +140,8 @@ static int ls_scfg_msi_domain_irq_alloc(
145 WARN_ON(nr_irqs != 1);
146
147 spin_lock(&msi_data->lock);
148 - pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS);
149 - if (pos < MSI_MAX_IRQS)
150 + pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
151 + if (pos < msi_data->irqs_num)
152 __set_bit(pos, msi_data->used);
153 else
154 err = -ENOSPC;
155 @@ -106,7 +165,7 @@ static void ls_scfg_msi_domain_irq_free(
156 int pos;
157
158 pos = d->hwirq;
159 - if (pos < 0 || pos >= MSI_MAX_IRQS) {
160 + if (pos < 0 || pos >= msi_data->irqs_num) {
161 pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
162 return;
163 }
164 @@ -123,15 +182,22 @@ static const struct irq_domain_ops ls_sc
165
166 static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
167 {
168 - struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc);
169 + struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
170 + struct ls_scfg_msi *msi_data = msir->msi_data;
171 unsigned long val;
172 - int pos, virq;
173 + int pos, size, virq, hwirq;
174
175 chained_irq_enter(irq_desc_get_chip(desc), desc);
176
177 - val = ioread32be(msi_data->regs + MSIR);
178 - for_each_set_bit(pos, &val, MSI_MAX_IRQS) {
179 - virq = irq_find_mapping(msi_data->parent, (31 - pos));
180 + val = ioread32be(msir->reg);
181 +
182 + pos = msir->bit_start;
183 + size = msir->bit_end + 1;
184 +
185 + for_each_set_bit_from(pos, &val, size) {
186 + hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
187 + msir->srs;
188 + virq = irq_find_mapping(msi_data->parent, hwirq);
189 if (virq)
190 generic_handle_irq(virq);
191 }
192 @@ -143,7 +209,7 @@ static int ls_scfg_msi_domains_init(stru
193 {
194 /* Initialize MSI domain parent */
195 msi_data->parent = irq_domain_add_linear(NULL,
196 - MSI_MAX_IRQS,
197 + msi_data->irqs_num,
198 &ls_scfg_msi_domain_ops,
199 msi_data);
200 if (!msi_data->parent) {
201 @@ -164,16 +230,118 @@ static int ls_scfg_msi_domains_init(stru
202 return 0;
203 }
204
205 +static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
206 +{
207 + struct ls_scfg_msir *msir;
208 + int virq, i, hwirq;
209 +
210 + virq = platform_get_irq(msi_data->pdev, index);
211 + if (virq <= 0)
212 + return -ENODEV;
213 +
214 + msir = &msi_data->msir[index];
215 + msir->index = index;
216 + msir->msi_data = msi_data;
217 + msir->gic_irq = virq;
218 + msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
219 +
220 + if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
221 + msir->bit_start = 32 - ((msir->index + 1) *
222 + MSI_LS1043V1_1_IRQS_PER_MSIR);
223 + msir->bit_end = msir->bit_start +
224 + MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
225 + } else {
226 + msir->bit_start = 0;
227 + msir->bit_end = msi_data->cfg->msir_irqs - 1;
228 + }
229 +
230 + irq_set_chained_handler_and_data(msir->gic_irq,
231 + ls_scfg_msi_irq_handler,
232 + msir);
233 +
234 + if (msi_affinity_flag) {
235 + /* Associate MSIR interrupt to the cpu */
236 + irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
237 + msir->srs = 0; /* This value is determined by the CPU */
238 + } else
239 + msir->srs = index;
240 +
241 + /* Release the hwirqs corresponding to this MSIR */
242 + if (!msi_affinity_flag || msir->index == 0) {
243 + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
244 + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
245 + bitmap_clear(msi_data->used, hwirq, 1);
246 + }
247 + }
248 +
249 + return 0;
250 +}
251 +
252 +static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
253 +{
254 + struct ls_scfg_msi *msi_data = msir->msi_data;
255 + int i, hwirq;
256 +
257 + if (msir->gic_irq > 0)
258 + irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
259 +
260 + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
261 + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
262 + bitmap_set(msi_data->used, hwirq, 1);
263 + }
264 +
265 + return 0;
266 +}
267 +
268 +static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
269 + .ibs_shift = 3,
270 + .msir_irqs = MSI_IRQS_PER_MSIR,
271 + .msir_base = MSI_MSIR_OFFSET,
272 +};
273 +
274 +static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
275 + .ibs_shift = 2,
276 + .msir_irqs = MSI_IRQS_PER_MSIR,
277 + .msir_base = MSI_MSIR_OFFSET,
278 +};
279 +
280 +static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
281 + .ibs_shift = 2,
282 + .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
283 + .msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
284 +};
285 +
286 +static const struct of_device_id ls_scfg_msi_id[] = {
287 + /* The following two misspelled compatibles are obsolete */
288 + { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
289 + { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
290 +
291 + { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg },
292 + { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
293 + { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
294 + { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
295 + { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
296 + {},
297 +};
298 +MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
299 +
300 static int ls_scfg_msi_probe(struct platform_device *pdev)
301 {
302 + const struct of_device_id *match;
303 struct ls_scfg_msi *msi_data;
304 struct resource *res;
305 - int ret;
306 + int i, ret;
307 +
308 + match = of_match_device(ls_scfg_msi_id, &pdev->dev);
309 + if (!match)
310 + return -ENODEV;
311
312 msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
313 if (!msi_data)
314 return -ENOMEM;
315
316 + msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
317 +
318 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
319 msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
320 if (IS_ERR(msi_data->regs)) {
321 @@ -182,23 +350,48 @@ static int ls_scfg_msi_probe(struct plat
322 }
323 msi_data->msiir_addr = res->start;
324
325 - msi_data->irq = platform_get_irq(pdev, 0);
326 - if (msi_data->irq <= 0) {
327 - dev_err(&pdev->dev, "failed to get MSI irq\n");
328 - return -ENODEV;
329 - }
330 -
331 msi_data->pdev = pdev;
332 spin_lock_init(&msi_data->lock);
333
334 + msi_data->irqs_num = MSI_IRQS_PER_MSIR *
335 + (1 << msi_data->cfg->ibs_shift);
336 + msi_data->used = devm_kcalloc(&pdev->dev,
337 + BITS_TO_LONGS(msi_data->irqs_num),
338 + sizeof(*msi_data->used),
339 + GFP_KERNEL);
340 + if (!msi_data->used)
341 + return -ENOMEM;
342 + /*
343 + * Reserve all the hwirqs
344 + * The available hwirqs will be released in ls1_msi_setup_hwirq()
345 + */
346 + bitmap_set(msi_data->used, 0, msi_data->irqs_num);
347 +
348 + msi_data->msir_num = of_irq_count(pdev->dev.of_node);
349 +
350 + if (msi_affinity_flag) {
351 + u32 cpu_num;
352 +
353 + cpu_num = num_possible_cpus();
354 + if (msi_data->msir_num >= cpu_num)
355 + msi_data->msir_num = cpu_num;
356 + else
357 + msi_affinity_flag = 0;
358 + }
359 +
360 + msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
361 + sizeof(*msi_data->msir),
362 + GFP_KERNEL);
363 + if (!msi_data->msir)
364 + return -ENOMEM;
365 +
366 + for (i = 0; i < msi_data->msir_num; i++)
367 + ls_scfg_msi_setup_hwirq(msi_data, i);
368 +
369 ret = ls_scfg_msi_domains_init(msi_data);
370 if (ret)
371 return ret;
372
373 - irq_set_chained_handler_and_data(msi_data->irq,
374 - ls_scfg_msi_irq_handler,
375 - msi_data);
376 -
377 platform_set_drvdata(pdev, msi_data);
378
379 return 0;
380 @@ -207,8 +400,10 @@ static int ls_scfg_msi_probe(struct plat
381 static int ls_scfg_msi_remove(struct platform_device *pdev)
382 {
383 struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
384 + int i;
385
386 - irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL);
387 + for (i = 0; i < msi_data->msir_num; i++)
388 + ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
389
390 irq_domain_remove(msi_data->msi_domain);
391 irq_domain_remove(msi_data->parent);
392 @@ -218,12 +413,6 @@ static int ls_scfg_msi_remove(struct pla
393 return 0;
394 }
395
396 -static const struct of_device_id ls_scfg_msi_id[] = {
397 - { .compatible = "fsl,1s1021a-msi", },
398 - { .compatible = "fsl,1s1043a-msi", },
399 - {},
400 -};
401 -
402 static struct platform_driver ls_scfg_msi_driver = {
403 .driver = {
404 .name = "ls-scfg-msi",
405 --- a/drivers/pci/host/Makefile
406 +++ b/drivers/pci/host/Makefile
407 @@ -17,7 +17,7 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx
408 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
409 obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
410 obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
411 -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
412 +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o pci-layerscape-ep-debugfs.o
413 obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
414 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
415 obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
416 --- /dev/null
417 +++ b/drivers/pci/host/pci-layerscape-ep-debugfs.c
418 @@ -0,0 +1,758 @@
419 +/*
420 + * PCIe Endpoint driver for Freescale Layerscape SoCs
421 + *
422 + * Copyright (C) 2015 Freescale Semiconductor.
423 + *
424 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
425 + *
426 + * This program is free software; you can redistribute it and/or modify
427 + * it under the terms of the GNU General Public License version 2 as
428 + * published by the Free Software Foundation.
429 + */
430 +
431 +#include <linux/kernel.h>
432 +#include <linux/module.h>
433 +#include <linux/debugfs.h>
434 +#include <linux/time.h>
435 +#include <linux/uaccess.h>
436 +#include <linux/kthread.h>
437 +#include <linux/slab.h>
438 +#include <linux/dmaengine.h>
439 +#include <linux/dma-mapping.h>
440 +#include <linux/freezer.h>
441 +
442 +#include <linux/completion.h>
443 +
444 +#include "pci-layerscape-ep.h"
445 +
446 +#define PCIE_ATU_INDEX3 (0x3 << 0)
447 +#define PCIE_ATU_INDEX2 (0x2 << 0)
448 +#define PCIE_ATU_INDEX1 (0x1 << 0)
449 +#define PCIE_ATU_INDEX0 (0x0 << 0)
450 +
451 +#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
452 +#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
453 +#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
454 +#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
455 +#define PCIE_MSI_OB_SIZE (4 * 1024) /* 4K */
456 +
457 +#define PCIE_MSI_MSG_ADDR_OFF 0x54
458 +#define PCIE_MSI_MSG_DATA_OFF 0x5c
459 +
460 +enum test_type {
461 + TEST_TYPE_DMA,
462 + TEST_TYPE_MEMCPY
463 +};
464 +
465 +enum test_dirt {
466 + TEST_DIRT_READ,
467 + TEST_DIRT_WRITE
468 +};
469 +
470 +enum test_status {
471 + TEST_IDLE,
472 + TEST_BUSY
473 +};
474 +
475 +struct ls_ep_test {
476 + struct ls_ep_dev *ep;
477 + void __iomem *cfg;
478 + void __iomem *buf;
479 + void __iomem *out;
480 + void __iomem *msi;
481 + dma_addr_t cfg_addr;
482 + dma_addr_t buf_addr;
483 + dma_addr_t out_addr;
484 + dma_addr_t bus_addr;
485 + dma_addr_t msi_addr;
486 + u64 msi_msg_addr;
487 + u16 msi_msg_data;
488 + struct task_struct *thread;
489 + spinlock_t lock;
490 + struct completion done;
491 + u32 len;
492 + int loop;
493 + char data;
494 + enum test_dirt dirt;
495 + enum test_type type;
496 + enum test_status status;
497 + u64 result; /* Mbps */
498 + char cmd[256];
499 +};
500 +
501 +static int ls_pcie_ep_trigger_msi(struct ls_ep_test *test)
502 +{
503 + if (!test->msi)
504 + return -EINVAL;
505 +
506 + iowrite32(test->msi_msg_data, test->msi);
507 +
508 + return 0;
509 +}
510 +
511 +static int ls_pcie_ep_test_try_run(struct ls_ep_test *test)
512 +{
513 + int ret;
514 +
515 + spin_lock(&test->lock);
516 + if (test->status == TEST_IDLE) {
517 + test->status = TEST_BUSY;
518 + ret = 0;
519 + } else
520 + ret = -EBUSY;
521 + spin_unlock(&test->lock);
522 +
523 + return ret;
524 +}
525 +
526 +static void ls_pcie_ep_test_done(struct ls_ep_test *test)
527 +{
528 + spin_lock(&test->lock);
529 + test->status = TEST_IDLE;
530 + spin_unlock(&test->lock);
531 +}
532 +
533 +static void ls_pcie_ep_test_dma_cb(void *arg)
534 +{
535 + struct ls_ep_test *test = arg;
536 +
537 + complete(&test->done);
538 +}
539 +
540 +static int ls_pcie_ep_test_dma(struct ls_ep_test *test)
541 +{
542 + dma_cap_mask_t mask;
543 + struct dma_chan *chan;
544 + struct dma_device *dma_dev;
545 + dma_addr_t src, dst;
546 + enum dma_data_direction direction;
547 + enum dma_ctrl_flags dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
548 + struct timespec start, end, period;
549 + int i = 0;
550 +
551 + dma_cap_zero(mask);
552 + dma_cap_set(DMA_MEMCPY, mask);
553 +
554 + chan = dma_request_channel(mask, NULL, test);
555 + if (!chan) {
556 + pr_err("failed to request dma channel\n");
557 + return -EINVAL;
558 + }
559 +
560 + memset(test->buf, test->data, test->len);
561 +
562 + if (test->dirt == TEST_DIRT_WRITE) {
563 + src = test->buf_addr;
564 + dst = test->out_addr;
565 + direction = DMA_TO_DEVICE;
566 + } else {
567 + src = test->out_addr;
568 + dst = test->buf_addr;
569 + direction = DMA_FROM_DEVICE;
570 + }
571 +
572 + dma_dev = chan->device;
573 + dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
574 +
575 + dma_sync_single_for_device(&test->ep->dev, test->buf_addr,
576 + test->len, direction);
577 +
578 + set_freezable();
579 +
580 + getrawmonotonic(&start);
581 + while (!kthread_should_stop() && (i < test->loop)) {
582 + struct dma_async_tx_descriptor *dma_desc;
583 + dma_cookie_t dma_cookie = {0};
584 + unsigned long tmo;
585 + int status;
586 +
587 + init_completion(&test->done);
588 +
589 + dma_desc = dma_dev->device_prep_dma_memcpy(chan,
590 + dst, src,
591 + test->len,
592 + dma_flags);
593 + if (!dma_desc) {
594 + pr_err("DMA desc constr failed...\n");
595 + goto _err;
596 + }
597 +
598 + dma_desc->callback = ls_pcie_ep_test_dma_cb;
599 + dma_desc->callback_param = test;
600 + dma_cookie = dmaengine_submit(dma_desc);
601 +
602 + if (dma_submit_error(dma_cookie)) {
603 + pr_err("DMA submit error....\n");
604 + goto _err;
605 + }
606 +
607 + /* Trigger the transaction */
608 + dma_async_issue_pending(chan);
609 +
610 + tmo = wait_for_completion_timeout(&test->done,
611 + msecs_to_jiffies(5 * test->len));
612 + if (tmo == 0) {
613 + pr_err("Self-test copy timed out, disabling\n");
614 + goto _err;
615 + }
616 +
617 + status = dma_async_is_tx_complete(chan, dma_cookie,
618 + NULL, NULL);
619 + if (status != DMA_COMPLETE) {
620 + pr_err("got completion callback, but status is %s\n",
621 + status == DMA_ERROR ? "error" : "in progress");
622 + goto _err;
623 + }
624 +
625 + i++;
626 + }
627 +
628 + getrawmonotonic(&end);
629 + period = timespec_sub(end, start);
630 + test->result = test->len * 8ULL * i * 1000;
631 + do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
632 + dma_release_channel(chan);
633 +
634 + return 0;
635 +
636 +_err:
637 + dma_release_channel(chan);
638 + test->result = 0;
639 + return -EINVAL;
640 +}
641 +
642 +static int ls_pcie_ep_test_cpy(struct ls_ep_test *test)
643 +{
644 + void *dst, *src;
645 + struct timespec start, end, period;
646 + int i = 0;
647 +
648 + memset(test->buf, test->data, test->len);
649 +
650 + if (test->dirt == TEST_DIRT_WRITE) {
651 + dst = test->out;
652 + src = test->buf;
653 + } else {
654 + dst = test->buf;
655 + src = test->out;
656 + }
657 +
658 + getrawmonotonic(&start);
659 + while (!kthread_should_stop() && i < test->loop) {
660 + memcpy(dst, src, test->len);
661 + i++;
662 + }
663 + getrawmonotonic(&end);
664 +
665 + period = timespec_sub(end, start);
666 + test->result = test->len * 8ULL * i * 1000;
667 + do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
668 +
669 + return 0;
670 +}
671 +
672 +int ls_pcie_ep_test_thread(void *arg)
673 +{
674 + int ret;
675 +
676 + struct ls_ep_test *test = arg;
677 +
678 + if (test->type == TEST_TYPE_DMA)
679 + ret = ls_pcie_ep_test_dma(test);
680 + else
681 + ret = ls_pcie_ep_test_cpy(test);
682 +
683 + if (ret) {
684 + pr_err("\n%s \ttest failed\n",
685 + test->cmd);
686 + test->result = 0;
687 + } else
688 + pr_err("\n%s \tthroughput:%lluMbps\n",
689 + test->cmd, test->result);
690 +
691 + ls_pcie_ep_test_done(test);
692 +
693 + ls_pcie_ep_trigger_msi(test);
694 +
695 + do_exit(0);
696 +}
697 +
698 +static int ls_pcie_ep_free_test(struct ls_ep_dev *ep)
699 +{
700 + struct ls_ep_test *test = ep->driver_data;
701 +
702 + if (!test)
703 + return 0;
704 +
705 + if (test->status == TEST_BUSY) {
706 + kthread_stop(test->thread);
707 + dev_info(&ep->dev,
708 + "test is running please wait and run again\n");
709 + return -EBUSY;
710 + }
711 +
712 + if (test->buf)
713 + free_pages((unsigned long)test->buf,
714 + get_order(PCIE_BAR4_SIZE));
715 +
716 + if (test->cfg)
717 + free_pages((unsigned long)test->cfg,
718 + get_order(PCIE_BAR2_SIZE));
719 +
720 + if (test->out)
721 + iounmap(test->out);
722 +
723 + kfree(test);
724 + ep->driver_data = NULL;
725 +
726 + return 0;
727 +}
728 +
729 +static int ls_pcie_ep_init_test(struct ls_ep_dev *ep, u64 bus_addr)
730 +{
731 + struct ls_pcie *pcie = ep->pcie;
732 + struct ls_ep_test *test = ep->driver_data;
733 + int err;
734 +
735 + if (test) {
736 + dev_info(&ep->dev,
737 + "Please use 'free' to remove the exiting test\n");
738 + return -EBUSY;
739 + }
740 +
741 + test = kzalloc(sizeof(*test), GFP_KERNEL);
742 + if (!test)
743 + return -ENOMEM;
744 + ep->driver_data = test;
745 + test->ep = ep;
746 + spin_lock_init(&test->lock);
747 + test->status = TEST_IDLE;
748 +
749 + test->buf = dma_alloc_coherent(pcie->dev, get_order(PCIE_BAR4_SIZE),
750 + &test->buf_addr,
751 + GFP_KERNEL);
752 + if (!test->buf) {
753 + dev_info(&ep->dev, "failed to get mem for bar4\n");
754 + err = -ENOMEM;
755 + goto _err;
756 + }
757 +
758 + test->cfg = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
759 + get_order(PCIE_BAR2_SIZE));
760 + if (!test->cfg) {
761 + dev_info(&ep->dev, "failed to get mem for bar4\n");
762 + err = -ENOMEM;
763 + goto _err;
764 + }
765 + test->cfg_addr = virt_to_phys(test->cfg);
766 +
767 + test->out_addr = pcie->out_base;
768 + test->out = ioremap(test->out_addr, PCIE_BAR4_SIZE);
769 + if (!test->out) {
770 + dev_info(&ep->dev, "failed to map out\n");
771 + err = -ENOMEM;
772 + goto _err;
773 + }
774 +
775 + test->bus_addr = bus_addr;
776 +
777 + test->msi_addr = test->out_addr + PCIE_BAR4_SIZE;
778 + test->msi = ioremap(test->msi_addr, PCIE_MSI_OB_SIZE);
779 + if (!test->msi)
780 + dev_info(&ep->dev, "failed to map MSI outbound region\n");
781 +
782 + test->msi_msg_addr = ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF) |
783 + (((u64)ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF + 4)) << 32);
784 + test->msi_msg_data = ioread16(pcie->dbi + PCIE_MSI_MSG_DATA_OFF);
785 +
786 + ls_pcie_ep_dev_cfg_enable(ep);
787 +
788 + /* outbound iATU for memory */
789 + ls_pcie_iatu_outbound_set(pcie, 0, PCIE_ATU_TYPE_MEM,
790 + test->out_addr, bus_addr, PCIE_BAR4_SIZE);
791 + /* outbound iATU for MSI */
792 + ls_pcie_iatu_outbound_set(pcie, 1, PCIE_ATU_TYPE_MEM,
793 + test->msi_addr, test->msi_msg_addr,
794 + PCIE_MSI_OB_SIZE);
795 +
796 + /* ATU 0 : INBOUND : map BAR0 */
797 + ls_pcie_iatu_inbound_set(pcie, 0, 0, test->cfg_addr);
798 + /* ATU 2 : INBOUND : map BAR2 */
799 + ls_pcie_iatu_inbound_set(pcie, 2, 2, test->cfg_addr);
800 + /* ATU 3 : INBOUND : map BAR4 */
801 + ls_pcie_iatu_inbound_set(pcie, 3, 4, test->buf_addr);
802 +
803 + return 0;
804 +
805 +_err:
806 + ls_pcie_ep_free_test(ep);
807 + return err;
808 +}
809 +
810 +static int ls_pcie_ep_start_test(struct ls_ep_dev *ep, char *cmd)
811 +{
812 + struct ls_ep_test *test = ep->driver_data;
813 + enum test_type type;
814 + enum test_dirt dirt;
815 + u32 cnt, len, loop;
816 + unsigned int data;
817 + char dirt_str[2];
818 + int ret;
819 +
820 + if (strncmp(cmd, "dma", 3) == 0)
821 + type = TEST_TYPE_DMA;
822 + else
823 + type = TEST_TYPE_MEMCPY;
824 +
825 + cnt = sscanf(&cmd[4], "%1s %u %u %x", dirt_str, &len, &loop, &data);
826 + if (cnt != 4) {
827 + dev_info(&ep->dev, "format error %s", cmd);
828 + dev_info(&ep->dev, "dma/cpy <r/w> <packet_size> <loop> <data>\n");
829 + return -EINVAL;
830 + }
831 +
832 + if (strncmp(dirt_str, "r", 1) == 0)
833 + dirt = TEST_DIRT_READ;
834 + else
835 + dirt = TEST_DIRT_WRITE;
836 +
837 + if (len > PCIE_BAR4_SIZE) {
838 + dev_err(&ep->dev, "max len is %d", PCIE_BAR4_SIZE);
839 + return -EINVAL;
840 + }
841 +
842 + if (!test) {
843 + dev_err(&ep->dev, "Please first run init command\n");
844 + return -EINVAL;
845 + }
846 +
847 + if (ls_pcie_ep_test_try_run(test)) {
848 + dev_err(&ep->dev, "There is already a test running\n");
849 + return -EINVAL;
850 + }
851 +
852 + test->len = len;
853 + test->loop = loop;
854 + test->type = type;
855 + test->data = (char)data;
856 + test->dirt = dirt;
857 + strcpy(test->cmd, cmd);
858 + test->thread = kthread_run(ls_pcie_ep_test_thread, test,
859 + "pcie ep test");
860 + if (IS_ERR(test->thread)) {
861 + dev_err(&ep->dev, "fork failed for pcie ep test\n");
862 + ls_pcie_ep_test_done(test);
863 + ret = PTR_ERR(test->thread);
864 + }
865 +
866 + return ret;
867 +}
868 +
869 +
870 +/**
871 + * ls_pcie_reg_ops_read - read for regs data
872 + * @filp: the opened file
873 + * @buffer: where to write the data for the user to read
874 + * @count: the size of the user's buffer
875 + * @ppos: file position offset
876 + **/
877 +static ssize_t ls_pcie_ep_dbg_regs_read(struct file *filp, char __user *buffer,
878 + size_t count, loff_t *ppos)
879 +{
880 + struct ls_ep_dev *ep = filp->private_data;
881 + struct ls_pcie *pcie = ep->pcie;
882 + char *buf;
883 + int desc = 0, i, len;
884 +
885 + buf = kmalloc(4 * 1024, GFP_KERNEL);
886 + if (!buf)
887 + return -ENOMEM;
888 +
889 + ls_pcie_ep_dev_cfg_enable(ep);
890 +
891 + desc += sprintf(buf + desc, "%s", "reg info:");
892 + for (i = 0; i < 0x200; i += 4) {
893 + if (i % 16 == 0)
894 + desc += sprintf(buf + desc, "\n%08x:", i);
895 + desc += sprintf(buf + desc, " %08x", readl(pcie->dbi + i));
896 + }
897 +
898 + desc += sprintf(buf + desc, "\n%s", "outbound iATU info:\n");
899 + for (i = 0; i < 6; i++) {
900 + writel(PCIE_ATU_REGION_OUTBOUND | i,
901 + pcie->dbi + PCIE_ATU_VIEWPORT);
902 + desc += sprintf(buf + desc, "iATU%d", i);
903 + desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
904 + readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
905 + desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
906 + readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
907 + desc += sprintf(buf + desc, "\tLOWER BUS 0x%08x\n",
908 + readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
909 + desc += sprintf(buf + desc, "\tUPPER BUS 0x%08x\n",
910 + readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
911 + desc += sprintf(buf + desc, "\tLIMIT 0x%08x\n",
912 + readl(pcie->dbi + PCIE_ATU_LIMIT));
913 + desc += sprintf(buf + desc, "\tCR1 0x%08x\n",
914 + readl(pcie->dbi + PCIE_ATU_CR1));
915 + desc += sprintf(buf + desc, "\tCR2 0x%08x\n",
916 + readl(pcie->dbi + PCIE_ATU_CR2));
917 + }
918 +
919 + desc += sprintf(buf + desc, "\n%s", "inbound iATU info:\n");
920 + for (i = 0; i < 6; i++) {
921 + writel(PCIE_ATU_REGION_INBOUND | i,
922 + pcie->dbi + PCIE_ATU_VIEWPORT);
923 + desc += sprintf(buf + desc, "iATU%d", i);
924 + desc += sprintf(buf + desc, "\tLOWER BUS 0x%08x\n",
925 + readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
926 + desc += sprintf(buf + desc, "\tUPPER BUSs 0x%08x\n",
927 + readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
928 + desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
929 + readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
930 + desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
931 + readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
932 + desc += sprintf(buf + desc, "\tLIMIT 0x%08x\n",
933 + readl(pcie->dbi + PCIE_ATU_LIMIT));
934 + desc += sprintf(buf + desc, "\tCR1 0x%08x\n",
935 + readl(pcie->dbi + PCIE_ATU_CR1));
936 + desc += sprintf(buf + desc, "\tCR2 0x%08x\n",
937 + readl(pcie->dbi + PCIE_ATU_CR2));
938 + }
939 +
940 + len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
941 + kfree(buf);
942 +
943 + return len;
944 +}
945 +
946 +/**
947 + * ls_pcie_ep_dbg_regs_write - write into regs datum
948 + * @filp: the opened file
949 + * @buffer: where to find the user's data
950 + * @count: the length of the user's data
951 + * @ppos: file position offset
952 + **/
953 +static ssize_t ls_pcie_ep_dbg_regs_write(struct file *filp,
954 + const char __user *buffer,
955 + size_t count, loff_t *ppos)
956 +{
957 + struct ls_ep_dev *ep = filp->private_data;
958 + struct ls_pcie *pcie = ep->pcie;
959 + char buf[256];
960 +
961 + if (count >= sizeof(buf))
962 + return -ENOSPC;
963 +
964 + memset(buf, 0, sizeof(buf));
965 +
966 + if (copy_from_user(buf, buffer, count))
967 + return -EFAULT;
968 +
969 + ls_pcie_ep_dev_cfg_enable(ep);
970 +
971 + if (strncmp(buf, "reg", 3) == 0) {
972 + u32 reg, value;
973 + int cnt;
974 +
975 + cnt = sscanf(&buf[3], "%x %x", &reg, &value);
976 + if (cnt == 2) {
977 + writel(value, pcie->dbi + reg);
978 + value = readl(pcie->dbi + reg);
979 + dev_info(&ep->dev, "reg 0x%08x: 0x%08x\n",
980 + reg, value);
981 + } else {
982 + dev_info(&ep->dev, "reg <reg> <value>\n");
983 + }
984 + } else if (strncmp(buf, "atu", 3) == 0) {
985 + /* to do */
986 + dev_info(&ep->dev, " Not support atu command\n");
987 + } else {
988 + dev_info(&ep->dev, "Unknown command %s\n", buf);
989 + dev_info(&ep->dev, "Available commands:\n");
990 + dev_info(&ep->dev, " reg <reg> <value>\n");
991 + }
992 +
993 + return count;
994 +}
995 +
996 +static const struct file_operations ls_pcie_ep_dbg_regs_fops = {
997 + .owner = THIS_MODULE,
998 + .open = simple_open,
999 + .read = ls_pcie_ep_dbg_regs_read,
1000 + .write = ls_pcie_ep_dbg_regs_write,
1001 +};
1002 +
1003 +static ssize_t ls_pcie_ep_dbg_test_read(struct file *filp,
1004 + char __user *buffer,
1005 + size_t count, loff_t *ppos)
1006 +{
1007 + struct ls_ep_dev *ep = filp->private_data;
1008 + struct ls_ep_test *test = ep->driver_data;
1009 + char buf[512];
1010 + int desc = 0, len;
1011 +
1012 + if (!test) {
1013 + dev_info(&ep->dev, " there is NO test\n");
1014 + return 0;
1015 + }
1016 +
1017 + if (test->status != TEST_IDLE) {
1018 + dev_info(&ep->dev, "test %s is running\n", test->cmd);
1019 + return 0;
1020 + }
1021 +
1022 + desc = sprintf(buf, "MSI ADDR:0x%llx MSI DATA:0x%x\n",
1023 + test->msi_msg_addr, test->msi_msg_data);
1024 +
1025 + desc += sprintf(buf + desc, "%s throughput:%lluMbps\n",
1026 + test->cmd, test->result);
1027 +
1028 + len = simple_read_from_buffer(buffer, count, ppos,
1029 + buf, desc);
1030 +
1031 + return len;
1032 +}
1033 +
1034 +static ssize_t ls_pcie_ep_dbg_test_write(struct file *filp,
1035 + const char __user *buffer,
1036 + size_t count, loff_t *ppos)
1037 +{
1038 + struct ls_ep_dev *ep = filp->private_data;
1039 + char buf[256];
1040 +
1041 + if (count >= sizeof(buf))
1042 + return -ENOSPC;
1043 +
1044 + memset(buf, 0, sizeof(buf));
1045 +
1046 + if (copy_from_user(buf, buffer, count))
1047 + return -EFAULT;
1048 +
1049 + if (strncmp(buf, "init", 4) == 0) {
1050 + int i = 4;
1051 + u64 bus_addr;
1052 +
1053 + while (buf[i] == ' ')
1054 + i++;
1055 +
1056 + if (kstrtou64(&buf[i], 0, &bus_addr))
1057 + dev_info(&ep->dev, "command: init <bus_addr>\n");
1058 + else {
1059 + if (ls_pcie_ep_init_test(ep, bus_addr))
1060 + dev_info(&ep->dev, "failed to init test\n");
1061 + }
1062 + } else if (strncmp(buf, "free", 4) == 0)
1063 + ls_pcie_ep_free_test(ep);
1064 + else if (strncmp(buf, "dma", 3) == 0 ||
1065 + strncmp(buf, "cpy", 3) == 0)
1066 + ls_pcie_ep_start_test(ep, buf);
1067 + else {
1068 + dev_info(&ep->dev, "Unknown command: %s\n", buf);
1069 + dev_info(&ep->dev, "Available commands:\n");
1070 + dev_info(&ep->dev, "\tinit <bus_addr>\n");
1071 + dev_info(&ep->dev, "\t<dma/cpy> <r/w> <packet_size> <loop>\n");
1072 + dev_info(&ep->dev, "\tfree\n");
1073 + }
1074 +
1075 + return count;
1076 +}
1077 +
1078 +static const struct file_operations ls_pcie_ep_dbg_test_fops = {
1079 + .owner = THIS_MODULE,
1080 + .open = simple_open,
1081 + .read = ls_pcie_ep_dbg_test_read,
1082 + .write = ls_pcie_ep_dbg_test_write,
1083 +};
1084 +
1085 +static ssize_t ls_pcie_ep_dbg_dump_read(struct file *filp,
1086 + char __user *buffer,
1087 + size_t count, loff_t *ppos)
1088 +{
1089 + struct ls_ep_dev *ep = filp->private_data;
1090 + struct ls_ep_test *test = ep->driver_data;
1091 + char *buf;
1092 + int desc = 0, i, len;
1093 +
1094 + buf = kmalloc(4 * 1024, GFP_KERNEL);
1095 + if (!buf)
1096 + return -ENOMEM;
1097 +
1098 + if (!test) {
1099 + dev_info(&ep->dev, " there is NO test\n");
1100 + kfree(buf);
1101 + return 0;
1102 + }
1103 +
1104 + desc += sprintf(buf + desc, "%s", "dump info:");
1105 + for (i = 0; i < 256; i += 4) {
1106 + if (i % 16 == 0)
1107 + desc += sprintf(buf + desc, "\n%08x:", i);
1108 + desc += sprintf(buf + desc, " %08x", readl(test->buf + i));
1109 + }
1110 +
1111 + desc += sprintf(buf + desc, "\n");
1112 + len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
1113 +
1114 + kfree(buf);
1115 +
1116 + return len;
1117 +}
1118 +
1119 +static const struct file_operations ls_pcie_ep_dbg_dump_fops = {
1120 + .owner = THIS_MODULE,
1121 + .open = simple_open,
1122 + .read = ls_pcie_ep_dbg_dump_read,
1123 +};
1124 +
1125 +static int ls_pcie_ep_dev_dbgfs_init(struct ls_ep_dev *ep)
1126 +{
1127 + struct ls_pcie *pcie = ep->pcie;
1128 + struct dentry *pfile;
1129 +
1130 + ls_pcie_ep_dev_cfg_enable(ep);
1131 +
1132 + ep->dir = debugfs_create_dir(dev_name(&ep->dev), pcie->dir);
1133 + if (!ep->dir)
1134 + return -ENOMEM;
1135 +
1136 + pfile = debugfs_create_file("regs", 0600, ep->dir, ep,
1137 + &ls_pcie_ep_dbg_regs_fops);
1138 + if (!pfile)
1139 + dev_info(&ep->dev, "debugfs regs for failed\n");
1140 +
1141 + pfile = debugfs_create_file("test", 0600, ep->dir, ep,
1142 + &ls_pcie_ep_dbg_test_fops);
1143 + if (!pfile)
1144 + dev_info(&ep->dev, "debugfs test for failed\n");
1145 +
1146 + pfile = debugfs_create_file("dump", 0600, ep->dir, ep,
1147 + &ls_pcie_ep_dbg_dump_fops);
1148 + if (!pfile)
1149 + dev_info(&ep->dev, "debugfs dump for failed\n");
1150 +
1151 + return 0;
1152 +}
1153 +
1154 +int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie)
1155 +{
1156 + struct ls_ep_dev *ep;
1157 +
1158 + pcie->dir = debugfs_create_dir(dev_name(pcie->dev), NULL);
1159 + if (!pcie->dir)
1160 + return -ENOMEM;
1161 +
1162 + list_for_each_entry(ep, &pcie->ep_list, node)
1163 + ls_pcie_ep_dev_dbgfs_init(ep);
1164 +
1165 + return 0;
1166 +}
1167 +
1168 +int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie)
1169 +{
1170 + debugfs_remove_recursive(pcie->dir);
1171 + return 0;
1172 +}
1173 +
1174 +MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
1175 +MODULE_DESCRIPTION("Freescale Layerscape PCIe EP controller driver");
1176 +MODULE_LICENSE("GPL v2");
1177 --- /dev/null
1178 +++ b/drivers/pci/host/pci-layerscape-ep.c
1179 @@ -0,0 +1,309 @@
1180 +/*
1181 + * PCIe Endpoint driver for Freescale Layerscape SoCs
1182 + *
1183 + * Copyright (C) 2015 Freescale Semiconductor.
1184 + *
1185 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
1186 + *
1187 + * This program is free software; you can redistribute it and/or modify
1188 + * it under the terms of the GNU General Public License version 2 as
1189 + * published by the Free Software Foundation.
1190 + */
1191 +
1192 +#include <linux/kernel.h>
1193 +#include <linux/delay.h>
1194 +#include <linux/interrupt.h>
1195 +#include <linux/module.h>
1196 +#include <linux/of_pci.h>
1197 +#include <linux/of_platform.h>
1198 +#include <linux/of_irq.h>
1199 +#include <linux/of_address.h>
1200 +#include <linux/pci.h>
1201 +#include <linux/platform_device.h>
1202 +#include <linux/resource.h>
1203 +#include <linux/debugfs.h>
1204 +#include <linux/time.h>
1205 +#include <linux/uaccess.h>
1206 +
1207 +#include "pci-layerscape-ep.h"
1208 +
1209 +struct ls_ep_dev *
1210 +ls_pci_ep_find(struct ls_pcie *pcie, int dev_id)
1211 +{
1212 + struct ls_ep_dev *ep;
1213 +
1214 + list_for_each_entry(ep, &pcie->ep_list, node) {
1215 + if (ep->dev_id == dev_id)
1216 + return ep;
1217 + }
1218 +
1219 + return NULL;
1220 +}
1221 +
1222 +static void ls_pcie_try_cfg2(struct ls_pcie *pcie, int pf, int vf)
1223 +{
1224 + if (pcie->sriov)
1225 + writel(PCIE_LCTRL0_VAL(pf, vf),
1226 + pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
1227 +}
1228 +
1229 +static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
1230 +{
1231 + u32 header_type = 0;
1232 +
1233 + header_type = readl(pcie->dbi + (PCI_HEADER_TYPE & ~0x3));
1234 + header_type = (header_type >> 16) & 0x7f;
1235 +
1236 + return header_type == PCI_HEADER_TYPE_BRIDGE;
1237 +}
1238 +
1239 +void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
1240 + u64 cpu_addr, u64 pci_addr, u32 size)
1241 +{
1242 + writel(PCIE_ATU_REGION_OUTBOUND | idx,
1243 + pcie->dbi + PCIE_ATU_VIEWPORT);
1244 + writel(lower_32_bits(cpu_addr),
1245 + pcie->dbi + PCIE_ATU_LOWER_BASE);
1246 + writel(upper_32_bits(cpu_addr),
1247 + pcie->dbi + PCIE_ATU_UPPER_BASE);
1248 + writel(lower_32_bits(cpu_addr + size - 1),
1249 + pcie->dbi + PCIE_ATU_LIMIT);
1250 + writel(lower_32_bits(pci_addr),
1251 + pcie->dbi + PCIE_ATU_LOWER_TARGET);
1252 + writel(upper_32_bits(pci_addr),
1253 + pcie->dbi + PCIE_ATU_UPPER_TARGET);
1254 + writel(type, pcie->dbi + PCIE_ATU_CR1);
1255 + writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
1256 +}
1257 +
1258 +/* Use bar match mode and MEM type as default */
1259 +void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
1260 + int bar, u64 phys)
1261 +{
1262 + writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
1263 + writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
1264 + writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
1265 + writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
1266 + writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
1267 + PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
1268 +}
1269 +
1270 +void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep)
1271 +{
1272 + ls_pcie_try_cfg2(ep->pcie, ep->pf_idx, ep->vf_idx);
1273 +}
1274 +
1275 +void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
1276 +{
1277 + if (size < 4 * 1024)
1278 + return;
1279 +
1280 + switch (bar) {
1281 + case 0:
1282 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
1283 + break;
1284 + case 1:
1285 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
1286 + break;
1287 + case 2:
1288 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
1289 + writel(0, bar_base + PCI_BASE_ADDRESS_3);
1290 + break;
1291 + case 4:
1292 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
1293 + writel(0, bar_base + PCI_BASE_ADDRESS_5);
1294 + break;
1295 + default:
1296 + break;
1297 + }
1298 +}
1299 +
1300 +void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size)
1301 +{
1302 + struct ls_pcie *pcie = ep->pcie;
1303 + void *bar_base;
1304 +
1305 + if (size < 4 * 1024)
1306 + return;
1307 +
1308 + if (pcie->sriov)
1309 + bar_base = pcie->dbi;
1310 + else
1311 + bar_base = pcie->dbi + PCIE_NO_SRIOV_BAR_BASE;
1312 +
1313 + ls_pcie_ep_dev_cfg_enable(ep);
1314 + ls_pcie_ep_setup_bar(bar_base, bar, size);
1315 +}
1316 +
1317 +static int ls_pcie_ep_dev_init(struct ls_pcie *pcie, int pf_idx, int vf_idx)
1318 +{
1319 + struct ls_ep_dev *ep;
1320 +
1321 + ep = devm_kzalloc(pcie->dev, sizeof(*ep), GFP_KERNEL);
1322 + if (!ep)
1323 + return -ENOMEM;
1324 +
1325 + ep->pcie = pcie;
1326 + ep->pf_idx = pf_idx;
1327 + ep->vf_idx = vf_idx;
1328 + if (vf_idx)
1329 + ep->dev_id = pf_idx + 4 + 4 * (vf_idx - 1);
1330 + else
1331 + ep->dev_id = pf_idx;
1332 +
1333 + if (ep->vf_idx)
1334 + dev_set_name(&ep->dev, "pf%d-vf%d",
1335 + ep->pf_idx,
1336 + ep->vf_idx);
1337 + else
1338 + dev_set_name(&ep->dev, "pf%d",
1339 + ep->pf_idx);
1340 +
1341 + list_add_tail(&ep->node, &pcie->ep_list);
1342 +
1343 + return 0;
1344 +}
1345 +
1346 +static int ls_pcie_ep_init(struct ls_pcie *pcie)
1347 +{
1348 + u32 sriov_header;
1349 + int pf, vf, i, j;
1350 +
1351 + sriov_header = readl(pcie->dbi + PCIE_SRIOV_POS);
1352 +
1353 + if (PCI_EXT_CAP_ID(sriov_header) == PCI_EXT_CAP_ID_SRIOV) {
1354 + pcie->sriov = PCIE_SRIOV_POS;
1355 + pf = PCIE_PF_NUM;
1356 + vf = PCIE_VF_NUM;
1357 + } else {
1358 + pcie->sriov = 0;
1359 + pf = 1;
1360 + vf = 0;
1361 + }
1362 +
1363 + for (i = 0; i < pf; i++) {
1364 + for (j = 0; j <= vf; j++)
1365 + ls_pcie_ep_dev_init(pcie, i, j);
1366 + }
1367 +
1368 + return 0;
1369 +}
1370 +
1371 +static struct ls_pcie_ep_drvdata ls1043_drvdata = {
1372 + .lut_offset = 0x10000,
1373 + .ltssm_shift = 24,
1374 + .lut_dbg = 0x7fc,
1375 +};
1376 +
1377 +static struct ls_pcie_ep_drvdata ls1046_drvdata = {
1378 + .lut_offset = 0x80000,
1379 + .ltssm_shift = 24,
1380 + .lut_dbg = 0x407fc,
1381 +};
1382 +
1383 +static struct ls_pcie_ep_drvdata ls2080_drvdata = {
1384 + .lut_offset = 0x80000,
1385 + .ltssm_shift = 0,
1386 + .lut_dbg = 0x7fc,
1387 +};
1388 +
1389 +static const struct of_device_id ls_pcie_ep_of_match[] = {
1390 + { .compatible = "fsl,ls1021a-pcie", },
1391 + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1392 + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1393 + { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
1394 + { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
1395 + { },
1396 +};
1397 +MODULE_DEVICE_TABLE(of, ls_pcie_ep_of_match);
1398 +
1399 +static int ls_pcie_ep_probe(struct platform_device *pdev)
1400 +{
1401 + struct ls_pcie *pcie;
1402 + struct resource *dbi_base, *cfg_res;
1403 + const struct of_device_id *match;
1404 + int ret;
1405 +
1406 + match = of_match_device(ls_pcie_ep_of_match, &pdev->dev);
1407 + if (!match)
1408 + return -ENODEV;
1409 +
1410 + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1411 + if (!pcie)
1412 + return -ENOMEM;
1413 +
1414 + pcie->dev = &pdev->dev;
1415 + INIT_LIST_HEAD(&pcie->ep_list);
1416 +
1417 + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1418 + pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
1419 + if (IS_ERR(pcie->dbi)) {
1420 + dev_err(&pdev->dev, "missing *regs* space\n");
1421 + return PTR_ERR(pcie->dbi);
1422 + }
1423 +
1424 + pcie->drvdata = match->data;
1425 + pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
1426 +
1427 + if (ls_pcie_is_bridge(pcie))
1428 + return -ENODEV;
1429 +
1430 + dev_info(pcie->dev, "in EP mode\n");
1431 +
1432 + cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
1433 + if (cfg_res)
1434 + pcie->out_base = cfg_res->start;
1435 + else {
1436 + dev_err(&pdev->dev, "missing *config* space\n");
1437 + return -ENODEV;
1438 + }
1439 +
1440 + ret = ls_pcie_ep_init(pcie);
1441 + if (ret)
1442 + return ret;
1443 +
1444 + ls_pcie_ep_dbgfs_init(pcie);
1445 +
1446 + platform_set_drvdata(pdev, pcie);
1447 +
1448 + return 0;
1449 +}
1450 +
1451 +static int ls_pcie_ep_dev_remove(struct ls_ep_dev *ep)
1452 +{
1453 + list_del(&ep->node);
1454 +
1455 + return 0;
1456 +}
1457 +
1458 +static int ls_pcie_ep_remove(struct platform_device *pdev)
1459 +{
1460 + struct ls_pcie *pcie = platform_get_drvdata(pdev);
1461 + struct ls_ep_dev *ep, *tmp;
1462 +
1463 + if (!pcie)
1464 + return 0;
1465 +
1466 + ls_pcie_ep_dbgfs_remove(pcie);
1467 +
1468 + list_for_each_entry_safe(ep, tmp, &pcie->ep_list, node)
1469 + ls_pcie_ep_dev_remove(ep);
1470 +
1471 + return 0;
1472 +}
1473 +
1474 +static struct platform_driver ls_pcie_ep_driver = {
1475 + .driver = {
1476 + .name = "ls-pcie-ep",
1477 + .owner = THIS_MODULE,
1478 + .of_match_table = ls_pcie_ep_of_match,
1479 + },
1480 + .probe = ls_pcie_ep_probe,
1481 + .remove = ls_pcie_ep_remove,
1482 +};
1483 +
1484 +module_platform_driver(ls_pcie_ep_driver);
1485 +
1486 +MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
1487 +MODULE_DESCRIPTION("Freescale Layerscape PCIe EP driver");
1488 +MODULE_LICENSE("GPL v2");
1489 --- /dev/null
1490 +++ b/drivers/pci/host/pci-layerscape-ep.h
1491 @@ -0,0 +1,115 @@
1492 +/*
1493 + * PCIe Endpoint driver for Freescale Layerscape SoCs
1494 + *
1495 + * Copyright (C) 2015 Freescale Semiconductor.
1496 + *
1497 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
1498 + *
1499 + * This program is free software; you can redistribute it and/or modify
1500 + * it under the terms of the GNU General Public License version 2 as
1501 + * published by the Free Software Foundation.
1502 + */
1503 +
1504 +
1505 +#ifndef _PCIE_LAYERSCAPE_EP_H
1506 +#define _PCIE_LAYERSCAPE_EP_H
1507 +
1508 +#include <linux/device.h>
1509 +
1510 +/* Synopsis specific PCIE configuration registers */
1511 +#define PCIE_ATU_VIEWPORT 0x900
1512 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
1513 +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
1514 +#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
1515 +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
1516 +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
1517 +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
1518 +#define PCIE_ATU_CR1 0x904
1519 +#define PCIE_ATU_TYPE_MEM (0x0 << 0)
1520 +#define PCIE_ATU_TYPE_IO (0x2 << 0)
1521 +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
1522 +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
1523 +#define PCIE_ATU_CR2 0x908
1524 +#define PCIE_ATU_ENABLE (0x1 << 31)
1525 +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
1526 +#define PCIE_ATU_LOWER_BASE 0x90C
1527 +#define PCIE_ATU_UPPER_BASE 0x910
1528 +#define PCIE_ATU_LIMIT 0x914
1529 +#define PCIE_ATU_LOWER_TARGET 0x918
1530 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
1531 +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
1532 +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
1533 +#define PCIE_ATU_UPPER_TARGET 0x91C
1534 +
1535 +/* PEX internal configuration registers */
1536 +#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
1537 +
1538 +/* PEX LUT registers */
1539 +#define PCIE_LUT_BASE 0x80000
1540 +#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug register */
1541 +
1542 +#define PCIE_LUT_LCTRL0 0x7F8
1543 +
1544 +#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
1545 +#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
1546 +#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
1547 +#define PCIE_LCTRL0_PF(pf) ((pf) << 16)
1548 +#define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
1549 +#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
1550 + PCIE_LCTRL0_VF(vf) | \
1551 + ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
1552 + PCIE_LCTRL0_CFG2_ENABLE)
1553 +
1554 +#define PCIE_NO_SRIOV_BAR_BASE 0x1000
1555 +
1556 +#define PCIE_SRIOV_POS 0x178
1557 +#define PCIE_PF_NUM 2
1558 +#define PCIE_VF_NUM 64
1559 +
1560 +struct ls_pcie_ep_drvdata {
1561 + u32 lut_offset;
1562 + u32 ltssm_shift;
1563 + u32 lut_dbg;
1564 +};
1565 +
1566 +struct ls_pcie {
1567 + struct list_head ep_list;
1568 + struct device *dev;
1569 + struct dentry *dir;
1570 + const struct ls_pcie_ep_drvdata *drvdata;
1571 + void __iomem *dbi;
1572 + void __iomem *lut;
1573 + phys_addr_t out_base;
1574 + int sriov;
1575 + int index;
1576 +};
1577 +
1578 +struct ls_ep_dev {
1579 + struct list_head node;
1580 + struct ls_pcie *pcie;
1581 + struct device dev;
1582 + struct dentry *dir;
1583 + int pf_idx;
1584 + int vf_idx;
1585 + int dev_id;
1586 + void *driver_data;
1587 +};
1588 +
1589 +struct ls_ep_dev *ls_pci_ep_find(struct ls_pcie *pcie, int dev_id);
1590 +
1591 +void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
1592 + u64 cpu_addr, u64 pci_addr, u32 size);
1593 +
1594 +/* Use bar match mode and MEM type as default */
1595 +void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
1596 + int bar, u64 phys);
1597 +
1598 +void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size);
1599 +
1600 +
1601 +void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep);
1602 +
1603 +int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie);
1604 +int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie);
1605 +
1606 +#endif /* _PCIE_LAYERSCAPE_EP_H */
1607 --- a/drivers/pci/host/pci-layerscape.c
1608 +++ b/drivers/pci/host/pci-layerscape.c
1609 @@ -35,12 +35,14 @@
1610 #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
1611 #define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
1612
1613 -/* PEX LUT registers */
1614 -#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
1615 +#define PCIE_IATU_NUM 6
1616 +
1617 +static void ls_pcie_host_init(struct pcie_port *pp);
1618
1619 struct ls_pcie_drvdata {
1620 u32 lut_offset;
1621 u32 ltssm_shift;
1622 + u32 lut_dbg;
1623 struct pcie_host_ops *ops;
1624 };
1625
1626 @@ -86,6 +88,14 @@ static void ls_pcie_drop_msg_tlp(struct
1627 iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
1628 }
1629
1630 +static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
1631 +{
1632 + int i;
1633 +
1634 + for (i = 0; i < PCIE_IATU_NUM; i++)
1635 + dw_pcie_disable_outbound_atu(&pcie->pp, i);
1636 +}
1637 +
1638 static int ls1021_pcie_link_up(struct pcie_port *pp)
1639 {
1640 u32 state;
1641 @@ -134,7 +144,7 @@ static int ls_pcie_link_up(struct pcie_p
1642 struct ls_pcie *pcie = to_ls_pcie(pp);
1643 u32 state;
1644
1645 - state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
1646 + state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
1647 pcie->drvdata->ltssm_shift) &
1648 LTSSM_STATE_MASK;
1649
1650 @@ -153,6 +163,9 @@ static void ls_pcie_host_init(struct pci
1651 ls_pcie_clear_multifunction(pcie);
1652 ls_pcie_drop_msg_tlp(pcie);
1653 iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
1654 +
1655 + ls_pcie_disable_outbound_atus(pcie);
1656 + dw_pcie_setup_rc(pp);
1657 }
1658
1659 static int ls_pcie_msi_host_init(struct pcie_port *pp,
1660 @@ -196,20 +209,39 @@ static struct ls_pcie_drvdata ls1021_drv
1661 static struct ls_pcie_drvdata ls1043_drvdata = {
1662 .lut_offset = 0x10000,
1663 .ltssm_shift = 24,
1664 + .lut_dbg = 0x7fc,
1665 + .ops = &ls_pcie_host_ops,
1666 +};
1667 +
1668 +static struct ls_pcie_drvdata ls1046_drvdata = {
1669 + .lut_offset = 0x80000,
1670 + .ltssm_shift = 24,
1671 + .lut_dbg = 0x407fc,
1672 .ops = &ls_pcie_host_ops,
1673 };
1674
1675 static struct ls_pcie_drvdata ls2080_drvdata = {
1676 .lut_offset = 0x80000,
1677 .ltssm_shift = 0,
1678 + .lut_dbg = 0x7fc,
1679 + .ops = &ls_pcie_host_ops,
1680 +};
1681 +
1682 +static struct ls_pcie_drvdata ls2088_drvdata = {
1683 + .lut_offset = 0x80000,
1684 + .ltssm_shift = 0,
1685 + .lut_dbg = 0x407fc,
1686 .ops = &ls_pcie_host_ops,
1687 };
1688
1689 static const struct of_device_id ls_pcie_of_match[] = {
1690 + { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
1691 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
1692 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1693 + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1694 { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
1695 { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
1696 + { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
1697 { },
1698 };
1699
1700 --- a/drivers/pci/host/pcie-designware.c
1701 +++ b/drivers/pci/host/pcie-designware.c
1702 @@ -478,6 +478,12 @@ int dw_pcie_wait_for_link(struct pcie_po
1703 return -ETIMEDOUT;
1704 }
1705
1706 +void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index)
1707 +{
1708 + dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index);
1709 + dw_pcie_writel_rc(pp, PCIE_ATU_CR2, 0);
1710 +}
1711 +
1712 int dw_pcie_link_up(struct pcie_port *pp)
1713 {
1714 u32 val;
1715 --- a/drivers/pci/host/pcie-designware.h
1716 +++ b/drivers/pci/host/pcie-designware.h
1717 @@ -82,5 +82,6 @@ int dw_pcie_wait_for_link(struct pcie_po
1718 int dw_pcie_link_up(struct pcie_port *pp);
1719 void dw_pcie_setup_rc(struct pcie_port *pp);
1720 int dw_pcie_host_init(struct pcie_port *pp);
1721 +void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index);
1722
1723 #endif /* _PCIE_DESIGNWARE_H */
1724 --- a/drivers/pci/pcie/portdrv_core.c
1725 +++ b/drivers/pci/pcie/portdrv_core.c
1726 @@ -44,52 +44,30 @@ static void release_pcie_device(struct d
1727 }
1728
1729 /**
1730 - * pcie_port_msix_add_entry - add entry to given array of MSI-X entries
1731 - * @entries: Array of MSI-X entries
1732 - * @new_entry: Index of the entry to add to the array
1733 - * @nr_entries: Number of entries already in the array
1734 + * pcibios_check_service_irqs - check irqs in the device tree
1735 + * @dev: PCI Express port to handle
1736 + * @irqs: Array of irqs to populate
1737 + * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1738 + *
1739 + * Return value: 0 means no service irqs in the device tree
1740 *
1741 - * Return value: Position of the added entry in the array
1742 */
1743 -static int pcie_port_msix_add_entry(
1744 - struct msix_entry *entries, int new_entry, int nr_entries)
1745 +int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1746 {
1747 - int j;
1748 -
1749 - for (j = 0; j < nr_entries; j++)
1750 - if (entries[j].entry == new_entry)
1751 - return j;
1752 -
1753 - entries[j].entry = new_entry;
1754 - return j;
1755 + return 0;
1756 }
1757
1758 /**
1759 * pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port
1760 * @dev: PCI Express port to handle
1761 - * @vectors: Array of interrupt vectors to populate
1762 + * @irqs: Array of interrupt vectors to populate
1763 * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1764 *
1765 * Return value: 0 on success, error code on failure
1766 */
1767 -static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1768 +static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask)
1769 {
1770 - struct msix_entry *msix_entries;
1771 - int idx[PCIE_PORT_DEVICE_MAXSERVICES];
1772 - int nr_entries, status, pos, i, nvec;
1773 - u16 reg16;
1774 - u32 reg32;
1775 -
1776 - nr_entries = pci_msix_vec_count(dev);
1777 - if (nr_entries < 0)
1778 - return nr_entries;
1779 - BUG_ON(!nr_entries);
1780 - if (nr_entries > PCIE_PORT_MAX_MSIX_ENTRIES)
1781 - nr_entries = PCIE_PORT_MAX_MSIX_ENTRIES;
1782 -
1783 - msix_entries = kzalloc(sizeof(*msix_entries) * nr_entries, GFP_KERNEL);
1784 - if (!msix_entries)
1785 - return -ENOMEM;
1786 + int nr_entries, entry, nvec = 0;
1787
1788 /*
1789 * Allocate as many entries as the port wants, so that we can check
1790 @@ -97,20 +75,13 @@ static int pcie_port_enable_msix(struct
1791 * equal to the number of entries this port actually uses, we'll happily
1792 * go through without any tricks.
1793 */
1794 - for (i = 0; i < nr_entries; i++)
1795 - msix_entries[i].entry = i;
1796 -
1797 - status = pci_enable_msix_exact(dev, msix_entries, nr_entries);
1798 - if (status)
1799 - goto Exit;
1800 -
1801 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1802 - idx[i] = -1;
1803 - status = -EIO;
1804 - nvec = 0;
1805 + nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSIX_ENTRIES,
1806 + PCI_IRQ_MSIX);
1807 + if (nr_entries < 0)
1808 + return nr_entries;
1809
1810 if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP)) {
1811 - int entry;
1812 + u16 reg16;
1813
1814 /*
1815 * The code below follows the PCI Express Base Specification 2.0
1816 @@ -125,18 +96,16 @@ static int pcie_port_enable_msix(struct
1817 pcie_capability_read_word(dev, PCI_EXP_FLAGS, &reg16);
1818 entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
1819 if (entry >= nr_entries)
1820 - goto Error;
1821 + goto out_free_irqs;
1822
1823 - i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
1824 - if (i == nvec)
1825 - nvec++;
1826 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = pci_irq_vector(dev, entry);
1827 + irqs[PCIE_PORT_SERVICE_HP_SHIFT] = pci_irq_vector(dev, entry);
1828
1829 - idx[PCIE_PORT_SERVICE_PME_SHIFT] = i;
1830 - idx[PCIE_PORT_SERVICE_HP_SHIFT] = i;
1831 + nvec = max(nvec, entry + 1);
1832 }
1833
1834 if (mask & PCIE_PORT_SERVICE_AER) {
1835 - int entry;
1836 + u32 reg32, pos;
1837
1838 /*
1839 * The code below follows Section 7.10.10 of the PCI Express
1840 @@ -151,13 +120,11 @@ static int pcie_port_enable_msix(struct
1841 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);
1842 entry = reg32 >> 27;
1843 if (entry >= nr_entries)
1844 - goto Error;
1845 + goto out_free_irqs;
1846
1847 - i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
1848 - if (i == nvec)
1849 - nvec++;
1850 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, entry);
1851
1852 - idx[PCIE_PORT_SERVICE_AER_SHIFT] = i;
1853 + nvec = max(nvec, entry + 1);
1854 }
1855
1856 /*
1857 @@ -165,41 +132,54 @@ static int pcie_port_enable_msix(struct
1858 * what we have. Otherwise, the port has some extra entries not for the
1859 * services we know and we need to work around that.
1860 */
1861 - if (nvec == nr_entries) {
1862 - status = 0;
1863 - } else {
1864 + if (nvec != nr_entries) {
1865 /* Drop the temporary MSI-X setup */
1866 - pci_disable_msix(dev);
1867 + pci_free_irq_vectors(dev);
1868
1869 /* Now allocate the MSI-X vectors for real */
1870 - status = pci_enable_msix_exact(dev, msix_entries, nvec);
1871 - if (status)
1872 - goto Exit;
1873 + nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec,
1874 + PCI_IRQ_MSIX);
1875 + if (nr_entries < 0)
1876 + return nr_entries;
1877 }
1878
1879 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1880 - vectors[i] = idx[i] >= 0 ? msix_entries[idx[i]].vector : -1;
1881 -
1882 - Exit:
1883 - kfree(msix_entries);
1884 - return status;
1885 + return 0;
1886
1887 - Error:
1888 - pci_disable_msix(dev);
1889 - goto Exit;
1890 +out_free_irqs:
1891 + pci_free_irq_vectors(dev);
1892 + return -EIO;
1893 }
1894
1895 /**
1896 - * init_service_irqs - initialize irqs for PCI Express port services
1897 + * pcie_init_service_irqs - initialize irqs for PCI Express port services
1898 * @dev: PCI Express port to handle
1899 * @irqs: Array of irqs to populate
1900 * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1901 *
1902 * Return value: Interrupt mode associated with the port
1903 */
1904 -static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1905 +static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1906 {
1907 - int i, irq = -1;
1908 + unsigned flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI;
1909 + int ret, i;
1910 + int irq = -1;
1911 +
1912 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1913 + irqs[i] = -1;
1914 +
1915 + /* Check if some platforms owns independent irq pins for AER/PME etc.
1916 + * Some platforms may own independent AER/PME interrupts and set
1917 + * them in the device tree file.
1918 + */
1919 + ret = pcibios_check_service_irqs(dev, irqs, mask);
1920 + if (ret) {
1921 + if (dev->irq)
1922 + irq = dev->irq;
1923 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1924 + if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
1925 + irqs[i] = irq;
1926 + return 0;
1927 + }
1928
1929 /*
1930 * If MSI cannot be used for PCIe PME or hotplug, we have to use
1931 @@ -207,41 +187,25 @@ static int init_service_irqs(struct pci_
1932 */
1933 if (((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) ||
1934 ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) {
1935 - if (dev->irq)
1936 - irq = dev->irq;
1937 - goto no_msi;
1938 + flags &= ~PCI_IRQ_MSI;
1939 + } else {
1940 + /* Try to use MSI-X if supported */
1941 + if (!pcie_port_enable_msix(dev, irqs, mask))
1942 + return 0;
1943 }
1944
1945 - /* Try to use MSI-X if supported */
1946 - if (!pcie_port_enable_msix(dev, irqs, mask))
1947 - return 0;
1948 -
1949 - /*
1950 - * We're not going to use MSI-X, so try MSI and fall back to INTx.
1951 - * If neither MSI/MSI-X nor INTx available, try other interrupt. On
1952 - * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
1953 - */
1954 - if (!pci_enable_msi(dev) || dev->irq)
1955 - irq = dev->irq;
1956 + ret = pci_alloc_irq_vectors(dev, 1, 1, flags);
1957 + if (ret < 0)
1958 + return -ENODEV;
1959
1960 - no_msi:
1961 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1962 - irqs[i] = irq;
1963 - irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
1964 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
1965 + if (i != PCIE_PORT_SERVICE_VC_SHIFT)
1966 + irqs[i] = pci_irq_vector(dev, 0);
1967 + }
1968
1969 - if (irq < 0)
1970 - return -ENODEV;
1971 return 0;
1972 }
1973
1974 -static void cleanup_service_irqs(struct pci_dev *dev)
1975 -{
1976 - if (dev->msix_enabled)
1977 - pci_disable_msix(dev);
1978 - else if (dev->msi_enabled)
1979 - pci_disable_msi(dev);
1980 -}
1981 -
1982 /**
1983 * get_port_device_capability - discover capabilities of a PCI Express port
1984 * @dev: PCI Express port to examine
1985 @@ -378,7 +342,7 @@ int pcie_port_device_register(struct pci
1986 * that can be used in the absence of irqs. Allow them to determine
1987 * if that is to be used.
1988 */
1989 - status = init_service_irqs(dev, irqs, capabilities);
1990 + status = pcie_init_service_irqs(dev, irqs, capabilities);
1991 if (status) {
1992 capabilities &= PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_HP;
1993 if (!capabilities)
1994 @@ -401,7 +365,7 @@ int pcie_port_device_register(struct pci
1995 return 0;
1996
1997 error_cleanup_irqs:
1998 - cleanup_service_irqs(dev);
1999 + pci_free_irq_vectors(dev);
2000 error_disable:
2001 pci_disable_device(dev);
2002 return status;
2003 @@ -469,7 +433,7 @@ static int remove_iter(struct device *de
2004 void pcie_port_device_remove(struct pci_dev *dev)
2005 {
2006 device_for_each_child(&dev->dev, NULL, remove_iter);
2007 - cleanup_service_irqs(dev);
2008 + pci_free_irq_vectors(dev);
2009 pci_disable_device(dev);
2010 }
2011
2012 @@ -499,7 +463,6 @@ static int pcie_port_probe_service(struc
2013 if (status)
2014 return status;
2015
2016 - dev_printk(KERN_DEBUG, dev, "service driver %s loaded\n", driver->name);
2017 get_device(dev);
2018 return 0;
2019 }
2020 @@ -524,8 +487,6 @@ static int pcie_port_remove_service(stru
2021 pciedev = to_pcie_device(dev);
2022 driver = to_service_driver(dev->driver);
2023 if (driver && driver->remove) {
2024 - dev_printk(KERN_DEBUG, dev, "unloading service driver %s\n",
2025 - driver->name);
2026 driver->remove(pciedev);
2027 put_device(dev);
2028 }
2029 --- a/include/linux/pci.h
2030 +++ b/include/linux/pci.h
2031 @@ -1823,6 +1823,7 @@ void pcibios_release_device(struct pci_d
2032 void pcibios_penalize_isa_irq(int irq, int active);
2033 int pcibios_alloc_irq(struct pci_dev *dev);
2034 void pcibios_free_irq(struct pci_dev *dev);
2035 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
2036
2037 #ifdef CONFIG_HIBERNATE_CALLBACKS
2038 extern struct dev_pm_ops pcibios_pm_ops;
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