kernel: bump 4.9 to 4.9.124
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 808-guts-support-layerscape.patch
1 From 45b0e1589b25ea3106a8c8d18bf653fde95baa9f Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Wed, 17 Jan 2018 15:34:22 +0800
4 Subject: [PATCH 20/30] guts: support layerscape
5
6 This is an integrated patch for layerscape guts support.
7
8 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
9 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
10 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
12 ---
13 drivers/soc/fsl/guts.c | 238 +++++++++++++++++++++++++++++++++++++++++++++++
14 include/linux/fsl/guts.h | 125 +++++++++++++++----------
15 2 files changed, 315 insertions(+), 48 deletions(-)
16 create mode 100644 drivers/soc/fsl/guts.c
17
18 --- /dev/null
19 +++ b/drivers/soc/fsl/guts.c
20 @@ -0,0 +1,238 @@
21 +/*
22 + * Freescale QorIQ Platforms GUTS Driver
23 + *
24 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
25 + *
26 + * This program is free software; you can redistribute it and/or modify
27 + * it under the terms of the GNU General Public License as published by
28 + * the Free Software Foundation; either version 2 of the License, or
29 + * (at your option) any later version.
30 + */
31 +
32 +#include <linux/io.h>
33 +#include <linux/slab.h>
34 +#include <linux/module.h>
35 +#include <linux/of_fdt.h>
36 +#include <linux/sys_soc.h>
37 +#include <linux/of_address.h>
38 +#include <linux/platform_device.h>
39 +#include <linux/fsl/guts.h>
40 +
41 +struct guts {
42 + struct ccsr_guts __iomem *regs;
43 + bool little_endian;
44 +};
45 +
46 +struct fsl_soc_die_attr {
47 + char *die;
48 + u32 svr;
49 + u32 mask;
50 +};
51 +
52 +static struct guts *guts;
53 +static struct soc_device_attribute soc_dev_attr;
54 +static struct soc_device *soc_dev;
55 +
56 +
57 +/* SoC die attribute definition for QorIQ platform */
58 +static const struct fsl_soc_die_attr fsl_soc_die[] = {
59 + /*
60 + * Power Architecture-based SoCs T Series
61 + */
62 +
63 + /* Die: T4240, SoC: T4240/T4160/T4080 */
64 + { .die = "T4240",
65 + .svr = 0x82400000,
66 + .mask = 0xfff00000,
67 + },
68 + /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
69 + { .die = "T1040",
70 + .svr = 0x85200000,
71 + .mask = 0xfff00000,
72 + },
73 + /* Die: T2080, SoC: T2080/T2081 */
74 + { .die = "T2080",
75 + .svr = 0x85300000,
76 + .mask = 0xfff00000,
77 + },
78 + /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
79 + { .die = "T1024",
80 + .svr = 0x85400000,
81 + .mask = 0xfff00000,
82 + },
83 +
84 + /*
85 + * ARM-based SoCs LS Series
86 + */
87 +
88 + /* Die: LS1043A, SoC: LS1043A/LS1023A */
89 + { .die = "LS1043A",
90 + .svr = 0x87920000,
91 + .mask = 0xffff0000,
92 + },
93 + /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
94 + { .die = "LS2080A",
95 + .svr = 0x87010000,
96 + .mask = 0xff3f0000,
97 + },
98 + /* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */
99 + { .die = "LS1088A",
100 + .svr = 0x87030000,
101 + .mask = 0xff3f0000,
102 + },
103 + /* Die: LS1012A, SoC: LS1012A */
104 + { .die = "LS1012A",
105 + .svr = 0x87040000,
106 + .mask = 0xffff0000,
107 + },
108 + /* Die: LS1046A, SoC: LS1046A/LS1026A */
109 + { .die = "LS1046A",
110 + .svr = 0x87070000,
111 + .mask = 0xffff0000,
112 + },
113 + /* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */
114 + { .die = "LS2088A",
115 + .svr = 0x87090000,
116 + .mask = 0xff3f0000,
117 + },
118 + /* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A */
119 + { .die = "LS1021A",
120 + .svr = 0x87000000,
121 + .mask = 0xfff70000,
122 + },
123 + { },
124 +};
125 +
126 +static const struct fsl_soc_die_attr *fsl_soc_die_match(
127 + u32 svr, const struct fsl_soc_die_attr *matches)
128 +{
129 + while (matches->svr) {
130 + if (matches->svr == (svr & matches->mask))
131 + return matches;
132 + matches++;
133 + };
134 + return NULL;
135 +}
136 +
137 +u32 fsl_guts_get_svr(void)
138 +{
139 + u32 svr = 0;
140 +
141 + if (!guts || !guts->regs)
142 + return svr;
143 +
144 + if (guts->little_endian)
145 + svr = ioread32(&guts->regs->svr);
146 + else
147 + svr = ioread32be(&guts->regs->svr);
148 +
149 + return svr;
150 +}
151 +EXPORT_SYMBOL(fsl_guts_get_svr);
152 +
153 +static int fsl_guts_probe(struct platform_device *pdev)
154 +{
155 + struct device_node *np = pdev->dev.of_node;
156 + struct device *dev = &pdev->dev;
157 + struct resource *res;
158 + const struct fsl_soc_die_attr *soc_die;
159 + const char *machine;
160 + u32 svr;
161 +
162 + /* Initialize guts */
163 + guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);
164 + if (!guts)
165 + return -ENOMEM;
166 +
167 + guts->little_endian = of_property_read_bool(np, "little-endian");
168 +
169 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
170 + guts->regs = devm_ioremap_resource(dev, res);
171 + if (IS_ERR(guts->regs))
172 + return PTR_ERR(guts->regs);
173 +
174 + /* Register soc device */
175 + machine = of_flat_dt_get_machine_name();
176 + if (machine)
177 + soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);
178 +
179 + svr = fsl_guts_get_svr();
180 + soc_die = fsl_soc_die_match(svr, fsl_soc_die);
181 + if (soc_die) {
182 + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
183 + "QorIQ %s", soc_die->die);
184 + } else {
185 + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");
186 + }
187 + soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
188 + "svr:0x%08x", svr);
189 + soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",
190 + (svr >> 4) & 0xf, svr & 0xf);
191 +
192 + soc_dev = soc_device_register(&soc_dev_attr);
193 + if (IS_ERR(soc_dev))
194 + return PTR_ERR(soc_dev);
195 +
196 + pr_info("Machine: %s\n", soc_dev_attr.machine);
197 + pr_info("SoC family: %s\n", soc_dev_attr.family);
198 + pr_info("SoC ID: %s, Revision: %s\n",
199 + soc_dev_attr.soc_id, soc_dev_attr.revision);
200 + return 0;
201 +}
202 +
203 +static int fsl_guts_remove(struct platform_device *dev)
204 +{
205 + soc_device_unregister(soc_dev);
206 + return 0;
207 +}
208 +
209 +/*
210 + * Table for matching compatible strings, for device tree
211 + * guts node, for Freescale QorIQ SOCs.
212 + */
213 +static const struct of_device_id fsl_guts_of_match[] = {
214 + { .compatible = "fsl,qoriq-device-config-1.0", },
215 + { .compatible = "fsl,qoriq-device-config-2.0", },
216 + { .compatible = "fsl,p1010-guts", },
217 + { .compatible = "fsl,p1020-guts", },
218 + { .compatible = "fsl,p1021-guts", },
219 + { .compatible = "fsl,p1022-guts", },
220 + { .compatible = "fsl,p1023-guts", },
221 + { .compatible = "fsl,p2020-guts", },
222 + { .compatible = "fsl,bsc9131-guts", },
223 + { .compatible = "fsl,bsc9132-guts", },
224 + { .compatible = "fsl,mpc8536-guts", },
225 + { .compatible = "fsl,mpc8544-guts", },
226 + { .compatible = "fsl,mpc8548-guts", },
227 + { .compatible = "fsl,mpc8568-guts", },
228 + { .compatible = "fsl,mpc8569-guts", },
229 + { .compatible = "fsl,mpc8572-guts", },
230 + { .compatible = "fsl,ls1021a-dcfg", },
231 + { .compatible = "fsl,ls1043a-dcfg", },
232 + { .compatible = "fsl,ls1046a-dcfg", },
233 + { .compatible = "fsl,ls2080a-dcfg", },
234 + { .compatible = "fsl,ls1088a-dcfg", },
235 + {}
236 +};
237 +MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
238 +
239 +static struct platform_driver fsl_guts_driver = {
240 + .driver = {
241 + .name = "fsl-guts",
242 + .of_match_table = fsl_guts_of_match,
243 + },
244 + .probe = fsl_guts_probe,
245 + .remove = fsl_guts_remove,
246 +};
247 +
248 +static int __init fsl_guts_init(void)
249 +{
250 + return platform_driver_register(&fsl_guts_driver);
251 +}
252 +core_initcall(fsl_guts_init);
253 +
254 +static void __exit fsl_guts_exit(void)
255 +{
256 + platform_driver_unregister(&fsl_guts_driver);
257 +}
258 +module_exit(fsl_guts_exit);
259 --- a/include/linux/fsl/guts.h
260 +++ b/include/linux/fsl/guts.h
261 @@ -30,83 +30,112 @@
262 * #ifdefs.
263 */
264 struct ccsr_guts {
265 - __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
266 - __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
267 - __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
268 - __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
269 - __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
270 - __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
271 + u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
272 + u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
273 + u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
274 + * Control Register
275 + */
276 + u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
277 + u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
278 + u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
279 u8 res018[0x20 - 0x18];
280 - __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
281 + u32 porcir; /* 0x.0020 - POR Configuration Information
282 + * Register
283 + */
284 u8 res024[0x30 - 0x24];
285 - __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
286 + u32 gpiocr; /* 0x.0030 - GPIO Control Register */
287 u8 res034[0x40 - 0x34];
288 - __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
289 + u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
290 + * Register
291 + */
292 u8 res044[0x50 - 0x44];
293 - __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
294 + u32 gpindr; /* 0x.0050 - General-Purpose Input Data
295 + * Register
296 + */
297 u8 res054[0x60 - 0x54];
298 - __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
299 - __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
300 - __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
301 + u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
302 + * Multiplex Control
303 + */
304 + u32 pmuxcr2; /* 0x.0064 - Alternate function signal
305 + * multiplex control 2
306 + */
307 + u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
308 u8 res06c[0x70 - 0x6c];
309 - __be32 devdisr; /* 0x.0070 - Device Disable Control */
310 + u32 devdisr; /* 0x.0070 - Device Disable Control */
311 #define CCSR_GUTS_DEVDISR_TB1 0x00001000
312 #define CCSR_GUTS_DEVDISR_TB0 0x00004000
313 - __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
314 + u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
315 u8 res078[0x7c - 0x78];
316 - __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
317 - __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
318 - __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
319 - __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
320 - __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
321 - __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
322 - __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
323 - __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
324 - __be32 autorstsr; /* 0x.009c - Automatic reset status register */
325 - __be32 pvr; /* 0x.00a0 - Processor Version Register */
326 - __be32 svr; /* 0x.00a4 - System Version Register */
327 + u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
328 + * Register
329 + */
330 + u32 powmgtcsr; /* 0x.0080 - Power Management Status and
331 + * Control Register
332 + */
333 + u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
334 + * Configuration Register
335 + */
336 + u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
337 + * Configuration Register
338 + */
339 + u32 pmcdr; /* 0x.008c - 4Power management clock disable
340 + * register
341 + */
342 + u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
343 + u32 rstrscr; /* 0x.0094 - Reset Request Status and
344 + * Control Register
345 + */
346 + u32 ectrstcr; /* 0x.0098 - Exception reset control register */
347 + u32 autorstsr; /* 0x.009c - Automatic reset status register */
348 + u32 pvr; /* 0x.00a0 - Processor Version Register */
349 + u32 svr; /* 0x.00a4 - System Version Register */
350 u8 res0a8[0xb0 - 0xa8];
351 - __be32 rstcr; /* 0x.00b0 - Reset Control Register */
352 + u32 rstcr; /* 0x.00b0 - Reset Control Register */
353 u8 res0b4[0xc0 - 0xb4];
354 - __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
355 + u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
356 Called 'elbcvselcr' on 86xx SOCs */
357 u8 res0c4[0x100 - 0xc4];
358 - __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
359 + u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
360 There are 16 registers */
361 u8 res140[0x224 - 0x140];
362 - __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
363 - __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
364 + u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
365 + u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
366 u8 res22c[0x604 - 0x22c];
367 - __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
368 + u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
369 u8 res608[0x800 - 0x608];
370 - __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
371 + u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
372 u8 res804[0x900 - 0x804];
373 - __be32 ircr; /* 0x.0900 - Infrared Control Register */
374 + u32 ircr; /* 0x.0900 - Infrared Control Register */
375 u8 res904[0x908 - 0x904];
376 - __be32 dmacr; /* 0x.0908 - DMA Control Register */
377 + u32 dmacr; /* 0x.0908 - DMA Control Register */
378 u8 res90c[0x914 - 0x90c];
379 - __be32 elbccr; /* 0x.0914 - eLBC Control Register */
380 + u32 elbccr; /* 0x.0914 - eLBC Control Register */
381 u8 res918[0xb20 - 0x918];
382 - __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
383 - __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
384 - __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
385 + u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
386 + u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
387 + u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
388 u8 resb2c[0xe00 - 0xb2c];
389 - __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
390 + u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
391 u8 rese04[0xe10 - 0xe04];
392 - __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
393 + u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
394 u8 rese14[0xe20 - 0xe14];
395 - __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
396 - __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
397 + u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
398 + u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
399 + * register
400 + */
401 u8 rese28[0xf04 - 0xe28];
402 - __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
403 - __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
404 + u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
405 + u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
406 u8 resf0c[0xf2c - 0xf0c];
407 - __be32 itcr; /* 0x.0f2c - Internal transaction control register */
408 + u32 itcr; /* 0x.0f2c - Internal transaction control
409 + * register
410 + */
411 u8 resf30[0xf40 - 0xf30];
412 - __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
413 - __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
414 + u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
415 + u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
416 } __attribute__ ((packed));
417
418 +u32 fsl_guts_get_svr(void);
419
420 /* Alternate function signal multiplex control */
421 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))