target/linux/layerscape/patches-4.9/819-flexcan-support-layerscape.patch

   1 From 2887442bd13bc8be687afc7172cb01c2b7f0dd3b Mon Sep 17 00:00:00 2001
   2 From: Yangbo Lu <yangbo.lu@nxp.com>
   3 Date: Thu, 5 Jul 2018 17:41:14 +0800
   4 Subject: [PATCH 31/32] flexcan: support layerscape
   5
   6 This is an integrated patch for layerscape flexcan support.
   7
   8 Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
   9 Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
  10 Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
  11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  12 ---
  13  drivers/net/can/flexcan.c | 212 ++++++++++++++++++++++----------------
  14  1 file changed, 123 insertions(+), 89 deletions(-)
  15
  16 --- a/drivers/net/can/flexcan.c
  17 +++ b/drivers/net/can/flexcan.c
  18 @@ -184,6 +184,7 @@
  19   *   MX53  FlexCAN2  03.00.00.00    yes        no         no        no
  20   *   MX6s  FlexCAN3  10.00.12.00    yes       yes         no       yes
  21   *   VF610 FlexCAN3  ?               no       yes        yes       yes?
  22 + * LS1021A FlexCAN2  03.00.04.00     no       yes         no       yes
  23   *
  24   * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
  25   */
  26 @@ -260,6 +261,10 @@ struct flexcan_priv {
  27         struct flexcan_platform_data *pdata;
  28         const struct flexcan_devtype_data *devtype_data;
  29         struct regulator *reg_xceiver;
  30 +
  31 +       /* Read and Write APIs */
  32 +       u32 (*read)(void __iomem *addr);
  33 +       void (*write)(u32 val, void __iomem *addr);
  34  };
  35
  36  static struct flexcan_devtype_data fsl_p1010_devtype_data = {
  37 @@ -276,6 +281,10 @@ static struct flexcan_devtype_data fsl_v
  38         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
  39  };
  40
  41 +static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
  42 +       .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
  43 +};
  44 +
  45  static const struct can_bittiming_const flexcan_bittiming_const = {
  46         .name = DRV_NAME,
  47         .tseg1_min = 4,
  48 @@ -288,32 +297,38 @@ static const struct can_bittiming_const
  49         .brp_inc = 1,
  50  };
  51
  52 -/* Abstract off the read/write for arm versus ppc. This
  53 - * assumes that PPC uses big-endian registers and everything
  54 - * else uses little-endian registers, independent of CPU
  55 - * endianness.
  56 +/* FlexCAN module is essentially modelled as a little-endian IP in most
  57 + * SoCs, i.e the registers as well as the message buffer areas are
  58 + * implemented in a little-endian fashion.
  59 + *
  60 + * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
  61 + * module in a big-endian fashion (i.e the registers as well as the
  62 + * message buffer areas are implemented in a big-endian way).
  63 + *
  64 + * In addition, the FlexCAN module can be found on SoCs having ARM or
  65 + * PPC cores. So, we need to abstract off the register read/write
  66 + * functions, ensuring that these cater to all the combinations of module
  67 + * endianness and underlying CPU endianness.
  68   */
  69 -#if defined(CONFIG_PPC)
  70 -static inline u32 flexcan_read(void __iomem *addr)
  71 +static inline u32 flexcan_read_be(void __iomem *addr)
  72  {
  73 -       return in_be32(addr);
  74 +       return ioread32be(addr);
  75  }
  76
  77 -static inline void flexcan_write(u32 val, void __iomem *addr)
  78 +static inline void flexcan_write_be(u32 val, void __iomem *addr)
  79  {
  80 -       out_be32(addr, val);
  81 +       iowrite32be(val, addr);
  82  }
  83 -#else
  84 -static inline u32 flexcan_read(void __iomem *addr)
  85 +
  86 +static inline u32 flexcan_read_le(void __iomem *addr)
  87  {
  88 -       return readl(addr);
  89 +       return ioread32(addr);
  90  }
  91
  92 -static inline void flexcan_write(u32 val, void __iomem *addr)
  93 +static inline void flexcan_write_le(u32 val, void __iomem *addr)
  94  {
  95 -       writel(val, addr);
  96 +       iowrite32(val, addr);
  97  }
  98 -#endif
  99
 100  static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 101  {
 102 @@ -344,14 +359,14 @@ static int flexcan_chip_enable(struct fl
 103         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 104         u32 reg;
 105
 106 -       reg = flexcan_read(&regs->mcr);
 107 +       reg = priv->read(&regs->mcr);
 108         reg &= ~FLEXCAN_MCR_MDIS;
 109 -       flexcan_write(reg, &regs->mcr);
 110 +       priv->write(reg, &regs->mcr);
 111
 112 -       while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 113 +       while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 114                 udelay(10);
 115
 116 -       if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 117 +       if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 118                 return -ETIMEDOUT;
 119
 120         return 0;
 121 @@ -363,14 +378,14 @@ static int flexcan_chip_disable(struct f
 122         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 123         u32 reg;
 124
 125 -       reg = flexcan_read(&regs->mcr);
 126 +       reg = priv->read(&regs->mcr);
 127         reg |= FLEXCAN_MCR_MDIS;
 128 -       flexcan_write(reg, &regs->mcr);
 129 +       priv->write(reg, &regs->mcr);
 130
 131 -       while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 132 +       while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 133                 udelay(10);
 134
 135 -       if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 136 +       if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 137                 return -ETIMEDOUT;
 138
 139         return 0;
 140 @@ -382,14 +397,14 @@ static int flexcan_chip_freeze(struct fl
 141         unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 142         u32 reg;
 143
 144 -       reg = flexcan_read(&regs->mcr);
 145 +       reg = priv->read(&regs->mcr);
 146         reg |= FLEXCAN_MCR_HALT;
 147 -       flexcan_write(reg, &regs->mcr);
 148 +       priv->write(reg, &regs->mcr);
 149
 150 -       while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 151 +       while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 152                 udelay(100);
 153
 154 -       if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 155 +       if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 156                 return -ETIMEDOUT;
 157
 158         return 0;
 159 @@ -401,14 +416,14 @@ static int flexcan_chip_unfreeze(struct
 160         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 161         u32 reg;
 162
 163 -       reg = flexcan_read(&regs->mcr);
 164 +       reg = priv->read(&regs->mcr);
 165         reg &= ~FLEXCAN_MCR_HALT;
 166 -       flexcan_write(reg, &regs->mcr);
 167 +       priv->write(reg, &regs->mcr);
 168
 169 -       while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 170 +       while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 171                 udelay(10);
 172
 173 -       if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 174 +       if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 175                 return -ETIMEDOUT;
 176
 177         return 0;
 178 @@ -419,11 +434,11 @@ static int flexcan_chip_softreset(struct
 179         struct flexcan_regs __iomem *regs = priv->regs;
 180         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 181
 182 -       flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 183 -       while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 184 +       priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 185 +       while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 186                 udelay(10);
 187
 188 -       if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 189 +       if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 190                 return -ETIMEDOUT;
 191
 192         return 0;
 193 @@ -434,7 +449,7 @@ static int __flexcan_get_berr_counter(co
 194  {
 195         const struct flexcan_priv *priv = netdev_priv(dev);
 196         struct flexcan_regs __iomem *regs = priv->regs;
 197 -       u32 reg = flexcan_read(&regs->ecr);
 198 +       u32 reg = priv->read(&regs->ecr);
 199
 200         bec->txerr = (reg >> 0) & 0xff;
 201         bec->rxerr = (reg >> 8) & 0xff;
 202 @@ -491,24 +506,24 @@ static int flexcan_start_xmit(struct sk_
 203
 204         if (cf->can_dlc > 0) {
 205                 data = be32_to_cpup((__be32 *)&cf->data[0]);
 206 -               flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);
 207 +               priv->write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);
 208         }
 209         if (cf->can_dlc > 4) {
 210                 data = be32_to_cpup((__be32 *)&cf->data[4]);
 211 -               flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);
 212 +               priv->write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);
 213         }
 214
 215         can_put_echo_skb(skb, dev, 0);
 216
 217 -       flexcan_write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);
 218 -       flexcan_write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
 219 +       priv->write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);
 220 +       priv->write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
 221
 222         /* Errata ERR005829 step8:
 223          * Write twice INACTIVE(0x8) code to first MB.
 224          */
 225 -       flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
 226 +       priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 227                       &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 228 -       flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
 229 +       priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 230                       &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 231
 232         return NETDEV_TX_OK;
 233 @@ -632,8 +647,8 @@ static void flexcan_read_fifo(const stru
 234         struct flexcan_mb __iomem *mb = &regs->mb[0];
 235         u32 reg_ctrl, reg_id;
 236
 237 -       reg_ctrl = flexcan_read(&mb->can_ctrl);
 238 -       reg_id = flexcan_read(&mb->can_id);
 239 +       reg_ctrl = priv->read(&mb->can_ctrl);
 240 +       reg_id = priv->read(&mb->can_id);
 241         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 242                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 243         else
 244 @@ -643,12 +658,12 @@ static void flexcan_read_fifo(const stru
 245                 cf->can_id |= CAN_RTR_FLAG;
 246         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 247
 248 -       *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
 249 -       *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
 250 +       *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
 251 +       *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
 252
 253         /* mark as read */
 254 -       flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 255 -       flexcan_read(&regs->timer);
 256 +       priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 257 +       priv->read(&regs->timer);
 258  }
 259
 260  static int flexcan_read_frame(struct net_device *dev)
 261 @@ -685,17 +700,17 @@ static int flexcan_poll(struct napi_stru
 262         /* The error bits are cleared on read,
 263          * use saved value from irq handler.
 264          */
 265 -       reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
 266 +       reg_esr = priv->read(&regs->esr) | priv->reg_esr;
 267
 268         /* handle state changes */
 269         work_done += flexcan_poll_state(dev, reg_esr);
 270
 271         /* handle RX-FIFO */
 272 -       reg_iflag1 = flexcan_read(&regs->iflag1);
 273 +       reg_iflag1 = priv->read(&regs->iflag1);
 274         while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
 275                work_done < quota) {
 276                 work_done += flexcan_read_frame(dev);
 277 -               reg_iflag1 = flexcan_read(&regs->iflag1);
 278 +               reg_iflag1 = priv->read(&regs->iflag1);
 279         }
 280
 281         /* report bus errors */
 282 @@ -705,8 +720,8 @@ static int flexcan_poll(struct napi_stru
 283         if (work_done < quota) {
 284                 napi_complete_done(napi, work_done);
 285                 /* enable IRQs */
 286 -               flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 287 -               flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
 288 +               priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 289 +               priv->write(priv->reg_ctrl_default, &regs->ctrl);
 290         }
 291
 292         return work_done;
 293 @@ -720,12 +735,12 @@ static irqreturn_t flexcan_irq(int irq,
 294         struct flexcan_regs __iomem *regs = priv->regs;
 295         u32 reg_iflag1, reg_esr;
 296
 297 -       reg_iflag1 = flexcan_read(&regs->iflag1);
 298 -       reg_esr = flexcan_read(&regs->esr);
 299 +       reg_iflag1 = priv->read(&regs->iflag1);
 300 +       reg_esr = priv->read(&regs->esr);
 301
 302         /* ACK all bus error and state change IRQ sources */
 303         if (reg_esr & FLEXCAN_ESR_ALL_INT)
 304 -               flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 305 +               priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 306
 307         /* schedule NAPI in case of:
 308          * - rx IRQ
 309 @@ -739,16 +754,16 @@ static irqreturn_t flexcan_irq(int irq,
 310                  * save them for later use.
 311                  */
 312                 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
 313 -               flexcan_write(FLEXCAN_IFLAG_DEFAULT &
 314 +               priv->write(FLEXCAN_IFLAG_DEFAULT &
 315                               ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
 316 -               flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
 317 +               priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
 318                               &regs->ctrl);
 319                 napi_schedule(&priv->napi);
 320         }
 321
 322         /* FIFO overflow */
 323         if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 324 -               flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
 325 +               priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
 326                 dev->stats.rx_over_errors++;
 327                 dev->stats.rx_errors++;
 328         }
 329 @@ -760,9 +775,9 @@ static irqreturn_t flexcan_irq(int irq,
 330                 can_led_event(dev, CAN_LED_EVENT_TX);
 331
 332                 /* after sending a RTR frame MB is in RX mode */
 333 -               flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
 334 +               priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 335                               &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
 336 -               flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
 337 +               priv->write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
 338                 netif_wake_queue(dev);
 339         }
 340
 341 @@ -776,7 +791,7 @@ static void flexcan_set_bittiming(struct
 342         struct flexcan_regs __iomem *regs = priv->regs;
 343         u32 reg;
 344
 345 -       reg = flexcan_read(&regs->ctrl);
 346 +       reg = priv->read(&regs->ctrl);
 347         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 348                  FLEXCAN_CTRL_RJW(0x3) |
 349                  FLEXCAN_CTRL_PSEG1(0x7) |
 350 @@ -800,11 +815,11 @@ static void flexcan_set_bittiming(struct
 351                 reg |= FLEXCAN_CTRL_SMP;
 352
 353         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
 354 -       flexcan_write(reg, &regs->ctrl);
 355 +       priv->write(reg, &regs->ctrl);
 356
 357         /* print chip status */
 358         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
 359 -                  flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
 360 +                  priv->read(&regs->mcr), priv->read(&regs->ctrl));
 361  }
 362
 363  /* flexcan_chip_start
 364 @@ -842,13 +857,13 @@ static int flexcan_chip_start(struct net
 365          * choose format C
 366          * set max mailbox number
 367          */
 368 -       reg_mcr = flexcan_read(&regs->mcr);
 369 +       reg_mcr = priv->read(&regs->mcr);
 370         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
 371         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
 372                 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
 373                 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
 374         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 375 -       flexcan_write(reg_mcr, &regs->mcr);
 376 +       priv->write(reg_mcr, &regs->mcr);
 377
 378         /* CTRL
 379          *
 380 @@ -861,7 +876,7 @@ static int flexcan_chip_start(struct net
 381          * enable bus off interrupt
 382          * (== FLEXCAN_CTRL_ERR_STATE)
 383          */
 384 -       reg_ctrl = flexcan_read(&regs->ctrl);
 385 +       reg_ctrl = priv->read(&regs->ctrl);
 386         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
 387         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
 388                 FLEXCAN_CTRL_ERR_STATE;
 389 @@ -881,29 +896,29 @@ static int flexcan_chip_start(struct net
 390         /* leave interrupts disabled for now */
 391         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
 392         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
 393 -       flexcan_write(reg_ctrl, &regs->ctrl);
 394 +       priv->write(reg_ctrl, &regs->ctrl);
 395
 396         /* clear and invalidate all mailboxes first */
 397         for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) {
 398 -               flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
 399 +               priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
 400                               &regs->mb[i].can_ctrl);
 401         }
 402
 403         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
 404 -       flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
 405 +       priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 406                       &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 407
 408         /* mark TX mailbox as INACTIVE */
 409 -       flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
 410 +       priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 411                       &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
 412
 413         /* acceptance mask/acceptance code (accept everything) */
 414 -       flexcan_write(0x0, &regs->rxgmask);
 415 -       flexcan_write(0x0, &regs->rx14mask);
 416 -       flexcan_write(0x0, &regs->rx15mask);
 417 +       priv->write(0x0, &regs->rxgmask);
 418 +       priv->write(0x0, &regs->rx14mask);
 419 +       priv->write(0x0, &regs->rx15mask);
 420
 421         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
 422 -               flexcan_write(0x0, &regs->rxfgmask);
 423 +               priv->write(0x0, &regs->rxfgmask);
 424
 425         /* On Vybrid, disable memory error detection interrupts
 426          * and freeze mode.
 427 @@ -916,16 +931,16 @@ static int flexcan_chip_start(struct net
 428                  * and Correction of Memory Errors" to write to
 429                  * MECR register
 430                  */
 431 -               reg_ctrl2 = flexcan_read(&regs->ctrl2);
 432 +               reg_ctrl2 = priv->read(&regs->ctrl2);
 433                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
 434 -               flexcan_write(reg_ctrl2, &regs->ctrl2);
 435 +               priv->write(reg_ctrl2, &regs->ctrl2);
 436
 437 -               reg_mecr = flexcan_read(&regs->mecr);
 438 +               reg_mecr = priv->read(&regs->mecr);
 439                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
 440 -               flexcan_write(reg_mecr, &regs->mecr);
 441 +               priv->write(reg_mecr, &regs->mecr);
 442                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
 443                               FLEXCAN_MECR_FANCEI_MSK);
 444 -               flexcan_write(reg_mecr, &regs->mecr);
 445 +               priv->write(reg_mecr, &regs->mecr);
 446         }
 447
 448         err = flexcan_transceiver_enable(priv);
 449 @@ -941,13 +956,13 @@ static int flexcan_chip_start(struct net
 450
 451         /* enable interrupts atomically */
 452         disable_irq(dev->irq);
 453 -       flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
 454 -       flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 455 +       priv->write(priv->reg_ctrl_default, &regs->ctrl);
 456 +       priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 457         enable_irq(dev->irq);
 458
 459         /* print chip status */
 460         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
 461 -                  flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
 462 +                  priv->read(&regs->mcr), priv->read(&regs->ctrl));
 463
 464         return 0;
 465
 466 @@ -972,8 +987,8 @@ static void flexcan_chip_stop(struct net
 467         flexcan_chip_disable(priv);
 468
 469         /* Disable all interrupts */
 470 -       flexcan_write(0, &regs->imask1);
 471 -       flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
 472 +       priv->write(0, &regs->imask1);
 473 +       priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
 474                       &regs->ctrl);
 475
 476         flexcan_transceiver_disable(priv);
 477 @@ -1089,25 +1104,25 @@ static int register_flexcandev(struct ne
 478         err = flexcan_chip_disable(priv);
 479         if (err)
 480                 goto out_disable_per;
 481 -       reg = flexcan_read(&regs->ctrl);
 482 +       reg = priv->read(&regs->ctrl);
 483         reg |= FLEXCAN_CTRL_CLK_SRC;
 484 -       flexcan_write(reg, &regs->ctrl);
 485 +       priv->write(reg, &regs->ctrl);
 486
 487         err = flexcan_chip_enable(priv);
 488         if (err)
 489                 goto out_chip_disable;
 490
 491         /* set freeze, halt and activate FIFO, restrict register access */
 492 -       reg = flexcan_read(&regs->mcr);
 493 +       reg = priv->read(&regs->mcr);
 494         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
 495                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
 496 -       flexcan_write(reg, &regs->mcr);
 497 +       priv->write(reg, &regs->mcr);
 498
 499         /* Currently we only support newer versions of this core
 500          * featuring a RX FIFO. Older cores found on some Coldfire
 501          * derivates are not yet supported.
 502          */
 503 -       reg = flexcan_read(&regs->mcr);
 504 +       reg = priv->read(&regs->mcr);
 505         if (!(reg & FLEXCAN_MCR_FEN)) {
 506                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
 507                 err = -ENODEV;
 508 @@ -1135,8 +1150,12 @@ static void unregister_flexcandev(struct
 509  static const struct of_device_id flexcan_of_match[] = {
 510         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
 511         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
 512 +       { .compatible = "fsl,imx53-flexcan", .data = &fsl_p1010_devtype_data, },
 513 +       { .compatible = "fsl,imx35-flexcan", .data = &fsl_p1010_devtype_data, },
 514 +       { .compatible = "fsl,imx25-flexcan", .data = &fsl_p1010_devtype_data, },
 515         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
 516         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
 517 +       { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
 518         { /* sentinel */ },
 519  };
 520  MODULE_DEVICE_TABLE(of, flexcan_of_match);
 521 @@ -1213,6 +1232,21 @@ static int flexcan_probe(struct platform
 522         dev->flags |= IFF_ECHO;
 523
 524         priv = netdev_priv(dev);
 525 +
 526 +       if (of_property_read_bool(pdev->dev.of_node, "big-endian")) {
 527 +               priv->read = flexcan_read_be;
 528 +               priv->write = flexcan_write_be;
 529 +       } else {
 530 +               if (of_device_is_compatible(pdev->dev.of_node,
 531 +                                           "fsl,p1010-flexcan")) {
 532 +                       priv->read = flexcan_read_be;
 533 +                       priv->write = flexcan_write_be;
 534 +               } else {
 535 +                       priv->read = flexcan_read_le;
 536 +                       priv->write = flexcan_write_le;
 537 +               }
 538 +       }
 539 +
 540         priv->can.clock.freq = clock_freq;
 541         priv->can.bittiming_const = &flexcan_bittiming_const;
 542         priv->can.do_set_mode = flexcan_set_mode;