target/linux/layerscape/patches-5.4/804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch

   1 From 3d21ebe0b870b9b65b3be0c1473e7148256c4d16 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
   3 Date: Tue, 24 Sep 2019 14:56:48 +0300
   4 Subject: [PATCH] MLKU-114-1 crypto: caam - reduce page 0 regs access to
   5  minimum
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 TODO:
  11
  12 1. if of_property_read_u32_index(,,index=0,) is to be used,
  13 DT bindings (fsl-sec4.txt) should be updated to mandate for
  14 -checked that all existing DTs are configured like this
  15 -this might create problems in the future, if DTs are needed where
  16 JR DT nodes would exist without the controller DT node
  17 (directly on simple bus etc.)
  18
  19 2. MCFGR (ctrl->mcr)
  20 How to determine caam_ptr_sz if MCFGR is not accesible?
  21
  22 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
  23 ---
  24  drivers/crypto/caam/caamalg.c  | 21 ++++++------
  25  drivers/crypto/caam/caamhash.c |  8 +++--
  26  drivers/crypto/caam/caampkc.c  |  4 +--
  27  drivers/crypto/caam/caamrng.c  |  4 +--
  28  drivers/crypto/caam/ctrl.c     | 78 ++++++++++++++++++++++++++----------------
  29  5 files changed, 68 insertions(+), 47 deletions(-)
  30
  31 --- a/drivers/crypto/caam/caamalg.c
  32 +++ b/drivers/crypto/caam/caamalg.c
  33 @@ -3520,13 +3520,14 @@ int caam_algapi_init(struct device *ctrl
  34          * First, detect presence and attributes of DES, AES, and MD blocks.
  35          */
  36         if (priv->era < 10) {
  37 +               struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon;
  38                 u32 cha_vid, cha_inst, aes_rn;
  39
  40 -               cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
  41 +               cha_vid = rd_reg32(&perfmon->cha_id_ls);
  42                 aes_vid = cha_vid & CHA_ID_LS_AES_MASK;
  43                 md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
  44
  45 -               cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
  46 +               cha_inst = rd_reg32(&perfmon->cha_num_ls);
  47                 des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >>
  48                            CHA_ID_LS_DES_SHIFT;
  49                 aes_inst = cha_inst & CHA_ID_LS_AES_MASK;
  50 @@ -3534,23 +3535,23 @@ int caam_algapi_init(struct device *ctrl
  51                 ccha_inst = 0;
  52                 ptha_inst = 0;
  53
  54 -               aes_rn = rd_reg32(&priv->ctrl->perfmon.cha_rev_ls) &
  55 -                        CHA_ID_LS_AES_MASK;
  56 +               aes_rn = rd_reg32(&perfmon->cha_rev_ls) & CHA_ID_LS_AES_MASK;
  57                 gcm_support = !(aes_vid == CHA_VER_VID_AES_LP && aes_rn < 8);
  58         } else {
  59 +               struct version_regs __iomem *vreg = &priv->jr[0]->vreg;
  60                 u32 aesa, mdha;
  61
  62 -               aesa = rd_reg32(&priv->ctrl->vreg.aesa);
  63 -               mdha = rd_reg32(&priv->ctrl->vreg.mdha);
  64 +               aesa = rd_reg32(&vreg->aesa);
  65 +               mdha = rd_reg32(&vreg->mdha);
  66
  67                 aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
  68                 md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
  69
  70 -               des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;
  71 +               des_inst = rd_reg32(&vreg->desa) & CHA_VER_NUM_MASK;
  72                 aes_inst = aesa & CHA_VER_NUM_MASK;
  73                 md_inst = mdha & CHA_VER_NUM_MASK;
  74 -               ccha_inst = rd_reg32(&priv->ctrl->vreg.ccha) & CHA_VER_NUM_MASK;
  75 -               ptha_inst = rd_reg32(&priv->ctrl->vreg.ptha) & CHA_VER_NUM_MASK;
  76 +               ccha_inst = rd_reg32(&vreg->ccha) & CHA_VER_NUM_MASK;
  77 +               ptha_inst = rd_reg32(&vreg->ptha) & CHA_VER_NUM_MASK;
  78
  79                 gcm_support = aesa & CHA_VER_MISC_AES_GCM;
  80         }
  81 --- a/drivers/crypto/caam/caamhash.c
  82 +++ b/drivers/crypto/caam/caamhash.c
  83 @@ -1991,12 +1991,14 @@ int caam_algapi_hash_init(struct device
  84          * presence and attributes of MD block.
  85          */
  86         if (priv->era < 10) {
  87 -               md_vid = (rd_reg32(&priv->ctrl->perfmon.cha_id_ls) &
  88 +               struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon;
  89 +
  90 +               md_vid = (rd_reg32(&perfmon->cha_id_ls) &
  91                           CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
  92 -               md_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
  93 +               md_inst = (rd_reg32(&perfmon->cha_num_ls) &
  94                            CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
  95         } else {
  96 -               u32 mdha = rd_reg32(&priv->ctrl->vreg.mdha);
  97 +               u32 mdha = rd_reg32(&priv->jr[0]->vreg.mdha);
  98
  99                 md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
 100                 md_inst = mdha & CHA_VER_NUM_MASK;
 101 --- a/drivers/crypto/caam/caampkc.c
 102 +++ b/drivers/crypto/caam/caampkc.c
 103 @@ -1099,10 +1099,10 @@ int caam_pkc_init(struct device *ctrldev
 104
 105         /* Determine public key hardware accelerator presence. */
 106         if (priv->era < 10)
 107 -               pk_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
 108 +               pk_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
 109                            CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT;
 110         else
 111 -               pk_inst = rd_reg32(&priv->ctrl->vreg.pkha) & CHA_VER_NUM_MASK;
 112 +               pk_inst = rd_reg32(&priv->jr[0]->vreg.pkha) & CHA_VER_NUM_MASK;
 113
 114         /* Do not register algorithms if PKHA is not present. */
 115         if (!pk_inst)
 116 --- a/drivers/crypto/caam/caamrng.c
 117 +++ b/drivers/crypto/caam/caamrng.c
 118 @@ -363,10 +363,10 @@ int caam_rng_init(struct device *ctrldev
 119
 120         /* Check for an instantiated RNG before registration */
 121         if (priv->era < 10)
 122 -               rng_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
 123 +               rng_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
 124                             CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
 125         else
 126 -               rng_inst = rd_reg32(&priv->ctrl->vreg.rng) & CHA_VER_NUM_MASK;
 127 +               rng_inst = rd_reg32(&priv->jr[0]->vreg.rng) & CHA_VER_NUM_MASK;
 128
 129         if (!rng_inst)
 130                 return 0;
 131 --- a/drivers/crypto/caam/ctrl.c
 132 +++ b/drivers/crypto/caam/ctrl.c
 133 @@ -379,7 +379,7 @@ start_rng:
 134                       RTMCTL_SAMP_MODE_RAW_ES_SC);
 135  }
 136
 137 -static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
 138 +static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon)
 139  {
 140         static const struct {
 141                 u16 ip_id;
 142 @@ -405,12 +405,12 @@ static int caam_get_era_from_hw(struct c
 143         u16 ip_id;
 144         int i;
 145
 146 -       ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
 147 +       ccbvid = rd_reg32(&perfmon->ccb_id);
 148         era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
 149         if (era)        /* This is '0' prior to CAAM ERA-6 */
 150                 return era;
 151
 152 -       id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
 153 +       id_ms = rd_reg32(&perfmon->caam_id_ms);
 154         ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
 155         maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
 156
 157 @@ -428,7 +428,7 @@ static int caam_get_era_from_hw(struct c
 158   * In case this property is not passed an attempt to retrieve the CAAM
 159   * era via register reads will be made.
 160   **/
 161 -static int caam_get_era(struct caam_ctrl __iomem *ctrl)
 162 +static int caam_get_era(struct caam_perfmon __iomem *perfmon)
 163  {
 164         struct device_node *caam_node;
 165         int ret;
 166 @@ -441,7 +441,7 @@ static int caam_get_era(struct caam_ctrl
 167         if (!ret)
 168                 return prop;
 169         else
 170 -               return caam_get_era_from_hw(ctrl);
 171 +               return caam_get_era_from_hw(perfmon);
 172  }
 173
 174  /*
 175 @@ -575,8 +575,8 @@ static int caam_probe(struct platform_de
 176         struct device_node *nprop, *np;
 177         struct caam_ctrl __iomem *ctrl;
 178         struct caam_drv_private *ctrlpriv;
 179 +       struct caam_perfmon __iomem *perfmon;
 180  #ifdef CONFIG_DEBUG_FS
 181 -       struct caam_perfmon *perfmon;
 182         struct dentry *dfs_root;
 183  #endif
 184         u32 scfgr, comp_params;
 185 @@ -616,9 +616,36 @@ static int caam_probe(struct platform_de
 186                 return ret;
 187         }
 188
 189 -       caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
 190 +       ring = 0;
 191 +       for_each_available_child_of_node(nprop, np)
 192 +               if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 193 +                   of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
 194 +                       u32 reg;
 195 +
 196 +                       if (of_property_read_u32_index(np, "reg", 0, &reg)) {
 197 +                               dev_err(dev, "%s read reg property error\n",
 198 +                                       np->full_name);
 199 +                               continue;
 200 +                       }
 201 +
 202 +                       ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
 203 +                                            ((__force uint8_t *)ctrl + reg);
 204 +
 205 +                       ctrlpriv->total_jobrs++;
 206 +                       ring++;
 207 +               }
 208 +
 209 +       /*
 210 +        * Wherever possible, instead of accessing registers from the global page,
 211 +        * use the alias registers in the first (cf. DT nodes order)
 212 +        * job ring's page.
 213 +        */
 214 +       perfmon = ring ? (struct caam_perfmon *)&ctrlpriv->jr[0]->perfmon :
 215 +                        (struct caam_perfmon *)&ctrl->perfmon;
 216 +
 217 +       caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
 218                                   (CSTA_PLEND | CSTA_ALT_PLEND));
 219 -       comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 220 +       comp_params = rd_reg32(&perfmon->comp_parms_ms);
 221         if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
 222                 caam_ptr_sz = sizeof(u64);
 223         else
 224 @@ -718,7 +745,7 @@ static int caam_probe(struct platform_de
 225                 return ret;
 226         }
 227
 228 -       ctrlpriv->era = caam_get_era(ctrl);
 229 +       ctrlpriv->era = caam_get_era(perfmon);
 230         ctrlpriv->domain = iommu_get_domain_for_dev(dev);
 231
 232  #ifdef CONFIG_DEBUG_FS
 233 @@ -727,8 +754,6 @@ static int caam_probe(struct platform_de
 234          * "caam" and nprop->full_name. The OF name isn't distinctive,
 235          * but does separate instances
 236          */
 237 -       perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
 238 -
 239         dfs_root = debugfs_create_dir(dev_name(dev), NULL);
 240         ret = devm_add_action_or_reset(dev, caam_remove_debugfs, dfs_root);
 241         if (ret)
 242 @@ -754,31 +779,24 @@ static int caam_probe(struct platform_de
 243  #endif
 244         }
 245
 246 -       ring = 0;
 247 -       for_each_available_child_of_node(nprop, np)
 248 -               if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 249 -                   of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
 250 -                       ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
 251 -                                            ((__force uint8_t *)ctrl +
 252 -                                            (ring + JR_BLOCK_NUMBER) *
 253 -                                             BLOCK_OFFSET
 254 -                                            );
 255 -                       ctrlpriv->total_jobrs++;
 256 -                       ring++;
 257 -               }
 258 -
 259         /* If no QI and no rings specified, quit and go home */
 260         if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
 261                 dev_err(dev, "no queues configured, terminating\n");
 262                 return -ENOMEM;
 263         }
 264
 265 -       if (ctrlpriv->era < 10)
 266 -               rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &
 267 +       if (ctrlpriv->era < 10) {
 268 +               rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
 269                            CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
 270 -       else
 271 -               rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
 272 +       } else {
 273 +               struct version_regs __iomem *vreg;
 274 +
 275 +               vreg = ring ? (struct version_regs *)&ctrlpriv->jr[0]->vreg :
 276 +                             (struct version_regs *)&ctrl->vreg;
 277 +
 278 +               rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>
 279                            CHA_VER_VID_SHIFT;
 280 +       }
 281
 282         /*
 283          * If SEC has RNG version >= 4 and RNG state handle has not been
 284 @@ -847,8 +865,8 @@ static int caam_probe(struct platform_de
 285
 286         /* NOTE: RTIC detection ought to go here, around Si time */
 287
 288 -       caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
 289 -                 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 290 +       caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
 291 +                 (u64)rd_reg32(&perfmon->caam_id_ls);
 292
 293         /* Report "alive" for developer to see */
 294         dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,