imx6: drop 3.14
[openwrt/openwrt.git] / target / linux / mcs814x / files-3.14 / arch / arm / boot / dts / mcs8140.dtsi
1 /*
2 * mcs8140.dtsi - Device Tree Include file for Moschip MCS8140 family SoC
3 *
4 * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
5 *
6 * Licensed under GPLv2.
7 */
8
9 /include/ "skeleton.dtsi"
10
11 / {
12 model = "Moschip MCS8140 family SoC";
13 compatible = "moschip,mcs8140";
14 interrupt-parent = <&intc>;
15
16 aliases {
17 serial0 = &uart0;
18 eth0 = &eth0;
19 };
20
21 cpus {
22 cpu@0 {
23 compatible = "arm,arm926ejs";
24 };
25 };
26
27 ahb {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges;
32
33 vci {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 ranges;
38
39 eth0: ethernet@40084000 {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 compatible = "moschip,nuport-mac";
44 reg = <0x40084000 0xd8 // mac
45 0x40080000 0x58>; // dma channels
46 interrupts = <4 5 29>; /* tx, rx, link */
47 nuport-mac,buffer-shifting;
48 nuport-mac,link-activity = <0>;
49 };
50
51 tso@40088000 {
52 reg = <0x40088000 0x1c>;
53 interrupts = <7>;
54 };
55
56 i2s@4008c000 {
57 compatible = "moschip,mcs814x-i2s";
58 reg = <0x4008c000 0x18>;
59 interrupts = <8>;
60 };
61
62 ipsec@40094000 {
63 compatible = "moschip,mcs814x-ipsec";
64 reg = <0x40094000 0x1d8>;
65 interrupts = <16>;
66 };
67
68 rng@4009c000 {
69 compatible = "moschip,mcs814x-rng";
70 reg = <0x4009c000 0x8>;
71 };
72
73 memc@400a8000 {
74 reg = <0x400a8000 0x58>;
75 };
76
77 list-proc@400ac0c0 {
78 reg = <0x400ac0c0 0x38>;
79 interrupts = <19 27>; // done, error
80 };
81
82 gpio: gpio@400d0000 {
83 compatible = "moschip,mcs814x-gpio";
84 reg = <0x400d0000 0x670>;
85 interrupts = <10>;
86 #gpio-cells = <2>;
87 gpio-controller;
88 num-gpios = <20>;
89 };
90
91 eepio: gpio@400d4000 {
92 compatible = "moschip,mcs814x-gpio";
93 reg = <0x400d4000 0x470>;
94 #gpio-cells = <2>;
95 gpio-controller;
96 num-gpios = <4>;
97 };
98
99 uart0: serial@400dc000 {
100 compatible = "ns16550";
101 reg = <0x400dc000 0x20>;
102 clock-frequency = <50000000>;
103 reg-shift = <2>;
104 interrupts = <21>;
105 status = "okay";
106 };
107
108 intc: interrupt-controller@400e4000 {
109 #interrupt-cells = <1>;
110 compatible = "moschip,mcs814x-intc";
111 interrupt-controller;
112 interrupt-parent;
113 reg = <0x400e4000 0x48>;
114 };
115
116 m2m@400e8000 {
117 reg = <0x400e8000 0x24>;
118 interrupts = <17>;
119 };
120
121 eth-filters@400ec000 {
122 reg = <0x400ec000 0x80>;
123 };
124
125 timer: timer@400f800c {
126 compatible = "moschip,mcs814x-timer";
127 interrupts = <0>;
128 reg = <0x400f800c 0x8>;
129 };
130
131 watchdog@400f8014 {
132 compatible = "moschip,mcs814x-wdt";
133 reg = <0x400f8014 0x8>;
134 };
135
136 adc {
137 compatible = "simple-bus";
138 #address-cells = <2>;
139 #size-cells = <1>;
140 // 8 64MB chip-selects
141 ranges = <0 0 0x00000000 0x4000000 // sdram
142 1 0 0x04000000 0x4000000 // sdram
143 2 0 0x08000000 0x4000000 // reserved
144 3 0 0x0c000000 0x4000000 // flash/localbus
145 4 0 0x10000000 0x4000000 // flash/localbus
146 5 0 0x14000000 0x4000000 // flash/localbus
147 6 0 0x18000000 0x4000000 // flash/localbus
148 7 0 0x1c000000 0x4000000>; // flash/localbus
149
150 sdram: memory@0,0 {
151 reg = <0 0 0>;
152 };
153
154 nor: flash@7,0 {
155 reg = <7 0 0x4000000>;
156 compatible = "cfi-flash";
157 bank-width = <1>; // 8-bit external flash
158 #address-cells = <1>;
159 #size-cells = <1>;
160 };
161 };
162
163 usb0: ehci@400fc000 {
164 compatible = "moschip,mcs814x-ehci", "usb-ehci";
165 reg = <0x400fc000 0x74>;
166 interrupts = <2>;
167 };
168
169 usb1: ohci@400fd000 {
170 compatible = "moschip,mcs814x-ohci", "ohci-le";
171 reg = <0x400fd000 0x74>;
172 interrupts = <11>;
173 };
174
175 usb2: ohci@400fe000 {
176 compatible = "moschip,mcs814x-ohci", "ohci-le";
177 reg = <0x400fe000 0x74>;
178 interrupts = <12>;
179 };
180
181 usb3: otg@400ff000 {
182 compatible = "moschip,msc814x-otg", "usb-otg";
183 reg = <0x400ff000 0x1000>;
184 interrupts = <13>;
185 };
186 };
187
188 };
189 };