target/linux/mediatek/patches-4.14/0122-soc-mediatek-pwrap-add-support-for-MT7622-SoC.patch

   1 From 87996dabef0d83bbd2ed5264b83b01224bc42968 Mon Sep 17 00:00:00 2001
   2 From: Chenglin Xu <chenglin.xu@mediatek.com>
   3 Date: Wed, 18 Oct 2017 16:28:48 +0800
   4 Subject: [PATCH 122/224] soc: mediatek: pwrap: add support for MT7622 SoC
   5
   6 Add the registers, callbacks and data structures required to make the
   7 PMIC wrapper work on MT7622.
   8
   9 Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
  10 Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
  11 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  12 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  13 ---
  14  drivers/soc/mediatek/mtk-pmic-wrap.c | 170 +++++++++++++++++++++++++++++++++++
  15  1 file changed, 170 insertions(+)
  16
  17 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
  18 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
  19 @@ -214,6 +214,36 @@ enum pwrap_regs {
  20         PWRAP_ADC_RDATA_ADDR1,
  21         PWRAP_ADC_RDATA_ADDR2,
  22
  23 +       /* MT7622 only regs */
  24 +       PWRAP_EINT_STA0_ADR,
  25 +       PWRAP_EINT_STA1_ADR,
  26 +       PWRAP_STA,
  27 +       PWRAP_CLR,
  28 +       PWRAP_DVFS_ADR8,
  29 +       PWRAP_DVFS_WDATA8,
  30 +       PWRAP_DVFS_ADR9,
  31 +       PWRAP_DVFS_WDATA9,
  32 +       PWRAP_DVFS_ADR10,
  33 +       PWRAP_DVFS_WDATA10,
  34 +       PWRAP_DVFS_ADR11,
  35 +       PWRAP_DVFS_WDATA11,
  36 +       PWRAP_DVFS_ADR12,
  37 +       PWRAP_DVFS_WDATA12,
  38 +       PWRAP_DVFS_ADR13,
  39 +       PWRAP_DVFS_WDATA13,
  40 +       PWRAP_DVFS_ADR14,
  41 +       PWRAP_DVFS_WDATA14,
  42 +       PWRAP_DVFS_ADR15,
  43 +       PWRAP_DVFS_WDATA15,
  44 +       PWRAP_EXT_CK,
  45 +       PWRAP_ADC_RDATA_ADDR,
  46 +       PWRAP_GPS_STA,
  47 +       PWRAP_SW_RST,
  48 +       PWRAP_DVFS_STEP_CTRL0,
  49 +       PWRAP_DVFS_STEP_CTRL1,
  50 +       PWRAP_DVFS_STEP_CTRL2,
  51 +       PWRAP_SPI2_CTRL,
  52 +
  53         /* MT8135 only regs */
  54         PWRAP_CSHEXT,
  55         PWRAP_EVENT_IN_EN,
  56 @@ -336,6 +366,118 @@ static int mt2701_regs[] = {
  57         [PWRAP_ADC_RDATA_ADDR2] =       0x154,
  58  };
  59
  60 +static int mt7622_regs[] = {
  61 +       [PWRAP_MUX_SEL] =               0x0,
  62 +       [PWRAP_WRAP_EN] =               0x4,
  63 +       [PWRAP_DIO_EN] =                0x8,
  64 +       [PWRAP_SIDLY] =                 0xC,
  65 +       [PWRAP_RDDMY] =                 0x10,
  66 +       [PWRAP_SI_CK_CON] =             0x14,
  67 +       [PWRAP_CSHEXT_WRITE] =          0x18,
  68 +       [PWRAP_CSHEXT_READ] =           0x1C,
  69 +       [PWRAP_CSLEXT_START] =          0x20,
  70 +       [PWRAP_CSLEXT_END] =            0x24,
  71 +       [PWRAP_STAUPD_PRD] =            0x28,
  72 +       [PWRAP_STAUPD_GRPEN] =          0x2C,
  73 +       [PWRAP_EINT_STA0_ADR] =         0x30,
  74 +       [PWRAP_EINT_STA1_ADR] =         0x34,
  75 +       [PWRAP_STA] =                   0x38,
  76 +       [PWRAP_CLR] =                   0x3C,
  77 +       [PWRAP_STAUPD_MAN_TRIG] =       0x40,
  78 +       [PWRAP_STAUPD_STA] =            0x44,
  79 +       [PWRAP_WRAP_STA] =              0x48,
  80 +       [PWRAP_HARB_INIT] =             0x4C,
  81 +       [PWRAP_HARB_HPRIO] =            0x50,
  82 +       [PWRAP_HIPRIO_ARB_EN] =         0x54,
  83 +       [PWRAP_HARB_STA0] =             0x58,
  84 +       [PWRAP_HARB_STA1] =             0x5C,
  85 +       [PWRAP_MAN_EN] =                0x60,
  86 +       [PWRAP_MAN_CMD] =               0x64,
  87 +       [PWRAP_MAN_RDATA] =             0x68,
  88 +       [PWRAP_MAN_VLDCLR] =            0x6C,
  89 +       [PWRAP_WACS0_EN] =              0x70,
  90 +       [PWRAP_INIT_DONE0] =            0x74,
  91 +       [PWRAP_WACS0_CMD] =             0x78,
  92 +       [PWRAP_WACS0_RDATA] =           0x7C,
  93 +       [PWRAP_WACS0_VLDCLR] =          0x80,
  94 +       [PWRAP_WACS1_EN] =              0x84,
  95 +       [PWRAP_INIT_DONE1] =            0x88,
  96 +       [PWRAP_WACS1_CMD] =             0x8C,
  97 +       [PWRAP_WACS1_RDATA] =           0x90,
  98 +       [PWRAP_WACS1_VLDCLR] =          0x94,
  99 +       [PWRAP_WACS2_EN] =              0x98,
 100 +       [PWRAP_INIT_DONE2] =            0x9C,
 101 +       [PWRAP_WACS2_CMD] =             0xA0,
 102 +       [PWRAP_WACS2_RDATA] =           0xA4,
 103 +       [PWRAP_WACS2_VLDCLR] =          0xA8,
 104 +       [PWRAP_INT_EN] =                0xAC,
 105 +       [PWRAP_INT_FLG_RAW] =           0xB0,
 106 +       [PWRAP_INT_FLG] =               0xB4,
 107 +       [PWRAP_INT_CLR] =               0xB8,
 108 +       [PWRAP_SIG_ADR] =               0xBC,
 109 +       [PWRAP_SIG_MODE] =              0xC0,
 110 +       [PWRAP_SIG_VALUE] =             0xC4,
 111 +       [PWRAP_SIG_ERRVAL] =            0xC8,
 112 +       [PWRAP_CRC_EN] =                0xCC,
 113 +       [PWRAP_TIMER_EN] =              0xD0,
 114 +       [PWRAP_TIMER_STA] =             0xD4,
 115 +       [PWRAP_WDT_UNIT] =              0xD8,
 116 +       [PWRAP_WDT_SRC_EN] =            0xDC,
 117 +       [PWRAP_WDT_FLG] =               0xE0,
 118 +       [PWRAP_DEBUG_INT_SEL] =         0xE4,
 119 +       [PWRAP_DVFS_ADR0] =             0xE8,
 120 +       [PWRAP_DVFS_WDATA0] =           0xEC,
 121 +       [PWRAP_DVFS_ADR1] =             0xF0,
 122 +       [PWRAP_DVFS_WDATA1] =           0xF4,
 123 +       [PWRAP_DVFS_ADR2] =             0xF8,
 124 +       [PWRAP_DVFS_WDATA2] =           0xFC,
 125 +       [PWRAP_DVFS_ADR3] =             0x100,
 126 +       [PWRAP_DVFS_WDATA3] =           0x104,
 127 +       [PWRAP_DVFS_ADR4] =             0x108,
 128 +       [PWRAP_DVFS_WDATA4] =           0x10C,
 129 +       [PWRAP_DVFS_ADR5] =             0x110,
 130 +       [PWRAP_DVFS_WDATA5] =           0x114,
 131 +       [PWRAP_DVFS_ADR6] =             0x118,
 132 +       [PWRAP_DVFS_WDATA6] =           0x11C,
 133 +       [PWRAP_DVFS_ADR7] =             0x120,
 134 +       [PWRAP_DVFS_WDATA7] =           0x124,
 135 +       [PWRAP_DVFS_ADR8] =             0x128,
 136 +       [PWRAP_DVFS_WDATA8] =           0x12C,
 137 +       [PWRAP_DVFS_ADR9] =             0x130,
 138 +       [PWRAP_DVFS_WDATA9] =           0x134,
 139 +       [PWRAP_DVFS_ADR10] =            0x138,
 140 +       [PWRAP_DVFS_WDATA10] =          0x13C,
 141 +       [PWRAP_DVFS_ADR11] =            0x140,
 142 +       [PWRAP_DVFS_WDATA11] =          0x144,
 143 +       [PWRAP_DVFS_ADR12] =            0x148,
 144 +       [PWRAP_DVFS_WDATA12] =          0x14C,
 145 +       [PWRAP_DVFS_ADR13] =            0x150,
 146 +       [PWRAP_DVFS_WDATA13] =          0x154,
 147 +       [PWRAP_DVFS_ADR14] =            0x158,
 148 +       [PWRAP_DVFS_WDATA14] =          0x15C,
 149 +       [PWRAP_DVFS_ADR15] =            0x160,
 150 +       [PWRAP_DVFS_WDATA15] =          0x164,
 151 +       [PWRAP_SPMINF_STA] =            0x168,
 152 +       [PWRAP_CIPHER_KEY_SEL] =        0x16C,
 153 +       [PWRAP_CIPHER_IV_SEL] =         0x170,
 154 +       [PWRAP_CIPHER_EN] =             0x174,
 155 +       [PWRAP_CIPHER_RDY] =            0x178,
 156 +       [PWRAP_CIPHER_MODE] =           0x17C,
 157 +       [PWRAP_CIPHER_SWRST] =          0x180,
 158 +       [PWRAP_DCM_EN] =                0x184,
 159 +       [PWRAP_DCM_DBC_PRD] =           0x188,
 160 +       [PWRAP_EXT_CK] =                0x18C,
 161 +       [PWRAP_ADC_CMD_ADDR] =          0x190,
 162 +       [PWRAP_PWRAP_ADC_CMD] =         0x194,
 163 +       [PWRAP_ADC_RDATA_ADDR] =        0x198,
 164 +       [PWRAP_GPS_STA] =               0x19C,
 165 +       [PWRAP_SW_RST] =                0x1A0,
 166 +       [PWRAP_DVFS_STEP_CTRL0] =       0x238,
 167 +       [PWRAP_DVFS_STEP_CTRL1] =       0x23C,
 168 +       [PWRAP_DVFS_STEP_CTRL2] =       0x240,
 169 +       [PWRAP_SPI2_CTRL] =             0x244,
 170 +};
 171 +
 172  static int mt8173_regs[] = {
 173         [PWRAP_MUX_SEL] =               0x0,
 174         [PWRAP_WRAP_EN] =               0x4,
 175 @@ -499,6 +641,7 @@ enum pmic_type {
 176
 177  enum pwrap_type {
 178         PWRAP_MT2701,
 179 +       PWRAP_MT7622,
 180         PWRAP_MT8135,
 181         PWRAP_MT8173,
 182  };
 183 @@ -927,6 +1070,9 @@ static int pwrap_init_cipher(struct pmic
 184         case PWRAP_MT8173:
 185                 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
 186                 break;
 187 +       case PWRAP_MT7622:
 188 +               pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
 189 +               break;
 190         }
 191
 192         /* Config cipher mode @PMIC */
 193 @@ -1071,6 +1217,15 @@ static int pwrap_mt2701_init_soc_specifi
 194         return 0;
 195  }
 196
 197 +static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
 198 +{
 199 +       pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
 200 +       /* enable 2wire SPI master */
 201 +       pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
 202 +
 203 +       return 0;
 204 +}
 205 +
 206  static int pwrap_init(struct pmic_wrapper *wrp)
 207  {
 208         int ret;
 209 @@ -1242,6 +1397,18 @@ static const struct pmic_wrapper_type pw
 210         .init_soc_specific = pwrap_mt2701_init_soc_specific,
 211  };
 212
 213 +static const struct pmic_wrapper_type pwrap_mt7622 = {
 214 +       .regs = mt7622_regs,
 215 +       .type = PWRAP_MT7622,
 216 +       .arb_en_all = 0xff,
 217 +       .int_en_all = ~(u32)BIT(31),
 218 +       .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
 219 +       .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
 220 +       .has_bridge = 0,
 221 +       .init_reg_clock = pwrap_common_init_reg_clock,
 222 +       .init_soc_specific = pwrap_mt7622_init_soc_specific,
 223 +};
 224 +
 225  static const struct pmic_wrapper_type pwrap_mt8135 = {
 226         .regs = mt8135_regs,
 227         .type = PWRAP_MT8135,
 228 @@ -1271,6 +1438,9 @@ static const struct of_device_id of_pwra
 229                 .compatible = "mediatek,mt2701-pwrap",
 230                 .data = &pwrap_mt2701,
 231         }, {
 232 +               .compatible = "mediatek,mt7622-pwrap",
 233 +               .data = &pwrap_mt7622,
 234 +       }, {
 235                 .compatible = "mediatek,mt8135-pwrap",
 236                 .data = &pwrap_mt8135,
 237         }, {